Reed Muller Error Correcting Code by Ramakrishnan Ranganathan

Acknowledgement An endeavor as demanding as research can never be successfully accomplished, but with the backing of people who stood by us during all travails of such a task, I could do it. So I take this golden opportunity to acknowledge all those who have directly or otherwise contributed to the success of my project. With most sincere and deepest sense of gratitude, I thank Mr. Sivarajan my guide for his valuable guidance and encouragement throughout the project. His immense encouragement and direction was the foremost to the completion of the project work. I am very grateful to my Head of the department Mrs. Siji, for her constant encouragement and valuable suggestions. I also thank Mrs. Babiyola, Mr. Balasubramanian and all other teachers who were of immense help to me through all phases of this course and the project

Abstract Reed Muller codes are some of the most effective error correcting codes. Error correcting codes are very useful in sending information over long distances or through channels where errors might occur in the message. They have become more prevalent as telecommunications have expanded and developed a use for codes that can self correct. D.E.Muller as I.S.Reed invented Reed Muller code in 1954.In 1972, a Reed Muller was used to by Mariner 9 to transmit Black and white photographs of mars. Reed Muller codes are relatively easy to decode and first order codes are especially efficient. In high-reliability aerospace, avionics, and military applications, single error correction (SEC) and double error detection (DED) may not provide adequate protection against faults. This makes multiple-error correction (MEC) highly desirable. Although many powerful error control methods including ReedSolomon are capable of correcting multiple bytes of error, the general drawback with these methods is latency (The time between initiating a request and receiving the answer) and speed. Most of these codes require at least several dozen cycles to complete the first correction. Fortunately, Reed-Muller error control codes possess multiple bit error correction capability with relatively low latency and high performance.

Description :

Define Requirements:

This block is going to specify the functionality of the device. Specify all the I/O, function, constraints (to optimize) like Area, Power, Delay(Propagation Delay )

and

performance requirements.

Schematic Entry & HDL :

The next block will include the architectural description to provide functional description between Input/Output ports of the design.

Schematic entry includes

combinational logic design and RTL (Register Transfer Level). Functional Description are written in HDL to achieve maximum reliability with minimum development time and to have synchronous mechanism between concurrent flows.

Simulation :

To verify the functionality of the design. This is done by forcing all the test scalars or vectors to the design file. As forcing the test values to the design consumes much time, writing a stimuli (TEST-BENCH) file would be the best way to verify the logic. 1. Design file – Synthesizable HDL 2. Test-Bench – Non-Synthesizable HDL Synthesis:

The Synthesis stage generates a netlist from the HDL code. The netlist is a lower level abstraction of the code, which will be used for the place and route process

Translate :

Process to convert the gate-level netlist to a logical Boolean expression is said to be Translate. Then optimization (making the best out of the design) is done on the Boolean expression by applying Karnaugh Map to reduce the redundant logic that is fetched.

Place and Route:

Place and Route are sub processes of Layout (geometric representation of a logic). During the placement phase, logic primitives are assigned to the physical location in the environment selected as a target technology. The main objective of placement is to ease routing of the design. Typically, placement algorithms attempt to minimize the total expected length of the interconnect required for the given placement. In addition, for specific target technology such as for example gate arrays, limited routing resources, routing channel congestions and delays imposed by interconnect have to be considered during the placement phase. The goal of a routing phase are not only 100% routed interconnect but the minimized routing delays which are imposed due to the parasitic effects on interconnect and routing resources.

Configuration:

Configuration is a process in which the circuit design (bitstream file) is downloaded into the FPGA. The method of configuring the FPGA determines the type of bitstream file.

FPGA Chip:

The process involved in this stage will only consist of the programming and encoding of the chip itself not the actual fabrication and testing because the chip is already provided.

INTRODUCTION Error correcting codes are very useful in sending information over long distances or through channels where errors might occur in the message. They have become more prevalent as telecommunications have expanded and developed a use for codes that can self-correct. Reed Muller co des were invented in 1954 by D. E. Muller and I. S. Reed. In 1972, a Reed Muller code was used by Mariner 9 to transmit black and white photographs of Mars, Reed Muller codes are relatively easy to decode, and first-order codes are especially efficient.

In high-reliability applications, memory can sustain multiple soft errors (An error that occurs occasionally which are said to be recoverable ) due to single or multiple event upsets caused by environmental factors (cosmic neutrons, alpha particles, etc.). The traditional Hamming code with SEC-DED capability cannot address these types of errors. It is possible to use powerful non-binary BCH code such as Reed-Solomon code to address multiple-bit errors. However, it could take at least a couple dozen cycles of latency to complete the first correction and run at a relatively slow speed. This project explores the possibility of using Reed-Muller (RM) code in memory interface applications to address multiple-bit soft errors. RM code is one of the error correction codes belonging to the Finite Geometry (A finite geometry is any geometric system that has only a finite number of points) family. Due to its orthogonal structure (Two signals are said to be orthogonal if they can be completely separated using the proper basis function [TDMA, the basis fn is TIME SLOT],[CDMA, the basis fn is CHIPPING CODE]), it is relatively easy to decode using the Majority-Logic Decoding (MLD) method. The following section is a brief explanation of the construct and decoding of simple RM code. Definition of Terms and Operations. The vector spaces used in this paper consist of strings of length 2m, where m is a positive integer, of numbers in F2 = f0; 1g. The codeword of a Reed_Muller code form a subspace of such a space. Vectors can be manipulated by three main operations: addition, multiplication, and the dot product. For two vectors x = (x1; x2; : : : ; xn) and y = (y1; y2; : : : ; yn), addition is defined by

x + y = (x1 + y1; x2 + y2; : : : ; xn + yn)

Reed-Muller codes are listed as RM(r,m), where r is the order of the code, and m is parameter related to the length of code, n = 2m. RM codes are related to binary functions on field F(2m) over the elements [0,1]. RM(0,m) codes are repetition codes, RM(m-1,m) codes are parity check codes. An rth order Reed-Muller code RM(r,m) is the set of all binary strings of length n = 2m associated with the Boolean polynomials p(x1; x2;…; xm) of degree at most r. A Boolean polynomial is a linear combination of Boolean monomials. A Boolean monomial p in the variables x1, x2, …, xm is the expression of the form

The degree of a monomial is deduced (concluded) from its reduced form (after rules xixj = xjxi and xi^ 2 = xi are applied), and it is equal to the number of variables. This rule extends to polynomials. Example of a polynomial of degree 3:

For example, the first order RM (1,3) code word size is 2 3 = 8 with single bit error correction capability. It has up to one in three variables: {1, x1, x2, x3} in each monomial as follow:

In the RM encoder, the code word is created by the following matrix multiplication:

Where M is the original message matrix, G is the generator matrix and C is the resulting code word.

The generation of the RM (1,3) code word C is described as:

The RM (1,3) generator matrix is:

The matrix multiplication results in the following encoder equations where Exclusive-OR operation is performed.

To decode an incoming code word C' back to its original message M', each message bit M'i is determined based on the majority of the corresponding orthogonal checksums Si,k generated from the incoming code word C'. In this case, there are four checksums for each original message bit M'2, M'1, and M'0.

The orthogonal checksums for decoding the original message are shown in Table 1.

Table 1: Orthogonal Checksums

The majority rules are simple, if more than two checksums result in a "1", the original message bit is "1". If more than two checksums result in a "0", the original message bit is "0". In the case of equal number of checksums resulting in 1s and 0s, the original message bit is undetermined. In other words, it has reached the correcting limit of this code. However, it is important to note, such an event also indicates the presence of quadruple error. The decoder should flag this as warning. Furthermore, any one group of the checksums can detect quadruple error independently.

To determine M'3, another partial code word C'' needs to be constructed based on the result of M'2, M'1, and M'0. C'' is derived from the following equations.

Once C' is determined, add the original code word with C'' forming the checksum S3:

S3 is eight bits long. The same majority rule applies. If more than four bits are 1s, M'3 is "1" and if more than four bits are 0s, M'3 is "0". The following is an example of the code in practice. Assume the message is {0101}. The resulting code word C is {01011010}. Let C2 be the corrupted bit. The code word becomes {01011110}. The orthogonal checksums Si,k are shown in Table 2.

Table 2: Example Orthogonal Checksums Si,k The individual message bit M'2, M'1, M'0 decoding is done independent from others except for M'3. In this case, a total of two stages are needed to decode the entire message. The decoding logic is relatively simple. This allows RM code to be fast and low in latency compared to equivalent cyclic code.

Taking the majority of the checksums, the message bits are M'0 = 1, M'1 = 0, and M'2 = 1. Based on this result, C'' is {01011010}. Add C'' with the original code word C' {01011110}. S3 becomes {00000100}. Hence, M'3 = 0. In summary, the original message is {0101} and the error position is C3 indicated by S3. Reed_Muller Code and Encoding Matrices. An rth order Reed_Muller code R(r;m) is the set of all binary strings (vectors) of length n = 2m associated with the Boolean polynomials p(x1; x2; : : : ; xm) of degree at most r. The 0th order Reed_Muller code R(0;m) consists of the binary strings associated with the constant polynomials 0 and 1; that is,

R(0,m) = {0; 1} = Rep(2m):

Thus, R(0;m) is just a repetition of either zeros or ones of length 2m. At the other extreme, the mth order Reed_Muller code R(m;m) consists of all binary strings of length 2m .To define the encoding matrix of R(r;m), let the first row of the encoding matrix be 1, the vector length 2m with all entries equal to 1. If r is equal to 0, then this row is the only one in the encoding matrix. If r is equal to 1, then add m rows corresponding to the vectors x1; x2; : : : ; xm to the R(0;m) encoding matrix. To form a R(r;m) encoding matrix where r is greater than 1, add (mr ) rows to the R(r-1;m) encoding matrix. These added rows consist of all the possible reduced degree r monomials that can be formed using the rows x1; x2; :::xm For example, when m = 3 we have

The rows x1x2 = 11000000, x1x3 = 10100000, and x2x3 = 10001000 are added to form

Finally, the row x1x2x3 = 10000000 is added to form

Another example of a Reed_Muller encoding matrix is

Encoding a message using Reed_Muller code R(r;m) is straightforward. Take the code we are using to be R(r;m). Its dimension I

In other words, the encoding matrix has k rows. We send messages in blocks of length k. Let m = (m1;m2; :mk) be a block, the encoded message Mc is

where Ri is a row of the encoding matrix of R(r;m).

For example, using R(1; 3) to encode m = (0110) gives

0 * (11111111) + 1*(11110000) +1*(11001100) + 0 * (10101010) = (00111100): Similarly, using R(2; 4)to encode m =(10101110010) gives (0011100100000101).

Second Order Reed-Muller Code

This reference design utilizes a second order 5th degree RM code to achieve multiple bit error correction. The message width of RM(2,5) code is 16 bits and the code word is 32 bits. Thereare five variables: X1, X2, X3, X4, X5. It can correct at most three random error bits and detect four random error bits. The generator matrix [G] is defined as:

The code word is generated similar to RM(1,3) mentioned previously. For example, code word bit 12 is generated as:

For RM(2,5) code, decoding is accomplished in three stages. The first stage consists of eight checksums for each message bit from M9 to M0. As an example, the checksums for M0 are:

Majority vote is taken to decide if the message bit is 0 or 1, similar to the previously described majority-rule method. For example, in first stage, if there are five or more equations yielding "1", then the corresponding message bit is "1". Likewise, the message bit is "0" if five or more equations yield a "0". If there are four equations yielding "1" and four equations yielding "0", it indicates a quadruple error. Hence, the original message can not be correctly decoded and the result is an unknown message bit.

Second stage decoding operates on the intermediate code word C''. It is created from the decoded message bits from the first decoding stage:

In this equation, C' is the original incoming code word, G2 is the lower portion of the generator matrix. Second-stage checksum generator creates checksums based on the partial

code word C''. There are sixteen checksums for each message bit from M14 to M10. The same majority rules apply.

Reference Design

The reference design consists of two components: the encoder and the decoder. They work independently as far as each component concerns. They operate based on the RM(2,5) code mentioned in previous section.

Encoder The encoder takes 16-bit message and encodes into 32-bit code word based on the RM(2,5) matrix multiplication. Figure 1 shows a block diagram of the encoder.

Error Diagnostics

To test the system, forced-error functions are part of the encoder. Deliberate bit errors can be injected in the code word at the output of the encoder. The FORCE_ERROR pins provide two error diagnostics modes. • Normal Operation Mode No bit error imposed on the output of the encoder.

• Bit Error Mode

Depending on the mode-type set by the FORCE_ERROR pins. Single, double, triple, and quadruple-bit error injection is supported. In bit error mode, one or more consecutive bit(s) is reversed (0 becomes 1 or 1 becomes 0) in the code word on the rising edge of the clock. The sequence moves from low order bits to high order bits. The sequence is repeated

long

the

error

mode

active.

Block Diagram for Encoder

Decoder Decoding Reed_Muller encoded messages is more complex than encoding them. The theory behind encoding and decoding is based on the distance between vectors. The distance between any two vectors is the number of places in the two vectors that have di_erent values. The distance between any two codewords in R(r;m) code is 2m - r. The basis for Reed_Muller encoding is the assumption that the closest codeword in R(r;m) to the received message is the original encoded message. Thus for e errors to be corrected in the received message, the distance between any two of the codewords in R(r;m) must be greater than 2e. The decoding method used is not very e_cient, but is straightforward to implement. It checks each row of the encoding matrix and uses majority logic to determine whether that row was used in forming the encoding message. Thus, it is possible to determine what the error-less encoded message was and what the original message was. This method of decoding is given by the following algorithm: Apply Steps 1 and 2 below, to each row of the matrix, starting from the bottom and working upwards. Step 1. Choose a row in the R(r;m) encoding matrix. Find 2m-r characteristic vectors (this process is described below) for that row, and then take the dot product of each of those rows with the encoded message.

Step 2. Take the majority of the values of the dot products and assign that value to the coefficient of the row.

Step 3. After doing Steps 1 and 2 for each row except the top row from the bottom of the matrix up, multiply each coeffcient by its corresponding row and add the resulting vectors to form My. Add this result to the received encoded message. If the resulting vector has more ones than zeros, then the top row's coefficient is 1,otherwise it is 0. Adding the top row, multiplied by its coefficient, to My gives the original encoded message. Thus, we can identify the errors. The vector formed by the sequence of coefficients starting from the top row of the encoding matrix and ending with the bottom row is the original message.

To find the characteristic vectors of any row of the matrix, take the monomial r associated with the row of the encoding matrix. Then, take E to be the set of all xi that are not in the monomial r, but are in the encoding matrix. The characteristic vectors are the vectors corresponding to the monomials in xi and ~xi, such that exactly one of xi or ~xi is in each monomial for all xi in E. For example, the last row of the encoding matrix R(2; 4) is associated with x3x4, so the characteristic vectors correspond to the following combinations of x1; x2; ~x1, and ~x2 : x1x2; x1x2; ~x1x2; ~x1~x2. These characteristic vectors have the property that the dot product is zero with all the rows in R(r;m) except therow to which the characteristic vectors correspond. 5. Example. If the original message is m = (0110) using R(1; 3), then the encoded message is Mc = (00111100). Because the distance in R(1; 3) is 23�1 = 4, this code can correct one error. Let the encoded message after the error be Me = (10111100): The characteristic vectors of the last row x3 = (10101010) are x1x2, x1_x2, _x1x2, and ~x1~x2. The vector associated with x1 is (11110000), so ~x1 = (00001111). The vector associated with x2 is (11001100), so ~x2 = (00110011). Therefore, we have x1x2 = (11000000), x1~x2 = (00110000), ~x1x2 = (00001100), and ~x1~x2 = (00000011). Taking the dot products of these vectors with Me, we get

(11000000) . (10111100) = 1; (00110000) . (10111100) = 0;

(00001100) . (10111100) = 0; (00000011) . (10111100) = 0:

We can conclude that the coefficient of x3 is 0.

Doing the same for the second to last row of the matrix, x2 = (11001100), we get the characteristic vectors x1x3, x1~x3, ~x1x3, and ~x1~x3. These vectors are (10100000), (01010000), (00001010), and (00000101), respectively. Taking the dot products of these vectors with Me, we get

(10100000) . (10111100) = 0; (01010000) . (10111100) = 1; (00001010) . (10111100) = 1; (00000101) . (10111100) = 1:

So, we can conclude that the coe_cient of x2 is 1. Doing the same for the second row of the matrix x1 = (11110000), we get

(10001000) . (10111100) = 0; (00100010) . (10111100) = 1; (01000100) . (10111100) = 1; (00010001) . (10111100) = 1: We can conclude that the coe_cient for x1 is also 1. If we add 0 * (10101010) and 1 * (11001100) and 1 * (11110000) we get My, which is equal to (00111100). Then we see that the sum of My and Me is equal to

(00111100) + (10111100) = (10000000): This message has more zeros than ones, so the coe_cient of the _rst row of the encoding matrix is zero. Thus we can put together coe_cients for the four rows of the matrix, 0,1,1, and 0, and see that the original message was (0110). We can also see that the error was in the _rst place of the error-free message Mc = (00111100).

Figure 2 shows the block diagram of the decoder.

The decoder has three decoding stages. Each stage is pipelined to maximize performance. It is possible to reduce latency (The condition of being temporarily inactive) all the way to zero by removing pipelines at the expense (sacrifice) of performance. The major components are the Orthogonal Checksum Generator (OCG) and Majority Logic Decoder (MLD).

•

First stage decodes message bit 9 to 0.

•

The second state decodes message bit 14 to 10.

•

The third stage decodes message bit 15.

With this method, each subsequent stage operates on the decoded message bits from the previous immediate stage.

Majority Logic Decoder : RM(r,m) codes can be decoded using the majority logic decoding. The basic idea of majority logic decoding is to build several checksums for each received code word element. Since each of the different checksums must all have the same value (i.e the value of the message word element weight), we can use a majority logic decoding to decipher the value of the message word element.

Once each order of the polynomial is decoded, the received word is modified accordingly by removing the corresponding codewords weighted by the decoded message contributions, up to the present stage. So for a r-th order RM code, we have to decode iteratively r+1, times before we arrive at the final received code-word. Also, the values of the message bits are calculated through this scheme; finally we can calculate the codeword by multiplying the message word (just decoded) with the generator matrix. One clue if the decoding succeeded, is to have an all-zero modified received word, at the end of r+1-stage decoding through the majority logic decoding. This technique was proposed by Irving. S. Reed, and is more general when applied to other finite geometry codes.

Check Sum Generator: A checksum is a form of redundancy check, (a redundancy check is extra data added to a message for the purposes of error detection.) a simple way to protect the integrity of data by detecting errors in data that are sent through space (telecommunications) or time (storage). It works by adding up the basic components of a message, typically the asserted bits, and storing the resulting value. Anyone can later perform the same operation on the data, compare the result to the authentic checksum and (assuming that the sums match) conclude that the message was probably not corrupted.

Stage –1: Orthogonal Checksum generator

Majority Logic Coding_S1:

Block Diagram Stage -1

STAGE-2 1. Code Generator:

2.Orthogonal checksum generator :

Block Diagram of Orthogonal Checksum Generator

Waveform of Orthogonal Check Sum Generator 3. MLD

Block Diagram for MLD

Waveform for MLD

STAGE 3:

1. Orthogonal Check Sum Generator

Block Diagram for Orthogonal Check Sum generator

Waveform of orthogonal checksum generator

2.MLD

Block Diagram for MLD

Waveform of MLD

Design Considerations Concatenation

Two similar codes can be cascaded to expand the message width. For a 32-bit wide message, two RM(2,5) codes are concatenated making C = {X, Y}, where X and Y are independent RM(2,5) code. Instead of combining two code words side by side {X0,...,X31,Y0,...,Y31}, it is recommended to interleave the code word such that the combined code word is {X0, Y0, X1, Y1,...X31,Y31}. This organization can enhance the correcting capability of certain consecutive bit errors. A concatenated 32-bit reference design is also available. Use Models For single-data rate (SDR) memory, the external memory interface width should be the same as the code word width. For double-data rate (DDR) memory applications, the external memory interface width can either be the same as the code word width or the message width (half the code word width). In the later case, half the code word can be accessed with both rising and falling edges at the memory. In both cases, the entire code word is accessed in one cycle on theuser side.

FPGA :

FPGA PROTOTYPING Design Specifications :

Chip design commences with design Specifications. Like the design should have these many no. i/p’s , o/p’s, function, propagation delay, area, power etc.. These ideas are then translated into architectural and electrical specifications. The architectural specifications define the functionality and partitioning of the topmodule into several manageable blocks, while the electrical specifications define the relationship between the blocks in terms of timing information.

RTL CODING :

The next phase involves the implementation of these specifications. In the past this was achieved by manually drawing the schematics, utilizing the components found in a cell library(logic cells). This process was time consuming and was impractical for design reuse. To overcome this problem, hardware description languages (HDL) were developed. As the name suggests, the functionality of the design is coded using the HDL. There are two main HDLs in use today, Verilog and VHDL.

Initially developed HDL is VHDL (Very High Speed IC HDL) * Harder to learn * As design gets complex – designing using VHDL gets complexed .

So, to replace VHDL, Language developers developed another HDL called Verilog which is similar to Programming Language ‘ C ‘.Now, Defence uses VHDL for security purpose and Verilog is used for Commercial purpose.

There are four levels of abstraction that may be used to represent the design: Data Flow level, Behavioral, sturcural, RTL. RTL is a combination of Data Level and Behavioural level. This type of coding is used to describe the functionality of the design and is synthesizable to form a structural netlist. This netlist comprises of the components from a target library and their respective connections; very similar to the schematic based approach.

The design is coded using the RTL style, in either Verilog or VHDL, or both.It can also be partitioned if necessary, into a number of smaller blocks to form a hierarchy, with a top-level block connecting all lower level blocks. Note : Use proper coding techniques eg : like incomplete if and else statement infer LATCH

RTL Simulation :

The next step is to check the functionality of the design by simulating the RTL code. The design is simulated by forcing all possible input values covering your design. So, that seems to be time consuming. Then designers started writing the stimuli for your design file which is called as TESTBENCH for simulation. This test bench is normally written in behavior HDL while the actual design is coded in RTL. It is important to note that the coverage of the design is totally dependent on the number of tests performed and the quality of the test bench. This is the reason why a sound test bench is extremely critical to the design. •

Design File – Synthesizable HDL

•

Test-Bench File – Non-Synthesizable HDL

Logic Synthesis : The process of converting RTL code to the gate-level netlist. This process is termed as synthesis. Synthesizing a design is an iterative process and begins with defining timing constraints for each block of the design. These timing constraints define the relationship of each signal with respect to the clock input for a particular block. In addition to the constraints, a file defining the synthesis environmentis also needed. The environment file specifies the technology cell libraries and other relevant information that DC uses during synthesis. The RTL code of the design and using the timing constraints, synthesizes the code to structural level, thereby producing a mapped gate level netlist. Once you generate a netlist, you can implement the design •

Implementation includes many phases –

Translate : Merge multiple design files into a single netlist.

–

Map: Group logical symbols from the netlist (gates) into physical components (slices and IOBs)

–

Place & Route : Place components onto the chip, connect the components, and extract timing data into reports.

•

Once a design is implemented, you must create a file that the FPGA can understand –

This file is called a bitstream: a BIT file (.bit extension)

•

The BIT file can be downloaded directly into the FPGA, or the BIT file can be converted into a PROM file, which stores the programming information

Floorplanning is the process of choosing the best grouping and connectivity of logic in a design. It is also the process of manually placing blocks of logic in an FPGA where the goal is to increase density, routability, or performance. Why floor plan : Floorplanning is an optional methodology that you can use to improve the performance of your automatically placed and routed design. Floorplanning is particularly useful on structured designs and data path logic. The Floorplanner helps you to determine where to place logic in the floorplan for optimal results. You can place data paths at the desired location on the die. - Map : Analyze TIming

Need for timing analysis •

To check whether design is working at the specified frequency or not

•

To detect the bug in the early phase of design

•

To find the Redundant Logic

•

To reduce the NRE cost

- Place & Route •

Analyze timing

•

Analyze power

Transistor Used in Chip are CMOS because of its Two important characteristics of CMOS devices are high noise immunity and low static power consumption. Significant power is only drawn when the transistors in the CMOS device are switching between on and off states. Consequently, CMOS devices do not produce as much waste heat as other forms of logic, for example transistor-transistor logic (TTL). CMOS also allows a high density of logic functions on a chip.

Field Programmable Gate Arrays (FPGAs)

Field Programmable Gate Arrays are called this because rather thanhaving a structure similar to a PAL or other programmable device, they are structured very much like a gate array ASIC. This makes FPGAs very nice for use in prototyping ASICs, or in places where and ASIC will eventually be used. For example, an FPGA maybe used in a design that need to get to market quickly regardless of cost. Later an ASIC can be used in place of the FPGA when the production volume increases, in order to reduce cost.

FPGA Architectures

Each FPGA vendor has its own FPGA architecture, but in general terms they are all a variation of that shown in Figure 8. The architecture consists of configurable logic blocks, configurable I/O blocks, and programmable interconnect. Also, there will be clock circuitry for driving the clock signals to each logic block, and additional logic resources such as ALUs, memory, and decoders may be available. The two basic types of programmable elements for an FPGA are Static RAM and anti-fuses.

Configurable Logic Blocks Configurable Logic Blocks contain the logic for the FPGA. In a large grain architecture, these CLBs will contain enough logic to create a small state machine. In a fine grain architecture, more like a true gate array ASIC, the CLB will contain only very basic logic. The diagram in Figure 9 would be considered a large grain block. It contains RAM for creating arbitrary combinatorial logic

functions. It also contains flip-flops for clocked storage elements, and multiplexers in order to route the logic within the block and to and from external resources. The muxes also allow polarity selection and reset and clear input selection.

FPGA Configurable Logic Block

Configurable I/O Blocks

A Configurable I/O Block, shown in Figure 10, is used to bring signals onto the chip and send them back off again. It consists of an input buffer and an output buffer with three state and open collector output controls. Typically there are pull up resistors on the outputs and sometimes pull down resistors.The polarity of the output can usually be programmed for active high or active low output and often the slew rate of the output can be programmed for fast or slow rise and fall times. In addition, there is often a flip-flop on outputs so that clocked signals can be output directly to the pins without encountering significant delay. It is done for

inputs so that there is not much delay on a signal before reaching a flip-flop which would increase the device hold time requirement.

FPGA Configurable I/O Block

Programmable Interconnect The interconnect of an FPGA is very different than that of a CPLD, but is rather similar to that of a gate array ASIC. In Figure 11, a hierarchy of interconnect resources can be seen. There are long lines which can be used to connect critical CLBs that are physically far from each other on the chip without inducing much delay. They can also be used as buses within the chip. There are also short lines which are used to connect individual CLBs which are located physically close to each other. There is often one or several switch matrices, like that in a CPLD, to connect these long and short lines together in specific ways. Programmable switches inside the chip allow the connection of CLBs to interconnect lines and interconnect lines to each other and to the switch matrix. Threestate buffers are used to connect many CLBs to a long line, creating a bus. Special long lines, called global clock lines, are specially designed for low impedance and thus fast propagation times. These are connected to the clock buffers and to each clocked element in each CLB. This is how the clocks are distributed throughout the FPGA.

FPGA Programmable Interconnect

Clock Circuitry

Special I/O blocks with special high drive clock buffers, known as clock drivers, are distributed around the chip. These buffers are connect to clock input pads and drive the clock signals onto the global clock lines described above. These clock lines are designed for low skew times and fast propagation times. As we will discuss later, synchronous design is a must with FPGAs, since absolute skew and delay cannot be guaranteed. Only when using clock signals from clock buffers can the relative delays and skew times be guaranteed.

Small vs. Large Granularity Small grain FPGAs resemble ASIC gate arrays in that the CLBs contain only small, very basic elements such as NAND gates, NOR gates, etc. The philosophy is that small elements can be connected to make larger functions without wasting too much logic. In a large grain FPGA, where the CLB can contain two or more flip-flops, a design which does not need many flip-flops will leave many of them unused. Unfortunately, small grain architectures require much more routing resources, which take up space and insert a large amount of delay which can more than compensate for the better utilization.

SRAM vs. Anti-fuse Programming There are two competing methods of programming FPGAs. The first, SRAM programming, involves small Static RAM bits for each programming element. Writing the bit with a zero turns off a switch, while writing with a one turns on a switch. The other method involves anti-fuses which consist of microscopic structures which, unlike a regular fuse, normally makes no connection. A certain amount of current during programming of the device causes the two sides of the anti-fuse to connect. The advantages of SRAM based FPGAs is that they use a standard fabrication process that chip fabrication plants are familiar with and are always optimizing for better performance. Since the SRAMs are reprogrammable, the FPGAs can be reprogrammed any number of times, even while they are in the system, just like writing to a normal SRAM. The disadvantages are that they are volatile, which means a power glitch could potentially change it. Also, SRAMbased devices have large routing delays

The advantages of Anti-fuse based FPGAs are that they are non-volatile and the delays due to routing are very small, so they tend to be faster. The disadvantages are that they require a complex fabrication process, they require an external programmer to program them, and once they are programmed, they cannot be changed.

Software Programming Encoder program

//----------------------------------------------------------------------------// encoder - Module //----------------------------------------------------------------------------//************************************************************************** //----------------------------------------------------------------------------// Filename:

encoder.v

//----------------------------------------------------------------------------// Description: //

Top level design for 16-bit Multiple Error Detection and Correction.

//---------------------------------------------------------------------------//----------------------------------------------------------------------------// `timescale 1ns/100ps

module encoder(clk, reset, force_error, data,code_out); input clk; input reset; input [2:0]force_error; input [15:0] data; output [31:0] code_out;

reg[31:0] single_error; reg[31:0] double_error;

reg[31:0] triple_error; reg[31:0] quad_error; reg[31:0] pent_error; reg [31:0] code_out; wire [31:0] enc_in;

assign enc_in[0] = data[15] ^ data[14] ^ data[13] ^ data[12] ^ data[11] ^ data[10] ^ data[9] ^ data[8] ^ data[7] ^ data[6] ^ data[5] ^ data[4] ^ data[3] ^ data[2] ^ data[1] ^ data[0]; assign enc_in[1] = data[15] ^ data[13] ^ data[12] ^ data[11] ^ data[10] ^ data[5] ^ data[4] ^ data[3] ^ data[2] ^ data[1] ^ data[0]; assign enc_in[2] = data[15] ^ data[14] ^ data[12] ^ data[11] ^ data[10] ^ data[8] ^ data[7] ^ data[6] ^ data[2] ^ data[1] ^ data[0]; assign enc_in[3] = data[15] ^ data[12] ^ data[11] ^ data[10] ^ data[2] ^ data[1] ^ data[0]; assign enc_in[4] = data[15] ^ data[14] ^ data[13] ^ data[11] ^ data[10] ^ data[9] ^ data[7] ^ data[6] ^ data[4] ^ data[3] ^ data[0]; assign enc_in[5] = data[15] ^ data[13] ^ data[11] ^ data[10] ^ data[4] ^ data[3] ^ data[0]; assign enc_in[6] = data[15] ^ data[14] ^ data[11] ^ data[10] ^ data[7] ^ data[6] ^ data[0]; assign enc_in[7] = data[15] ^ data[11] ^ data[10] ^ data[0]; assign enc_in[8] = data[15] ^ data[14] ^ data[13] ^ data[12]^ data[10] ^ data[9] ^ data[8] ^ data[6] ^ data[5] ^ data[3] ^ data[1]; assign enc_in[9] = data[15] ^ data[13] ^ data[12] ^ data[10] ^ data[5] ^ data[3] ^ data[1]; assign enc_in[10] = data[15] ^ data[14] ^ data[12] ^ data[10] ^ data[8] ^ data[6] ^ data[1]; assign enc_in[11] = data[15] ^ data[12] ^ data[10] ^ data[1]; assign enc_in[12] = data[15] ^ data[14] ^ data[13] ^ data[10] ^ data[9] ^ data[6] ^ data[3]; assign enc_in[13] = data[15] ^ data[13] ^ data[10] ^ data[3]; assign enc_in[14] = data[15] ^ data[14] ^ data[10] ^ data[6]; assign enc_in[15] = data[15] ^ data[10]; assign enc_in[16] = data[15] ^ data[14] ^ data[13] ^ data[12] ^ data[11] ^ data[9] ^ data[8] ^ data[7] ^ data[5] ^ data[4] ^ data[2]; assign enc_in[17] = data[15] ^ data[13] ^ data[12] ^ data[11] ^ data[5] ^ data[4] ^ data[2]; assign enc_in[18] = data[15] ^ data[14] ^ data[12] ^ data[11] ^ data[8] ^ data[7] ^ data[2];

assign enc_in[19] = data[15] ^ data[12] ^ data[11] ^ data[2]; assign enc_in[20] = data[15] ^ data[14] ^ data[13] ^ data[11] ^ data[9] ^ data[7] ^ data[4]; assign enc_in[21] = data[15] ^ data[13] ^ data[11] ^ data[4]; assign enc_in[22] = data[15] ^ data[14] ^ data[11] ^ data[7]; assign enc_in[23] = data[15] ^ data[11]; assign enc_in[24] = data[15] ^ data[14] ^ data[13] ^ data[12] ^ data[9] ^ data[8] ^ data[5]; assign enc_in[25] = data[15] ^ data[13] ^ data[12] ^ data[5]; assign enc_in[26] = data[15] ^ data[14] ^ data[12] ^ data[8]; assign enc_in[27] = data[15] ^ data[12]; assign enc_in[28] = data[15] ^ data[14] ^ data[13] ^ data[9]; assign enc_in[29] = data[15] ^ data[13]; assign enc_in[30] = data[15] ^ data[14]; assign enc_in[31] = data[15];

always @(posedge clk or posedge reset) begin : single_error_gen if (reset == 1'b1) begin single_error <= 32'h00000001 ; // '1' represents LSB and 0 is MSB end else begin single_error[0] <= single_error[31] ; single_error[31:1] <= single_error[30:0] ; end end

always @(posedge clk or posedge reset) begin : double_error_gen if (reset == 1'b1)

begin double_error <= 32'h00000003 ; // '3' represents LSB nd 0 is MSB end else begin double_error[0] <= double_error[31] ; double_error[31:1] <= double_error[30:0] ; end end

always @(posedge clk or posedge reset) begin : triple_error_gen if (reset == 1'b1) begin triple_error <= 32'h00000007 ; // '7' represents LSB and 0 is MSB end else begin triple_error[0] <= triple_error[31] ; triple_error[31:1] <= triple_error[30:0] ; end end

always @(posedge clk or posedge reset) begin : quad_error_gen if (reset == 1'b1) begin quad_error <= 32'h0000000f ; end else

begin quad_error[0] <= quad_error[31] ; quad_error[31:1] <= quad_error[30:0] ; end end

always @(posedge clk or posedge reset) begin : pent_error_gen if (reset == 1'b1) begin pent_error <= 32'h0000001f ; end else begin pent_error[0] <= pent_error[31] ; pent_error[31:1] <= pent_error[30:0] ; end end always @(enc_in or force_error or single_error or double_error or triple_error or quad_error or pent_error)

case (force_error) 3'b000 :

code_out <= enc_in ^ 32'h00000000 ; // 0 error feedthrough

3'b001 :

code_out <= enc_in ^ single_error[31:0] ;

3'b010 :

code_out <= enc_in ^ double_error[31:0] ; // 2-bit error walk-thru

3'b011 :

code_out <= enc_in ^ triple_error[31:0] ;

3'b100 :

code_out <= enc_in ^ quad_error[31:0] ;

3'b101 :

code_out <= enc_in ^ pent_error[31:0] ;

default : code_out <= enc_in ; endcase

// 1 bit error walk-thru

endmodule

// The encoder implements the following RM[2,5] matrix

// 1 1

1 1 1

1 1

0 0 0

1 1 1

0 0 0

1 1 1

0 0 0

1 1 1

0 0 0

1 1 1

0 0

1 1

0 0

1 1

0 0 0

1 1 1

0 0 0

1 1 1

0 0

1 1

0 1

0 1 0

1 0 1

0 1

1 0

0 1 1

0 0 1

1 0

0 1

0 0 1

0 1 1

0 1

1 1

0 0 0

1 1 1

0 0 0

1 1 1

0 0

0 1

0 0 0

0 1 0

0 0 0

0 1 0

0 0 0

1 0 1

0 0 0

1 0 1

0 0

0 1

0 0

1 0

0 0 0

0 1 1

0 0 0

0 1 1

0 0 0

0 0 1

0 0 0

0 0 1

0 0

1 0

0 0

0 1

0 0 0

0 0 1

0 0 0

0 0 1

0 0 0

0 1 1

0 0 0

0 1 1

0 0

0 1

0 0

0 1

0 0 0

0 1 0

0 0 0

1 0 1

0 0

0 1

//X1

//X2

//X3

//X4

//X5

//X1X2

//X1X3

//X1X4

//X1X5

//X2X3

//X2X4 1 0

0 0 0

0 1 1

0 0 0

0 0 1

0 0

1 0

0 1

0 0 0

0 0 1

0 0 0

0 1 1

0 0

0 1

0 0

0 1 0

0 0 1

0 0

0 1

0 0 0

0 0 1

0 1

0 0

0 0 1

0 0

//X2X5

//X3X4

//X3X5

//X4X5

Code for Clock/Reset

// `timescale 1ns/100ps module clkrst(clkin,reset,clk2x, locked); input clkin; input reset; output clk2x; output locked;

wire clk0, clkfb, clk2x_dcm, clk;

BUFG buf1 (.I ( clk0 ), .O ( clkfb )); BUFG buf2 (.I ( clk2x_dcm ), .O ( clk2x ));

DCM DCM_inst ( .CLK0(clk0),

// 0 degree DCM CLK ouptput

.CLK180(), // 180 degree DCM CLK output

.CLK270(), // 270 degree DCM CLK output .CLK2X(clk2x_dcm), // 2X DCM CLK output .CLK2X180(), // 2X, 180 degree DCM CLK out .CLK90(), // 90 degree DCM CLK output .CLKDV(), // Divided DCM CLK out (CLKDV_DIVIDE) .CLKFX(), // DCM CLK synthesis out (M/D) .CLKFX180(), // 180 degree CLK synthesis out .LOCKED(locked), // DCM LOCK status output .PSDONE(), // Dynamic phase adjust done output .STATUS(), // 8-bit DCM status bits output .CLKFB(clkfb), // DCM clock feedback .CLKIN(clkin), // Clock input (from IBUFG, BUFG or DCM) .DSSEN(), .PSCLK(), // Dynamic phase adjust clock input .PSEN(),

// Dynamic phase adjust enable input

.PSINCDEC(), // Dynamic phase adjust increment/decrement .RST(reset)

// DCM asynchronous reset input

);

Endmodule

Code for Orthogonal Checksum Generator 1

//-----------------------------------------------------------------------------

// ocs_gen_s1 - Module //----------------------------------------------------------------------------//----------------------------------------------------------------------------// Filename:

ocs_gen_s1.v

//----------------------------------------------------------------------------// Description: //

Top level design for 16-bit Multiple Error Detection and Correction.

// //----------------------------------------------------------------------------//-----------------------------------------------------------------------------

// Orthogonal checksum generator 1

// `timescale 1ns/100ps

module ocs_gen_s1(code_in,x9_s1,x8_s1,x7_s1,x6_s1,x5_s1,x4_s1,x3_s1,x2_s1, x1_s1,x0_s1); input [31:0] code_in; output [7:0] x9_s1; output [7:0] x8_s1; output [7:0] x7_s1; output [7:0] x6_s1; output [7:0] x5_s1; output [7:0] x4_s1; output [7:0] x3_s1; output [7:0] x2_s1; output [7:0] x1_s1; output [7:0] x0_s1;

assign x9_s1[7] = code_in[0] ^ code_in[1] ^ code_in[2] ^ code_in[3];

assign x9_s1[6] = code_in[4] ^ code_in[5] ^ code_in[6] ^ code_in[7]; assign x9_s1[5] = code_in[8] ^ code_in[9] ^ code_in[10] ^ code_in[11]; assign x9_s1[4] = code_in[12] ^ code_in[13] ^ code_in[14] ^ code_in[15]; assign x9_s1[3] = code_in[16] ^ code_in[17] ^ code_in[18] ^ code_in[19]; assign x9_s1[2] = code_in[20] ^ code_in[21] ^ code_in[22] ^ code_in[23]; assign x9_s1[1] = code_in[24] ^ code_in[25] ^ code_in[26] ^ code_in[27]; assign x9_s1[0] = code_in[28] ^ code_in[29] ^ code_in[30] ^ code_in[31];

assign x8_s1[7] = code_in[0] ^ code_in[1] ^ code_in[4] ^ code_in[5]; assign x8_s1[6] = code_in[2] ^ code_in[3] ^ code_in[6] ^ code_in[7]; assign x8_s1[5] = code_in[8] ^ code_in[9] ^ code_in[12] ^ code_in[13]; assign x8_s1[4] = code_in[10] ^ code_in[11] ^ code_in[14] ^ code_in[15]; assign x8_s1[3] = code_in[16] ^ code_in[17] ^ code_in[20] ^ code_in[21]; assign x8_s1[2] = code_in[18] ^ code_in[19] ^ code_in[22] ^ code_in[23]; assign x8_s1[1] = code_in[24] ^ code_in[25] ^ code_in[28] ^ code_in[29]; assign x8_s1[0] = code_in[26] ^ code_in[27] ^ code_in[30] ^ code_in[31];

assign x7_s1[7] = code_in[9] ^ code_in[8] ^ code_in[1] ^ code_in[0]; assign x7_s1[6] = code_in[11] ^ code_in[10] ^ code_in[3] ^ code_in[2]; assign x7_s1[5] = code_in[13] ^ code_in[12] ^ code_in[5] ^ code_in[4]; assign x7_s1[4] = code_in[25] ^ code_in[24] ^ code_in[17] ^ code_in[16]; assign x7_s1[3] = code_in[15] ^ code_in[14] ^ code_in[7] ^ code_in[6]; assign x7_s1[2] = code_in[27] ^ code_in[26] ^ code_in[19] ^ code_in[18]; assign x7_s1[1] = code_in[29] ^ code_in[28] ^ code_in[21] ^ code_in[20]; assign x7_s1[0] = code_in[31] ^ code_in[30] ^ code_in[23] ^ code_in[22];

assign x6_s1[7] = code_in[17] ^ code_in[16] ^ code_in[1] ^ code_in[0]; assign x6_s1[6] = code_in[19] ^ code_in[18] ^ code_in[3] ^ code_in[2]; assign x6_s1[5] = code_in[21] ^ code_in[20] ^ code_in[5] ^ code_in[4]; assign x6_s1[4] = code_in[25] ^ code_in[24] ^ code_in[9] ^ code_in[8];

assign x6_s1[3] = code_in[23] ^ code_in[22] ^ code_in[7] ^ code_in[6]; assign x6_s1[2] = code_in[27] ^ code_in[26] ^ code_in[11] ^ code_in[10]; assign x6_s1[1] = code_in[29] ^ code_in[28] ^ code_in[13] ^ code_in[12]; assign x6_s1[0] = code_in[31] ^ code_in[30] ^ code_in[15] ^ code_in[14];

assign x5_s1[7] = code_in[6] ^ code_in[4]^ code_in[2] ^ code_in[0]; assign x5_s1[6] = code_in[7] ^ code_in[5]^ code_in[3] ^ code_in[1]; assign x5_s1[5] = code_in[14] ^ code_in[12]^ code_in[10] ^ code_in[8]; assign x5_s1[4] = code_in[22] ^ code_in[20]^ code_in[18] ^ code_in[16]; assign x5_s1[3] = code_in[15] ^ code_in[13]^ code_in[11] ^ code_in[9]; assign x5_s1[2] = code_in[23] ^ code_in[21]^ code_in[19] ^ code_in[17]; assign x5_s1[1] = code_in[30] ^ code_in[28]^ code_in[26] ^ code_in[24]; assign x5_s1[0] = code_in[31] ^ code_in[29]^ code_in[27] ^ code_in[25];

assign x4_s1[7] = code_in[10] ^ code_in[8]^ code_in[2]^ code_in[0]; assign x4_s1[6] = code_in[11] ^ code_in[9]^ code_in[3]^ code_in[1]; assign x4_s1[5] = code_in[14] ^ code_in[12]^ code_in[6]^ code_in[4]; assign x4_s1[4] = code_in[26] ^ code_in[24]^ code_in[18]^ code_in[16]; assign x4_s1[3] = code_in[15] ^ code_in[13]^ code_in[7]^ code_in[5]; assign x4_s1[2] = code_in[27] ^ code_in[25]^ code_in[19]^ code_in[17]; assign x4_s1[1] = code_in[30] ^ code_in[28]^ code_in[22]^ code_in[20]; assign x4_s1[0] = code_in[31] ^ code_in[29]^ code_in[23]^ code_in[21];

assign x3_s1[7] = code_in[18] ^ code_in[16] ^ code_in[2]^ code_in[0]; assign x3_s1[6] = code_in[19] ^ code_in[17] ^ code_in[3]^ code_in[1]; assign x3_s1[5] = code_in[22] ^ code_in[20] ^ code_in[6]^ code_in[4]; assign x3_s1[4] = code_in[26] ^ code_in[24] ^ code_in[10]^ code_in[8]; assign x3_s1[3] = code_in[23] ^ code_in[21] ^ code_in[7]^ code_in[5]; assign x3_s1[2] = code_in[27] ^ code_in[25] ^ code_in[11]^ code_in[9]; assign x3_s1[1] = code_in[30] ^ code_in[28] ^ code_in[14]^ code_in[12];

assign x3_s1[0] = code_in[31] ^ code_in[29] ^ code_in[15]^ code_in[13];

assign x2_s1[7] = code_in[12]^ code_in[8]^ code_in[4]^ code_in[0]; assign x2_s1[6] = code_in[13]^ code_in[9]^ code_in[5]^ code_in[1]; assign x2_s1[5] = code_in[14]^ code_in[10]^ code_in[6]^ code_in[2]; assign x2_s1[4] = code_in[28]^ code_in[24]^ code_in[20]^ code_in[16]; assign x2_s1[3] = code_in[15]^ code_in[11]^ code_in[7]^ code_in[3]; assign x2_s1[2] = code_in[29]^ code_in[25]^ code_in[21]^ code_in[17]; assign x2_s1[1] = code_in[30]^ code_in[26]^ code_in[22]^ code_in[18]; assign x2_s1[0] = code_in[31]^ code_in[27]^ code_in[23]^ code_in[19];

assign x1_s1[7] = code_in[20]^ code_in[16]^ code_in[4]^ code_in[0]; assign x1_s1[6] = code_in[21]^ code_in[17]^ code_in[5]^ code_in[1]; assign x1_s1[5] = code_in[22]^ code_in[18]^ code_in[6]^ code_in[2]; assign x1_s1[4] = code_in[28]^ code_in[24]^ code_in[12]^ code_in[8]; assign x1_s1[3] = code_in[23]^ code_in[19]^ code_in[7]^ code_in[3]; assign x1_s1[2] = code_in[29]^ code_in[25]^ code_in[13]^ code_in[9]; assign x1_s1[1] = code_in[30]^ code_in[26]^ code_in[14]^ code_in[10]; assign x1_s1[0] = code_in[31]^ code_in[27]^ code_in[15]^ code_in[11];

assign x0_s1[7] = code_in[24]^ code_in[16]^ code_in[8]^ code_in[0]; assign x0_s1[6] = code_in[25]^ code_in[17]^ code_in[9]^ code_in[1]; assign x0_s1[5] = code_in[26]^ code_in[18]^ code_in[10]^ code_in[2]; assign x0_s1[4] = code_in[28]^ code_in[20]^ code_in[12]^ code_in[4]; assign x0_s1[3] = code_in[27]^ code_in[19]^ code_in[11]^ code_in[3]; assign x0_s1[2] = code_in[29]^ code_in[21]^ code_in[13]^ code_in[5]; assign x0_s1[1] = code_in[30]^ code_in[22]^ code_in[14]^ code_in[6]; assign x0_s1[0] = code_in[31]^ code_in[23]^ code_in[15]^ code_in[7]; endmodule

Code for Majority Logic Detector 1

//----------------------------------------------------------------------------// MLD_s1 - Module //----------------------------------------------------------------------------//************************************************************************** // //----------------------------------------------------------------------------// Filename:

MLD_s1.v

//----------------------------------------------------------------------------// Description: //

Top level design for 16-bit Multiple Error Detection and Correction.

//----------------------------------------------------------------------------//`timescale 100ns/1ns module MLD_s1(clk, x9_s1,x8_s1,x7_s1,x6_s1,x5_s1,x4_s1,x3_s1,x2_s1,x1_s1,x0_s1,x, error); input clk; input reset; input [7:0] x9_s1; input [7:0] x8_s1; input [7:0] x7_s1; input [7:0] x6_s1; input [7:0] x5_s1; input [7:0] x4_s1; input [7:0] x3_s1;

reset,

input [7:0] x2_s1; input [7:0] x1_s1; input [7:0] x0_s1; output [9:0] x; output [1:0] error;

wire [7:0] xp [9:0]; // wire [9:0] error_p; wire [9:0] y; wire [9:0] x; reg [1:0] error; wire [3:0] syndrome;

always @(posedge clk or posedge reset) begin if (reset) begin error <= 2'b0; end else begin case (syndrome) 4'b0000 : error <= 2'b00; // inputs are all zeros - no error 4'b1000 : error <= 2'b00; // inputs are all ones - no error 4'b0001 : error <= 2'b01; 4'b0010 : error <= 2'b01; 4'b0011 : error <= 2'b01; 4'b0101 : error <= 2'b01; 4'b0110 : error <= 2'b01; 4'b0111 : error <= 2'b01;

4'b0100 : error <= 2'b10; // four ones/zeros quad error default : error <= 2'b11; // invalid errors endcase end end

assign syndrome = x0_s1[7] + x0_s1[6] + x0_s1[5] + x0_s1[4] + x0_s1[3] + x0_s1[2] + x0_s1[1] + x0_s1[0]; assign x = y; assign xp[9] = x9_s1; // 8-bit value is passed to 8-bit port assign xp[8] = x8_s1; assign xp[7] = x7_s1; assign xp[6] = x6_s1; assign xp[5] = x5_s1; assign xp[4] = x4_s1; assign xp[3] = x3_s1; assign xp[2] = x2_s1; assign xp[1] = x1_s1; assign xp[0] = x0_s1;

// replicate(to duplicate) MLD for each bit using logic implementation

genvar i; generate

for (i=0; i < 10; i=i+1) begin: u1_MLD MLD_adder_s1 inst (

.datain(xp[i]), .dataout(y[i]) ); end

endgenerate

endmodule

Code for Majority Logic Detector Adder

//----------------------------------------------------------------------------// MLD_adder_s1 - Module //----------------------------------------------------------------------------//************************************************************************** //----------------------------------------------------------------------------// Filename:

MLD_adder_s1.v

//----------------------------------------------------------------------------// Description: //

Top level design for 16-bit Multiple Error Detection and Correction.

// //-----------------------------------------------------------------------------

//`timescale 1ns / 100ps //`timescale 100ps / 1ps

module MLD_adder_s1(datain,dataout);

input [7:0] datain; output dataout;

wire [3:0] sum;

assign sum = datain[7] + datain[6] datain[1] + datain[0];

+ datain[5] + datain[4] + datain[3] + datain[2]

assign dataout = sum[2] ^ sum[3];

//xor to reduce logic level

endmodule

Code for Code generator 2

//----------------------------------------------------------------------------// code_gen_s2 - Module //----------------------------------------------------------------------------//************************************************************************** //

// //************************************************************************** //----------------------------------------------------------------------------// Filename:

code_gen_s2.v

//----------------------------------------------------------------------------// Description: //

Top level design for 16-bit Multiple Error Detection and Correction.

// //----------------------------------------------------------------------------//

// //-----------------------------------------------------------------------------

//`timescale 1ns/100ps

module code_gen_s2(data,code_in, code_out); input [9:0] data; input [31:0] code_in; output [31:0] code_out;

assign code_out[0] = code_in[0] ^ data[9] ^ data[8] ^ data[7] ^ data[6] ^ data[5] ^ data[4] ^ data[3] ^ data[2] ^ data[1] ^ data[0]; assign code_out[1] = code_in[1] ^ data[5] ^ data[4] ^ data[3] ^ data[2] ^ data[1] ^ data[0]; assign code_out[2] = code_in[2] ^ data[8] ^ data[7] ^ data[6] ^ data[2] ^ data[1] ^ data[0]; assign code_out[3] = code_in[3] ^ data[2] ^ data[1] ^ data[0]; assign code_out[4] = code_in[4] ^ data[9] ^ data[7] ^ data[6] ^ data[4] ^ data[3] ^ data[0]; assign code_out[5] = code_in[5] ^ data[4] ^ data[3] ^ data[0]; assign code_out[6] = code_in[6] ^ data[7] ^ data[6] ^ data[0]; assign code_out[7] = code_in[7] ^ data[0]; assign code_out[8] = code_in[8] ^ data[9] ^ data[8] ^ data[6] ^ data[5] ^ data[3] ^ data[1]; assign code_out[9] = code_in[9] ^ data[5] ^ data[3] ^ data[1]; assign code_out[10] = code_in[10] ^ data[8] ^ data[6] ^ data[1]; assign code_out[11] = code_in[11] ^ data[1]; assign code_out[12] = code_in[12] ^ data[9] ^ data[6] ^ data[3]; assign code_out[13] = code_in[13] ^ data[3]; assign code_out[14] = code_in[14] ^ data[6]; assign code_out[15] = code_in[15] ; assign code_out[16] = code_in[16] ^ data[9] ^ data[8] ^ data[7] ^ data[5] ^ data[4] ^ data[2]; assign code_out[17] = code_in[17] ^ data[5] ^ data[4] ^ data[2]; assign code_out[18] = code_in[18] ^ data[8] ^ data[7] ^ data[2];

assign code_out[19] = code_in[19] ^ data[2]; assign code_out[20] = code_in[20] ^ data[9] ^ data[7] ^ data[4]; assign code_out[21] = code_in[21] ^ data[4]; assign code_out[22] = code_in[22] ^ data[7]; assign code_out[23] = code_in[23] ; assign code_out[24] = code_in[24] ^ data[9] ^ data[8] ^ data[5]; assign code_out[25] = code_in[25] ^ data[5]; assign code_out[26] = code_in[26] ^ data[8]; assign code_out[27] = code_in[27] ; assign code_out[28] = code_in[28] ^ data[9]; assign code_out[29] = code_in[29] ; assign code_out[30] = code_in[30] ; assign code_out[31] = code_in[31] ; endmodule Code for Orthogonal Check sum generator 2

//----------------------------------------------------------------------------// ocs_gen_s2 - Module //----------------------------------------------------------------------------//************************************************************************** // //************************************************************************** //----------------------------------------------------------------------------// Filename:

ocs_gen_s2.v

//----------------------------------------------------------------------------// Description: // //

Top level design for 16-bit Multiple Error Detection and Correction. Further details can be found in XAPP715

//-----------------------------------------------------------------------------

//`timescale 1ns/100ps

module ocs_gen_s2(code_in,x14_s2,x13_s2,x12_s2,x11_s2,x10_s2); input [31:0] code_in; output [15:0] x14_s2; output [15:0] x13_s2; output [15:0] x12_s2; output [15:0] x11_s2; output [15:0] x10_s2;

assign x14_s2[15] = code_in[1]^ code_in[0]; assign x14_s2[14] = code_in[17]^ code_in[16]; assign x14_s2[13] = code_in[9]^ code_in[8]; assign x14_s2[12] = code_in[25]^ code_in[24]; assign x14_s2[11] = code_in[5]^ code_in[4]; assign x14_s2[10] = code_in[21]^ code_in[20]; assign x14_s2[9] = code_in[13]^ code_in[12]; assign x14_s2[8] = code_in[29]^ code_in[28]; assign x14_s2[7] = code_in[3]^ code_in[2]; assign x14_s2[6] = code_in[19]^ code_in[18]; assign x14_s2[5] = code_in[11]^ code_in[10]; assign x14_s2[4] = code_in[27]^ code_in[26]; assign x14_s2[3] = code_in[7]^ code_in[6]; assign x14_s2[2] = code_in[23]^ code_in[22]; assign x14_s2[1] = code_in[15]^ code_in[14]; assign x14_s2[0] = code_in[31]^ code_in[30];

assign x13_s2[15] = code_in[2]^ code_in[0];

assign x13_s2[14] = code_in[18]^ code_in[16]; assign x13_s2[13] = code_in[10]^ code_in[8]; assign x13_s2[12] = code_in[26]^ code_in[24]; assign x13_s2[11] = code_in[6]^ code_in[4]; assign x13_s2[10] = code_in[22]^ code_in[20]; assign x13_s2[9] = code_in[14]^ code_in[12]; assign x13_s2[8] = code_in[30]^ code_in[28]; assign x13_s2[7] = code_in[3]^ code_in[1]; assign x13_s2[6] = code_in[19]^ code_in[17]; assign x13_s2[5] = code_in[11]^ code_in[9]; assign x13_s2[4] = code_in[27]^ code_in[25]; assign x13_s2[3] = code_in[7]^ code_in[5]; assign x13_s2[2] = code_in[23]^ code_in[21]; assign x13_s2[1] = code_in[15]^ code_in[13]; assign x13_s2[0] = code_in[31]^ code_in[29];

assign x12_s2[15] = code_in[4]^ code_in[0]; assign x12_s2[14] = code_in[20]^ code_in[16]; assign x12_s2[13] = code_in[12]^ code_in[8]; assign x12_s2[12] = code_in[28]^ code_in[24]; assign x12_s2[11] = code_in[6]^ code_in[2]; assign x12_s2[10] = code_in[22]^ code_in[18]; assign x12_s2[9] = code_in[14]^ code_in[10]; assign x12_s2[8] = code_in[30]^ code_in[26]; assign x12_s2[7] = code_in[5]^ code_in[1]; assign x12_s2[6] = code_in[21]^ code_in[17]; assign x12_s2[5] = code_in[13]^ code_in[9]; assign x12_s2[4] = code_in[29]^ code_in[25]; assign x12_s2[3] = code_in[7]^ code_in[3]; assign x12_s2[2] = code_in[23]^ code_in[19];

assign x12_s2[1] = code_in[15]^ code_in[11]; assign x12_s2[0] = code_in[31]^ code_in[27];

assign x11_s2[15] = code_in[8]^ code_in[0]; assign x11_s2[14] = code_in[24]^ code_in[16]; assign x11_s2[13] = code_in[12]^ code_in[4]; assign x11_s2[12] = code_in[28]^ code_in[20]; assign x11_s2[11] = code_in[10]^ code_in[2]; assign x11_s2[10] = code_in[26]^ code_in[18]; assign x11_s2[9] = code_in[14]^ code_in[6]; assign x11_s2[8] = code_in[30]^ code_in[22]; assign x11_s2[7] = code_in[9]^ code_in[1]; assign x11_s2[6] = code_in[25]^ code_in[17]; assign x11_s2[5] = code_in[13]^ code_in[5]; assign x11_s2[4] = code_in[29]^ code_in[21]; assign x11_s2[3] = code_in[11]^ code_in[3]; assign x11_s2[2] = code_in[27]^ code_in[19]; assign x11_s2[1] = code_in[15]^ code_in[7]; assign x11_s2[0] = code_in[31]^ code_in[23];

assign x10_s2[15] = code_in[16]^ code_in[0]; assign x10_s2[14] = code_in[24]^ code_in[8]; assign x10_s2[13] = code_in[20]^ code_in[4] ; assign x10_s2[12] = code_in[28]^ code_in[12]; assign x10_s2[11] = code_in[18]^ code_in[2] ; assign x10_s2[10] = code_in[26]^ code_in[10]; assign x10_s2[9] = code_in[22]^ code_in[6]; assign x10_s2[8] = code_in[30]^ code_in[14]; assign x10_s2[7] = code_in[17]^ code_in[1]; assign x10_s2[6] = code_in[25]^ code_in[9];

assign x10_s2[5] = code_in[21]^ code_in[5]; assign x10_s2[4] = code_in[29]^ code_in[13]; assign x10_s2[3] = code_in[19]^ code_in[3]; assign x10_s2[2] = code_in[27]^ code_in[11]; assign x10_s2[1] = code_in[23]^ code_in[7]; assign x10_s2[0] = code_in[31]^ code_in[15];

endmodule

Code for Majority Logic Decoder 2

//----------------------------------------------------------------------------// MLD_s2 - Module //----------------------------------------------------------------------------//**************************************************************************

//************************************************************************** //----------------------------------------------------------------------------// Filename:

MLD_s2.v

//----------------------------------------------------------------------------// Description: //

Top level design for 16-bit Multiple Error Detection and Correction.

// //----------------------------------------------------------------------------//-----------------------------------------------------------------------------

//`timescale 1ns/100ps

module MLD_s2(clk,x14_s2,x13_s2,x12_s2,x11_s2,x10_s2,x); input clk;

input [15:0] x14_s2; input [15:0] x13_s2; input [15:0] x12_s2; input [15:0] x11_s2; input [15:0] x10_s2; output [14:10] x;

// wire [14:10] error_p; wire [15:0] xq [14:10]; wire [14:10] x;

assign xq[14] = x14_s2; assign xq[13] = x13_s2; assign xq[12] = x12_s2; assign xq[11] = x11_s2; assign xq[10] = x10_s2;

genvar j; generate for (j=10; j < 15; j=j+1) begin: u2_MLD MLD_adder_s2 inst ( .datain(xq[j]), .dataout(x[j]) ); end endgenerate

endmodule

Code For Majority Logic Decoder Adder 2

//----------------------------------------------------------------------------// MLD_adder_s2 - Module //----------------------------------------------------------------------------//************************************************************************** // //************************************************************************** //----------------------------------------------------------------------------// Filename:

MLD_adder_s2.v

//----------------------------------------------------------------------------// Description: //

Top level design for 16-bit Multiple Error Detection and Correction.

// //-----------------------------------------------------------------------------

//`timescale 1ns/100ps

module MLD_adder_s2(datain,dataout); input [15:0] datain; output dataout; //

output error;

wire [4:0] sum;

assign sum = datain[15] + datain[14] + datain[13] + datain[12] + datain[11] + datain[10] + datain[9] + datain[8] + datain[7] + datain[6]

+ datain[5] + datain[4]

+ datain[3] + datain[2]

+ datain[1] + datain[0];

assign dataout = sum[3] ^ sum [4]; // xor to reduce logic level //assign error = (sum == 5'b01000);

endmodule

Code for Orthogonal Checksum Generator 3

//----------------------------------------------------------------------------// ocs_gen_s3 - Module //----------------------------------------------------------------------------//----------------------------------------------------------------------------// Filename:

ocs_gen_s3.v

//----------------------------------------------------------------------------// Description: //

Top level design for 16-bit Multiple Error Detection and Correction.

// //-----------------------------------------------------------------------------

//----------------------------------------------------------------------------// `timescale 1ns/100ps

module ocs_gen_s3(datain,code_in, code_out); input [4:0] datain; input [31:0] code_in;

output [31:0] code_out;

wire [14:10] data;

assign data = datain; assign code_out[0] = code_in[0] ^ data[14] ^ data[13] ^ data[12] ^ data[11] ^ data[10]; assign code_out[1] = code_in[1]

^ data[13] ^ data[12] ^ data[11] ^ data[10];

assign code_out[2] = code_in[2] ^ data[14] assign code_out[3] = code_in[3]

^ data[12] ^ data[11] ^ data[10]; ^ data[12] ^ data[11] ^ data[10];

assign code_out[4] = code_in[4] ^ data[14] ^ data[13] assign code_out[5] = code_in[5]

^ data[11] ^ data[10];

^ data[13]

^ data[11] ^ data[10];

assign code_out[6] = code_in[6] ^ data[14]

^ data[11] ^ data[10];

assign code_out[7] = code_in[7]

^ data[11] ^ data[10];

assign code_out[8] = code_in[8] ^ data[14] ^ data[13] ^ data[12] assign code_out[9] = code_in[9]

^ data[10];

^ data[13] ^ data[12]

assign code_out[10] = code_in[10] ^ data[14] assign code_out[11] = code_in[11]

^ data[10];

^ data[12] ^ data[12]

^ data[10]; ^ data[10];

assign code_out[12] = code_in[12] ^ data[14] ^ data[13] assign code_out[13] = code_in[13]

^ data[13]

^ data[10]; ^ data[10];

assign code_out[14] = code_in[14] ^ data[14]

^ data[10];

assign code_out[15] = code_in[15]

^ data[10];

assign code_out[16] = code_in[16] ^ data[14] ^ data[13] ^ data[12] ^ data[11]; assign code_out[17] = code_in[17]

^ data[13] ^ data[12] ^ data[11];

assign code_out[18] = code_in[18] ^ data[14] assign code_out[19] = code_in[19]

^ data[12] ^ data[11]; ^ data[12] ^ data[11];

assign code_out[20] = code_in[20] ^ data[14] ^ data[13] assign code_out[21] = code_in[21]

^ data[13]

assign code_out[22] = code_in[22] ^ data[14] assign code_out[23] = code_in[23]

^ data[11]; ^ data[11]; ^ data[11];

^ data[11];

assign code_out[24] = code_in[24] ^ data[14] ^ data[13] ^ data[12];

assign code_out[25] = code_in[25]

^ data[13] ^ data[12];

assign code_out[26] = code_in[26] ^ data[14] assign code_out[27] = code_in[27]

^ data[12]; ^ data[12];

assign code_out[28] = code_in[28] ^ data[14] ^ data[13]; assign code_out[29] = code_in[29]

^ data[13];

assign code_out[30] = code_in[30] ^ data[14]; assign code_out[31] = code_in[31];

endmodule

Code for Majority Logic Decoder 3 //----------------------------------------------------------------------------// MLD_s3 - Module //----------------------------------------------------------------------------//**************************************************************************

//************************************************************************** //----------------------------------------------------------------------------// Filename:

MLD_s3.v

//----------------------------------------------------------------------------// Description: //

Top level design for 16-bit Multiple Error Detection and Correction.

// //----------------------------------------------------------------------------//-----------------------------------------------------------------------------

//`timescale 1ns/100ps

module MLD_s3(clk,reset,x15_s3,x); input clk; input reset; input [31:0] x15_s3; output x;

wire [2:0] sum0_0, sum0_1, sum0_2, sum0_3, sum0_4, sum0_5, sum0_6, sum0_7; wire [3:0] sum1_0, sum1_1, sum1_2, sum1_3; //wire [11:0] sum1; wire [4:0] sum2_0, sum2_1;

wire [5:0] sum;

//reg x;

assign sum0_0 = x15_s3[31] + x15_s3[30] + x15_s3[29] + x15_s3[28]; assign sum0_1 = x15_s3[27] + x15_s3[26] + x15_s3[25] + x15_s3[24]; assign sum0_2 = x15_s3[23] + x15_s3[22] + x15_s3[21] + x15_s3[20]; assign sum0_3 = x15_s3[19] + x15_s3[18] + x15_s3[17] + x15_s3[16]; assign sum0_4 = x15_s3[15] + x15_s3[14] + x15_s3[13] + x15_s3[12]; assign sum0_5 = x15_s3[11] + x15_s3[10] + x15_s3[9] + x15_s3[8]; assign sum0_6 = x15_s3[7] + x15_s3[6] + x15_s3[5] + x15_s3[4]; assign sum0_7 = x15_s3[3] + x15_s3[2] + x15_s3[1] + x15_s3[0];

assign sum1_0 = sum0_0 + sum0_1; assign sum1_1 = sum0_2 + sum0_3; assign sum1_2 = sum0_4 + sum0_5; assign sum1_3 = sum0_6 + sum0_7;

assign sum2_0 = sum1_0 + sum1_1; assign sum2_1 = sum1_2 + sum1_3;

assign sum= sum2_0 + sum2_1;

assign x = sum[4] ^ sum[5];

endmodule

Reference

[1] Arazi, Benjamin, _A Commonsense Approach to the Theory of Error Correcting Codes,_ MIT Press, 1988. [2] Ho_man, D. G. et al., _Coding Theory; the Essentials,_ Marcel Dekker Inc., 1991. [3] Mann, Henry B., _Error Correcting Codes,_ John Wiley and Sons, 1968. [4] Purser, Michael, _Introduction to Error-Correcting Codes,_ Artech House Inc., Norwood, MA, 1995. [5] Reed, Irving S., _A Class of Multiple-Error-Correcting Codes and Decoding Scheme,_ MIT Lincoln Laboratory, 1953. [6] Roman, Steven, _Coding and Information Theory,_ Springer-Verlag, 1992. [7] Van Lindt, J. H., _Introduction to Coding Theory,_ Springer-Verlag, 1982.