WLCSP (Fan-in WLP)
A JCET Company
Wafer Level Chip Scale Package
STATS ChipPAC offers high performance fan-in wafer level packaging (FIWLP) solutions that provide significant package footprint reductions, lower cost, improved electrical performance, and a relatively simpler construction over conventional wirebond or interposer packaging technologies. HIGHLIGHTS
WAFER LEVEL CHIP SCALE PACKAGING
• 200mm & 300mm wafer bumping offers advanced technology in WLP services that enable higher current densities & increased reliability • Repassivation, Redistribution, Bumping and IPD layer options available • Full turnkey wafer bumping & Flip Chip-in-Package assembly capability
Wafer Level Chip Scale Package (WLCSP) offers one of the most compact package footprints, providing increased functionality, improved thermal performance and finer pitch interconnection to the printed circuit board. With WLCSP, all of the manufacturing process steps are performed in parallel at the silicon wafer level rather than sequentially on individual chips to achieve a package that is essentially the same size as the die. The resultant package has dielectrics, thin film metals, and solder bumps directly on the surface of the die with no additional packaging. The basic structure of the WLCSP has an active surface with polymer coatings and bumps with bare silicon exposed on the remaining sides and back of the die.
FEATURES • WLCSP body sizes qualified up to 6x6mm • Ball count ranges depending on pitch size and up to 300 • Die services available for 8”-12” wafers • In-house thin film on wafer processing & bumping • Full service wafer bumping with Polyimide or PBO dielectric options for wafer repassivation, redistribution and IPD layers • Bumps formed by printed paste, electroplate or ball drop solder bump technologies • Minimum available flip chip bump pitch of 150µm • Large bump (220-500µm) processing at 0.35mm pitch & greater for Flip Chip-on-Board & WLCSP applications • For larger pitch applications, either printed paste bumping or mechanical ball drop available • Eutectic and Pb-free solder • Copper under bump metallization (UBM) & redistribution layers (RDL) available • Wafer level IPD & thick copper (8-12µm) conductors available • Underfilling of substrate mounted bumped die may or may not be required depending on customer’s specific application & reliability requirements • Underfilling by overmolding is feasible • Low cure temperature polymers available • Flexible bare die processing • Compatible with conventional SMT assembly and test techniques
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Breakthrough FlexLine™ Wafer Level Manufacturing STATS ChipPAC’s innovative approach to WLCSP manufacturing, known as the FlexLine™ method, provides customers freedom from wafer diameter constraints, while enabling supply chain simplification and significant cost reductions that are not possible with a conventional manufacturing flow. This FlexLine™ manufacturing method delivers an unmatched level of flexibility and cost savings for fan-in and fan-out wafer level packaging. Superior Quality, Lower Costs: eWLCSP™ The encapsulation material that is a part of the FlexLine manufacturing process has enabled an innovative WLCSP packaging technology called encapsulated Wafer Level Chip Scale Package (eWLCSP™). An intrinsic feature of eWLCSP™ is the thin polymer casing formed on the back and four sidewalls of the die, providing mechanical robustness and resistance to chipping, cracking and handling damage, as well as improved long term reliability compared to traditional bare die WLCSP. eWLCSP provides a measurable increase in overall component strength of more than 50% over traditional WLCSP structures. The combined benefits of superior quality, lower cost structure and the ease of conversion through a drop-in replacement make eWLCSP™ a compelling value proposition.
APPLICATIONS A small, lightweight, high performance semiconductor solution, WLCSP is a compelling, cost effective solution for space constrained mobile applications and other portable consumer and industrial devices.
WLCSP (Fan-in WLP)
A JCET Company
Wafer Level Chip Scale Package
PROCESS HIGHLIGHTS
COMPONENT LEVEL RELIABILITY TESTING
Die Thickness
8” 200-760µm (8-30mils) 12” 250-790µm (10-32mils) Bumped Die Height 0.3mm minimum; 0.40mm and 0.80mm standard Printed Bump Height 70µm Solder Sphere Diameter 250µm ball drop Bump Pitch 0.50mm, 0.40mm, 0.35mm, 0.30mm Redistribution 10µm lines, 10µm spaces Visual Inspection Automatic optical inspection with electronic wafer mapping
Moisture Sensitivity Level Eutectic printed bump: JEDEC Level 1 @ 220°C
STANDARD MATERIALS
THERMAL PERFORMANCE
Dielectric Material RDL UBM Solder Alloy
• Thermal performance in the 20-40°C/W range for a 5mm x 5mm die
Ball Electroplate
Polymide & PBO Sputtered AlCu, Plated Cu AlCu/NiV/Cu, Ti/NiV/Cu, Plated Cu Eutectic (standard and ultra-low alpha) including Pb-free SAC 405, 305 or 105 (95.5Sn/4.0Ag/0.5Cu, 96.5Sn/3.0Ag/0.5Cu or 98.5Sn/1.0Ag/0.5Cu) Hi Pb, Eutectic, Pb-free; LF35 (available on request) Hi Pb, Eutectic, Pb-free
RELATED SERVICES Wafer Thinning Backside Coating Marking Packing Options
CROSS-SECTIONS WLCSP
Fully automated backgrinding & mechanical polishing Laminated coating Laser marking Fully automated die pick/place into custom pocket tape/reel or waffle pack media (Not to scale)
Pb-free printed bump: JEDEC Level 1 @ 260°C
Temperature Cycling
-55°C/125°C, 1000 cycles (eutectic & Pb-free printed bumps)
High Temperature Storage 150°C, 1000 hrs (eutectic & Pb-free printed bumps) Multiple Solder Reflow 5x, 10x and 20x reflows with minimal reduction in bump shear strength
Pressure Cooker Test
121°C/ 100% RH, 168 hrs
without thermal enhancement
• Application specific thermal characterization available upon request
ELECTRICAL PERFORMANCE • Dependent on application design, and capable to beyond 10GHz • Application specific electrical characterization available upon request • Thick Cu for high current low inductance applications
TEST SERVICES Wafer level testing is an important process for yield enhancement of flip chip packages and a final test requirement for WLCSPs. STATS ChipPAC’s best-in-class test services include: • Product Engineering support • Probe capability
eWLCSP™
• Program generation/conversion • High volume wafer sort
FLEXLINE™ PROCESS FLOW
UBM
FOC (Bump on I/O) 200mm only RPV (Repassivation)
Bump
UBM P1
RDL 3M (Redistribution)
Runner
P2 P1
Runner
Thick Copper RDL (12µm) 200mm only Plated Cu RDL/UBM
Backgrind (opt)
Si wafer dicing
Laser marking
Reconstitution
Pkg singulation
Redistribution
Pkg pick & place
Ball drop / reflow
Ship in TnR
Bump
P2 P1
RDL 4M (Redistribution)
Si wafer backgrind Bump
UBM
Bump
PI-2
Panel probe
PI-1 (optional)
WLCSP Bumped Bare Die Corporate Office Global Offices
10 Ang Mo Kio St. 65, #04-08/09 Techpoint, Singapore 569059 Tel: 65-6824-7777 Fax: 65-6720-7823 USA 510-979-8000
CHINA 86-21-5976-5858
KOREA 82-32-340-3114
SWITZERLAND 41-22-929-5658
The STATS ChipPAC logo is a registered trademark of STATS ChipPAC Pte. Ltd. Trademark registered in United States. Singapore company registration number 199407932D. All other product names and other company names herein are for identification purposes only and may be the trademarks or registered trademarks of their respective owners. STATS ChipPAC disclaims any and all rights in those marks. STATS ChipPAC makes no guarantee or warranty of its accuracy in the information given, or that the use of such information will not infringe on intellectual rights of third parties. Under no circumstances shall STATS ChipPAC be liable for any damages whatsoever arising out of the use of, or inability to use the materials in this document. STATS ChipPAC reserves the right to change the information at any time and without notice. ©Copyright 2016. STATS ChipPAC Pte. Ltd. All rights reserved. Apr 2016