COTS February 2019 by RTC Media

February 2019, Volume 21 – Number 2 • cotsjournalonline.com

JOURNAL

The Journal of Military Electronics & Computing

How the private sector can help Britain’s Skynet-6 program An Introduction to Brushless DC Motors for Next-Generation Missile Actuation Systems Pentek’s New QuartzXM SoM Speeds Custom Deployment of RFSoC in Critical Environments

The Journal of Military Electronics & Computing JOURNAL

COTS (kots), n. 1. Commercial off-the-shelf. Terminology popularized in 1994 within U.S. DoD by SECDEF Wm. Perry’s “Perry Memo” that changed military industry purchasing and design guidelines, making Mil-Specs acceptable only by waiver. COTS is generally defined for technology, goods and services as: a) using commercial business practices and specifications, b) not developed under government funding, c) offered for sale to the general market, d) still must meet the program ORD. 2. Commercial business practices include the accepted practice of customer-paid minor modification to standard COTS products to meet the customer’s unique requirements. —Ant. When applied to the procurement of electronics for he U.S. Military, COTS is a procurement philosophy and does not imply commercial, office environment or any other durability grade. E.g., rad-hard components designed and offered for sale to the general market are COTS if they were developed by the company and not under government funding.

SPECIAL FEATURES 14

How the private sector can help Britain’s Skynet-6 program

By Kim Hampson, Marketing Director for Viasat Government Systems

An Introduction to Brushless DC Motors for Next-Generation Missile Actuation Systems

By Charles Frick, Analog Devices, Inc.

SYSTEM DEVELOPMENT 24

DEPARTMENTS 06 Publisher’s Note

Sometimes I think it is a bit too much

The Inside Track

Pentek’s New QuartzXM SoM Speeds Custom Deployment of RFSoC in Critical Environments John Reardon, Contributing Editor

COT’S PICKS 28

Editor’s Choice for February

COTS Journal | February 2019

The Journal of Military Electronics & Computing

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COTS Journal | February 2019

PUBLISHER’S NOTE

John Reardon, Publisher

Sometimes I think it is a bit too much In my role as Publisher of COTS Journal, I am continually challenged to stay on top of technology and standards. Although I enjoy learning and being challenge, at times the number of acronyms is a bit daunting. Recently I had the opportunity to speak to a CEO of small Engineering Design firm. The confusion on what standards were being employed to affirm “best practices” left me a bit dazed. The first concern I had was how the term “best practices” was thrown around as if paying attention to something was sufficient to affirm that the “right thing” was being done. For example, when we spoke about checking for counterfeit components, I was told that they didn’t have that problem as they “seldom” purchased outside of mainstream suppliers. I was told that controlling software down to the Bios was a matter of “Best Practices” – so I asked him if they did that. It was at this point he went quiet. I decided to change tacks a bit and asked if he felt the “best practices” he employed were sufficient to protect his shareholders from liabilities. I don’t want to put my friend on the hot seat, but having listened to larger companies address these issues gave me a clear understanding that “Best Practices” doesn’t mean they adhere to the highest standards, but rather they are doing their best. Some sources that help define best practices: FAR Federal Acquisition Regulation Law and Legal Definition. Federal Acquisition Regulation (“FAR”) is a set of principles that govern the government procurement process. It regulates purchasing of goods and services by government. Generally all government agencies are required to comply with FAR.

COTS Journal | February 2019

DFAR The DFARS are the Defense Federal Acquisition Regulations Supplement, a supplement to the FAR that provides the DoD specific acquisition regulations. The office of the Under Secretary of Defense for Acquisition Technology and Logistics maintains the Defense Procurement and Acquisition Policy

FIPS The Federal Information Processing Standard (FIPS) Publication 140-2, (FIPS PUB140-2), is a U.S. government computer security standard used to approve cryptographic modules. ITAR ITAR (International Traffic in Arms Regulations) and the EAR (Export Administration Regulations) are export control regulations run by different departments of the US Government. Both of them are designed to help ensure that defense related technology does not get into the wrong hands. NIST The U.S. Department of Defense (DOD) published a threepage interim rule to the Defense Federal Acquisition Regulation Supplement (DFARS) that gives government contractors

a deadline of December 31, 2017 to implement the requirements of National Institute of Standard Technology’s (NIST) Special Publication 800-171. Common Criteria Common Criteria (CC) is an international set of guidelines and specifications developed for evaluating information security products, specifically to ensure they meet an agreed-upon security standard for government deployments. ... Common Criteria has two key components: Protection Profiles and Evaluation Assurance Levels. ISO The International Organization for Standardization is an international standard-setting body composed of representatives from various national standards organizations. Founded on 23 February 1947, the organization promotes worldwide proprietary, industrial and commercial standards.. MIL-STD or MIL-SPEC In the United States, military contractors, commercial entities, educational institutions, etc., often purchase products to the requirements set forth by the United State’s Military Test Specifications. These standards are often referred to using acronyms such as, “MILSTD” Military Standard, “MIL-SPEC” Military Specifications, or (informally) “MilSpecs” Military Specifications. They represent a set of very well thought out test specifications and procedures that are designed to achieve the high-quality and high-reliability objectives of the U.S. Department of Defense.

COTS Journal | February 2019

The

INSIDE TRACK

Global Aerospace Defense Contractor Deploys BIO-key Fingerprint Technology to Enable Windows Hello for Business Bio-key announced that a global security and Aerospace company has purchased and deployed BIO-key’s fingerprint reader solutions in support of the company’s initial roll out of Microsoft Windows 10 and Windows Hello for Business. The customer is a multi-billion dollar Aerospace Defense company that provides products and services to governments around the globe. This is the second large Aerospace Defense contractor to deploy BIO-key’s fingerprint technology since the introduction of the NIST 800-171 mandate for strong authentication to protect the confidentiality of controlled unclassified information.

chased SidePass, which connects directly to the USB port on laptops and tablets. Both EcoID and SidePass have been tested and qualified by Microsoft to bear the Windows Hello-ready mark.

“When an organization of this magnitude migrates to biometric authentication it establishes another milestone for the adoption of biometric technology for the enterprise,” stated Mike DePasquale, Chairman & CEO, BIO-key. “Organizations of this size and scope make technology and infrastructure decisions that must stand the test of time. BIO-key has purposefully aligned with Microsoft to ensure that our products and our product development complement the leadership and direction they are offering their customers. Microsoft has made a bold statement to its enterprise customers, that biometric sign-in is the future of authentication, with the introduction and promotion of Windows Hello for Business.”

Windows Hello for Business enhances security while improving the user experience with a simplified biometric log-on. For this deployment, the customer selected EcoID, BIO-key’s most popular enterprise-level compact fingerprint scanner. EcoID is ideal for desktops, laptop docking stations, or thin clients, connecting to the device via a USB cable. The customer also pur-

NVIDIA is opening a new robotics research lab in Seattle

The biometric authentication platform offered by Windows Hello and enabled by BIO-key scanners augments existing security platforms by delivering stronger security and with an unmatched user experience.

itors, and student interns will perform foundational research in these areas. To ensure the research stays relevant to real-world robotics

problems, the lab will investigate its work in the context of large scale, realistic scenarios for interactive manipulation.

Near the University of Washington campus led by Dieter Fox, senior director of robotics research at NVIDIA and professor in the UW Paul G. Allen School of Computer Science and Engineering. The charter of the lab is to drive breakthrough robotics research to enable the next generation of robots that perform complex manipulation tasks to safely work alongside humans and transform industries such as manufacturing, logistics, healthcare, and more. “In the past, robotics research has focused on small, independent projects rather than fully integrated systems. We’re bringing together a collaborative, interdisciplinary team of experts in robot control and perception, computer vision, human-robot interaction, and deep learning,” said Fox. Close to 50 research scientists, faculty visCOTS Journal | February 2019

The

INSIDE TRACK

OSS Receives $1.13 Million Initial Purchase Order for a Mobile Government GPUltima Computing System

U.S. Army mobile systems with our EB2400 PCIe ExpressBox,” said Steve Cooper, OSS president and CEO. “With this order, we are providing an upgrad-

One Stop Systems, Inc. has received a $1.13 million initial purchase order from an applied science and IT company for a government mobile shelter application.

OSS will provide the GPUltima systems as an integrated solution for radio frequency data acquisition, recording, playback, processing, spectrum signal analysis and archiving. They will be housed in highly ruggedized containers, with racks designed to absorb jolts and shocks.

This purchase order is the first major win for the company’s rack-mounted GPUltima Computing System. The integrated rack-mounted system can accommodate up to 14.3 petaflops of computational clusters with up to eight nodes, with each node containing up to 16 accelerators, dual-socket servers, uninterruptable power supplies, and NVMe storage with archiving capability. “Since 2014, we have been working in partnership with this valued customer, supporting

Raytheon Company wins $37 million contract supporting Evolved Sea Sparrow Missile Raytheon Co. is being awarded a $37,902,562 cost-plus-fixed-fee modification to previously-awarded to exercise options in support of Evolved Sea Sparrow Missile (ESSM) design agent, in-service support and technical engineering support services. Fiscal 2019 other country; fiscal 2018 weapons

COTS Journal | February 2019

ed system for ‘AI-on-the-fly,’ where previously unheard-of amounts of storage and computational power can be deployed close to where the underlying data is being collected. The customer selected us for our system’s ease of access, serviceability and expandability, which altogether give them an extra edge to go beyond the competition.”

Steve Cooper, Founder and CEO of OSS

procurement (Navy); fiscal 2019 research, development, test and evaluation (Navy); Foreign Military Sales; and fiscal 2019 operations and maintenance funding in the amount of $16,663,004 will be obligated at time of award, and funds in the amount of $208,225 will expire at the end of the current fiscal year. This is a sole-source contract pursuant to an international agreement between the U.S. and nine other countries. The Naval Sea Systems Command is the contracting activity.

The rack will be designed to hold a wide range of OSS products, such as 3U Compute Accelerators with NVIDIA Tesla. They can also include the company’s PCIe x16 solutions and partner products, and support certain commercial equipment via customized plug-and-play applications.

Raytheon Company wins $72 million contract action for the production of Aegis Weapon System fire control system Raytheon Co., Integrated Defense Systems, Marlborough, Massachusetts, was awarded a $72,463,134 firm-fixed-price, cost-plus-fixed-fee, cost-only undefinitized contract action for the production of Aegis Weapon System fire control system MK 99 equipment, Aegis Modernization production requirements, and associated engineering services.

The

INSIDE TRACK

Mercury Systems Receives $2.1M Order for Digital RF Memory Devices for Airborne Electronic Warfare Training Application

GDCA Inc. and Abaco Systems Strike Deal to Avoid Embedded EOL for Customers

Mercury Systems, Inc. announced that it received a $2.1 million order from a leading defense prime contractor for low-latency, multirole digital RF memory (DRFM) modules used in an advanced electronic warfare (EW) training program for an Air Force platform. The order is expected to be shipped over the next several quarters.

Abaco announced that the company has won significant orders from a major US prime contractor for its 3U Xilinx® Zynq® Ultrascale+™ MPSoC Processors with 1553 interface modules. They will be deployed over the next seven years within the central processing module of an advanced, next generation airborne radar system designed to deliver enhanced warfighter survivability.

Enea signs Agreement worth 4.2 MUSD for Embedded DP Enea has signed an agreement with a total value of 4.2 MUSD over two years, covering embedded Deep Packet Inspection (DPI) software for a global North American Tier 1 Network Equipment Provider. The deal, which is part of Enea’s expected business volume for 2019, includes both software licenses as well as associated support and maintenance The agreement covers Enea’s Qosmos

Mercury’s Digital RF Memories (DRFMs) are highly configurable target generators/transponders, signal delay lines or coherent Electronic Countermeasure (ECM) simulators.

ixEngine, which is a DPI-based classification and metadata engine that recognizes over 3,100 protocols and can extract over 5,000 metadata. The network equipment provider will embed Qosmos ixEngine in its networking solution, which needs a detailed understanding of network traffic to leverage multiple network paths for different applications. In this case, Qosmos ixEngine provides granular traffic information used as input for higher-level functions such as WAN optimization, Quality of Service (QoS), firewalling, and reporting.

Total value of the program to Abaco over its lifetime is expected to be up to $36 million. The system uses an open architecture design to deliver flexibility in deployment and the potential to simply and cost-effectively upgrade in response to evolving threats. “Situational awareness is one of the keys to maximizing personnel safety and security in the face of a broad array of ever-changing electronic warfare hazards, and requires the highest possible data bandwidth and processing performance,” said John Muller, Chief Growth Office at Abaco. “FPGA technology is a classic response: not only does it deliver the necessary throughput and bandwidth, but it also responds to the need to maximize flexibility, allowing the system to be rapidly and easily modified or enhanced as new requirements emerge.”

Ethan Plotkin, President and CEO GDCA COTS Journal | February 2019

The

INSIDE TRACK

Systel Selected to Support U.S. Navy NTCDL Program with Rugged HighDensity Computing Servers

Systel has been selected to support the U.S. Navy’s Network Tactical Common Data Link (NTCDL) system with rugged high-density computing servers. Systel will support NTCDL in partnership with Falstrom Company, which will design, build, qualify, and deliver the Below Deck Electronic Rack Assemblies to BAE Systems, the program’s prime contractor.

NTCDL provides the US Navy with the ability to simultaneously transmit and receive real‐time intelligence, surveillance, and reconnaissance data across disparate networks. “We are proud to support Falstrom, BAE Systems, and the United States Navy with rugged high-performance computers,” said Vimal Kothari, president of Systel. “Systel’s technology expertise and experience designing and manufacturing tactical computing solutions for the armed forces enables us to provide best-in-class computing for the modern warfighter.”

Navy Tactical Common Data Link - NTCDL

Developing production requirements, partnerships, systems, and infrastructure will be critical to harnessing lucrative growth opportunities, finds Frost & Sullivan Frost & Sullivan forecasts an estimated launch demand for 11,746 small satellites for new constellation installations and replacement missions by 2030. Such demand would take the small-satellite launch services market past the $69 billion mark and present significant growth opportunities throughout the industry. In order to keep up with market de12

COTS Journal | February 2019

mand, Frost & Sullivan anticipates innovative solutions will be deployed across the value chain including launch, manufacturing, and supply chain. In such an evolving market it will be critical for market participants to develop long-term sustainable partnerships to maintain and establish robust business operations. “The small-satellite launch service market is gaining pace with 89 small satellites launched in the third quarter of 2018. We also saw seven new players joining the small-satellite launch services race,” said Kamalanathan Kaspar, Senior Industry Analyst, Space.

SPECIAL FEATURE

How the private sector can help Britain’s Skynet-6 program By Kim Hampson, Marketing Director for Viasat Government Systems

A Service Based Interoperable Network can insure the MOD can be meet its Connectivity Demands What do the UK’s new aircraft carriers, stealth fighters and active duty military personnel all have in common?

The need for ubiquitous, high-speed, secure and resilient connectivity. The British military is fielding an impressive array of new weapons, from Queen Elizabeth-class carriers and F-35 fighters to upgraded armored vehicles. All of these projects — as well as an increasing number of legacy systems — share a voracious appetite for connectivity. Without access to sufficient connectivity, even the most sophisticated weapon will be left at a substantial disadvantage — potentially putting warfighters in harm’s way.

“The UK has an enormous opportunity to make the most of new capabilities being driven by private-sector SATCOM providers, including Viasat.” — Ken Peterman, Viasat.

COTS Journal | February 2019

The UK Ministry of Defence (MoD) recognized the importance of connectivity more than a decade ago when it began the Skynet-5 program, a public-private contract in which the MoD outsourced satellite communications (SATCOM) services to a commercial organization, as a fully managed service. This included the provision and operations of satellites, upgrades to ground stations and the delivery of user terminals and support. The Skynet-5 contract is ending in late 2022, and the final shape of Skynet-6 isn’t clear. What is clear is that the world has changed over the past decade. The UK’s commitments continue to span the globe from the Baltics to the Pacific, even as multiple defense priorities compete for scarce funding. As threats from adversaries evolve, coalition operations have now become the norm, which in turn demands access to an advanced SATCOM network to improve col-

laboration and enhance mission effectiveness. As adversaries move to develop sophisticated space weapons, including anti-satellite capabilities, demand for a robust, secure and high-speed SATCOM network is soaring. Which leaves the question: How will Skynet-6 respond to this mix of peril and promise? One option is for the UK government to build on its experience of outsourcing SATCOM and move to a service-based interoperable network. This approach leverages the best of private-sector innovation to ensure the MoD can meet the connectivity demands required to deter adversary threats – all at reduced cost and reduced risk to the UK government. Ken Peterman, president of Government

Systems at Viasat, is meeting with a number of MoD and coalition senior leaders to advocate for such a system. “By moving to an interoperable network that combines the power of government purpose-built systems with the rapid technological advancements being driven by the private sector, the MoD can easily transition to the high-speed, secure, resilient and ubiquitous system required to adopt new and emerging technologies and deter both current and future threats,” Peterman says. Viasat believes that if the MoD were to empirically analyze commercial SATCOM services in a defense context, the results would reveal that the most reliable, secure,

user-friendly and cutting-edge services available to meet the needs of defense forces are readily available today. This means offering capabilities such as network layering and resiliency, rapid scalability, cybersecurity, real-time awareness of network threats, and the ability to quickly incorporate the latest technology and practices. “The UK has an enormous opportunity to make the most of new capabilities being driven by private-sector SATCOM providers, including Viasat,” Peterman adds. “These private-sector advancements will satisfy emerging mission requirements, optimize existing assets and provide access to a wide range of new technologies — all at lower cost and lower risk to the MoD.”

HMS Queen Elizabeth COTS Journal | February 2019

A hybrid network As an example of adaptability, he points to Viasat’s Hybrid Adaptive Network (HAN)satellite architecture concept — a flexible, scalable system not locked to any single vendor. HAN architectures can simultaneously work with government and private networks as well as multiple satellite orbital regimes and frequency bands to significantly enhance the capabilities of armed forces. Steve Beeching, managing director of Viasat UK, echoes the need for the MoD to move to a HAN based SATCOM architecture. “In an era where the threats to the UK and its strategic partners have become so diverse,

COTS Journal | February 2018

working closely with industry is going to offer the UK government the ability to provide effective integrated platform solutions — which remain at the forefront of technology — into the hands of our armed forces with unprecedented speed,” Beeching says. Peterman believes that ultimately, military SATCOM must offer the same reliability and ease of use that commercial civilian customers have come to expect. “We have a new generation of warfighters who have grown up accustomed to an always-connected civilian way of life,” he says. “The private sector is capable of deliver HAN networks today,

which will create a nearly seamless transition to Skynet-6 as well as provide access to a range of advanced capabilities.” Beeching notes that Viasat is involved in a number of discussions with UK senior leaders to ensure the Armed Forces have access to the latest connectivity services required for them to maintain a tactical edge across today’s data-driven battlespace. “We have the opportunity to work with the MoD and partners to develop the most sophisticated SATCOM system ever built, and we’re looking forward to what the future has in store for Skynet-6,” Beeching says.

SPECIAL FEATURE

An Introduction to Brushless DC Motors for Next-Generation Missile Actuation Systems By Charles Frick, Analog Devices, Inc. Munition systems are quickly becoming as cost constrained as other areas of engineering as costs rise and customers demand smaller and longer-range products. To effectively drive and control these munitions in flight, a small control actuation system (CAS) makes small precise adjustments to place fins and adjust airflow over the body. Traditionally, these systems were pneumatic or driven via a brushed dc motor with a gearbox, but modern advancements in motor drives, including brushless dc motors (BLDC), have enabled smaller, lighter, cheaper, and more efficient CAS designs. However, this comes at the price of added system complexity to drive the three phases of the BLDC. The added complexity comes from several sources. First, while a traditional brushed dc motor only requires a single H-bridge, a BLDC requires three separate pairs of MOSFETs to drive the phases. This adds a small amount of cost and requires additional land area on the PCB. When driving these MOSFETs, care must be taken to avoid current shoot through that could destroy the MOSFETs if both the top and bottom are enabled at the same time. Particular attention must be paid to the dead time inserted between the top and bottom drive lines for the pulse width modulation (PWM). From a software perspective, a regular brushed motor can be controlled using a simple PID loop, while a BLDC will require more advanced loops and commutation strategiesâ&#x20AC;&#x201D; typically measuring the winding currents, phase voltages, rotor angle, and speed.

Construction of a BLDC A BLDC is a collection of electromagnets on the stator with permanent magnets attached on the movable rotor. The motor can be either 18

COTS Journal | February 2019

Fig. 1: Inrunner vs. outrunner.

an inrunner (magnets on the inside of the coils) or an outrunner (magnets outside the coils). Figure 1 shows a BLDC inrunner and outrunner. In both cases, three phases of wires are wound (U, V, W or A, B, C) around teeth in the stator. These windings are energized in sequence to attract and repel the permanent magnets (in red/blue). A standard microprocessor or DSP does not have the current drive strength to adequately energize the coils directly and thus a power inverter stage consisting of MOSFETs (two per phase) is typically used to convert the PWM drive from the control interface to the required high voltage drive for the motor. Normally, the three-phase invert-

Fig. 2: Three phase inverter and switching states.

off, the voltages applied to the windings can reach a maximum of 2/3 Ă&#x2014; VDC. A natural extension of this strategy is to apply PWM to each pair of MOSFETs. By changing the duty cycle of the PWM waveforms, the generated voltage in the windings can create a wide range of voltages depending on the resolution of the PWM generation system. Without PWM, a very natural commutation strategy is to simply energize each pair of windings in series (that is, block commutation or Fig. 3: Switch representations in state space and split into Sector I through six step commutation). Sector VI. For this strategy, one or two phases are pulled high while the remaining windings are driven er uses six N-Channel MOSFETs (see the top portion of Figure 2 on previous page), which low. By energizing the phases in sequence, the produce the switching states shown in the magnets on the rotor are pulled to each phase bottom portion of Figure 2. There are several and the rotor begins to rotate. To determine switching states that are not shown: 001, 010, what phases to energize, three Hall effect sen011, and 101. A 1 indicates one of the top three sors are typically mounted 60 electrical degrees MOSFETs is enabled. These states map to a state apart on the stator. The Hall effect sensors despace representation, as detailed by the six sec- tect each of the rotor magnets and generate a tors in Figure 3. By turning the switches on and 3-bit digital sequence, which is used to deter-

mine the next commutation region. While this strategy works well for low cost motor control systems, the strategy suffers from torque ripple at low speeds. Additionally, this torque ripple causes acoustic noise and introduces positional error if the motor is used for positioning/servo applications.1 Sinusoidal commutation works on the principle of aligning the stator currents with the stator flux in the BLDC. A BLDC moves based on the trapezoidal current through the windings. Each of these currents should be 120 degrees out of phase. A permanent magnet synchronous motor (PMSM) is similar to a BLDC, but requires sinusoidal currents to drive. A block diagram of how to drive a PMSM is presented in Figure 4. Simple speed control is achieved by using a velocity sensor or by using an estimation based on a position shaft sensor and motor parameters. Sinusoidal drive works particularly well at low speeds, but falls apart at higher speeds as the electrical frequency of the required sine wave must also increase with speed. At higher speeds, the motor requires higher torques, which introduce lag into the phase currents.2 To properly control at higher speeds, phase advances must typically be introduced to keep the torque and flux vectors properly aligned. To overcome this problem, a more advanced control scheme called field-oriented control (FOC) can be implemented. As with other commutation strategies, FOC can be

Fig. 4: Sinusoidal drive of a PMSM. COTS Journal | February 2019

Fig. 5: FOC block diagram.

implemented sensorless with estimations of position and speed based on the back-EMF generated by the windings, or sensored with position and current sensors. The basis of FOC is the control of the torque and flux vectors going into the windings of the motor. The generation of these vectors comes from the desired speed input to the motor.

be transformed into the reference frame of the rotor (Figure 6) to produce the Vα and Vβ using the Park transform. The next step in FOC is to convert Vα and Vβ to PWM values sent to the PWM inverter unit. Typically, either a sinusoidal modulation scheme (SPWM) or a space vector modulation scheme (SVPWM or SVM) is used for this process.

Using the electrical and mechanical constants of the motor (the moment of inertia, friction coefficient, inductance and resistance of the stator windings, and back-EMF constant), the PI loops from Figure 5 transform the desired speed into dc quantities. To control the electrical cycle of the motor, these quantities must

As mentioned previously, by controlling the switching of the MOSFETs within the power inverter, a space vector representation can be created, as in Figure 3. The space between adjacent unit vectors is coded to produce a sector between 1 and 6 to correspond to the six switching sectors of the electrical cycle of

Fig. 6: Transformation of control parameters in FOC. 20

COTS Journal | February 2019

commutation. A close-up of Sector 1 from Figure 3 is shown in Figure 7. The voltage vector VREF is composed of the voltage vectors Vα and Vβ, and the angle θ is the inverse tangent of Vd divided by Vq.3 Figure 7 on next page shows that the VREF can be derived by using two adjacent unit vectors (V1 and V2) and spending specifictime in each state (corresponding to a duty cycle). This duty cycle can be calculated by using equations similar to those derived from the vector math (see Figure 8 on next page). U, V, W Vector Equation Calculation From the equations in Figure 7, the PWM

time can be found by using a normalized time of 1.0 (equal to a full 100 percentduty cycle) and subtracting the Tn and Tn+1. The sector can be determined through additional calculations, as shown in Figure 9 shown on next page.

Fig. 7: Sector 1 of state space.

Once the duty cycles are calculated and sent to the PWM module of the controller, openloop control using FOC has been achieved. Now feedback must be integrated to achieve closed loop control. As Figure 4 shows, the three windings’ currents are measured and transformed using the inverse Clarke and inverse Park transforms. To measure these currents, several different strategies can be used: shunt sensing in line with each phase winding, a single low-end shunt between the bottom three MOSFETs and ground, phase shunts beneath each MOSFET to ground, or high side shunts between each top MOSFET and the VDC. If the design is cost constrained,

Fig. 8: Sector times from reference vectors.

the method using two shunts in line with the windings provides a good measurement as this provides a straightforward way of measuring two winding currents directly. The third current can be calculated by using Kirchhoff ’s current law and a sum of 0. An additional benefit is that the current can be measured at any moment, rather than only when the bottom or top MOSFETs are enabled. After measuring these currents, they should be normalized to the range of [–1, +1] using the max current measurable by the shunt system.

Fig. 9: Sector determination.

For position and speed sensing, either encoders (relative or absolute), Hall effect sensors, resolvers, or magnetic angular sensors can be used. However, depending on the resolution of the sensor, additional estimation schemes of the position and velocity may be necessary. ReCOTS Journal | February 2019

time spent servicing the PWM interrupt is time not spent servicing other aspects of the control processor (such as serial interfaces to PC-based programs). With a PWM frequency of 30 kHz, each PWM ISR is only 33.3 µs. So, every microsecond matters! Care must be taken to minimize computational overhead for sine and cosine and other floating-point computations. Generally, it is preferred to keep the FOC routine to under 50 percent of the available PWM ISR time, so the processor can service other peripherals such as the UART to service less important tasks such as changing desired speeds or setting a new position.

Selected Components to Consider Fig. 10: Block diagram of motor control signal chain.

gardless of the technology, the angle measured must be converted to the electrical angle to synchronize the commutation with the actual rotor position and enable the rotor transforms. The angular speed must also be known, but this is typically kept in the mechanical domain to match the desired input speed. With the actual position and speed of the rotor known, the inverse/reverse Park and Clarke transforms can be performed to convert the phase currents from the stationary stator reference frame to the rotating reference frame in the d, q reference frame. The PI loops for the resulting current and speed error terms create

error vectors that are then fed back into the forward Park and Clarke transforms and the control process can repeat. So how quickly should this process repeat? The answer varies depending on the motor characteristics. The PWM frequency is usually chosen to be outside the audible range of hearing (15 kHz to 30 kHz) such that the motor doesn’t audibly resonate. FOC and the required control loops are then implemented within the PWM interrupt service routine, such that new values for the PWM are available for the next PWM cycle. This places tight timing restrictions on the FOC routine as any

Given the already complex nature of implementing FOC, a careful selection of parts can help to minimize additional system integration challenges. Analog Devices offers several parts for motor control signal chains. These parts include gate drivers, absolute angle and Hall effect sensors, current sensors, and isolation products. A simple block diagram of components for a motor control signal chain can be seen in Figure 10. At a high level, the BLDC shaft position and speed are sensed using the ADA4571 AMR angle sensor and AD22151 magnetic field transducer. The phase winding currents are measured using inline shunt resistors and the AD8418 current sense amplifiers remove the PWM common-mode voltage. The LTC234518 8× 18-bit ADC converts the 6 analog voltage from the sensors to the digital realm for the microcontroller. The microcontroller uses these signals to calculate the PWM duty cycle, which is sent to the hardware timers. The LT1158 MOSFET drivers act as gate drivers for the six MOSFETs of the power inverter. The LT1158 is an integrated half bridge N-Channel MOSFET driver. While the supply can range from 5 V to 30 V dc, the input PWM waveform logic can accept a TTL or CMOS level. Additionally, a single PWM input is converted to the high and low MOSFET drive signals while the chip automatically inserts an adaptive dead time. This means that the PWM frequency can change dynamically and dead time is automatically inserted to protect the MOSFETs from current shoot-through without requiring changes to PWM timer code or registers.

Fig. 11: LT1158 dual N-channel MOSFET driver. 22

COTS Journal | February 2019

The ADA4571 integrated anisotropic magnetoresistive (AMR) sensor is capable of measuring 180 degrees of rotation to within 0.5°. This sensor runs from a single 2.7 V to 5 V supply and consumes only 7 mA with temperature com-

Fig. 14: LTC2345 block diagram.

pensation enabled. The output of this sensor is two analog sine waves (VSIN, VCOS) centered around 2.5 V (5 V supply). Once the voltages of VSIN and VCOS are digitized, they can be converted to an angle via the simple formula:

Equation 1

To measure 360 degrees of absolute rotation, the ADA4571 can be combined with a linear output magnetic field (Hall effect) sensor such as the AD22151. The AD22151 is designed for single 5 V supply operation and outputs a voltage proportional linear to the magnetic field applied perpendicularly to the package. During normal operation, the device draws a maximum of 10 mA and can detect bipolar or unipolar fields with varying amounts of gain. The benefit of this sensor is the analog output voltage, which can be easily added to a system already measuring analog quantities such as current sensor outputs or additional analog angle sensors. By placing the AD22151 perpendicular to the ADA4571, the outputs can be fused together in software to allow for sensing of 360° of motion of a shaft mounted diametric magnet. Along with the angle sensors, sensored FOC

requires precise measurement of the phase currents through a BLDC. The AD8418 is a bidirectional zero-drift current sense amplifier well suited for the task. This external shunt amplifier works with a gain of 20 V/V across temperature with a common-mode rejection range of –2 V to +70 V. The amplifier also senses bidirectional currents through the shunt, which is particularly useful when measuring phase currents for BLDCs. The part is designed to work with a supply voltage VS between 2.7 V and 5 V, with the analog output voltage centered around the VS/2. If the supply is chosen for 5 V, the output is centered around 2.5 V, as with the ADA4571. With analog output sensors, the results must be converted to the digital domain. While a multitude of ADCs exist, the LTC2345 is particularly applicable for motor control due to 8 simultaneously sampling channels. Sampling is synchronized to a single rising edge on the convert line. Phase currents and the absolute angle sensor outputs can then be synchronized to the same time instant during center aligned PWM. The single 5 V supply operation simplifies power supply design, while still drawing less than 20 mA. A separate digital logic output voltage allows the LTC2345 to interface to lower voltage microcontrollers, processors, or FPGAs. Due to the flexible nature of the analog input ranges, the 2.5 V offset of the position and current sensors can automatically be removed in hardware by using the (IN–) analog input channels. Data can be clocked out of the LTC2345 using the SDO outputs at various clock rates depending on the required sampling throughput.

Conclusion With the increasing prevalence of BLDCs in control actuation systems, more advanced algorithms, sensors, and drive circuitry are required. Sinusoidal and FOC are two commutation strategies that afford precise control of a BLDC. Both strategies require precise measurement of the rotor angle of the BLDC, which can be difficult without the right components. However, the ADA4571 and AD22151 simplify this measurement. The LT1158 simplifies PWM drive lines for the three phases for a BLDC by reducing PWM lines and removing calculations of dead time. The AD8418 simplifies winding current and the LTC2345 easily digitizes and synchronizes multiple analog sensor outputs. These parts represent a small portion of the Analog Devices portfolio for motor control applications.

References 1 Shiyoung Lee. “A Comparison Study of the Commutation Methods for the Three-Phase Permanent Magnet Brushless DC Motor.” 2009. 2 Danielle Collins. “FAQ: What Is Sinusoidal Commutation for DC Motors?” Motion Control Tips. 3 Jin-Woo Jung. “Project #2 Space Vector PWM Inverter.” Ohio State University, February 2005. Murray, Aengus, Dara O’Sullivan, and Jens Sorensen. “Model-Based Design Streamlines Embedded Motor Control System Development.” Analog Devices, Inc., April 2015.

COTS Journal | February 2019

SYSTEM DEVELOPMENT

Pentek’s New QuartzXM SoM Speeds Custom Deployment of RFSoC in Critical Environments John Reardon, Contributing Editor

In adopting the Xilinx RFSoC, Pentek was able to bring a bit of brilliance to the needs of today’s high speed interconnects.

The Model 6001 Quartz eXpress Module is the only high-performance system-on-module to offer the Xilinx Zynq UtlraScale+ RFSoC FPGA. The QuartzXM measures only 2.5 by 4 inches and allows for full use of the FPGA functions in multiple form factors.

The RFSoC The RFSoC is based on the UltraScale+ MPSoC. The MPSoC is a system on a chip architecture that includes up to quad ARM Cortex-A53 processors and two ARM Cortex-R5 real-time processors all integrated into a FPGA. Building on this foundation the RFSoC adds eight 4 GSPS 12 bit A/D’s each equipped with programmable digital down converters and eight 6.4 GSPS 14 bit D/As. Each is equipped with Digital Up converters.

Figure 1 - The Xilinx UltraScale+ MPFPGA diagram compared to the RFCSoC Diagram. 24

COTS Journal | February 2019

Designing with the RFSoC The unique challenges that Pentek faced in designing with the circuit density and small size of the IC was no small task. Designing and laying out the PCB for the analog interface containing 16 channels requires attention to every detail to maintain signal quality and reduce crosstalk. The RFSoC’s gigabit serial interfaces are capable of running at higher than 32 Gb/Sec. Couple this with a target audience that will be putting the modules in harshest environments possible, created extreme challenges to the design team. The goal of providing a platform that allowed access to the full feature set of the Xilinx part was hard enough on its own, but it also had design goals that were challenged by SWaP (Space Weight and Power). Taking

them in inverse order, power was the most challenging. Considerations such as the use of JESD204 as a possible solution were problematic adding nearly 1 watt per lane. Space and weight were simple enough as the RFSoC incorporated a densely pack circuitry that miniaturized everything into a single IC, the concern was the I/O and how to route it. Managing data rates using parallel LVDS pairs is part of the brilliance that Pentek was able to incorporate in the module. One technique employed was the to use a 1:2 demultiplexed interface where data is sent over two parallel interfaces each at half the sample rate. This keeps each 12-bit interface below the maximum clock rate allowed by the FPGA LVDS interface but allows the data needed to support a 2 GHz sample rate.

The Target Applications

Figure 2 - The RFSoC Footprint

You have to conclude that when Xilinx conceived the Ultrascale+ RFSoC, their focus was on the 5G market and all that entailed. Pentek, with a strong working relationship with Xilinx immediately saw the opportunity and concluded that this part would be perfect for many applications addressed by todayâ&#x20AC;&#x2122;s military. Recognizing the need for field deployed HPCâ&#x20AC;&#x2122;s, being able to incorporate advantages in Space, Weight and Power and knowing that la-

Figure 3 - The Quartz eXpress SOM from Pentek COTS Journal | February 2019

tency issues were of concern with the current solutions, created the vision for the QuartzXM SoM. It is easy to conceive the immediate advantages of the QuartzXM. From Phase Array RADARs to massive multi-input/output antennas from targeting systems to surveillance the densely packed Quartz XM opens up possibilities.

Interested in getting your copy of

Tools and Support Pentek has developed the Navigator FDK (FPGA Design Kit) that provides all the IP functions as blocks that can be used in Xilinx’s Vavado IP integrator, giving the IP designer immediate access to the products entire FPGA design as a block diagram. Individual IP blocks can be modified to meet the application requirements. This fast start tool is simple to use and will allow for the end use application to be expedited for a custom IP solution.

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COTS Journal | February 2019

February 2019

COT’S PICKS Acromag Releases New 6U OpenVPX Single Board Computer with Intel® Xeon® E3 CPU and Extensive I/O Support

This new processor board provides cost-effective, high-performance computing plus support for many I/O peripherals including XMC and AcroPack® mPCIe mezzanine modules. The VPX6860 series features the 6th Generation Skylake Intel Xeon E3-1505M processor and CM236 PCH chipset for wide-ranging I/O support. Expanded memory performance comes with up to 32GB of DDR4 ECC SODIMMs that are firmly attached to the board but removable for security or upgrades. This SBC is designed for commercial off-the-shelf (COTS) applications and manufactured in the USA with a minimum 7-year life expectancy. Front I/O air-cooled and conduction-cooled versions are offered.

3U VPX processor model to provide a 6U version with greater I/O flexibility,” stated Robert Greenfield, Acromag’s Business Development Manager. “We added dual 40GbE ports and two slots for XMC and AcroPack I/O modules.” A broad array of I/O options includes dual USB 3.0, a mini-display port, and RJ45 gigabit Ethernet on the front panel. Backplane I/O supports PCIe Gen3 x16 on the expansion plane, dual 40 GBASE-KR4 on the data plane, plus dual 1000BASE-T and 1000BASEBX on the control plane. Two M.2 expansion sites offer plenty of on-board data storage. Other I/O includes four RS-232/422/485, two USB 3.0, two USB 2.0, two Display Port, two SATA III, eight GPIO, and audio capabilities. XMC and AcroPack module slots can add FPGA or other I/O processing.

“Acromag is expanding on the popularity of our

New 10-Gigabit Ethernet XMC Modules Feature Quad SFP+ Ports or Dual XAUI Rear I/O and Support for a PCIe x8 Gen3 Interface Acromag’s new XMC630 Series modules offer up to four independent 10-gigabit Ethernet interface ports. The XMC mezzanine card mounts on VME,

VPX, PCIe and other embedded computing carrier boards. An industry-leading Intel® XL710 Ethernet Controller provides high-performance network connectivity with advanced off-load and virtualization capabilities. Two models are available. The air-cooled XMC631 model has four SFP+ connectors on the front panel for fiber optic or copper

The AcroExpress processor boards are ideal for military and aerospace applications that require high-performance computing, expansive I/O support, and advanced cooling management. Acromag www.acromag.com

media transceivers. The rear I/O model XMC632 routes two XAUI interfaces to the P16 connector and is compatible with conduction-cooling frames. Optional VITA 61 connectors enable PCI Express 3.0 data rates across eight highspeed serial lanes on the XMC P15 connector. Designed for COTS applications, these XMC modules are ideal for use in defense, aerospace, industrial, and scientific research computing systems. Extended temperature operation is supported for -40 to 85°C. “Acromag responded to increasing demand for faster networking and higher density with these Quad 10GbE NIC modules” stated Robert Greenfield, Acromag’s Business Development Manager. “Using the latest Intel Ethernet Controller technologies, we can help customers rapidly move data between systems.” Acromag www.acromag.com

COTS Journal | February 2019

February 2019

COT’S PICKS DDC-I, Core Avionics & Industrial and North Atlantic Industries Partner to Deliver High-Performance SafetyCritical DO-178C Display Solutions for Avionics DDC-I announced it is working with Core Avionics & Industrial (CoreAVI), Arm, and North Atlantic Industries (NAI) to deliver an integrated safety-critical display and GPU computing solution designed for next-generation avionics systems. The smart display solution, utilizing the Arm®Cortex®-A53 multicore processor on AMD’s E9171 GPU, integrates the Deos DO-178 real-time operating system with CoreAVI’s newest safety-critical VkCore™ SC Vulkan®-based driver suite and VkCoreGL™ SC OpenGL®-based graphics and video libraries, all deployed on NAI’s 3U, single-slot OpenVPX singe-board computers. The integrated platform gives avionics OEMs a high-performance embedded platform for developing and deploying complex 2D/3D graphics and advanced streaming video in a scalable, DO-254/DO-178C package that is certifiable to Design Assurance Level (DAL) A. “Arm has significant expertise in functional safety across automotive and industrial markets, where we continue to lead the way in advanced safety compute,” said Neil Stroud, director of technology strategy, Embedded & Automotive Line of Business, Arm. “Alongside DDC-I, CoreAVI, and North Atlantic Industries, we will apply this expertise to our mutual customers to deliver a best-in-class Arm-based avionics platform with safety-critical RTOS and OpenGL graphics.”

“Deos with SafeMC multicore technology provides advanced facilities like safe scheduling and cache partitioning that enable avionics OEMs to take full advantage of the high-performance multicore processing capabilities that Cortex-A53 brings,” said Greg Rose, vice president of marketing and product management at DDC-I. “It also provides a time- and space-partitioned architecture that makes it ideal for hosting avionics display applications utilizing CoreAVI Safety Critical OpenGL libraries. Now, avionics developers can hit the ground running with a COTS avionics display platform that is fully integrated and ready to certify to DO-178C DAL A.” “CoreAVI’s DO-178C DAL A certifiable Vulkan-based drivers and OpenGL SC-based libraries provides our avionics customers with the state-ofthe-art graphics and compute capabilities that the newest generation of applications require,” added Dan Joncas, Executive Vice President of Sales and Marketing at CoreAVI. “We’re excited to collaborate on this innovative joint solution with DDC-I, ARM, and NAI to provide our customers with a platform that unlocks the best performance possible using the latest graphics processors for avionics from CoreAVI.” “Our highly-integrated, 3U, single-slot, OpenVPX 68GP2 single-board computers are certifiable to DO-254 DAL A and offer avionics OEMs the latest AMD E9171 and Xilinx Quad Core Arm Cortex-A53 Zynq Ultrascale+ SoC technology,” said Lino Massafra, vice president of sales and marketing at NAI. “CoreAVI’s and DDC-I’s DO-178C DAL A certifiable VkCore SC, OpenGL SC and Deos running on the 68GP2 meets the most demanding video processing requirements with the least

SWaP-C”. “We look forward to working with the best-in-class video, processor and OS suppliers!” The Arm Cortex-A53 is a high-performance, low-power 64-bit multicore processor that features one to four cores and is based on the Arm®v8-A architecture. Utilized by leading CPU and SoC manufacturers such as NXP and Xilinx, the Cortex-A53 is backward compatible with the 32-bit Arm architecture and provides up to 64 kbytes of L1 cache and 2 Mbytes of L2 cache. The multicore processor features DSP and NEON SIMD extensions, a VFPv4 floating point unit for each core, hardware virtualization support, and Arm®TrustZone® security extensions. DDC-I’s Deos is a field proven, safety-critical, avionics RTOS that is used to host a multitude of flight-critical functions, such as air data computers, air data inertial reference units, cockpit video, displays and flight instrumentation, flight management systems, engine management, and many more. Built from the ground up for safety-critical applications, Deos was the first RTOS certified to DO-178 DAL A and is the only certifiable timeand space-partitioned COTS RTOS that has been created using RTCA DO-178, Level A processes from the very first day of its product development. Deos features deterministic real-time response as well as time and space partitioning. Deos also features patented slack scheduling and cache partitioning, which enables it to deliver higher CPU utilization than any other certifiable safety-critical COTS RTOS. Deos is supported on x86, Arm, and PowerPC microprocessors. CoreAVI’s VKCore SC driver suites and VkCoreGL SC application libraries are certifiable to DO-178C DAL A, and the VkCoreGL SC libraries are FACE-aligned. VkCore SC drivers support multi-threading, multiple partitions, Hypervisor Multicore, mixed DAL and virtualized graphics, context management, integrated video capture, and GPU security. All CoreAVI drivers are designed and developed from the ground up to enhance safety, reliability and security and have a high technology readiness level. DDC-I www.ddci.com

COTS Journal | February 2019

February 2019

COT’S PICKS Adder Annouces World First with New 4K Solution • Dual-head 4K, video, audio and USB over a single fiber connection • Easy migration to 4K without costly rip and replace • Pixel-perfect, color accurate at 4K60 • Proven to meet 4K content demand

ITY range means the ALIF4000 can be phased in to an existing network without disruption, downtime or the costly need to rip and replace. The ALIF4000 delivers pixel-perfect picture quality, audio and USB to single or dual 4K screens over a single fiber link. At the same time, it supports mixed 1Gb and 10Gb networks and gives customers the right size technology with an opportunity to embrace 4K when they’re ready.

Adder Technology has announced the world’s first dual-head, high performance 4K IP KVM matrix over a single fiber with the launch of the ADDERLink™ INFINITY 4000 Series (ALIF4000). The adoption of 4K technology continues to rise dramatically. It is predicted that the global 4K display market will be worth $52bn by 2020 (up by 188% vs 2015)[1]. The projected growth of 4K technology, and the increasing demand for 4K content, means the launch of the ALIF4000 series is perfectly timed to support IP KVM users as they move to 4K environments. Full compatibility with the existing INFIN-

VadaTech Announces New Zynq UltraScale+ RFSoC FPGA, Double AMC, MTCA.4q VadaTech embedded boards, enabling software and application-ready platforms, announces the AMC575. The AMC575 utilizes the Xilinx XCZU29DR RFSoC and is compliant to AMC.1, AMC.2, AMC.3 and AMC.4 specifications. The unit has an on-board, re-configurable FPGA which interfaces directly to the AMC FCLKA, TCLKA-D. The module has dual bank of 64-bit wide DDR-4 memory with ECC for a total of 16 GB. This allows for large buffer sizes to be stored during processing as well as for queuing the data to the host. The RFSoC device includes 16 ADC (12-bit at 2 GSPS) and 16 DAC (14-bit at 6.4 GSPS) with analog I/O routed to a MicroRTM per MTCA.4. Clock and trigger I/O are provided. The front panel also has the interface to the DisplayPort, dual USB, RS232 ports as well as dual high-density connector for external I/O (total of 128 single ended or 64 differential). The XCZU29DR includes a quad-core ARM 30

COTS Journal | February 2019

The ALIF4000 will help organizations across a wide range of industries integrate 4K content into their everyday work quickly and efficiently. Cortex-A53 application processing unit and dual-core Cortex-R5 real-time processing as well as over 4,200 DSP, 930 K logic cells and over 60 MB of internal memory (including 22.5 Mb of UltraRAM).

John Stevens, director of engineering at Los Angeles-based post-production house The Foundation, said, “The launch of the ALIF4000 series gives us the opportunity to take control and add 4K functionality to our existing infrastructure, as and when we need it, without having to rip and replace; meaning we can continue to meet our customers’ growing need for 4K output.” The ALIF4000 series simplifies the adoption and efficiency of 4K IP KVM by offering 4K, USB and audio all through a single fiber connection. This makes it the ideal solution for anyone looking to implement single or dual 4K screens into an IP KVM environment. Adrian Dickens, managing director at Adder Technology, said, “When speaking with customers during the development of the ALIF4000, we discovered that many were delaying the shift to 4K to avoid the costly hardware upgrades, swap-outs or full rip and replace jobs that they believed were required to gain 4K video support. Adder Technology www.adder.com

AMC575 Module also has on board 64 GB of Flash, 128 MB of boot flash and an SD Card as an option VadaTech Incorporated www.vadatech.com

February 2019

COTâ&#x20AC;&#x2122;S PICKS

Pixus Develops Ruggedized Software Defined Radio Solutions

Pixus Technologies has developed ruggedized versions of commercial software defined radios. The RX310, the first in the series of small form factor ruggedized devices, utilizes the USRP software defined radios from Ettus Research, a National Instruments brand. The weatherproof

enclosure features IP67 sealing for water and dust ingress. It is also designed for MIL-STD-810 for shock/vibration and MIL-STD-461 for EMI. The RX310 contains two extended bandwidth daughterboard slots covering 10 MHz â&#x20AC;&#x201C; 6 GHz with up to 160 MHz of baseband bandwidth, dual 1/10 GigE high-speed interfaces, and a large user-programmable Kintex-7 FPGA. The unit is 302mm wide x 400mm long x 98mm tall with conduction-cooled fins for heat dissipation.

The RX310 series can be used in various types of airborne, shipboard, ground vehicle, or outdoor designs. Example applications include SIG-INT, spectrum monitoring, passive RADAR, smart agriculture, smart energy, and prototyping systems for advanced wireless standards. Pole-mount and other special mounting options are available. Light-rugged versions of the enclosure are also available upon request, as well as ruggedized versions of other software defined radios offered by Ettus Research. Pixus Technologies www.pixustechnologies.com/

AdaCore Joins the RISC-V Foundation to Provide C and Ada Compilation Support GNAT Pro and GNAT Community tool chains available both for professionals and hobbyists AdaCore today announced its membership in the RISC-V Foundation, a non-profit organization chartered to standardize and promote the free and open RISC-V instruction set architecture (ISA) together with its hardware and software ecosystem. RISC-V is an open instruction set initially developed by the Computer Science Division of the EECS Department at the University of California, Berkeley. Today the RISC-V Foundation

comprises more than 200 members building the first open, collaborative community of software and hardware innovators powering a new era of processor innovation. The RISC-V ISA can be implemented through either open or proprietary architectures, offering silicon designers a unique way to take advantage of a cleanly designed assembly language associated with an existing software ecosystem. In joining the RISC-V Foundation, AdaCore is bringing the Ada and SPARK programming languages to the forefront of the technologies available to RISC-V developers, offering a unique environment for safety- and security-critical applications developed on this platform. AdaCore www.adacore.com

COTS Journal | February 2019

February 2019

COT’S PICKS PikeOS is the only Embedded RTOS Separation Kernel that is certified according to Common Criteria EAL3+ world-wide. SYSGO’s PikeOS hypervisor has been certified according to Common Criteria EAL 3+. The subject of certification by the German Federal Office for Information Security (BSI) is the separation kernel in PikeOS, which ensures a strict separation of applications running on the same hardware through spatial and temporal partitioning. Such a separation is required above all in security-critical systems and is generally mandatory for the certification of the overall system. The certification by the BSI was carried out for the PikeOS Separation Kernel Version 4.2.2 (build number s5400) for the platforms X86_64, ARMv7 and ARMv8. PikeOS is thereby currently the only real-time operating system worldwide that holds a Common Criteria certification for its separation performance. In addition, PikeOS is also certified for various safety standards, making it particularly suitable for applications that have both safety and

Mercury Systems Ships First SpaceQualified Commercial Solid State Drives for Low Earth Orbit Satellite Application Mercury Systems, Inc. announced the first prototype shipments of the Company’s 3U TRRUST-Stor™ VPX RT space-qualified secure solid-state drives (SSD) to two leading suppliers of low Earth orbit (LEO) satellites. Designed to operate reliably in high radiation environments, this device is the first commercial SSD leveraging VITA 78 SpaceVPX™ standards to reduce customer cost and mitigate program risk. In addition to commercial satellite applications, this

COTS Journal | February 2019

security requirements, particularly in the aerospace, automotive and railway industries as well as in industrial or medical systems. PikeOS also supports the simultaneous operation of applica-

Jastroch, Director of Marketing Communication at SYSGO.”The certification according to the Common Criteria confirms this approach and is a new milestone for both us and the industry as a whole.” For developers of critical systems, certification not only means secure and effective separation of applications, but also a faster and more cost-effective certification of their entire system, as the operating system itself no longer needs to be considered in this process.

tions of different criticality and the combination of real-time applications with less time-critical applications. “We have designed PikeOS from the ground up for certifiable systems in security-critical environments, thereby enabling our customers to design their systems to the principle of ‘Safety & Security by Design’ from the outset,” said Markus device is ideally suited for high-altitude aircraft, airborne weapons and mission-critical ground computing systems. “Customer demand for commercial radiation-tolerant SSD devices for LEO satellites has far surpassed our expectations as we continue to gain share in this dynamic market,” said Iain Mackie, Vice President and General Manager of Mercury’s Microelectronics Secure Solutions group. “I am immensely proud of the employees of our Phoenix Advanced Microelectronics Center who have successfully demonstrated that Mercury’s innovative next-generation business model unlocks value for satellite designers and manufacturers around the globe.”

“With Common Criteria, the PikeOS separation kernel is now certified to one of the most established and rigorous security standards on which most industry-specific standards are based,” says Dr. Dominic Eschweiler, Director Security Certification at SYSGO.”Especially in the context of government applications, certification according to Common Criteria is often a mandatory requirement. In addition, having a certified PikeOS enables developers from all industries to have a solid, certified foundation for their systems.” SYSGO’ www.sysgo.com

At the heart of the SSD is Mercury’s proprietary NAND controller with BuiltSECURE™ error correcting code (ECC) algorithms. These ECC algorithms mitigate radiation-induced byte errors, thereby enabling sustainable reliability and fault tolerance that are not available with competing storage solutions. As Mercury maintains 100% authority over the controller and its implementation, this device is readily customizable for non-traditional use cases when deemed critical to a customer’s program. Mercury Systems, Inc. www.mrcy.com

February 2019

COT’S PICKS Microchip’s First Libero SoC Design Suite Release Boosts FPGA Designer Productivity and Delivers One Unified Design Suite for Latest Families New version delivers significant productivity gains while marking major production milestones for the low-power PolarFire™ FPGA family As each new generation of devices scale, Field Programmable Gate Array (FPGA) designs are increasing in complexity and resource utilization, making designer productivity essential to accelerating time to market.

Libero SoC v12.0 Microchip Technology Inc., Libero SOC delivering new gains in runtime and quality of results, as well as one unified design suite for all the company’s latest-generation FPGA families, including new production releases of PolarFire FPGAs. Libero SoC v12.0 reduces design flow runtimes and, with the improved quality of results, it provides results in fewer design iterations and improves customer productivity. By upgrading to Libero SoC v12.0, designers will see runtime reduction of 60 percent for timing, 25 percent for place and route and 18 percent for power results. They will also see an average increase of four percent in quality of results for larger designs and a 10 percent improvement

for the PolarFire MPF300/TS-1 device. “Libero SoC v12.0 is the result of our determination to offer a comprehensive, easy-toadopt, easy-to-learn FPGA design suite,” said Rajeev Jayaraman, vice president of software for the FPGA business unit at Microchip’s Microsemi subsidiary. “This latest release is focused on delivering the many essential elements needed for efficient design implementation, while further enabling the growing adoption of the low-power PolarFire family across each of our key market segments.” Libero SoC v12.0 is being released simultaneously with the production release of the PolarFire MPF100T, PolarFire MPF200T and PolarFire MPF300T devices. The release includes production timing and power for PolarFire MPF300T-1 devices, as well as support for two new industry-leading devices for the aerospace and defense market segments—the low-power, radiation-tolerant RT4G150L, which offers 25 percent savings for standard speed grade; and military-grade support for the SmartFusion2 M2S150T/S FCV484 device. One unified design suite for PolarFire, IGLOO2, SmartFusion2 and RTG4 FPGAs eliminates the need for designers to qualify multiple pieces of software when working across product families. Libero SoC v12.0 now supports FPGA Hardware Breakpoint (FHB) for RTG4 and PolarFire devices, PCIe debug support for PolarFire and continuous transceiver eye monitoring using SmartDebug. The new release also improves Double Date Rate (DDR) memory performance by an average of 29 percent in high-effort mode and 39 percent in regular-effort mode. Enhanced Tool Command Language (TCL) support enables a much-requested feature where customers can run the entire design flow on the command line if they so choose. Microchip Technology www.microchip.com

COTS Journal | February 2019

COTS COTS

Index

ADVERTISERS

Company Page# Website AIM .................................................... 16 ................................ www.aim-online.com Atrenne Integrated Solutions ........... 34 ................................... www.atrenne.com Avalex Technoogies .......................... 5 ...................................... www.avalex.com Behlman Electronics ......................... BC .................................. www.behlman.com CDI .................................................... 17 ..................................... www.cdvinc.com Chassis Plans .................................... 8 ............................ www.chassisplans.com Interface Concept ............................... 26 ..................... www.interfaceconcept.com Mercury Systems ................................ 4 ................................. www.tms.mrcy.com MPL ................................................... 34 ............................................. www.mpl.ch North Alantic Industries .................... IBC ......................................... www.nail.com OSS ................................................... 27 ...................... www.onestopsystems.com Pentek ............................................. IFC .................................... www.pentek.com Phoenix International ....................... 23 .................................. www.phenxint.com PICO Electronics, Inc ........................ 33 ....................... www.picoelectronics.com Red Rock Technologies, Inc .............. 34 ............................ www.redrocktech.com Supermicro ...................................... 27 ............................ www.supermicrot.com Systel .............................................. 12/23 . .................................www.systelusa.com Vicor Cororation................................ 13/34 ... www.vicorpower.com/defense-aero. COTS Journal (ISSN#1526-4653) is published monthly at; 3180 Sitio Sendero, Carlsbad, CA. 92009.

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Periodicals Class postage paid at San Clemente and additional mailing offices. POSTMASTER: Send address changes to COTS Journal, 3180 Sitio Sendero, Carlsbad, CA. 92009.

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COTS Journal | February 2019