COTS Journal by RTC Media

July 2017, Volume 19 – Number 7 • cotsjournalonline.com

The Journal of Military Electronics & Computing JOURNAL

FPGA Choices Vie for Military Processing Dominance

XILINX AND INTEL PSG (ALTERA) OWN 80% OF THE MARKET SPECIAL PURPOSE APPLIANCES FUEL SINGULARITY FPGA: IT IS ALL ABOUT INTEGRATION

An RTC-Media Publication RTC MEDIA, LLC

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The Journal of Military Electronics & Computing JOURNAL

CONTENTS

COTS (kots), n. 1. Commercial off-the-shelf. Terminology popularized in 1994 within U.S. DoD by SECDEF Wm. Perry’s “Perry Memo” that changed military industry purchasing and design guidelines, making Mil-Specs acceptable only by waiver. COTS is generally defined for technology, goods and services as: a) using commercial business practices and specifications, b) not developed under government funding, c) offered for sale to the general market, d) still must meet the program ORD. 2. Commercial business practices include the accepted practice of customer-paid minor modification to standard COTS products to meet the customer’s unique requirements. —Ant. When applied to the procurement of electronics for he U.S. Military, COTS is a procurement philosophy and does not imply commercial, office environment or any other durability grade. E.g., rad-hard components designed and offered for sale to the general market are COTS if they were developed by the company and not under government funding.

July 2017 Volume 19 Number 7

FEATURED p.10 FPGA Choice Vie for Military Processing Dominance SPECIAL FEATURE FPGA From the Leaders 12

FPGA Choice Vie for Military Processing Dominance

DEPARTMENTS 6 Editorial The Future of FPGA in Military is Bright

John Koon

SYSTEM DEVELOPMENT FPGA Applications and Case Study 18

Special Purpose Appliances Fuel Singularity

FPGA: It’s all About Integration

Reducing DDR Memory SWaP is Priority for Avionics

Case Study: SoCs and FPGAs Tackle Facial Tracking—Part 2

Xilinx’s Winning Strategy in Defense Market

The Inside Track a. Interview of Intel PSG (Altera) b. Interview of Xilinx

Rick Studley, Themis Computer

Geoff Tate, Flex Logix, Inc.

Philip Fulmer, Mercury Systems

Timothy Hunter, HCL Rocheste, Denes Molner, IXI Technology

David Gamba, Xilinx

DATA SHEET The FPGA Ecosystem and Products Round up 36

Xilinx Artix-7 and Ultrascale FPGA

FPGA Boards with DRAM or 12 GB Memory

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COTS Journal | July 2017

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EDITORIAL John Koon, Editor-in-Chief

The Future of FPGA in Military is Bright

bout year and half ago, Intel spent $16.7 billion to buy Altera, one of the leaders in field-programmable gate array (FPGA) technology. This was more than double what Intel spent when purchasing McAfee, a security company. What is in it for Intel? In the Intel Developers Forum (IDF) 2016 (also the last IDF), Intel made it clear it was seeking new markets to conquer. Only a small portion of the conference was devoted to PC. Data Centers and 5G were among the target markets. Currently Intel owes 90% of the market share but the gap is closing from competitors such as ARM (now owned by Sunsoft). FPGA provides more flexibility and functions on the chip can be reprogrammed to optimize various functions. For example, the graphic processor units (GPU) are frequently idle and consuming power. With FPGA, the GPU functions can be reprogrammed and free up other resources. Potentially, FGPA will be a key function in Data Center. What is more important, FPGA can help Intel to scale across the technology stack including Data Center, edge products, gateways and IoT things. When the acquisition occurred, Dan McNamara was put in charge of Altera now called the Intel Programmable Solutions Group (PSG) and today, McNamara is still running PSG. His vision is to deliver the next generation customized, integrated solutions for the future Data Center and IoT related business to help Intel to remain the lead in silicon. But Xilinx is still the king of FPGA with estimated annual revenue of $2.3 billion. Its products cover a broad range of applications include aerospace & defense, automotive, broadcast , data center, industrial, medical,

test & measurement, wired & wireless communications. The Altera/ Intel alignment may push the Intel competitor to choose Xilinx. The use of FPGA in military is just as broad including ruggedized hardware including single board computers (SBC), control, diagnostics, radar, video and communications. The fact that it is so much harder to do hardware field upgrade than, say, in an industrial environment, makes FPGA an attractive solution. Furthermore, itâ&#x20AC;&#x2122;s scalable and software configurable features can create new applications on-the-fly and increase system security. In the event of a disaster, the contents of sensible information as well as the hardware function can be wiped out clean so enemies cannot be reverse-engineered to get the top secrets. Additional benefits include built-in security features such as anti-tampering and DPA-resistant countermeasures. (See FPGA Choice Vie for Military Processing Dominance article for more details). The future of FPGA in military is bright and the growth is gradual and steady with broad applications. In this special edition of exploring FPGA, COTS Journal will interview the leaders Xilinx and Intel (Altera) on this subject. Additionally, the lead article will cover the FPGA market and other players. What may not be obvious to many is the vast number of companies participating in the FPGA ecosystems. Many SBC vendors such as Acromag, Curtis Wright, Mercury and Enclustra are using FPGA modules to build boards used in military. Third party companies in design, diagnostics, software and hardware development also participate in FPGA. In this issue, besides many FPGA articles, we try to include as many FGPA products as possible. If you are part of the worldwide FPGA participants but are left out in the inclusion, please let me know so we will include your products next time.

Figure 1 Xilinx, the leader in FPGA, offers the all programmable Xilinx VIRTEX UltraScale Plus with a migration path from the Kintex UltraScale and UltraScale Plus family.

COTS Journal | July 2017

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INSIDE TRACK Interview with Ryan Kenny of Intel Programmable Solutions Group (PSG) (formerly Altera) variants through 2.5D and tiled manufacturing flows. There are many ways for these heterogenous components to authenticate and secure one another as well, spurring investment in new boot and protection technologies. 2. Describe the “state of the art” and key benefits of Altera’s high-end, advanced line of FPGA products.

Ryan Kenny is a strategic marketing manager in Intel’s Programmable Solutions Group, and focused on the Military, Aerospace, and Government business. His career has included work in Air Force acquisitions, and FPGA-based system development in space and communications systems while at Lockheed Martin. He holds Master degrees in Electrical Engineering and Business.

1. How does FPGA impact military embedded systems design? What will FPGA look like in 5 years? FPGAs have long been an important tool in the toolbox of heterogenous computing in high performance computing and data centers, but now heterogenous solutions are finding their way into the field and data endpoints as well. This has driven the development of SoCs and multiprocessor SoCs as well as the ‘tile structures’ of system in package FPGA products. This in turn drives another trend towards heterogenous design, modelling, and testing multi-processor systems on higher level language design and synthesis flows. FPGAs increasingly offer more ‘hardened’ content, but users in turn demand custom

COTS Journal | July 2017

The key advantages of the Intel PSG Stratix 10 family of high performance FPGAs include domestic manufacturing, floating point hardened processing and design support, and the flexibility of Intel’s ‘EMIB’ bridge die interconnect technology. The EMIB interconnect and packaging capability provides many future variants of the Stratix 10 architecture to include in-package memory, opportunities to integrate customer ASICs and silicon, and a variety of transceiver variants and transceiver technology refreshes that don’t require a respin of the entire silicon device. Moving security into a hardened microprocessor (Secure Device Manager) also provides the FPGA with in-field firmware upgradeability to literally ‘patch’ your FPGA when security vulnerabilities are discovered in today’s ‘internet of things’ environment. 3. Describe the “state of the art” and key benefits of Altera’s costoptimized line of FPGA products. Intel PSG’s recent release of the Cyclone 10 GX family brings the military user a smaller, high performance product with advanced transceiver protocol support and advanced security features to include bitstream protection and authentication, and side channel

attack resistance. There are few low-cost solutions in the market to meet as wide an array of protocol and security standards as the new Cyclone 10 GX device. 4. Intel acquiring Altera puts Altera FPGA technology is a unique position relative to competing FPGA vendors. What is the technology “here and now” advantages to Altera FPGA customers of the Intel relationship? What are the future advantages—in terms of integrated FPGA/ Intel Processor solutions? Intel is obviously a much larger and highly integrated company with far greater investment in research and development than we had as Altera. The advantages of access to this R&D are in two places: first, in the development of intellectual property and silicon features across all of Intel’s product lines. This IP spans areas of communication protocols, storage, security, virtualization, and accelerators of all kinds, and all of it is now available for inclusion in the FPGA roadmap. The second place this R&D brings value to FPGA customers is investment in software development capabilities for CPU + FPGA systems, virtualization, and libraries of accelerators that automate both the software component and the FPGA accelerator component. The future of the Intel data center is to enable customers to easily develop and port applications to hybrid processor systems, and we will bring this same ease of use to military customers developing across multiple processing topologies. All of this is on top of the most obvious advantage we provide through vertical integration: early access to the world’s

most advance chip manufacturing facilities and advances to drive even higher speed and higher density FPGA and SoC products. 5. Can you give an example of a military application (it can be specific customer or a general application category) where Altera FPGAs are particularly well suited? Military and intelligence agencies have enormous data storage and retrieval requirements, and they’ve been accelerated even more by developments in machine intelligence and ‘big data’ analysis initiatives. This has created demand for FPGA-driven products by Secturion Systems, including the DarkStor high speed and failsafe encrypted storage system and the DarkLink 10/40/100G MACsec link encryptor. Although software and processor encryption dominates the cloud and datacenter industry, FPGA-based hardware encryption and accelerators fill the Government and military niche far better. Intel FPGAs are the right silicon technology to meet the demanding reliability, failsafe, and real time requirements of sensitive intelligence data, and provide field upgradeability to hardware that will see longer mission life than traditional network support equipment. Built-in FPGA security features, as well as additional system security designed into the systems by Secturion, provide military-grade system protection as well. Intel Programmable Solutions Group (PSG) (formerly Altera) San Jose, CA. (408) 544-7000 www.altera.com

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INSIDE TRACK MILITARY MARKET WATCH Interview with David Gamba of Xilinx

David Gamba is the Senior Director of Xilinx’s Aerospace and Defense Vertical Marketing team and has worked in the programmable logic industry for 16 years. He has led teams that introduced revolutionary PLD industry firsts such as OpenCL and Hard Floating Point, which resulted in the first ever high-volume programmable logic acceleration deployment in the data center. 1. How does FPGA impact military embedded systems design? What will FPGA look like in 5 years? The importance of SWAPC continues to increase in military embedded system design, requiring architects and designers to search out improved approaches for increasing integration while controlling costs. Xilinx All Programmable FPGAs continue to offer architects and designers the ultimate in flexible, high performance, low power integration capabilities, advancing from the basic logic, memory, DSP and SerDes building blocks from a couple of years ago to now including the software programmability of ARM-based FIND the products featured in this section and more at

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COTS Journal | July 2017

processors, greatly increased memory capacity with integrated gigabyte memories and brand new capabilities such as high-speed RF and mixed-signal processing. Additionally, the security capabilities of Xilinx All Programmable FPGAs such as anti-tamper (AT) and information assurance (IA) continue to advance at an accelerated rate, helping to address the increasing security needs of military embedded systems. Future Xilinx All Programmable FPGAs will continue to integrate more functionality and capabilities along with additional enhancements to security capabilities. The future Xilinx FPGAs in military embedded systems will also evolve from being intelligent devices to self-learning devices using machine learning. These devices will leverage the advanced capabilities along with partial reconfiguration and in-field upgrade capabilities to create adaptable military embedded systems which can easily morph to address changing needs while still meeting the stringent SWAPC requirements of these systems. 2. Describe the “state of the art” and key benefits of Xilinx’s high-end, advanced line of FPGA products. Based on the UltraScale architecture, the latest Virtex device families provide the highest performance and integration capabilities in both planar and FinFET nodes, including the highest serial I/O at 56G, the highest signal processing bandwidth at

21.2 TeraMACs of DSP compute performance, and the highest logic capacity at 5 million System Logic Cells. They also deliver the highest on-chip memory density with up to 500Mb of total on-chip integrated memory, plus up to 8GB of HBM Gen2 integrated inpackage for 460GB/s of memory bandwidth. Virtex devices pack a punch with integrated IP for PCI Express, Interlaken, 100G Ethernet with FEC, and Cache Coherent Interconnect for Accelerators (CCIX). Xilinx All Programmable 3D ICs utilize stacked silicon interconnect (SSI) technology to break through the limitations of Moore’s law and deliver the capabilities to satisfy the most demanding design requirements. Third-generation 3D IC technology provides registered inter-die routing lines enabling >600 MHz operation, with abundant and flexible clocking. As the industry’s most capable FPGA family, the devices are ideal for applications ranging from 1+ Tb/s networking, smart NIC, machine learning, and Data Center Interconnect, to fullyintegrated radar/early-warning systems. 3. Describe the “state of the art” and key benefits of Xilinx’s cost-optimized line of FPGA products. The Xilinx All Programmable Cost-Optimized Portfolio comprises five families that are optimized for specific capabilities: • Spartan-7 devices offer the best in class performance per watt,

small form factor packaging and feature the MicroBlaze soft processor running over 200 DMIPs with 800Mb/s DDR3 support built on 28nm technology. These devices are ideal for industrial, consumer, and automotive applications. • A rtix-7 devices provide the highest performance-per-watt fabric, transceiver line rates, DSP processing, and AMS integration in a cost-optimized FPGA. This family is the best value for a variety of cost and power-sensitive applications including software-defined radio, machine vision cameras, and low-end wireless backhaul. • T he Zynq-7000 All Programmable SoC (AP SoC) family integrates the software programmability of an ARM-based processor with the hardware programmability of an FPGA. The Zynq-7000 family is the best price to performance-per-watt SoC platform for your unique application requirements. • Spartan-6 devices offer industry leading connectivity features such as high logic-to-pin ratios, small form-factor packaging, MicroBlaze soft processor, 800Mb/s DDR3 support, and a diverse number of supported I/O protocols. These devices are ideally suited for a range of advanced bridging applications found in automotive infotainment, consumer, and industrial automation. • T he CoolRunner-II and XA CoolRunner-II 1.8V CPLD families lead the industry with their high-performing, low-power ca-

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INSIDE TRACK MILITARY MARKET WATCH pabilities in a single-chip, instanton, nonvolatile technology. 4. Can you give an example of a military application (it can be specific customer or a general application category) where Xilinx FPGAs are particularly well suited? Xilinx All Programmable aerospace and defense solutions outperform other alternatives in addressing today’s Spec-

trum threats, which demand significant compute density and products that meet their SWAPC requirements. Xilinx’s All Programmable devices allow the platform to remain relevant in the era of ‘Gorilla Electronic Warfare’. For example, a new RADAR developed with Xilinx solutions may sometime be jammed, spoofed and attacked. Because Xilinx All Programmable devices are used, the RADAR can change

its waveforms and algorithms utilizing Xilinx’s widest and fastest DSP blocks and agnostic IOs. An alternative solution like an ASIC would prevent the math from ever changing, thus limiting the RADAR’s response time to the new threats. Xilinx is also leading the way with its offering our All Programmable RFSoCs – 16nm FinFET technology that monolithically embeds world-class analog ADCs

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COTS Journal | July 2017

SPECIAL FEATURE FPGA Choices Vie for Military Processing Dominance

COTS Journal | July 2017

SPECIAL FEATURE

FPGA Choice Vie for Military Processing Dominance The field programmable gate array (FPGA) technology has come a long way since its invention by co-founder, Ross Freeman, of Xilinx in 1984. No longer is the application limited to only PC computing, its broad range of applications include aerospace & defense, automotive, broadcast , data center, industrial, medical, test & measurement, wired & wireless communications. John Koon, Sr. Editor

ts application in military is gaining momentum for many different reasons. Xilinx and Altera (acquired by Intel in 2015) are the major players followed by Microsemi, Quick Logic and Achronix (not in order). We have done extensive interviews on all five companies to give you the latest updates on the development of FPGA in military.

Why FPGA is Suitable for Military Embedded System Design? As we all know, the design considerations of Size, Weight, Power and Cost (SWaP-C) are always a challenge and a balancing act. FPGA is no exception. Other top reasons cited for choosing FPGA are flexibility, higher level of security, and better performance per watt (includes deterministic and parallelized low-latency capability). Additional comments

COTS Journal | July 2017

SPECIAL FEATURE

Figure 1 Intel PSG Stratix10 and Cyclone10 GX families include domestic manufacturing, floating point hardened processing and design support.

include FPGA provides partial reconfiguration capabilities and can perform better for a narrow set of pre-defined compute functions. It is very important in the battle field and related missions for systems to be field programmable and upgradable easily. As security is becoming more and more critical, FPGA helps increase the level of security in connectivity in cyberspace as well as self-destroyed when deemed necessary. With reduction in size through integration, costs can be expected to decline overtime and that is good news. For years, hackers and enemies have launched the Simple Power Analysis (SPA) and Differential Power Analysis (DPA) attacks. The cryptography research division of Rambus has developed a fundamental solutions and techniques to protect against such attacks, along with supporting tools, programs, and services. Many companies including Microsoft, Broadcom, Qualcomm, Boeing and NVIDIA, have obtained licenses from Rambus to use this countermeasure method and Microsemi was the first company to license this.

How FPGA Products Are Used in Military Applications In a conflict engagement, the enemy may jam, spoof and attack the hardwired RADAR system and paralyze it. When 14

COTS Journal | July 2017

Xilinxâ&#x20AC;&#x2122;s All Programmable devices are used, the RADAR can change its waveforms and algorithms utilizing Xilinxâ&#x20AC;&#x2122;s DSP blocks and agnostic IOs to overcome the problem. Big data is another application. Military and intelligence agencies have enormous data storage and retrieval requirements, with new use of machine-to-machine communication, machine learning and intelligence, demand for big data analytics will drive

demand for Intel PSG (Altera) based, military grade Big Data Storage Security systems (DarkStor and DarkLink) provided by Secturion Systems. These systems support speed up to 100-Gbps in full-duplex mode. Secturion Systems is an Intel PSG (Altera) OEM specializes in end-to-end cloud security. Intel is a big pusher of firmwarebased security, it is expected that some of these technologies will be implemented in future development of Intel PSG (Altera) products. If sensor processing is required in many of the military applications, then Quick Logic has just the solutions. They integrated sensor processing in the FPGA makes it simple for users. In embedded military autonomous vehicle applications where safety-critical systems operation and security is required, Microsemi FPGA will come in handy. Often systems need to operate in contested environments where an adversary is actively spoofing, tampering, and/or trying to disable or degrade system capability. Microsemi FPGAs are architected to achieve the above goals and provide single event upset (SEU) immunity in the device configuration and fault tolerant hardware design. In the event a defense system is compromised, the anti-tamper protections ensure mission-critical customer intellectual property is safe and secure from adversary compromise.

Figure 2 Coveloz offers the BACH development kit which helps developers diagnose the Intel PSG (Altera) Cyclone-based, multi-protocol, AES67 audio networking (RAVENNA, NMOS, AES67/ Dante compatible) products.

SPECIAL FEATURE

Figure 3 Achronix’s Speedster22i FPGA is a standalone FPGA designed for high performance wireline applications. The hardened IP provides communication interfaces including multiple 100G Ethernet ports, 100G Interlaken ports, PCIe gen3 x8 and up to 6 DDR3 controllers.

FPGA Solutions From the Leaders Xilinx is the leader of FPGA and has always been the first one to bring out new technology like the 20 and 16-nanometer products. History is about to occur again with the 7—nanometer development. Today, Xilinx offers the high-end UltraScale architecture based Virtex families and five cost-optimized portfolios including the Spartan-7, Artix-7, the Zynq-7000, Spartan-6 and the CoolRunner-II. Intel PSG (Altera) offers the Intel PSG Stratix 10 and Cyclone 10 GX families include domestic manufacturing, floating point hardened processing and design support. Figure 1 and 2. (See details in Xilinx and Intel PSG (Altera) interviews). QuickLogic’s EOS S3 sensor processing system is a multi-core SoC which enables a wide range of concurrent sensor applications from simple processing to computationally demanding algorithms for smartphone, wearable and IoT applications. The integration of programmable, processing, memory and interface IP provides the benefits of low power consumption to achieve the sophisticated, context-aware and always-on functions. QuickLogic’s latest addition includes the embedded FPGA (eFPGA) which can be integrated into other SoC designs. This allows post-fabrication changes, power optimization and reduces chip-to-chip delays between FPGA and SoC. Achronix’s Speedster22i FPGA is a standalone FPGA designed for high performance wireline applications. The hardened IP provides communication interfaces including multiple 100G Ethernet ports, 100G Interlaken ports, PCIe gen3 x8 and up to 6 DDR3 controllers. Additionally, Achronix offers the eFPGA, Speedcor technology, which can be customized to be a fix point DSP or floating point DSP function (in machine learning application), parallel engine (in convolution neural network application) or customized

COTS Journal | July 2017

SPECIAL FEATURE unique memory architectures in Speedcore IP ( for distributed TCAM application). Figure 3. During system operation, cryptographic calculations performed in an integrated circuit (IC) will soon reveal the secret key through a side channel unless countermeasures are used. Microsemi’s SmartFusion2 and IGLOO2 FPGA (the first

FPGAs with licensed DPA countermeasures from Rambus) product families have built-in DPA-resistant countermeasures for bitstream protection. Additionally, by passing the CRI-accredited third-party security test performed by Riscure, Inc., Microsemi has been granted the use of the “DPA padlock” security logo in conjunction with these devices. Figure 4.

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In cybersecurity, the security key management is important. During the manufacturing process, it is easy for the security key of a device to be duplicated. Licensed from Intrinsic ID, BV, Microsemi has developed a physically unclonable function in the SmartFusion2 and IGLOO2 FPGA families. Based on the intrinsic device-to-device differences generated randomly during the manufacturing process to create a unique secret ID, or “fingerprint” to derive a repeatable AES-256 “key-encryption” key used for wrapping and storing other keys. As a result, the device will be unclonable because of its unique “fingerprint”.

What Will the Future Look Like? FPGA will continue to evolve and improve for the military applications. The trends can be summarized in five points. • More advanced integration will take place. Size, weight and power – cost (SWAPC) will continue to be the driving force of military embedded system design and push for more integration of advanced functions including DSP, software programmability of ARM-based processors, gigabyte memories, and brand new capabilities such as high-speed RF and mixed-signal processing. • Continued demand for better security. All FPGA will include many built-in security measure such as anti-tamper (AT) and information assurance (IA). Other functions such as cryptologically-secured supply chain risk management processes as well as on-chip security monitoring and firewalls. As pointed out by Paul Quintana, Director Military Vertical Marketing, Microsemi , “We have seen more functional capabilities at lower power today than FPGAs of 5 years ago and this trend will continue”. • Mobility will grow. It will continue to drive demand in the area of combat wearable and battery powered devices and IoT sensors. Expect to see more and more lower-power FPFA-based devices and as more advance functions and IP integrated, device will become less power hungry as well. • FPGA Products will be easier to use. With machine learning to aid the development of natural language processing, object de-

SPECIAL FEATURE

Figure 4 Microsemi’s SmartFusion2 and IGLOO2 FPGA families are designed based on the intrinsic device-to-device differences generated randomly during the manufacturing process to create a unique secret ID or “fingerprint” to ensure the devices be unclonable.

tection, threat assessment, robotic controls, sensor fusion and more, FPGA will become easier to use, according to Steve Mensor, VP of Achronix. • Military intelligence such as that used by the Army requires big data analytics and big data center. FGPA is expected to play a key role here. As logistic planning, battle campaign strategy development, enemy scouting, cybersecurity and IoT sensor generating more and more data, demand for FPGA will continue to grow.

Conclusions In this article, five leading companies have provided their input regarding the current and future development of FPGA in the embedded military applications. From PC applications in the early days, FPGA have evolved and are now used in many new applications including military. The article went on to explain why FPGA is suitable for military use with examples and end with an observation of what future FPGA will look like.

COTS Journal | July 2017

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SYSTEM DEVELOPMENT FPGA Applications and Case Study

Special Purpose Appliances Fuel Singularity Since the early 1980’s each next-generation system architecture has exhibited the characteristic of physically collapsing to the next highest level of integration. Parallel bus structures provided physical support, power and signaling to enable a building block approach to developing solutions – especially for embedded computing platforms. What is next? Rick Studley, CTO of Themis Computer

MEbus was the most successful of the embedded, parallel bus systems, having been in wide spread use from at least 1983 through 2005. While VMEbus products may remain available out through the year 2020, its days are more than numbered. VMEbus, and follow-on products from Sun Microsystems and others are illustrative of the characteristic integration mentioned above. In 1983, a VME system was typically configured w/ a CPU, DRAM, EEPROM, SRAM, Disk Controller, Serial Mux and many other assorted IO boards. Configuring these systems was a challenge and there was no dominant leader in embedded SW space until VxWorks and the emergence of Linux. In circa 1987, Motorola introduced the MVME 147 Single Board Computer that combined CPU, DRAM, SCSI controller, SIO, PIO and EPROM on a single-slot VME board. Similar Single Board Computers followed from Force Computers, Themis Computer and others. In the late 1980’s and through the 90’s Sun Microsystems & Ethernet emerged as a threat to both embedded board suppliers with their parallel bus structures, and mini computer manufacturers with their closed and proprietary architectures – eventually challenging small main frames. Arguably, it was Sun Microsystems that introduced the 1U Blade, or “pizza box”, a self-contained, network based computer of a configuration 18

COTS Journal | July 2017

“When the network is as fast as the computer’s internal links, the machine disintegrates across the net into a set of special purpose appliances” – George Gilder, 2001 commonly deployed today. In Sun’s hay day, one of their common taglines was, “the network is the computer”, and ironically that was the problem. General-purpose processors (CPUs) will soon reach the physical limits of Moore’s Law. Memory & TB storage capacity are commodities for most users and PCI Express, Ethernet (TCP/IP), Microsoft Windows and Linux are ubiquitous. In 2017 the network “problem” has largely been solved with availability of contemporary high speed, non-blocking fabrics, analogous to crossbar switches formerly confined to chips, boards and backplanes. A singularity has been reached as George Gilder predicted more than 15 years ago. Coincident with widespread adoption of resilient Equal Cost, Multi-Path (ECMP) fabrics, a series of seismic shifts have been occurring across the IT landscape. Leading among these are in the areas of: • Social Media • Cryptography & Cryptanalysis • Big Data Analytics

• Artificial Intelligence • Virtual & Augmented Reality • Autonomous vehicles

The core enabler for the expanding role of virtually every one of these technologies is the emergence of hybrid computing platforms. New server architectures from, (e.g.) Intel and IBM now or will soon accommodate closely coupled co-processors, or application accelerators, in the form of a General Purpose Graphics Processing Unit (GPGPU) and Field Programmable Gate Arrays (FPGAs). Today, RDMA and GPU-direct protocols facilitate transferring intermediate results directly from (e.g.) GPU to GPU with minimal host involvement. The problem with conventional computer architectures is that they are increasingly economically incapable of scaling to meet the challenges of many signals processing; artificial intelligence; augmented reality; big data analytics and autonomous vehicle applications. Hence the focus on GPGPUs and FPGAs as accelerators for ap-

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Figure 1 Use of existing FPGAs and GPGPUs have demonstrated the ability to speed up an almost unlimited range of applications; speech recognition, digital signal processing, medical imaging, bioinformatics, data mining and more.

plications that can leverage “embarrassingly parallel devices” to augment Industry Standard COTS infrastructures in very cost effective ways. With current technologies, hybrid architectures can yield better than a 10x price/performance advantage over conventional architecture solutions. Different applications place different demands on compute resources. Applications that work well on one processor may be largely unsuitable to another. This may also be true for distinct phases within a single application. GPGPU and FPGA accelerators’ extensive parallel computing resources and

increasingly programmer-friendly development environments make them a good fit for accelerating compute-intensive and data parallel parts of an application. FPGAs and GPGPUs are at the end points on the spectrum of possible accelerators. Either, or together, they often achieve better performance than CPUs on specific workloads. FPGAs are highly customizable, while GPGPUs provide massive parallel execution resources and high memory bandwidth. When mapping application-to-accelerator, the following factors should be taken into consideration: • Programmability

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COTS Journal | July 2017

SYSTEM DEVELOPMENT

Figure 2 The military utilizes rugged high performance servers with GPGPUs, such as the Themis RES-NT2, for SIGINT, desktop virtualization, and image processing.

• Performance • Programming cost • Sources of Overhead in design flows In the case of “overhead in design flows”, current instantiations of accelerators are typically PCI Express based add-in boards. New, high-speed buses have also emerged (e.g., NVlink, OmniPath and CAPI), and future multi-chip hybrid packages or on-chip devices will reduce communications overhead by placing CPU and accelerator on the same high speed busses, and in the same memory domain.

GPGPUs or FPGAs? GPGPUs and FPGAs are already widely used and the differences between CPU, GPGPU and FPGA are easily understood and basic comparisons are simple. The problem lies in which to use when. To understand, first requires an understanding of which application maps well to each accelerator, and what, if any issues arise in an acceleration methodology. Many of today’s workloads are significantly different from workloads traditional CPUs were designed to handle. For example, Big Data and Machine Learning code size is typically measured in thousands of Lines of Code (LOC), orders of magnitude fewer LOC than traditional applications, but with data to be processed increasing at an exponential rate. 20

COTS Journal | July 2017

As a result: • Workload processing required for (e.g.) Big Data and Machine Learning differ from traditional applications that sometimes measured in the millions of LOC. In this case, performance comes from replicating this code across many servers • The amount of data to be processed is increasing at an exponential rate, is streaming in nature and, in many cases, has real-time response requirements (e.g., autonomous vehicles) • For many years the semiconductor industry has been giving us exponential increases in transistors per chip (Moore’s Law) • With only linear increases in compute performance with each new generation of processor To meet this challenge, hybrid processing architectures, more suited to these types of workloads are gaining ground by offering application access to dedicated accelerators with thousands of scalable, massively parallel compute nodes on a single chip or array of devices. The solution: rather than speed up a few cores, add a massive number of cores for those data sets, or phases of an application that can take advantage. Common solutions integrate GPGPUs and/or

FPGAs with COTS processors to handle these specific workloads. In general, use of existing FPGAs and GPGPUs has demonstrated the ability to speed up an almost unlimited range of applications, some of which are seen in figure 1. When evaluating applications, there may seem to be considerable overlap in general terms – e.g., FFTs, Digital signal processing, bioinformatics, medical imaging, etc. GPUs are SIMD machines, inexpensive, commodity parallel devices with huge market penetration as accelerators for a large and growing number of applications. GPGPUs feature two particular strengths: raw compute (FLOPS) and high memory bandwidth. Most difficult computational problems fall within these two categories. FPGAs are typically best for streaming operations on data sets where the use of some sort of fixed-point computations (or, possibly block floating point – which is sort of a fixed point operation) is sufficient. Historically, floating point operations kill FPGAs, as do any kind of history based processing where the historic data is more than a few Kbytes. FPGAs are generally unsuitable for Overlapped FFTs, (i.e., where you use some new data and some old data) as is any processing with conditionals or branching is also unsuitable for FPGAs. GPUs are also not good at handling the sort of history data as described in an Overlapped FFT, and some instances it may be better to do the overlap in a CPU and then move the data. Any hybrid computing strategies must be weighed against associated latencies that may be incurred. In order to maximize the value of a GPU, the problem set should be such that you can use all or most of the cores in a GPU, and there are two ways to achieve this: 1. Ensure the data size for each function performed is large. E.g., a very large FFT (> 1K point) might be able to use many of those cores; 2. Block processing. E.g., collect enough data to do (n) number of FFTs, where that number of FFTs, of a particular size, allows you to actually exercise most, if not all of the cores in the GPU The challenge for #1, above is obvious, the problem for #2 is that this increases pro-

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SYSTEM DEVELOPMENT cessing latency, which may be unacceptable. If neither is achievable, you will be dealing with a relatively high power device that burns a considerable amount of power even if you are not using all the cores and, in this case, an FPGA may be a better answer.

Programmability Programming methodologies range from direct hardware designs for FPGAs, through assembly and domain specific languages, to high-level languages by GPGPUs. A significant challenge is to understand application behavior on each accelerator model to determine how to partition an application into phases that may then execute on available accelerators in the most efficient and cost-effective way. GPGPUs, such as those found in the Themis RES-NT2, are flexible and “easy” to program using high level languages and APIs that abstract away hardware details. Compared with hardware modifications in FPGAs, changing functions is as straightforward as rewriting and recompiling code. NVIDIA CUDA and OpenCL are language APIs and development environments for programming GPGPUs. GPUs implement data-parallel portions of applications by assigning each thread the task of processing one data point. Threads are independent and execute in parallel. Domain specific libraries can be used as building blocks to ease parallel programming on the GPU. These high level languages have the advantage of not requiring programmers to master domain-specific languages to program the CPU. For example, CUDA is an extension of C and an associated API for programming general-purpose applications for all NVIDIA GPGPUs – once an application has been developed, it will remain portable to nextgeneration GPUs. The programming model for a CUDA kernel is scalar, not vector. In CUDA, the GPU is treated as a co-processor that executes data-parallel kernels with thousands of threads. Threads are grouped into thread blocks. Threads within a block can share data using fast shared-memory primitives and synchronize using hardware-supported barriers. Communication among thread blocks is limited to coordination through much slower global memory. FPGAs consist of hundreds of thousands of programmable logic blocks and

programmable interconnects that can be used to create custom “soft core” logic functions. Many FPGAs include some hardwired functionality for common functions, for example, the inclusion of complete “hard core” ARM processors. FPGAs are mostly programmed using hardware description languages such as VHDL and Verilog. VHDL is a hardware description language supporting the description of circuits at a range of abstraction levels varying from gate level netlists up to purely algorithmic behavior. Very efficient hardware can be developed in VHDL, but it requires a good deal of programming effort. There is a growing trend to use highlevel languages such as SystemC and Hadel-C, or even OpenCL, to raise FPGA programming from gate-level to high-level, modified C syntax. It’s important to understand the limitations with these languages, e.g., Handel-C does not support pointers and standard floating point. No free lunch. The flexibility of programming a GPGPU comes at a cost. GPGPUs offer many processing cores with thousands of hardware thread contexts executing programs in a single program, multiple data (SPMD) fashion. They provide a large block memory architecture highly optimized for bandwidth such that they achieve performance by executing multiple hundreds of threads running simultaneously. GPU memory is highly optimized for bandwidth because the GPU programming model requires data be copied to memory before it can be processed, which means two extra memory operations (one write and read). GPUs are power efficient only if all, or a large number of cores are used, and most current accelerators work in separate memory spaces from their control processors. System throughput is heavily dependent on data transference from main memory to device memory via PCI Express bus. Data copy latency increases linearly with the size of the transferred data, which has potential to adversely impact overall performance. Transferring data to and from global memory precludes a true streaming approach to data processing. Future hybrid systems will have CPU and GPU in the same domain and that memory transfer will not be required. Problems that don’t map well to GPGPUs are generally too small or too unpre-

dictable and may map more effectively to FPGAs. Very small problems lack the gross parallelism required to use all the threads on a GPGPU or alternately fit within the lowlevel cache of a CPU. Unpredictable problems have too many meaningful branches that may prevent data from efficiently streaming from GPU memory to the cores, or they reduce parallelism by breaking the SIMD paradigm. Examples of these types of problems include: • Most graph algorithms • Sparse linear algebra • Small signal processing problems (FFTs smaller than 1K points) • Search • Sort As the industry approaches the limits of Moore’s Law, the data processing domain will increasingly become a more tightly integrated hybrid entity. Disparate processing elements will take advantage of common, cache-coherent high-speed inter-CPU links and a common memory space. While this hybrid CPU/accelerator module will in many instances require use of the highest speed links in the system, it will remain just as much an appliance as: graphics, IO, storage and special function devices on the fabric – whether that fabric is PCIe Fabric, Ethernet or Infiniband. Software-defined data center technology and high performance ECMP fabrics will enable re-aggregation of these special purpose appliances into a specific system as required by the application. Themis Fremont, CA. (510) 252-0870 www.themis.com

COTS Journal | July 2017

SYSTEM DEVELOPMENT FPGA Applications and Case Study

FPGA: It’s all About Integration The FPGA industry is undergoing a major transition and like other high-tech markets, integration is the key driver. Geoff Tate, CEO of Flex Logix, Inc.

ntil recently, FPGA chips have stood alone on PC boards surrounded by processors and memory. However, it’s now clear that integrating this technology is the next logical step to advancing chip design. At first, only FPGA companies were playing in this trend. In 2011, Xilinx introduced the first all programmable SoC integrating an FPGA with a microprocessor system. In 2016, Intel bought Altera to integrate FPGA with Xeon processors. More recently, other suppliers have emerged with embedded FPGA solutions in both soft and hard IP across a range of process nodes. The suppliers include Achronix, Adicsys, Efinix, Flex Logix, Menta and Quicklogic. Foundries supported include TSMC, GlobalFoundries and SMIC from 65nm to 14nm with embedded FPGAs from 100 LUTs to >100K LUTs in size.

When Embedded FPGA Makes Sense If an existing FPGA SoC meets customers’ requirements, integrating embedded FPGA may not be needed. However, there are many advantages to embedded FPGA, especially for aerospace/defense customers who purchase about 10% of all FPGAs today. The ability to reconfigure RTL at any time can eliminate expensive chip spins, enable one chip to address many customers and applications, and extend the life of chips and systems. Other advantages include the following: 24

COTS Journal | July 2017

Figure 1 The EFLX can be converted to a Rad-Hard embedded FPGA as they both use the standard cell library

- Eliminates packaging and power-hungry SERDES for smaller, lighter, lower power solutions. - Provides customers with the exact size FPGA they need. - Provides the exact options customers need, in the right amounts. Customers can get MACs (multiplier accumulators) and embedded RAM of any type and size. While traditional FPGA is only dual port, embedded FPGA can support single port, any width and parity and/or ECC. - Enables chip designers to use process node/ foundries in the US, whereas traditional FPGAs are only manufactured in Asia. - Comes as radiation-hardened whereas FPGAs are just radiation tolerant.

to >100K LUTs with optional MACs and embedded RAM of any kind. Typical porting time for EFLX to any process node including US foundries and Trusted Foundries is 6 months. It can also be converted to a Rad-Hard embedded FPGA as they both use the standard cell library. Additionally, the patented programmable interconnect, EFLX has density similar to full-custom designs from Xilinx and Altera (measured in LUTs/square millimeter). See figure.

Summary

EFLX Embedded FPGA

The trend towards integrating embedded FPGA into SoCs is rapidly increasing. Just like ARM saw its embedded processor IP become integrated on nearly every logic chip today, embedded FPGA will undergo that same market proliferation.

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SYSTEM DEVELOPMENT FPGA Applications and Case Study

Reducing DDR Memory SWaP is Priority for Avionics Military avionics systems demand high-speed DDR4 memory that’s both ruggedized and geared for low size, weight and power (SWaP) requirements. Philip Fulmer, Director of Product Marketing Mercury Systems

o address the broad range of perils faced by the modern war fighter, defense electronics are growing increasingly sophisticated with a wide range of sensor subsystems detecting, analyzing, and responding to potentially threatening scenarios. To do so, each of these subsystems requires data acquisition, digitization, processing, and storage modules. These highly complex subsystems together yield a massive volume of data to be processed in short periods of time. From a system-level architecture perspective, designers face a dilemma where they must integrate additional components and circuitry into a fixed allocation of board space. Missions, particularly in avionics operations, require smaller and lighter weight form factors. This constraint drives the designer towards the challenging goal of adding even more sensor functionality while reducing overall system size and weight. Also, system performance while processing this large data volume may be constrained by a heavily taxed memory hierarchy, resulting in data transfers from high-speed memory to lowspeed memory. Many mission objectives can only be achieved with higher capacity, high-speed memories more tightly packed into the smallest of physical footprints.

COTS Journal | July 2017

State-of-Art in Memory A state-of-the-art system configuration includes at least one processor and/or FPGA with fourth-generation double data rate (DDR) SDRAM. Figure 1a displays eighteen discrete DDR4 devices of 1 Gbyte capacity each used to provide a total of 16 Gbytes of DRAM supporting the application’s processing requirements with error correcting code (ECC). The eighteen devices are equally distributed over the available two-dimensional board space available to the designer.

Mercury Systems’ packaging technology exploits the unused third dimension by vertically stacking and connecting memory in a low-profile, highly ruggedized package, as shown in Figure 1b. By replacing seventeen individual 1 Gbyte DRAM devices with one Mercury memory device, space savings of 75 percent are achieved; the system designer is now free to use the newly available 75 percent board space for placement of other components needed to integrate additional sensor functionality without over-

Figure 1 (a) Conventional 16 Gbyte memory solution with discrete devices. (b) Mercury’s spacesaving 16 Gbyte high density secure memory device with integrated error correcting code.

A46_CotsJrnl_2-25x9_875V8_A45.qxd 3/24/17 1:58

SYSTEM DEVELOPMENT

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Figure 2 With each successive generation of DDR memory, Mercury has refined its miniaturization technology to offer improved densities.

burdening the memory hierarchy.

Embedding Security and Trust Semiconductor memory is an important commodity used in the construction of packaged memory devices, including discrete memory devices and multi-chip modules containing multiple die in a single package, including Mercury’s high-density memory product offerings. The commercial market has no shortage of suppliers capable of producing commercial-, industrial-, and automotive-grade memory solutions in chip package form. However, the majority of these suppliers manufacture their products outside of the United States. Of particular concern, some are in close proximity to highly unpredictable foreign governments. Although this is of no consequence during extended times of peace, supply chain continuity is far from assured in the event of a military conflict in or around these tumultuous regions. To provide the highest degree of supply chain continuity, semiconductor memory should be sourced exclusively from trusted domestic corporations. The same scrutiny should then be applied to vendors of other materials and components used in the manufacturing process of these memory products. Through judicious selection of supply chain vendors, security and trust can be embedded into the bill of materials of any military component.

Security of commodity components, however, is insufficient to produce a truly secure and trusted memory product for a defense application. As an additional layer of security, Mercury’s memory devices are designed and manufactured in a Defense Microelectronics Activity (DMEA) trusted facility. This facility also maintains AS9100, ISO 9001, JESTD001, and IPC 610 Class 3 certifications. Furthermore, Mercury’s commitment to industrial security excellence is evidenced by the Company’s 2016 James S. Cogswell Outstanding Security Achievement Award from the Defense Security Service. Mercury’s most popular memory products are based on DDR memory technologies. With each successive generation of DDR memory, Mercury has continued to refine its miniaturization technology to offer improved densities without compromising data transfer rates (Figure 2). Mercury’s DDR4 products even include decoupling capacitors and calibration resistors pre-integrated into the package. Figure 3 graphically displays the density improvement, expressed in Gbytes of capacity per square millimeter of physical footprint, attained with advances in packaging technology. The simultaneous reduction in physical footprint with higher memory capacities with each successive generation of DRAM technology further reduces size and weight burdens on avionics computing systems.

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COTS Journal | July 2017

SYSTEM DEVELOPMENT

Figure 3 Advances in military-grade packaging technology have been introduced with each successive generation of DDR memory technology to offer advances in memory density.

Mitigating the Risk of Failure Although Mercury’s memory products are precision engineered to withstand harsh operating environments, special attention has also been provided to the mechanical and electrical interface between the device and the customer’s printed circuit board.

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second-level board reliability. Every memory device manufactured by the company is subjected to burn-in and electrically tested to ensure only the highest quality product is shipped to customers. For applications requiring extended temperature qualification or other custom environmental testing, Mercury partners closely with customers to deliver product screened to application-specific requirements. Nothing is more catastrophic to a military program than sudden and unexpected obsolescence issues disrupting supply continuity. It’s important to make every effort to support long-term platforms until raw materials are no longer available. With well-established customer relationships and endof-life business processes, Mercury offers component end of life management with last-time buy opportunities. In many cases, form-fit-function compatible replacements can be custom engineered.

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Advances in packaging technology now enable military-hardened memory devices to be commercially manufactured in spacesaving footprints. System-level architects designing tomorrow’s advanced avionics computing platforms now have the freedom to scale up the memory available for data processing while simultaneously reducing size, weight, and power. Manufactured in a DMEA-trusted facility, Mercury’s high density secure memory solutions offer uncompromised security and trust integrated throughout the entire product life cycle. Mercury Systems is currently engaging with customers in design opportunities that require DDR4 performance levels in highly constrained physical environments or harsh operating environments. The specifications of Mercury’s DDR4 products are subject to change as designs are finalized through collaborative initiatives with customers. As

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SYSTEM DEVELOPMENT FPGA Applications and Case Study

Case Study: SoCs and FPGAs Tackle Facial Tracking—Part 2 A facial tracking system design example examines the issues and tradeoffs of using FPGA technology versus other alternatives in a power-constrained environment. Timothy Hunter, Principal Engineer, HCL Rochester Denes Molner, Engineering Director, IXI Technology

This is Part 2 of a two-part article series. Part 1 appeared in the June issue of COTS Journal.

hile Part 1 in this article series explored the performance and cost benefits through optimal functional partitioning, the next requirement to examine is energy consumption. Energy is the time integral of power consumption. It is important to properly size a system to meet both the peak power and average energy requirements. Embedded computer systems that are powered directly from the grid, are typically less constrained from an energy consumption point of view. In particular devices that remain continuously “on” are expected to enter a low power or sleep state very quickly when the device is idle. Further, devices that are networked may also require quick wake-up times to return to an operational state. While some of these market specific requirements may not apply to embedded computer systems, the general need to reduce energy consumption always apply.

mon so we will not consider these in our power/energy analysis. The general purpose embedded computer solution show in the top half of Figure 1 has a x86 core processor with chipset plus an FPGA. Depending on the CPU selected power consumption ranges from 15-90W for the processor alone. The optimized embedded SoC show in the bottom half of Figure 1 integrates the traditional chipset functions + a dual/

quad core CPU into a single package. An external FPGA is still required to connect to a camera interface. Depending on the CPU selected power consumption is less than 10W for the SoC alone.

Dynamic Power Adjustment The key to managing energy consumption is to monitor the system operation at a regular period and dynamically reduce/turn off functions that are not re-

General Embedded vs. SoC If we look at our example of a video capture system that performs facial tracking we can simplify the embedded computer as shown in Figure 1. The camera and monitor, if so equipped, are com30

COTS Journal | July 2017

Figure 1 (Top half shows general purpose computer solution with a x86 core processor with chipset plus an FPGA. Bottom half shows optimized embedded SoC combining chipset functions and a dual/quad core CPU into a single package.

SYSTEM DEVELOPMENT

quired. Most CPU/SoC’s provide some degree of dynamic power adjustment. Intel core processor monitor processor loading and move between various “C-states” to reduce momentary power draw. Voltage and clock speeds are reduced as well as halting clocks to CPU subsystems not in use. Beyond automatic or under the hood power reductions the next level requires careful attention to system design. Powering down portions of a board or SoC can provide significant energy savings beyond simple CPU throttling. However, the designer must ensure that any remote devices that remain active are electrically isolated - an interface that is powered off on one board but connected to another board that remains powered on, can create leakage currents through ESD protection diodes in the devices I/O buffers. These reverse biased junctions or forward biased ESD diodes can partially power a chip causing CMOS latch up or even permanent damage to I/O. Also consider that the time to bring a device/interface back to a fully operational state including power up, software driver reload and configuration must be less than any maximum latency requirements for that interface. Figure 2 is an energy plot vs platform mode. A sample “workload” was created to highlight the periodic nature of an application that does work for a short burst and then remains idle for a period of time before requiring a burst of work again. As can be seen implementing a partial power off mode can result in significant energy savings, 40 percent in our example workload. Energy savings similar to this may allow a remote sensing device to operate 24 hours per day in all weather conditions or a UAV to extend its flight time by 2 hours. Partial power down does require careful system and software design.

Data Storage and Movement

Embedded computer storage and data movement requirements track closely with the need for increased performance. Worldwide Cloud storage requirements are predicted to exceed 7 Exabytes or 1018 bytes in 2017 with no reduction in the foreseeable future. IP traffic alone is estimated to exceed 8 Zettabytes 1021 bytes in 2018. To combat the increasing

volumes of data moving through networks and being stored in the cloud, the concept of “edge computing” or “fog computing” devices has gained increased attention over the past few years. In reality edge or fog computing is nothing more than distributed processing. The central idea is to push as much computing to the devices/sensors/edge of the cloud as possible which will reduce the amount of data being transferred and stored in re-

mote/centralized resources. A case in point is our example of facial tracking. The traditional model would be to have one or more cameras connected to a network where a centralized server collects, stores and processes the data. A simple HD camera operating at 30 FPS and using raw 444 formatted data will require 186 Mbytes/s. Scaling this to a 4K camera increases the bandwidth to 796 Mbyte/s transfer rate. Storing raw

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Figure 2 The graph shows an energy plot vs platform mode.

data for a one hour period would then require around 0.7 Terabytes of storage. Almost all system that capture and store video data will use 420 format which reduces the storage and bandwidth by a factor of 8. Applying H.265 VHEC encoding can provide an additional minimum compression ratio of 25:1 yielding a storage requirement of 0.1 Terabytes per day. A more elegant way might be to store data around “periods of interest”. This could be accomplished by deleting time periods where no one is in the field of view. Alternately video data could be saved when a person of interest was to enter the field of view. Facial tracking and identification must be pushed to the edge where the camera sensor is housed or first order video data stream aggregation occurs. In order to accomplish these types of optimized data processing, the embedded computer system must have sufficient compute power and local storage. Performing the initial facial tracking and optionally facial identification are the only way to reduce both the storage and bandwidth requirements of a surveillance system.

General Purpose Input / Outputs, or GPIO, requirements are product and marketplace specific. GPIO might be connected to an external sensor, a relay contact, an external switch, an actuator to control a motor or valve, an actuator to a visual indicator such as an LED, a camera shutter, etc. GPI’s may be required to generate an interrupt to the processor. The logic levels and type of GPIO can range from single ended Open Collector, TTL or LV-CMOS

to differential standards such as LVDS or RS-422. Differential signaling is preferred for long distances or operation in an electrically “noisy” environment but requires 2 wires, positive and negative for each I/O. Communications interfaces add further complexity to the design of an embedded computer. There are literally 100’s of different types of communications interfaces tailored to specific applications. There are essentially two classes of communications interfaces buses and networks. A bus, such as PCI, consists of many wires and it typically implemented on one or more boards connected directly to each other. Networks allow systems to communicate with other systems that are physically separated. The physical separation could be feet or miles or more. Networks can be split into two subgroups wired and wireless. Wired networks such as Ethernet have cables with 2 to 10 and occasionally more conductors. Wireless networks by definition have no “wires” however they do require an antenna of some type. Communications interfaces vary in bandwidth from Kbits/sec for traditional MODEMS to 100 Gbits/s for 100GbE. Wireless networks, 802.11ad, can theoretically support up to 7 Gbps. The key parameters behind selecting one or more of these communications interfaces in-

I/O and Communication Interfaces The final embedded computer trend that should be examined is the need for more IO and communications interfaces. 32

COTS Journal | July 2017

Figure 3 IXI Technology’s General Purpose Processor module in the OpenVPX 3U form factor.

SYSTEM DEVELOPMENT

clude: (1). Required Bandwidth between devices or systems – peak and sustained; (2). Latency – how long does it take to send a message and receive a response; (3). Distance between devices or systems; (4). Power required – active and standby; (5). Security requirements – encryption; and (6). Cost. Unfortunately, there is no one perfect solution. In fact, the optimal solution may be a combination of communications interfaces. Specific markets such as the PC industry or automotive industry have made some communication standards ubiquitous and lowered the implementation costs. A few of the common external interfaces found in a variety of products includes: • USB – USB2.0 and USB3.0. Consumer marketplace

3). Among the IXI Technology GPP card’s features are an Intel ATOM E38xx processor—single/dual/quad cores operating at 1.9GHz; 2/4/8 Gbytes of DDR3 DRAM; Up to 1 Terabyte mSATA drive; Front panel Dual mode Display Port– DP direct connect and VGA/HDMI via DP adapter cable; 3 Gbit Ethernet ports with IEEE-1588 – One front panel 1000BaseT and Dual

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• CAN – vehicle and mechanical systems • FLEXRay – automobile industry • HDMI & DP – video interface • RS232 & RS485 – low speed, industrial and consumer PC

• PCIe – most widely used interface. Scalable through multiple serial lanes

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• Ethernet – many derivative standards, speeds and PHY’s. Consumer and industrial marketplace

Internal embedded computer interfaces include

backplane 1000BaseRX; and a variety of I/O including Dual CAN 2.0, Quad UART – RS232/422/485, Dual SPI ports 2, Dual IEEE 1553 2 and GPIO.

Onboard embedded RuSH™ technology. Switchable Battleshort and NED functions.

• HyperTransport & RapidIO – similar to PCIe • SPI & I2C– lower speed chip to chip interface

Broad Range of Requirements The key to any embedded computer based system is to offer a variety of low and high-speed communications interfaces that can be used to meet a broad range of product requirements. The article has explored the complex subject of optimized embedded computing solutions for military/aerospace/industrial environments. The key to delivering an optimized solution is to start with the system and fully define all the requirements. IXI Technology has developed a General Purpose Processor module in the OpenVPX 3U form factor that provides a wide variety of options to meet embedded computer platform requirements (Figure

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SYSTEM DEVELOPMENT FPGA Applications and Case Study

Xilinx’s Winning Strategy in Defense Market Over the past several years, Xilinx has increased its aerospace and defense market share in the Programmable Logic Device (PLD) market from a 49% share in 2010 to more than 55% today, basically winning about a point of market share annually. David Gamba, Senior Director, Aerospace and Defense Vertical Marketing, Xilinx

here are several reasons behind this marked increase in market share over the past decade. Xilinx All Programmable solutions address the aerospace and defense market seeking more than just an FPGA product. The company has also continued predictable and successful process technology node migrations and product introductions. In addition, Xilinx has continued to expand and proliferate its Defense Grade (XQ) and Space Grade (XQR) product offerings that are targeted to support aerospace and defense application needs. For aerospace and defense contractors needing to have the absolute lowest possible size and weight to meet form factor requirements in board area constrained systems, Xilinx also sells bare die for further SWAP-C requirements beyond the small form factor package offerings. Xilinx has been offering Defense Grade and Space Grade products for several generations of product offerings. The Xilinx Defense Grade devices offer aerospace and defense customers a 100% fullrange of extended temperature testing (-55oC to 125oC), mask set control, fully leaded (Pb) content, ruggedized packaging, anti-counterfeiting features, support of fail-safe information assurance and anti-tamper technology along with extended lifetime support options. The Xilinx Space Grade devices include the 34

COTS Journal | July 2017

Virtex-5QV, the industry’s first high-performance rad-hard reconfigurable FPGA device for processing-intensive space systems. These off-the-shelf devices offer the highest density, performance and integration relative to rad-hard ASICs or traditional one-time programmable products. Both the Defense Grade and Space Grade devices come with no NRE for the mask sets. Xilinx will continue to proliferate our Defense Grade and Space Grade devices in our UltraScale and UltraScale+ product family offerings. Xilinx is well positioned to continue its growth across multiple markets, including aerospace and defense, as the company continues to focus on integrating more advanced technology into its All Programmable solutions portfolio. One such example is the expansion of the Xilinx UltraScale+ product family to include integrated High-Bandwidth Memory (HBM), which enhances the UltraScale+ device capabilities significantly for use in radar, electronic warfare and high-performance computing applications. Early this year, Xilinx unveiled a disruptive integration and architectural breakthrough for 5G wireless with RFclass analog technology. The company’s new RFSoC solution is the industry’s first monolithic integration of programmable logic and multiple high-speed analog

mixed signal channels on a single die and will have significant use cases for radar and electronic warfare. These technology and product announcements illustrate the breadth of Xilinx All Programmable offerings for aerospace and defense applications. Xilinx San Jose, CA. (408) 559-7778 www.xilinx.com

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DATA SHEET

FPGA Ecosystem and Product Listing Roundup

H.264 ENCODER FPGA Core Offers High Speed Micro Footprint A2e Technologies (A2e) supports multiple FPGA processor companies - a Certified Design Partner with Xilinx, Design Services Network partner with Altera and a design partner with Microsemi. Available services include FPGA design and verification ,communication systems such as using Xilinx High Level Synthesis (HLS), software and FPGA design with the MicroBlaze softcore and the multi-ARM core versions of Zynq and UltraScale(+) devices. Additionally, A2e has completed Zynq/ UltraScale based system utilizing Linux, bare metal, other RTOS on all ARM cores or an asymmetric system with a different OS on each core. Market segments served include aerospace, medical diagnostic equipment, surveillance cameras, drones and other products. H.264 ENCODER FPGA Core: • Supports H.264 variable and fixed bitrate encoding of video streams • Latency reduced from 1 frame to less than 1ms for a 1080p30 video stream • Encodes video data at 1.5 clocks/pixel • Typical clock rate is 95Mhz for Xilinx SPARTAN 6 and Zynq 7020. • Search range: 80 X 48 pixels, Full, 1/2, 1/4 pixel resolution • Support for intra 4 x 4 DC prediction, Single or Multiple slices via firmware control, YUV 4:2:0 video input. • Available as FPGA specific netlist. A2e Technologies San Diego, CA (877) 223-8359 www.a2etechnologies.com

COTS Journal | July 2017

APA7-200 Offers a Reconfigurable FPGA Xilinx Artix-7 FPGA Module with Extended MiniPCIe

The ADM-XRC-KU1 Combines Reconfigurable XMC and Xilinx Ultrascale FPGA Module.

Acromag provides modularizing FPGA technology into a COTS-based offering for the MIL-AERO, Defense and Scientific markets. By designing FPGAs into IP, PMC and XMC form factors, Acromag has made it very simple for customers to install the appropriate solution and use our Engineering Design Kit to program the board to their specific needs. With front or rear I/O and conduction cooled options (-40 to +85 degree C) the user has a wide range of selections to interface our product into their system requirements. This FPGA module is available with TTL, 485/422, or LVDS I/O, uses less than 5 watts of power and are priced at sub $1000 in single quantity.

Alpha Data offers FPGA accelerator boards that combine FPGA technologies with fast external memory and high speed serial interfaces for low latency and high bandwidth data processing applications ( financial trading, mathematical system modelling, real-time video image processing, industrial and military/aerospace). Alpha Data products come in XMC, VPX and PCIe formats. The latest offering is the ADMXRC-KU1.

• FPGA device: Xilinx Artix-7 FPGA Model XC7A35T. • FPGA configuration: Download via flash memory Example FPGA program IP integrator block diagram provided for PCIe bus 1 lane Gen 1 interface, DMA controller, on chip block RAM, flash memory and control of field I/O. See EDK kit. • Field I/O Interface: PCIe bus 1 lane Gen 1 interface. • I/O Connector: 100 pin field I/O connector. • Bus Speed: 2.5 Gbps (Generation 1). • Memory: 128k space required, 1 base address register. • Operating temperature: Air Cooled with heat sink -40 to 80°C; Air Cooled without heat sink -40 to 70 degree C.

Acromag Wixom, MI 48393 (248) 624-1541 www.acromag.com

• Board Format : XMC • Host I/F : PCI Express Gen2 x4 • Target Device(s) : Xilinx Kintex UltraScale {KU060, KU115} (A1517) • SDRAM : 8GBytes in 4 independent banks of DDR4 SDRAM (2400 MT/S) • FLASH : 2x QSPI serial NOR Flash • FLASH : Configuration Flash provides an initialization design for automatic loading into the target FPGA. • The KU1 is supplied with the ADM-XRCKU1 Support & Development kit (SDK) along with ADB3 Driver for Windows / Linux / VxWorks.

Alpha Data Golden, CO 80401 (303) 954-8768 www.alpha-data.com

DATA SHEET

FPGA ECOSYSTEM AND PRODUCT LISTING ROUND UP

Links to the full data sheets for each of these products are posted on the online version of this section.

WILDSTAR UltraKVP ZP DRAM Features FPGA Boards with Zynq UltraScale+ MPSoC Controllers

Xilinx Zynq UltraScale+ based Mercury+ XU1 Offers Plug and Play Convenience

CHAMP-FX4, 4th Generation 6U FPGA Card, Combines Three Xilinx Virtex-7 FPGAs and 12 GB Memory

Annapolis Micro Systems designs and manufacture COTS and modified COTS FPGAbased Boards and Systems for data acquisition, high performance computing and digital signal processing applications. Four FPGA boards have been announced that integrate a powerful Xilinx Zynq UltraScale+ MPSoC (Zync+) controller. The quad-core ARM’s higher performance eliminates the need for a separate Single Board Computer (SBC) in many digital signal processing systems. The Zynq+ features a 64-bit quad-core ARM® Cortex-A53 running up to 1.3 GHz, plus a dualcore 32-bit Cortex-R5 real-time processor running up to 533 MHz. This is a significant upgrade from the Zync-7000 SoC, which housed a 32-bit dualcore ARM Cortex-A9 running up to 766 MHz.

Based in Zürich, Switzerland, Enclustra offers FPGA design service and a whole range of FPGA-based modules and FPGAoptimized IP cores from high-speed hardware or HDL firmware to embedded software from specification to prototyping. The Mercury+ XU1 system-on-chip (SoC) module combines Xilinx's Zynq UltraScale+ MPSoC-series device with fast DDR4 ECC SDRAM, eMMC flash, quad SPI flash, dual Gigabit Ethernet PHY, dual USB 3.0 and an RTC and thus forms a complete and powerful embedded processing system. The product comes with full documentation and a reference design. Linux can be compiled with a few clicks using the Enclustra Build Environment and all required files, including FPGA bitstream, will automatically be generated. • Xilinx Zynq Ultrascale+ MPSoC with ARM quad-core Cortex-A53, ARM dualcore Cortex-R5, Mali-400MP2 GPU and 16nm FinFET+ FPGA fabric • Up to 8 GB DDR4 ECC SDRAM • 64 MB QSPI flash and 16 GB eMMC flash • PCIe Gen2 ×4 endpoint • 16 × 6/8/12.5 gigabits per sec MGT • 2 × Gigabit Ethernet • 2 × USB 3.0 and 2 × USB 2.0 (host & host/device)

Curtiss-Wright Defense Solutions offers FPGA products for radar, EW, SIGINT, and wide-band data communications applications in the defense and aerospace markets. Primary focus includes rugged 3U and 6U OpenVPX module form factors as well as XMC mezzanine module solutions. Additional products include SBCs, DSP cards, GPGPU modules, network switches, data recorders, and IO modules for mil-aero systems. The CHAMP-FX4 is the flagship 6U product Based on the Xilinx Virtex-7 FPGA designed for embedded, high-performance digital signal and image processing applications. Curtiss-Wright’s 4th generation 6U FPGA card, the CHAMP-FX4 combines the dense processing resources of three large Xilinx Virtex-7 FPGAs with over 12 GB of memory resources, all on a rugged 6U OpenVPX (VITA 65) form factor module. • FPGA device: Xilinx Virtex-7, 585T, X690T. Number of FPGAs is 3 + 2 x 2 GB DDR3L SDRAM (64-bit data paths) + 2 x 18 MB QDRII+ SRAM (36-bit W/R data). • Processor subsystem Device: ZYNQ-7030 (-2 speed grade) 676 pkg with dual ARM Cortex A9 of 800 MHz and memory: 64KB L1 cache, per core, 512 KB shared L2. • Mezzanine sites: FMC/VITA 57 + 80 differential pairs + 4 bidirectional SerDes (build option to increase to x8 byMoving x4 backplane connections). • Serial RapidIO: IDT 8-port Gen2 SRIO switch (IDT 80HCPS1432) and backplane ( four x4 Gen2 on P1), at 5.0 Gb/s

• The Zynq+ memory bandwidth also surges, with DDR4 DRAM now running up to 1200 MHz. • The four new Annapolis boards with Zynq+ are spread across three form factors – 6U OpenVPX, 3U OpenVPX, and PCIe – and are available in air or conduction-cooled configurations. • Two Zynq+ options are available for ach 6U OpenVPX COTS board: • XCZU9EG or XCZU15EG. The ZU9 has 600K logic cells and 2,520 DSP slices; the ZU15 has 747K logic cells and 3,528 DSP slices. • Each includes 4 HSS lines running up to 16Gbps to the other Kintex UltraScale or Virtex UltraScale+ FPGAs, as well as two 10Gbps-capable HSS lines to the backplane for off-board communication with protocols such as 10GbE.

Annapolis Micro Systems Annapolis, MD 21401 (410) 841-2514 www.annapmicro.com

Enclustra GmbH Zürich | Switzerland +41 43 3433933 www.enclustra.com

Curtiss-Wright Defense Solutions Ashburn, Va. ds@curtisswright.com www.curtisswrightds.com

COTS Journal | July 2017

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Company Page# Website

Acromag, Inc.......................................46........................... www.acromag.com

Pentek.................................................25.............................. www.pentek.com

AIM......................................................31..........................www.aimonline.com

Phoenix International...........................4............................ www.phenxint.com

Aitech Defense Systems, Inc................7...............................www.rugged.com

PICMG.................................................28.................................www.picmg.org

Dawn VME...........................................33.......................... www.dawnvme.com

Pico Electronics, Inc............................27................. www.picoelectronics.com

Elma Electronics.................................19................................. www.elma.com

Pixus Technologies..............................29.............www.pixustechnologies.com

GAIA Converter....................................22.................. www.gaia-converter.com

Positronic Industries, Inc.....................38............. www.connectpositronic.com

Great River Technology........................15...................www.greatrivertech.com

Star Communications Inc....................40......................www.starcommva.com

High Assurance...................................41.................. www.highassurance,com

SynQor..................................................5................................www.synqor.com

Intelligent Systems Source..................44.. www.intelligentsystemssource.com

Themis................................................16.........................www.hyperunity.com

LCR Embedded....................................11........ www.lcrembeddedsystems.com

Vicor Corporation.............................42-43...................... www.vicorpower.com

Mercury Systems, Inc. .........................2.................................. www.mrcy.com

VPT......................................................17...........................www.vptpower.com

Microsemi.............................................9..........................www.microsemi.com

WinSystems.........................................21.......................www.winsystems.com

New Wave DV.......................................29.......................www.newwavedv.com

XILINX.................................................35................................... ww.xilinx.com

One Stop Systems...............................45................www.onestopsystems.com

COTS Gallery Ad..................................40.........................................................

COTS Journal (ISSN#1526-4653) is published monthly at 940 Calle Negocio, Suite 230, San Clemente, CA 92673. Periodicals Class postage paid at San Clemente and additional mailing offices. POSTMASTER: Send address changes to COTS Journal, 940 Calle Negocio, Ste. 230, San Clemente, CA 92673.

COTS Journal | July 2017

Index

Company Page# Website

COTS

PRODUCT GALLERY AcroPack® APA7-200 FPGA PCIe-based Boards The APA7-200 series provides a FPGA based user-configurable bridge between a host processor and a custom digital interface via PCI Express. These boards offer a low-cost, high-performance FPGA solution. Developed for adaptive filtering & processing applications. • Low Cost: Under $1,000 USD • Conduction or air-cooled options • Low Power: +3.3V (±5%) 500mA Typical • Flexible I/O: RS485/422, LVDS, TTL, TTL & RS485/422 • COTS Designed • Superior Software Tools (Drivers & EDK) • PCI Express Generation 1 interface • Reconfigurable Xilinx® Artix-7® FPGA • VPX, XMC and PCIe Carrier Options

Interface Concept Phone: (877) 295-7084 Web: www.acromag.com/acropacks

3U OpenVPX Front-end processing board based on Kintex® UltraScale™ FPGA. The IC-FEP-VPX3d front-end processing board combines a user programmable Kintex® UltraScale™ FPGA, two banks of DDR4, general purpose I/O, together with a FMC+ site (FPGA Mezzanine Card) in a single 3U OpenVPX slot. The FMC+ site that is compliant with VITA 57.4 standard, provides additional High Speed serial links to the FMC, while keeping a backward compatibility with the legacy FMC (VITA57.1). This board is ideally suited for demanding computing applications such as Radar, Electronic warfare, etc. It is one of the core building blocks of next High Performance Embedded Computing (HPEC) systems. IC provides the remaining building blocks: COTS Ethernet Switching and COTS Intel/NXP Single board computers boards. • 16 differential pairs from • One Kintex® UltraScale™ FPGA FPGA on P2 • Two banks of DDR4 • Four *128 Mbytes of QSPI Flash memory • 1 * FMC+ site • Four *4-lanes fabric ports on P1/P2

Interface Concept Phone: (510) 656 3400 Web: www.interfaceconcept.com

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COTS Journal | July 2017

• Eight 125 MSPS, 16-bit ADC channels • Xilinx Artix-7 FPGA • 89 dB SFDR, 72 dBFS SNR A/Ds • DIO on P16 (differential pairs) • 4 lane PCI Express 2.0 interface supports continuous data streaming at 1600 MB/s • Multiple modules may be clocked and triggered externally to allow perfect synchronization of arbitrarily large capture meshes • Flexible deployment options to meet myriad packaging, power and weight constraints • Utilize the XA-RX within any PCI Express desktop, industrial PC or PXIe chassis via available adapters • Can natively be installed within a unique range of diminutive, embedded PC products.

Innovative Integration Phone: (805) 383-8994 Web: www.innovative-dsp.com

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POWER COMPONENT DESIGN METHODOLOGY

Solving the Power Challenges of SWaP-C Requirements for MIL-COTS Applications Application Examples using the Power Component Design Methodology See examples of how using Vicor components help meet SWaP-C requirements Avionics Computer Challenges Low profile components (8 mm), facilitate a redundant compact solution and meet high temperature (125Â°C) requirements. Learn more about solving the challenges in Avionics Computer >

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Communications Equipment Challenges The DCMâ&#x20AC;&#x2122;s fixed switching frequency (750 kHz) enables a compact EMI filter to meet stringent conducted noise specifications.

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Airborne Equipment Challenges Scalable modular DCM based design, enables high power, regulated outputs with up to 200 mF of bulk capacitance.

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Custom DCM

Jammers and Countermeasure Challenges

BCM

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High efficiency ZVS regulators (95%) enable high temperature operation with minimal power de-rating.

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UAV Challenges

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DCM

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DCM

24V

300V

DCM

24V

Lightweight DCMs (29.2g) enable a scalable high density power design. Learn more about solving the challenges in UAV Equipment >

300V

Tether L4

Expanding the Family of MIL-COTS Products MIL-COTS Isolated Regulated Converter Modules

MIL-COTS Isolated Regulated Converter Modules

MIL-COTS DCM™ DC-DC Converter Modules in a ChiP Package >

MIL-COTS DCM™ DC-DC Converter Modules in a VIA Package >

Input Voltages:

9.0 – 50 VDC, 16 – 50 VDC, 160 – 420 VDC

Output Voltages: 3.3V, 5V, 12V, 15V, 24V, 28V, 48V Output Power:

3623 ChiP: Up to 320W 4623 ChiP: Up to 500W

Efficiency:

Up to 93%

Dimensions:

3623 ChiP: 38.7 x 22.8 x 7.3 mm 4623 ChiP: 47.9 x 22.8 x 7.3 mm

16 – 50 VDC, 160 – 420 VDC

Output Voltages: 5V, 12V, 15V, 24V, 28V, 48V Output Power:

3414 VIA: Up to 320W 3714 VIA: Up to 500W

Efficiency:

Up to 93%

Dimensions:

3414 VIA: 89.5 x 35.6 x 9.4 mm 3714 VIA: 95.3 x 35.6 x 9.4 mm

MIL-COTS PI31xx DC-DC Converter Modules > Input Voltages:

28 VDC (16 – 50 VDC)

Output Voltages: 3.3V, 5V, 12V, 15V Output Power:

Up to 50W

Efficiency:

Up to 88%

Dimensions:

22.0 x 16.5 x 6.7 mm

Point-of-Load Regulators (MIL-COTS Compatible) Cool-Power® ZVS Buck Regulators > Input Voltages:

12V nominal (8 – 18V) 24V nominal (8 – 36V) 48V nominal (36 – 60V)

Output Voltages: Wide output range (1 – 16V) Output Current: 8A, 9A, 10A, and 15A versions Efficiency:

Up to 96.5% Light load and full load high efficiency performance

Dimensions:

LGA SiP: 10 x 14 x 2.56 mm LGA SiP: 10 x 10 x 2.56 mm

MIL-COTS Filter Modules MFM DCM Filter > n Provides MIL-STD-461 EMI filtering and MIL-STD-704 and MIL-STD-1275 transient protection n For use with 28V and 270V nominal input voltage DCM products

MQPI Filter > n Provides MIL-STD-461 EMI filtering n For use with MIL COTS PI31xx regulators

Cool-Power® ZVS Buck-Boost Regulators > Input Voltages:

8 – 60V 16 – 34V 21 – 60V

Output Voltages: 10 –50V 21 – 36V 36 – 54V 12 – 34V Output Power:

Up to 240W continuous

Efficiency:

Up to 98% efficiency at >800 kHz FSW

Dimensions:

LGA SiP: 10 x 14 x 2.56 mm

Design your Power System in 90 seconds using the Power System Designer Tool. Learn how to get to market faster with 4 easy steps: www.vicorpower.com/video/psd

Flash Storage Array with 200TB capacity in four removable canisters

50TB data in each 7 Lb. removable canister

• 100Gb Inﬁniband or Ethernet connections • MIL-STD 810 and 461 tested • Two versions: airborne and ground • 4U rackmount unit

(877) 438-2724

www.onestopsystems.com

SWa P

Great Things Do Come In Small Packages ▪ 4 Gen Intel® Core® i7 Haswell CPU ▪ Shock and vibration-tested (MIL-STD-810G) ▪ MIL-STD-38999 high-density connectors ▪ IP67 sealed against dirt and water ▪ PMC/XMC expansion ▪ SWaP-optimized ▪ Advanced thermal management ▪ Optional removable solid state drives with RAID support th

The ARCX rugged mission computer offers great flexibility to meet ever-changing requirements with unique expansion features.

We have the I/O to meet your embedded application requirements:

▪ FPGA ▪ Analog/Digital ▪ Counter/Timer ▪ Serial Communication ▪ Multifunction I/O ▪ 10-Gigabit Ethernet Visit Acromag.com/ARCX

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