COTS Journal

September 2017, Volume 19 – Number 9 • cotsjournalonline.com

The Journal of Military Electronics & Computing JOURNAL

Future Intelligence using C4ISR

DESIGNING MICROPHONIC SENSITIVE DEVICES IN MILITARY VEHICLES VPX IN DATA TO DECISION CHAIN INTEGRATED FPGA OFFLOAD HOST CPU

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The Journal of Military Electronics & Computing JOURNAL

CONTENTS

COTS (kots), n. 1. Commercial off-the-shelf.

Terminology popularized in 1994 within U.S. DoD by SECDEF Wm. Perry’s “Perry Memo” that changed military industry purchasing and design guidelines, making Mil-Specs acceptable only by waiver. COTS is generally defined for technology, goods and services as: a) using commercial business practices and specifications, b) not developed under government funding, c) offered for sale to the general market, d) still must meet the program ORD. 2. Commercial business practices include the accepted practice of customer-paid minor modification to standard COTS products to meet the customer’s unique requirements.

—Ant. When applied to the procurement of electronics for he U.S. Military, COTS is a procurement philosophy and does not imply commercial, office environment or any other durability grade. E.g., rad-hard components designed and offered for sale to the general market are COTS if they were developed by the company and not under government funding.

September 2017 Volume 19 Number 9

FEATURED p.8 Navy Modernization Wins the Future War with the C4ISR Program

SPECIAL FEATURE Modern War 08

Navy Modernization Wins the Future War with the C4ISR Program John Koon, Sr. Editor

SYSTEM DEVELOPMENT Focus on Ruggedized Military Solutions 12

Integrated FPGA Offload Host CPU in 1U Server

14

Innovative Thermal Management in HPEC VPX systems

16

Mechanical Design Considerations for Microphonic Sensitive Devices in Military Vehicles

20

Naval COTS Systems at the Crossroads: ATCA & VPX

32 Products

Thierry Wastiaux, Interface Concept

Sergey Sokol, Analog Devices, Inc.

Best Practices to Future-Proof Mil Test Systems with FPGA Hardware in the Loop Brian Durwood, Keysight Technologies, Inc.

The Role of VPX in the Data to Decision Chain

30

Advancements of the digital interface to increase bandwidth into the FPGA

6 Editorial

Ameet Dhillon, Accolade Technology

26

DEPARTMENTS

Roy Keeler, ADLINK

Tommy Neu, Texas Instruments

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COTS Journal | September 2017

3

JOURNAL

The Journal of Military Electronics & Computing

Editorial

Sr. EDITOR John Koon, johnk@rtc-media.com MANAGING EDITOR Aaron Foellmi, aaronf@rtc-media.com

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GUEST EDITORIAL David Jedynak, Curtiss-Wright Defense Solutions

Naval COTS Systems at the Crossroads: ATCA & VPX

A

bout five years ago the U.S. Navy selected the Advanced

platforms and consider how they can be adopted and incorporated

Telecommunications Computing Architecture (ATCA) as

into the VPX ecosystem. VPX, defined, overseen and updated contin-

its “board/blade and backplane” open standard of choice.

uously by the VITA trade association, directly reflects and responds

The selection of ATCA was, to a great extent, driven by the

to the needs of the aerospace and defense market. This would be an

clear advantages that derive from leveraging “commercial market”

opportune time for VITA to consider defining a variant VPX-card

standards, such as the wide variety of vendors and the competi-

that addresses the specific needs of benign naval environments. In

tive pricing typically associated with high volume products. The

addition, the industry could consider a deeper “6U-long” VPX-blade

strengths of the ATCA architecture are largely driven by the require-

that would match the ATCA real estate advantage. We have reached

ments and huge scale of the telecommunications market. For ex-

a cross-road where the Navy should be encouraged to compare its

ample, ATCA cards were originally designed for climate controlled,

experiences with ATCA with the robust and mature VPX architec-

benign telecom environments in buildings. They’ve often proven a

ture. By leveraging the “goodness” of ATCA and combining it with

good fit for the relatively benign environments typical of naval plat-

the now well-established strengths of the VPX ecosystem, naval

forms that require significantly less cooling and ruggedization than

customers could also leverage all of the work that has been done in

those that system designers usually encounter on SWaP-constrained

recent years by VPX suppliers to support important DoD initiatives

ground vehicles and airborne platforms.

like HOST, MORA, and SOSA. It’s time for the Navy to take another

In 2012, when the Navy made its decision, the VPX system architecture was just coming into its own. At the time, while VPX’s market acceptance as the de facto successor to VME was gaining momentum, the newer standard lacked the history and familiarity that helped the Navy select ATCA. Another advantage that ATCA had over VPX was the amount of module real estate available to the board designer. ATCA’s larger size, both wider and longer than a 6U VPX card, provides the designer with the option to integrate more memory and more processing functionality.

Today, we are in a transitional period, with VPX ascendant and well established as the open architecture of choice for rugged deployed aerospace and defense applications. It makes sense to take a look at those strengths that the ATCA architecture brings to naval 6

COTS Journal | September 2017

look at VPX. They’ll like what they see.

COTS Journal | August 2017

7

SPECIAL FEATURE Modern War

Figure 1 The future war will be won with not only firing power, but on data intelligence and cyber superiority. The Navy’s C4ISR program (Command, Control, Communications, Computers, Intelligence, Surveillance and Reconnaissance) enables its modernization to gain an upper hand. (Photo courtesy of Lockheed Martin, a leader in C4ISR solutions)

8

COTS Journal | September 2017

SPECIAL FEATURE

Navy Modernization Wins the Future War with the C4ISR Program Future warfare will be fought and won on intelligence and technologies.

The key to winning is more than just faster ships, planes and powerful missiles. The C4ISR program includes information (lots of it) collection and how it is used. The Navy is very serious about modernization and has a big budget to support C4ISR. John Koon, Sr. Editor

T

he C4ISR program (Command, Control, Communications, Computers, Intelligence, Surveillance and Reconnaissance) is driving the Navy modernization. What started some twenty years ago, C4ISR is turning into a critical driving force in winning future battles. The program is under Code 31 of the Naval Research and Development Framework. Computer power has increased fighting power in the air, on the ground, underwater and in cyberspace. This is especially true for cyberwar. Code 31 covers a broad range of technologies. Among them are Mathematics, Electronics, Computer & Information Sciences and their applications in Command & Control, Communications, Cyber, EW, Intelligence, Surveillance and Reconnaissance. It further subdivides into Division 311 (Mathematics, Computer and Information Sciences /MCIS), Division 312 (Electronics, Sensors and Networks

COTS Journal | September 2017

9

SPECIAL FEATURE

Figure 2 $5.1 Billion awarded to General Dynamics for the next generation U.S. Navy’s Ballistic-Missile Submarine. The photo shows the concept design of the submarine. (Photo courtesy of General Dynamic)

Research) and Division 313 (Applications and Transitions).

Division 311 represents the Office of Naval Research (ONR) Mathematics, Computer and Information Sciences (MCIS) Division. It uses basic research, applied research and advanced technology development efforts in mathematics, computer and information sciences that address Navy and Department of Defense needs in computation, information processing, information operation, information assurance and cyber security, decision tools, and command and control with specific focus on enabling rapid, accurate decision making in network centric environments. All of these will enable precision in command and control. It is similar to the old saying of “work smarter, rather than harder.”

Division 312 represents the Office of Naval Research (ONR) Electronics, Sensors and Network Research Division. It aims to achieve the objectives of enabling technologies to deliver products of minimum size, weight, power and cost (SWaP-C).

Its integrated program of basic, applied, and advanced development research into technologies that enable new and innovative uses of the electromagnetic spectrum in support of the Navy and Marine Corps mission. Also includes research in surface and aerospace surveillance, communications, electronic warfare, navigation and electronics.

The following are the areas of focus.

• Surveillance • Communications and Networking 10

COTS Journal | September 2017

• Electronic Warfare • Navigation • Electronics Didision 313 represents Applications and Transitions technology to enhance warfighting capabilities to C4ISR, electronic warfare, air and missile defense. It stresses precision timekeeping and navigation acquisition programs. Area of focus includes FNC Execution Oversight, FNC Transition Agreements and Coordination, Technology Road mapping and FNC Business Plan.

The Navy’s C4ISR programs oversees and promote related solutions. Contractors who qualified for these programs may be awarded multiyear contracts with minimum guarantee and potential to extend to reach the maximum awards. The Navy Modernization C4ISR program is broad.

In the past few months, the Navy awarded four contracts out of nine proposals worth $173.9 million for training services supporting the C4ISR platform over the next five years (three base periods with two optional years). The four recipients included Alion Science and Technology, Camber Corp., Del Rey Systems & Technology and ManTech International. Additionally, the Navy awarded another $137.8 million contract for platform integration and systems engineering services. Contractors will provide solutions including design, engineering and integrate net-centric C4ISR systems. These awards cover three base years with two optional years for additional funding. The recipients included Booz Allen Hamilton, Geocent and Solute. Geocent

will provide the Navy with Software and Systems support in web enabled systems implementing both physical and cyber security needs. Like all other contractors, Geocent will have the opportunity to win the extension based on performance.

Another company that scored big is General Dynamics Information Technologies with a $52 million contract to provide cybersecurity, IT software and systems engineering services to Commander, Naval Meteorology and Oceanography Command and Navy Information Forces over the next five years. The work on the contract will be conducted at the Stennis Space Center, Mississippi; Monterey, California; and Washington, D.C. But there is no comparison with the $5.1 billion awarded to Electric Boat, Electric Boat (a wholly owned subsidiary of General Dynamics), for the next U.S. Navy’s Ballistic-Missile Submarine. This project includes the Integrated Product and Process Development (IPPD) contract for the design and delivery of the lead Columbiaclass submarine, the next-generation seabased strategic weapon. Figure 1. “Working closely with the Navy and the submarine industrial base, Electric Boat will continue to lead critical aspects of the Columbiaclass development effort, including design, material procurement, construction and operating-cost reduction, to achieve an affordable and effective program,” said Electric Boat President Jeffrey S. Geiger according to the press release.

Other prime contractors are not sitting idle. Lockheed Martin, a leader in

SPECIAL FEATURE C4ISR develops solution on “data to decision cycle.” applying artificial intelligence products and machine-to-machine capabilities that automate the intelligence cycle and enhance real-time situational awareness. Figure 2. Based on an open architectures and cross domain solutions LMC is able to develop software-centric systems that facilitates rapid change and supports coalition interoperability.

One of the requirements to maintain leadership in future battlespace is to have the capability of continuous situational awareness. Working with enterprise level ‘systems of systems,’ LMC merges the operations C4 (command & control, computer and communication) with the intelligence (ISR) environments to provide a layered, integrated view of the battlespace resulting in the ability to really ‘see’ everything that is happening in the battlespace. The future war will be won, not just on firing power, but by super intelligence and data management. “From developing the enterprise system that directs flying operations for U.S. military forces to enabling the Ballistic Missile Defense System to operate as a global network, Lockheed Martin is at the forefront of transformational architectures that combine effects to create an orchestrated force.” according to Dr. Rob Smith, Vice President of C4ISR. Lockheed Martin has been awarded multiple contracts including the Missile Defense Agency’s Command, Control, Battle Management and Communications (C2BMC) system and U.S. Navy’s Tactical Tomahawk Weapon Control System (TTWCS).

The Navy modernization has just started. There are many grounds to be covered. One of them is cyberwar. The Office of Naval Research (ONR) cooperates with Dr. Binoy Ravindran, an engineering professor at Virginia Tech to develop future system under the name “Popcorn Linux” that could revolutionize how military and commercial computing systems perform.

It is an operating system that can compile different programming languages into a single cyber tongue. “By applying Popcorn Linux to longtime, legacy Navy and Marine Corps computer systems, we can improve software without requiring thousands of man-hours to rewrite millions of lines of code,” said Dr. Wen Masters, head of ONR’s

C4ISR Department. “This could yield significant savings in maintenance costs.” C4ISR will continue to propel future technology development of the Navy to maintain its leadership in defense of both the physical and the cyberspace.

Office of Naval Research Corporate Strategic Communications Arlington, VA (703) 696-5031 www.onr.navy.mil

General Dynamics Electric boat Groton, Conn.

(860) 433-3000 www.gdeb.com Lockheed Martin Denver, Colorado (610) 531-7673 www.lockheedmartin.com/C4ISR

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COTS Journal | September 2017

11

SPECIAL FEATURE Focus on Ruggedized Military Solutions

Integrated FPGA Offload Host CPU in 1U Server A terrific way to supercharge your 1U industry standard server is to embed a “native” FPGA right on the motherboard. The FPGA performs specialized functions and runs algorithms which offload the host CPU; significantly enhancing performance and throughput.

Ameet Dhillon, Director of Business Development, Accolade Technology

W

e are all familiar with the term “industry-standard” or “commercial off-the-shelf (COTS)” servers.

The generally accepted understanding is these are servers which contain readily available components such as an x86 CPU, memory, storage, networking card and a ubiquitous operating system such as Linux or Windows. We usually think of companies such as Dell or HP as suppliers of these industry standard servers and for a long time have been accustomed to accept that the best platform for our applications is an industry standard server. This is certainly true for a large percentage of applications, but we shouldn’t automatically assume there are no other options.

A slight twist to the industry standard server which includes all the standard components would be the addition of an onboard FPGA. I don’t mean an FPGA as a “bolt-on” in the form of a PCIe adapter/NIC (though that is a valid solution as well), but rather an FPGA that is mounted onto the motherboard and wired up to interact with the various components around it. Just like all the other components, the FPGA performs a specific and vital function; namely host CPU offload. An FPGA is a programmable device well suited to performing application specific functions or algorithms. These functions run the gamut from something very specific such as a proprietary security algo12

COTS Journal | September 2017

Figure 1 ATLAS-1000 Platform

rithm to more generic requirements such as time stamping, packet filtering or data deduplication. A repetitive and CPU intensive task is the ideal candidate for offload to an FPGA. It is not uncommon that through FPGA assist an application can reduce CPU load by over 50%. In addition, FPGA offload enables remarkable scaling of applications previously restricted by CPU bottlenecks.

While the benefits of an onboard or “native” FPGA can be very compelling, there are at least two potential downsides to keep in mind. The first is simply cost. Integrating an FPGA can add a relatively significant cost factor to the server. However, the return on investment (ROI) is usually quite apparent.

Since FPGA offload dramatically reduces the burden on your host CPU(s) thereby optimizing application performance, these added benefits are well worth the cost. The second downside is the complexity of pro-

gramming an FPGA. In the FPGA world, you don’t call someone a programmer but rather a “designer” or “design engineer”.

This is because FPGAs are not programmed in common languages such as C or Java.

Rather FPGAs are designed using Verilog or VHDL which are hardware description languages (HDLs) used to model electronic systems. For this reason, it is often not possible for a software application development team to program an FPGA with the specific offload functions or algorithms they need to achieve the desired level of CPU offload.

The solution to this dilemma is to partner with a vendor that has depth and expertise in FPGA design and can provide comprehensive offload functions as well as custom features tailored for each specific customer scenario.

Accolade Technology is a vendor that fits such a profile with its ATLAS-1000 FPGA integrated platform. Figure 1 shows the 1U,

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Like industry standard servers, the ATLAS-1000 provides a multi-core Intel CPU, memory and storage along with an FPGA loaded with packet processing capabilities such as lossless packet capture, packet filtering, nanosecond precision timestamping, deduplication, flow classification and multi-core DMA. In addition to the onboard FPGA, the platform has several other unique attributes such as direct GPS decode on the motherboard, pluggable interface modules that support 10 or 40G and a small footprint that accommodates two ATLAS-1000 units mounted side-by-side in a standard 19-inch

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COTS Journal | September 2017

13

SPECIAL FEATURE SPECIAL FEATURE

Focus on Ruggedized Military Solutions

Innovative Thermal Management in HPEC VPX systems As the customer demand for putting ever increasing processing power in each High Performance Embedded Computer (HPEC) VPX System, finding new ways for extracting the heat out of each system slot has become essential to reach challenging specifications with very stringent requirements for small size and weight, low power consumption and competitive pricing. Thermal management cannot be considered anymore as an afterthought and designers must introduce new innovative cooling techniques and solutions to achieve performance goals, right at the start at the design phase.

Thierry Wastiaux, Senior Vice President Strategy & Marketing, Interface Concept

Thermal simulation

T

o maximize the processing power in each slot of a VPX chassis while controlling costs, Interface Concept has developed coupled fluid and thermal simulation models. These numerical models have been assessed through experiment.

They are systematically used during the design phase of the products.

These simulations tools allow computing, with good precision, the internal temperature of the components. More importantly, they provide reliable improvement indications when changing the design assumptions. This greatly helps engineers in defining the best cost effective solutions for component placement and design of thermal interfaces (pads, gap fillers, and compound) and heat sink. These simulations are key to design plug-in units able to sustain the long thermal cycle tests beyond the standards, requested by demanding customers. That is the reason why Interface Concept keeps on developing its own simulation tools as well as dedicated thermal measurement benches.

sis of cost effective VPX air cooled designs leading to lightweight and cost effective solutions for operating temperature within the [0,55°C] range (AC1 VITA 47 Operating Temperature Class).

Interface Concept has worked on improving the cooling of VITA 48.1 compliant products to extend the temperature range of operation. The goal is to drive the costs down by avoiding the use of other less cost effective solutions based for instance on the VITA 48.2 conduction cooled or VITA 48.5 Air Flow Through standards when more thermal power dissipation is needed.

VITA 48.1 cooling

Air cooling innovation

The VITA 48.1 open standard defines the mechanical specifications of air cooled VPX plug-in units. This standard is the ba-

A good example of this new approach is the IC-INT-VPX3d single computer board that features an Intel ÂŽ Xeon D-1559 pro-

14

COTS Journal | September 2017

Figure 1 IC-INT-VPX3d equipped with standard air cooled mechanical solution

cessor shown on figure 1 with its standard mechanical solution. The thermal performances of air cooled plug-in units are somehow limited. The limitations are mainly due to forced convection physics. One of the main issues comes from the fact that the air typically flows outside the heat sink as it can be seen on the velocity field picture of figure 2 a). This means that part of the air flow does not participate in the heat exchange. The air kinetic energy provided by the systems ( fans, blower‌) is simply wasted. This phenomenon is illustrated by the temperature field shown on figure 2 b).

Staying on air cooled VPX products and systems that are usually preferred as they are easier to manage, the classical approach to improve this situation is to move to other solutions as Air flow through (VITA 48.5) or other proprietary similar schemes. However these solutions have some drawbacks. They tend to increase the weight of the products that is not wanted especially on airborne solutions. They also prevent a natural air cooling of the PCB itself where components may be soldered at the bottom side of the plug-in unit. They usually lead to a significant cost increase.

For air cooled designs, Interface Concept has chosen the path to stay on the VITA 48.1 standard and to develop innovative thermal and mechanical solutions. Among the efforts made, the air flow path has been

SPECIAL FEATURE

a

b

Figure 2 Computed fields across 3U plug-in-unit. a) Transverse velocity. b) Temperature.

optimized. New principles have also been used to greatly improve the efficiency of the heat sink itself. In addition new features have been developed to optimize the thermal contact with the components.

All this effort has led to the design of the enhanced air cooled IC-INT-VPX3d shown on figure 3. The performances of this enhanced plug-in unit compared to the standard one have been tested within a fully

Figure 3 IC-INT-VPX3d equipped with enhanced air cooled mechanical solution

instrumented air cooled chassis. By design the Intel® Xeon 1559 processor constantly adapts its operation scheme to stay under the junction temperature limits. When increasing the cooling, the available power of the processor will increase. In term of watts, this power can increase up to a maximum level of 45 W for the Intel® Xeon 1559 processor. This maximum level (Thermal Design Power) represents the average power the processor dissipates when operating at Base Frequency with all core active. At this level, the user gets the maximum performance from the processor.

The results of the test of the compared performances between the standard and the enhanced solution of the IC-INT-VPX3d

product are summarized in figure 4 below.

It can be seen that when using a standard air cooled approach and whatever the air flow you are blowing into the chassis, the full 45W TDP of the Xeon D1559 cannot be reached at 70°C ambient temperature (AC3 VITA 47 Operating Temperature Class). So to get the maximum available power from the processor, this standard design can only be used in the AC1 VITA 47 Operating Temperature Class [0,55°C]. The plot shows that with the enhanced Interface Concept design, the full power of the processor is available at 70°C ambient temperature proving the validity of the approach.

This innovative VITA 48.1 thermal design is now used on all the new products as the IC-FEP-VPX3d for instance, that is a plug-in unit featuring a powerful Xilinx® Ultrascale KU115 FPGA for front end processing. Another example is the IC-PPC-VMEb board featuring two T2081 QorIQ® processors the full power of them being available in a legacy VME chassis considerably enhancing the processing power per slot when

retrofitting a VME system.

By constantly improving its numerical simulation tools and its experiment benches, Interface Concept keeps on developing new thermal management solutions.

Together with industrial and academic partners, the R&D effort is particularly directed towards the topics of conductivity and innovative heat spreading solutions for air cooled and conduction cooled designs.

Interface Concept Quimper, France 33 (0) 2 98 57 30 30 http://www.interfaceconcept.com

Figure 4 Comparison between standard and enhanced solution tested in the same chassis.

COTS Journal | September 2017

15

SPECIAL FEATURE SPECIAL FEATURE

Focus on Ruggedized Military Solutions

Mechanical Design Considerations for Microphonic Sensitive Devices in Military Vehicles Modern RF/microwave electronic systems and subsystems often rely on precision frequency sources that contain microphonic-sensitive components, like DROs, crystal oscillators, etc. Designing enclosures and other mechanical structures for such systems and subsystems presents substantial challenges, especially when aimed at mobile applications. The requirement to reduce size, weight, and power (SWaP) makes this task even more challenging for mechanical engineers working in the field of electronic packaging design. This article describes considerations for finding the optimal balance for often conflicting requirements like minimizing size while providing adequate sway space for vibe isolated modules/ components, maintaining high rigidity of the structure while minimizing weight, and other details. We will touch on the constraints imposed by SWaP reduction requirements and on vibe isolation system designs as well. However, a more detailed review would require a separate article.

Sergey Sokol, Analog Devices, Inc.

Introduction

M

icrophonic-sensitive devices and/ or components are often used in modern electronic systems and subsystems. When such a system or subsystem is intended for mobile applications, such as missiles, aircraft, or shipboard uses, the microphonic-sensitive device needs to be protected against shocks and vibrations to reduce degradation of electrical performance such as phase noise, spurious, etc. This can be achieved with passive or active vibe isolation systems. Active vibe isolation systems generally require significantly more space, are heavier than passive vibe isolation systems, and require power, which is usually at a premium in mobile systems and subsystems. Therefore, we will limit our discussion to applications where only passive, elastomer-based vibe isolation systems are utilized. However, most recommendations presented here will improve the performance of the systems/subsystems that employ active vibe isolation.

Background All the mechanical structures of an electronic system/subsystem can be viewed as a mechanical oscillator, as the unsupported sections of it, between attachment points to the next higher level assembly, will deflect under load. If such an external load is cyclical in nature, like the vibration of an 16

COTS Journal | September 2017

airframe or a ship hull, the structure will exhibit properties of an oscillator with its own natural frequency driven by rigidity of the structure and its mass. The more rigid the structure, the higher the natural frequency.

The higher the mass, the lower the natural frequency. This relationship between the aforementioned properties of the structure, pertinent to a simple harmonic motion type of response, is best described using the following equations:

Where is the radial frequency, k is the spring constant, and m is the mass of our system/subsystem. It is expressed in radians per second. To convert this into cycles per second, or Hertz (Hz), we need to convert radians into full cycles:

Structural Design Structures intended for mounting vibe isolated, microphonic-sensitive devices usually serve as a chassis for the subsystem or system as a whole. To get the most performance out of a passive vibe isolation system, it is beneficial to design a chassis as rigid as possible. This will move the resonant frequency of the structure as far away

Figure 1 FEA model (ANSYS) of a carrier plate under vibration. from the resonant frequency of a vibe isolated dielectric resonator oscillator (DRO) as possible. In this case, when determining the chassis resonant frequency, one must include the masses and/or point-loads of all the modules mounted to it. At this stage, using finite element analysis (FEA) software for determining the natural frequency appears to be more practical.

Ideally, the natural frequency ( fn) of the whole structure should be higher than the operating (electrical) frequency of the suspended microphonic-sensitive device ( for example, DRO). However, with modern devices operating in the GHz range, it’s hardly possible. Still, it’s advisable to push for the highest possible fn of the structure to minimize linear displacements of such structures under shock and vibration.

In the case of new designs, using multiple mounting points along each side of

SPECIAL FEATURE members is a very effective way to improve response of the structure exposed to shock/ vibe environments.

Material Sets

Figure 2 Preferred locations for microphonicsensitive devices.

the structure helps keep fn reasonably high.

However, it might be more difficult to achieve higher fn when one is working on a drop-in replacement design, where mounting points are often located far from each other, given the general tendency that each next-generation system/ subsystem is smaller and lighter than the previous one. That requires spanning considerable distances, which corresponds with the lower natural frequencies of the structure, in general.

Using the Full Extent of the Envelope to Improve the Rigidity of the Structure Quite often, the mechanical engineer working on packaging design for mobile applications is pressured to keep the lowest possible cover height or housing depth based on the height of the tallest electrical components in the volume to be encapsulated/covered. While it’s reasonable from the standpoint of minimizing the weight (and, often, cost of parts), it would be a bad tradeoff for designs where a passive vibe isolation system is employed. In these cases, the cover height (or housing depth) is one of the most powerful contributors to the rigidity of the structure. Steiner’s theorem of parallel axis describes this relationship very well.

Where I is a moment of inertia with respect to a given axis; Icm is a moment of inertia with respect to the axis drawn through the center of gravity; m is mass; and d is the distance between the two aforementioned axes (axes are parallel to each other).

As deflection of the structure is reverseproportional to the moment of inertia, increasing the distance between structural

While a mechanical engineer has very little leverage for choosing materials for printed circuit boards, microwave substrates, surface-mount components, or related items, where the major driving force is electrical performance regardless of structural properties (essentially, turning such parts of the design into dead weight from the structural standpoint), the materials used for enclosures and chassis can and need to be selected based on their structural properties.

Quite often, the choice is made in favor of the lowest density materials (aluminum and magnesium are rather popular from that standpoint), without taking into consideration other important properties, such as the modulus of elasticity (aka Young’s modulus) and Poisson’s ratio. The more appropriate approach, however, would be to use a quality one might call specific stiffness—a ratio between Young’s modulus and density. Namely, the elastic modulus per mass density of the material. From this standpoint, both aluminum and steel are about equally attractive as the specific stiffness is about the same for both. In one of our experiments, aluminum stiffener was replaced with steel stiffener for comparison.

Both configurations performed well, but the one with steel stiffener produced higher Q; therefore, aluminum was chosen for the final design.

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Figure 3 Example of actual design where a microphonic-sensitive device was placed in the middle of a higher level assembly.

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SPECIAL FEATURE

Figure 4 Example of actual design where a microphonic-sensitive device was placed in the middle of a higher level assembly.

For extreme situations, there are some exotic materials available, like CE7, CE11, and aluminum-silicon-carbide (AlSiC).

Some of them require extensive custom tooling, which translates into significantly longer lead times and cost. Others can be machined using conventional CNC milling machines (like CE7 and CE11), but require carbide tools with TiN coating to produce acceptable surface quality. The main advantage of such materials is the specific stiffness. These materials have a much higher

Young’s modulus than aluminum, while having about the same density. Disadvantages include high cost and a limited number of suppliers for such materials—which makes cost reduction for designs employing such materials quite difficult to achieve.

The comparison in Table 1 shows why aluminum is the material of choice, given its affordability, ease of machining, well developed plating processes, and other advantages. Diamond is added as a reference point only. We don’t suggest using it as a structural material for systems or subsystems, although its specific stiffness value appears very attractive.

Location, Location, Location Location is not as important in design as it is in real estate, but location is still very important for designing systems and subsystems that require vibe isolation of microphonic-sensitive modules. Vibe isolated modules located symmetrically with respect to mounting points of system’s or subsys-

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tem’s chassis will behave more predictably than the one located asymmetrically. In cases where two levels of vibe isolation are employed— one immediately around the sensitive component and the other at the next level assembly—symmetry needs to be maintained at both levels.

Placing the vibe isolated payload right in the geometrical center of the next higher level assembly is challenging—expect a rather strong pushback from electrical engineers and PCB designers as such placement would leave a less-than-optimal configuration of the real estate available for electrical component placement and PCB routing. However, this is a small price to pay compared with greater electrical performance degradation due to uneven loading of the vibe isolation system, resulting in a more complex and asymmetrical nature of mechanical vibration imposed on microphonic-sensitive components/modules.

Positive Side Effects of Designing for Microphonic-Sensitive Devices Most structures for microphonic-sensitive devices are designed with the reduction of displacement under shock/vibe in mind.

Therefore, they are overdesigned from the point of view of pure structural integrity.

This gives mechanical engineers peace of mind when it comes to overloading such structures for accelerated life testing, concerns about excessive flexing under load leading to violation of customer envelope, and other similar circumstances.

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COTS Journal | September 2017

The most generic architecture of a subsystem or system consists of several microwave modules aimed at possessing adequate structural qualities suited to carry vibe isolated payload, as is depicted in Figure 4.

The modules are mounted on both sides of a carrier plate, which also serves as a thermal conduction interface to the customer’s mounting surfaces (usually considered an infinite heatsink), in addition to structural service duties. The structural rigidity is ensured by adding top and bottom stiffening plates, which would be positioned in close proximity to the limits of the envelope defined by the customer’s specifications. Multiple linkages ensure a solid connection between both stiffening plates. Structures

SPECIAL FEATURE like this allow for maintaining significant structural rigidity over quite long spans between mounting points at the interface/ airframe. In cases where room between the outer surfaces of the microwave modules and customer’s envelope is very limited, steel stiffening plates will be more effective than aluminum ones.

Bolted Interfaces as Mechanical Attenuators In addition to a passive vibe isolation system, bolted interfaces between the airframe and vibe isolated payload act as vibration dampeners based on the micromovements they allow and the friction associated with those micromovements. Therefore, the more sequential bolted interfaces exist between the mounting tabs of the subsystem’s chassis and the attachment points for microphonic-sensitive device/module, the greater the attenuation of the vibrations propagating through the structure from the customer’s airframe to the module.

Frequency Plans Are Needed for Mechanical Design Subsystem/system fn should be far away from the natural frequencies of every module mounted onto it, unless one of the modules serves as a chassis for the entire subsystem/system. In that case, the fn for the module shall be calculated/modeled for the configuration where all modules (mass loads) are attached. The aforementioned mass loads will lower/ reduce the fn of the so-called chassis module.

Mixed Material Sets Requires Careful Analysis Designs with mixed material sets for structural components need to be carefully analyzed for the possible consequences of CTE mismatches ( for example, stainless steel 316 (16 ppm/°C), aluminum 6061 (23.6 ppm/°C). With the change of temperature, such mismatch may produce statically preloaded conditions leading to an increase of fn for structures comprised of parts with dissimilar CTE. If there are no other parts/ sections of the structure whose fn is higher, but not close to the fn of the module/section in question, this shift is of no consequence. However, if there are structures with a rather small offset of its fn to the fn of the chassis module, then the two natural

frequencies may end up closer to each other than desired, producing some degree of mutual amplification of shock/vibration—not quite reaching resonance yet, but an undesirable condition nevertheless.

If the next higher fn module is constructed from similarly form materials with different CTEs, its fn will increase as well, helping to maintain the delta fn in the safe region. This illustrates the positive effects of consistency in design practices, which reduces the likelihood of less than desirable outcomes at hardware testing.

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Conclusion Designing enclosures and other mechanical structures for systems and subsystems containing microphonic-sensitive devices presents substantial challenges.

However, there are certain specific considerations and design approaches that allow for a greater degree of first-pass success. Understanding the nature of the degradation of electrical performance due to mechanical impact is one of the most helpful qualities mechanical engineers working in the field of electronic packaging design can possess.

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19

SPECIAL FEATURE SPECIAL FEATURE

Focus on Ruggedized Military Solutions

Best Practices to Future-Proof Mil Test Systems with FPGA Hardware in the Loop As the lifespan of FPGA based ATE systems extends to 10, 20 plus years, practical techniques emerge which help ensure portability, operation, and maintainability long after the original coding is executed.

Brian Durwood, R&D Engineer, Keysight Technologies, Inc. & NDIA FPGA Usage Committee Member

F

PGAs are carving out an ever-increasing role in the deployment of flexible test solutions for large scale systems.

They extend the useful life of a test rig by providing some expandable hardware for new features. Major T&M companies “rent” user accessible FPGA space to extend the value and life of the instrument.

A subtle downside in the long-term cost of ownership is the portability of the customer created FPGA gateware or FPGA based test processes. ATE operators may find themselves with inadequately documented FPGA gateware that effectively locks them into a single brand, or worse, has become an orphan and must be recreated and requalified from scratch.

While any crystal ball is imperfect, we will explain practices to maximize the longterm portability in ATE equipment FPGA gateware. This helps to preserve the original investment and future choice of vendor.

How does the FPGA fit into ATE? FPGA Hardware in the Loop explained there are two common approaches to HIL (Hardware in the loop) as it applies to T&M instruments. While there are no explicit industry terms for these, we’ll identify them as Incremental and Internal.

Incremental resources are typically deployed in a modular architecture by which system components are individual modules slotted into a standard chassis. The screen 20

COTS Journal | September 2017

Figure 1a & 1b Modular form factors are most typical for adding “Incremental” FPGA assets. PXI has vertical slots, AXI has horizontal.

and keyboard are external. The two current popular form factors are PXI and AXI (Figure 1). Each format offers an optional module dedicated to adding a largely open FPGA to the instrument stack. In PXI (the more common of the two), these FPGA modules run $5,000 – $10,000 and integrate via electrical connection in the PXI chassis back plane, or via optical connector off the front panel. In a chassis, this might be slotted in between the signal generator and the digitizer. The pros are scalability and flexibility. You can add one or more functions per incremental module, nearly indefinitely. The cons are mostly the I/O. This approach is limited to the bandwidth of either the PXI bus, or the optical front panel connectors.

Internal resources are created by “renting space” on the actual instrument FPGA. Users insert applications in so called “green space” or “sandbox” that is “gasketed” from the code required to interface to the system and to run the actual instrument (Figure 2).

Internal FPGA access resides in the instrument motherboard FPGA where it “rents” space. Internal is the most tightly coupled and streams as fast as the instrument. But co-residing with system code is complex. FPGA design uses place and route to deploy an algorithm in the FPGA gates and resources. If a design is tweaked and accidentally needs more of a limited resource, (e.g. a DSP block) than available, timing can fail. This can be hard and time consuming

SPECIAL FEATURE

Design Entry Methods

Figure 2 Internal HIL deployment “gaskets” the system FPGA between User “green” space and Factory “blue” space.

to debug. Engineers often save these recompiles for the end of the day. However, if the gasket is well engineered or values being tweaked have little impact on hardware resources, “Internal” excels for streaming.

Just to dive in a little deeper in the Internal FPGA solution, some FPGA or T&M manufacturer’s software use Partial Reconfiguration to temporary depopulate noncritical features to free up FPGA space. In this method, you are provided a schematic representation of the design flow. In this example , the light red boxes are identified by the instrument manufacturer as requisite and cannot be removed. All else can be temporarily deleted to make space. Since the FPGA programming is just a boot up file, all features come back on the next power cycle.

There are over 2 dozen FPGA design tools, most of which are incompatible in that design files are not portable. Ironically, underneath most of them are the same two place and route tools that go the “last mile” to the actual FPGA. Most senior FPGA engineers will recommend using vendor neutral, modular, HDL to avoid lock-in. Let’s pull that apart a bit and explain.

Vendor Neutral. Each FPGA vendor often offers very useful preconfigured blocks.

For instance, high performance DSP applications will often require getting locked into one vendor’s DSP library. FPGA engineers will avoid vendor specific blocks as much as possible, or clearly segregate them when their performance is needed.

Modular. Just as in software, “spaghetti code” refers to monolithic projects for which sections cannot be improved without impacting the rest of the code. Best practices suggest programming one function per code module with well-defined interfaces and module-level verification that archives with the design files.

HDL. VHDL and Verilog are relatively equivalent, public, hardware description languages that natively compile to most brands of FPGA. They are harder to write in and becoming less common in EE college programs.

HDL blocks can be deployed within software

Figure 3 HDLs are the most portable design method but take some hardware skill (code from Wikipedia).

COTS Journal | September 2017

21

SPECIAL FEATURE from T&M instrument vendors. This may backfire if you’re going to mix and match instruments. The schematic entry method in Figure 3, is an example of a T&M vendor’s tool. It enables a non-FPGA programmer to change values within a reference design. Typically, this is just a shell over the FPGA manufacturer’s tool, such that closing timing issues may require “lifting the hood” and working with HDL anyway. It may be most prudent to retain the original design and test files in modular HDL (Figure 3).

High Level Synthesis (HLS) tools are promising, but still evolving. They let engineers describe algorithms in C, C++ or OpenCL (Figure 4). HLS “abstracts” away hardware to enable software engineers to compile automatically to FPGA. But achieving speed and efficient use of FPGA hardware resource takes practice.

Summary How to minimize vendor lock-in: 1.

Device independent design methodologies wherein you avoid, or abstract for easy replacement, all

22

COTS Journal | September 2017

manufacturer specific cores and libraries, where it can be done without compromising quality of results and schedule.

2. Ascribe to general software design “hygiene” practices of reusable modular coding with one function per block. If the budget allows, independently verify each module and attach the documentation to the files.

When lock in is inevitable or worthwhile FPGA System on Chip (SoC) is becoming mainstream. It includes a small processor (typically ARM), that can be deployed in single instances, such as a microcontroller, or in multiple instances parallel processing.

Embedded CPUs are great for control, selfcal, and acting as a “traffic cop” in an ATE system. Regardless of multiple vendors having processors identified as ARM, code is not always portable. Note that introducing a processor makes the FPGA more hackable.

FPGAs resist hacking by their lack of an operating system.

Advanced DSP functions are mainstream to FPGAs. Hence, the FPGA manufacturers have particularly rich DSP libraries.

Customers can commission “sandboxes” from equipment manufacturers to facilitate modification of FFT or other in-line processor functions.

These tweaks often lock to a brand.

Web-based FPGA compute arrays are winning a role in ATE data analytics acceleration. In a situation like ship-board systems it is not realistic, but in land based systems, compelling applications may arise.

The web based FPGA arrays are brand specific.

Figure 3 HDLs are the most portable design method but take some hardware skill (code from Wikipedia).

Other considerations towards preserving usability for future teams Archive design and test code with the exact set of software used originally. This is non-trivial. Place and route routines are improved to increase the efficiency with which they use available logic resources. This may change the physical implementation of an unchanged design from tool generation to the next. In contrast to compiling C to CPUs, with FPGAs, the co-optimized physical routing implementation of a design means that more things can change between tool generations.

If elements of the test stack are deployed on a COTS FPGA board, consider archiving a spare. They are manufactured in relatively small runs and compatibility is best assured by acquiring back-ups from the same batch.

FPGAs are useful in test stacks, offering customization and incremental streaming capabilities. You will see more test gear offering access to FPGAs. It can be part of a robust, long-lived system with a little forethought and hygiene.

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High Performance Cloud Computing: A Better Approach The Deep Learning Future

Google CEO Sundar Pichai, called deep learning, “a core, transformative way by which we’re rethinking how we’re doing everything.”

Deep learning is here – and it is changing everything. Tomorrow’s disruptive technologies and applications are being driven by deep learning. These advancements have already revolutionized autonomous driving cars, genome-based personalized medicine, fraud prevention, energy conservation, earthquake detection, deep space exploration, and many more life-enhancing pursuits. All made possible by exponential speeds, machine learning algorithms at the center of AI, and, really smart people.

Deep Learning Requirements

There are challenges. Deep learning and the associated massive data sets require high performance computing and storage.

NVIDIA Tesla P100 GPUs deliver up to 50X greater performance than traditional data center platforms. Plus, the projected growth of GPU usage outside traditional graphic acceleration is expected to increase by 5X over the next five years. For some time, the industry has viewed Tesla P100s as the benchmark for

high-performance GPU accelerated computing. New offerings from AMD and IBM are being released, as well as the imminent availability of NVIDIAs own Volta GPU. Custom FPGAs and ASICs are also getting attention among the deep learning crowd.

Nevertheless, high performance computing comes at a price.

The Traditional Path to Deep Learning

This level of computer performance requires significant capital investment, with systems starting at $150,000 US for a simple 8 GPU node like the Volta GPU-enabled DGX-1. A small GPU cluster of several multi-GPU systems costs upwards of $1M US,

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and larger clusters can run several million dollars each. On-demand, virtualized cloud computing offered by Amazon, Google and Microsoft, optimistically promise ubiquitous data crunching: access to vast, scalable resources for everyone. Yet, with the high cost of cutting-edge technology, the major cloud services aren’t offering the latest-generation multi-GPU solutions and clusters to all users; virtualized or not. It is understandable that companies feel held captive to capitalizing the equipment they need. Forecasts for deep learning software and hardware services alone are on a long-term 55-60% CAGR (compound annual growth rate). There is a better approach

A Better Approach

There is a movement to address the shortage of on-demand, state-of-the-art deep learning cloud computing.

SkyScale offers world-class cloud-based, dedicated multi-GPU hardware platforms and fast SSD storage for lease to customers desiring the fastest performance available. SkyScale builds, configures, and manages high-reliability, dedicated systems in secure and strategic facilities.

Why a Dedicated and Secure Environment is Critical

Virtualization is a key security and productivity concern.

Virtualized environments allocate resources of single nodes to multiple users managed by the system. Servers, storage, even individual GPU modules all get shared. In this scenario, security and the integrity of a job that’s running can be compromised.

Here’s a quick case study: Case Study (True Story) Company X initiated HPC service using one of the major cloud computing service providers. The HPC technology was the best they offered, but was not the latest generation. Configuration was complicated and under supported. Time was of the essence so Company X continued forward despite the deficiencies.

Thirty days into the project they were hit with large unexpected bills due to the elastic and demand-based pricing structure of

the service. It was a virtualized service. When more users log into the system, the pricing rises without the user’s knowledge.

Virtualization can also lead to users being locked out of the system. Company X was kicked off the service with minutes notice while their program was running so available resources could be shared by all comers and revenue could be maximized by the cloud supplier.

The end result: The Company got half-the-performance at more than twice-the-price than they would have with SkyScale.

(See Table 1 for comparison) SkyScale was founded by the leading manufacturer of super reliable, ultra-fast multi-GPU accelerators and storage. They create no-holds-barred computers for government contractors, oil and gas exploration, financial analysis, product and software development, radar and sonar defense, genomics, drug development, medical imaging, and many more. Whether you intend to use an HPC environment online or are looking to purchase a complete solution, SkyScale provides a quick and economical path toward a solution.

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SPECIAL FEATURE SPECIAL FEATURE

Focus on Ruggedized Military Solutions

The Role of VPX in the Data to Decision Chain In the rapidly evolving modern battlefield, today’s military relies on the timely analysis of aggregated Intelligence to fulfill short-term mission and long-term strategic aims. The technology that enables this requirement needs to be both open and robust to ensure rapid deployment and efficient use of resources in the face of loss of connectivity while being secure against attack.

Roy Keeler, Senior Product Manager, ADLINK

“

W

e’re going to find ourselves in the not-too-distant future swimming in sensors and drowning in data.”

This is a quote from retired Lt. Gen. David A. Deptula, Air Force deputy chief of staff for Intelligence, Surveillance and Reconnaissance (ISR) on January 2010.

Lt. Gen. Deptula’s comments highlight the military’s need for application-ready intelligent platforms to make sense of the data. The U.S. DoD and Agencies are moving towards cloud computing to establish a single, secure information environment that enables commanders to connect to, access and share the information they need in order to operate effectively. It allows them to maintain a strategic and tactical advantage over adversaries through information dominance by fully leveraging an optimal mix of approved government and commercial cloud service providers. Ultimately, both government and commercial cloud installations are used to harness all of the existing data.

The ability for Field Command Posts to aggregate considerable amounts of information and fuse it into advanced situational awareness requires significant processing power and sufficient network bandwidth with server-grade processors, broadband Ethernet and powerful GPGPUs. That’s one challenge the Army is facing 26

COTS Journal | September 2017

Figure 1 The combination of rugged hardware, deployed cloud applications, and a common data structure enables the capture of data that is critical for analytics useful in the field and the future.

as it works to deliver the next generation of command post equipment to support a more agile, expeditionary force. While the right technologies now exist -- from wireless tactical networks to intelligent power systems to mission command apps -- how they fit is still a matter of debate.

The Army’s Command Post 2025 vision, approved in the fall of 2015, emphasizes the burdens that the cumbersome, complex legacy command posts pose. They require

hundreds of feet of wires and cables, a deluge of transit cases and tents, and an entire day and a platoon of soldiers to assemble.

The vision aims to reduce that footprint by introducing integrated, scalable command post models that enable expeditionary maneuver across a broad mission set -- without sacrificing the advanced information technology that contributed to command post expansion in the first place.

This is where cloud and fog computing

SPECIAL FEATURE

Figure 2 Typical scenario of secure forwarding of data between fog subsystems containing edge node applications communicating with each other on a LAN, and other nodes and subsystems that are connected over a WAN.

can play a major role in the battlefield of the future. Cloud and fog computing, also referred to as deployed cloud (Figure 1), when coupled with the appropriate hardware, applications and a common data structure, will enable authorized users to harness the power of Big Data analytics.

This enables low-latency access to required data elements, regardless of location or device. But cloud technologies are not always available at the edge because of performance and resource constraints.

Fog computing extends the cloud computing paradigm to the edge of the network, overcoming latency and poor or intermittent bandwidth connectivity.

Fog enables the secure forwarding of data between fog subsystems containing edge node applications communicating with each other on a Local Area Network (LAN), and other nodes and subsystems that are connected over a Wide Area Network (WAN). Fog computing elements can continue to be used even if disconnected from the core network. The offloading of computational tasks from resource-poor mobile devices to more powerful machines in the vicinity is termed cyber-foraging. Figure 2 depicts a typical use case senario for fog computing.

The key elements of cloud/fog architecture include servers that are forward deployed, for example, on the battlefield much closer to the troops. The servers are discoverable, which is fundamental to how users access the services they provide. Users are able to discover the services they require at runtime without knowing the exact IP address of these applications in advance. The servers are typically Virtual Machine (VM) based so that computational resources and applications can be provisioned on demand. They can operate in a fully disconnected mode, with connection

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COTS Journal | September 2017

27

SPECIAL FEATURE

Figure 3 ADLINK’s VPX3010 is a This SWaP-optimized rugged VPX blade with the Intel® Xeon® Processor D SoC provides faster processing and GPGPU acceleration for boosted workload throughput..

to the cloud only required in some types of provisioning scenario, for example, if VMs and apps hosted in local cloudlet repositories need to be updated because newer versions have been made available.

Furthermore, mobile networks onboard ground vehicle platforms require reliable IP networking solutions, including rugged network routers and Ethernet switches, to connect tactical mission systems and sensors at the network edge. Rugged VPX based Ethernet subsystems and card solutions do just that. VPX’s small footprint enables manned and unmanned systems to securely and affordably deploy digital network architectures that empower situational awareness and network centric operations.

These products become the network backbone for delivering secure data, video, and voice services to mobile network nodes in very demanding environments.

In addition to hardware, commercial applications such as Vortex DDS by PrismTech (an ADLINK company) and Wind River’s Helix Device Cloud provide efficient, secure and interoperable Internet scale real-time data sharing. Middleware such as this is key enabler for systems that have to reliably and securely deliver high volumes of real-time data with stringent end-to-end qualities-of-service (QoS).

Vortex DDS, based on Data Distribution Service for real-time systems, provides LAN or WAN deployment over private or 28

COTS Journal | September 2017

public networks, clouds and fog networks with seamless integration to legacy and third-party applications with support for connectors for different communication technologies. Wind River’s Helix Device Cloud solution is the platform for remote control of IoT devices. Helix provides a centralized, cloud-based console for deploying, provisioning, monitoring, troubleshooting, and managing your entire fleet of IoT devices over their operating life.

In order for all this software to work, powerful local sensor processing is required. Sensor processing located at the edge of the cloud reduces the raw incoming sensed data into a coherent data set, from raw radar data into identified terrain and objects for actionable response. Or it stores the raw data for offline processing at a later date. In addition, local exploitation of raw data is needed in real time, such as target identification and tracking or IED detection These requirements are driving edge processors to do traditional applications in lower a SWAP envelope, for example using Intel Atom and ARM processors for low-level processing. Edge processors are also able to do more sophisticated applications in existing SWAP envelope utilizing powerful Intel Xeon® and FPGA processors as well as GPGPU processors from NVIDIA and AMD. The general-purpose graphics processing unit -- GPGPU for short -- represents perhaps the most revolutionary

leap in computer processing capability in decades for aerospace and defense applications. Not only does it offer advanced graphics rendering and massively parallel processing, but its capabilities in artificial intelligence and machine learning also are just being explored. The GPGPU chip has potentially hundreds of separate processing cores. Originally, these were for rendering complex graphics, and later for massively parallel processing. Today, they are considered artificial intelligence engines; each core can mimic a neuron in the human brain to offer machine learning.

VPX technology plays a key role in the Data to Decision chain by providing the compute power required at the tactical edge. VPX contains a rich ecosystem of processors, I/O, sensors and sub-systems than can provide the intelligence required to implement the Data to Decisions model.

Today many vendors now offer VPX products suitable for developing a tactical cloud computing environment for aerospace and defense.

For instance, COTS vendors offer rugged small form factor display computers that combine state-of-the-art CPU technology with the latest graphics processing units (GPUs) to deliver desktop performance to the rugged military and aerospace market. In addition to meeting increased demand for graphics rendering performance, these computers can also

SPECIAL FEATURE

support a 16-lane PCI Express implementation, providing the maximum available communication bandwidth to a CPU. VPX platforms can leverage the Intel Xeon D architecture’s capabilities to improve security and efficiency of the network. To simplify the implementation of distributed computing at the edge of the network, fog computing enables secure and interoperable data exchanges between fog subsystems containing high-performance edge node applications. They communicate with each other on a local area network (LAN), and other nodes and subsystems that are connected over a wide area network (WAN). In order to optimize both processing overhead and network bandwidth efficiency, fog computing enables the edge devices to be configured so that only “data of interest” is forwarded to the WAN. Leading this technological evolution is the ADLINK VPX3010 processor blade with 12-core Intel Xeon Processor D-1500 SoC which implements Intel’s new micro-server architecture to introduce the high-performance computing power formerly limited to larger form factors into embedded environments. This VPX processor blade includes dual 10G-KR with up to three 1G Ethernet ports latest platform aimed at meeting the rugged and standards-based requirements of today’s military and aerospace applications.

With products like ADLINK’s VPX3010, (Figure 3) system designers now have greater capability to collect, store, analyze, and share data, and more scope to convert that data into good, timely decisions. VPX is at the heart of this evolution, and will continue to be an important driver for systems designers well into the future.

In addition, OpenVPX and VPX switches and routers enable the vision of networked military and aerospace systems by providing systems integrators with a fast and powerful way to interconnect chassis, cards, and CPUs through switched Gigabit and 10-Gigabit Ethernet, as well as sRIO & InfiniBand links. Operating at wirespeed, Ethernet switching and routing can be used to architect the infrastructure for unified (Ethernet only) or hybrid (Ethernet control and other switched data-plane fabric) networks for transferring IP-based control and data packets within advanced

military systems.

Conclusion VPX offers designers a rich ecosystem of building blocks from multiple suppliers throughout the industry and these are but a few examples of how VPX technology can be used to develop Data to Decision systems. As the demand for timely, accurate and actionable information continues the

VPX community will be there to design and supply robust deployable systems to support today’s warfighters requirements for application-ready intelligent platforms.

ADLINK Technology San Jose, CA (408) 460-0200 military@adlinktech.com. www.adlinktech.com

Dawn Powers VPX Dawn’s PSC-6238 VITA 62 compliant 3U VPX Power Supply for conduction cooled systems is designed to operate in a military environment over a wide range of temperatures at high power levels. Up to 800 Watts available power.

Onboard embedded RuSH™ technology. Switchable Battleshort and NED functions.

Dawn is the leader in VITA 62 compliant power supplies for the mission critical market. Wide range of standard features, highly configurable through custom firmware.

Rugged, Reliable and Ready.

You need it right.

You want Dawn.

(510) 657-4444 dawnvme.com COTS Journal | September 2017

29

SPECIAL FEATURE SPECIAL FEATURE

Focus on Ruggedized Military Solutions

Advancements of the digital interface to increase bandwidth into the FPGA The benefits of phased array or active electronic scanned array (AESA) radar systems have been known for many years.

The basic idea is to replace the single, high power transmitter (exciter) and receiver with a large array of lower power transmitter and receiver elements. A great illustration is replacing a high power light bulb with multiple lower power LEDs. Tommy Neu, System Engineer, Texas Instruments

M

odern phased array radars consist of hundreds to tens of thousands of radiating elements. The beam of the individual elements is steered digitally by adjusting its power and phase. The beams of multiple elements can be bundled together (“beam forming”) by controlling the constructive and destructive interference of multiple elements. Beam forming is used to improve the radar range and achieve better target accuracy. Furthermore, steering the beams digitally removes the motor and hydraulics which eliminates the most common single point of failures and reduces system cost.

In order to identify smaller targets in ‘noisy’ environments, the phased array radar needs better resolution and accuracy by increasing the array size and number of elements. The data collection and synchronization of various receivers can quickly turn into a huge challenge. Misalignment of even a single sample across elements cannot be tolerated.

Until the recent industry adoption of the JESD204B digital interface, a parallel low-voltage differential signaling (LVDS) interface was the standard digital interconnect between data converters and FPGAs. Synchronizing multiple LVDS based converters requires a large scale timing calibration to ensure proper sample alignment across analog-to-digital converters (ADCs) 30

COTS Journal | September 2017

Figure 1 Timing skew challenges when interfacing multiple ADCs to an FPGA with parallel digital interconnects.

SPECIAL FEATURE

and digital-to-analog converters (DACs).

This entails careful trace length matching across all digital interconnects across all data converter as illustrated in Figure 1.

As one can imagine the parallel interface naturally restricts the number of converters that can be connected to one FPGA. A 250 MHz bandwidth captured by a 14-bit 1GSPS ADC for example requires 15 data signals (14-bit data plus one clock) or 30 pins from the FPGA. In order to improve the data transfer efficiency per IO pin, several different industries (defense, telecommunications, etc.) were pushing for a different digital interface that would support higher throughput rates.

In 2008, the JESD204A standard was introduced which uses a serial high speed interface with line rates up to 3.125GBPS. Due to the inherent 8b/10b encoding, a 3.125GBPS data rate only transmits about 156MSPS per differential pair from a 14bit or 16bit converter. Hence a 14-bit 1GSPS ADC still would require eight lanes or 16 pins. A true breakthrough in data transmission occurred in 2011 when the JESD204B standard was introduced and widely adopted by FPGAs. It supports data rates up to 12.5GBPS. That same 14-bit 1GSPS ADC now only requires two lanes to connect up with the FPGA, see Table 1. For the first time FPGAs can connect to a large number of high-speed data converters and enable large scale phased array radars.

Later this year likely the next iteration of the JESD204 standard (JESD204C) will be ratified which targets data rates beyond 25GBPS along with a more efficient encoding scheme (64/66b instead of 8b/10b). This drastic increase in data throughput per lane will enable a significant instantaneous bandwidth increase using modern GSPS RF sampling converters.

Texas Instruments Dallas, TX (972) 995-2011 www.ti.com/data-converters/overview.html

JESD204A

JESD204B

JESD204C*

Max supported data rate

3.125GBPS

12.5GBPS

25+GBPS

Data throughput per lane

2.5GBPS

10GBPS

24+GBPS

# of lanes for 14-bit 1GSPS ADC

8

2

1

# of lanes for a 14-bit 3GSPS ADC

24

6

3

# of lanes for a 12-bit 6.4GBPS ADC (ADC12DJ3200)

32

8

4

Table 1 Data throughput and number of lanes required for different JESD204 standards

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COTS Journal | September 2017

31

COTS

FIND the products featured in this section and more at

PRODUCTS

intelligentsystemssource.com

Acromag's New Ethernet Communication Modules Offer Optional Power Over Ethernet

Windows/Linux Embedded Computer with Kintex7 FPGA, Dual FMC IO Sites, Integrated Timing Support

AcroPack® AP580 Series provides 1Gb Ethernet communication plus a unique option for power over Ethernet on a PCIe format to provide power to powered devices.

Acromag has added to their PCIe-based AcroPack® modules - the AP580 Series. These mini boards provide a single Ethernet 10, 100, or 1000 Mbps port. An optional Power Over Ethernet (POE) model, AP580E-POE-LF, provides 52V DC and up to 10 watts of power to powered devices (PD). The POE Ethernet communication avoids other traffic on a network and is ideal for a video camera, VOIP phone, or any other PD devices. A down facing plug-in 100 pin connector ensures a secure connection for your I/O. This board supports Intel i210 Ethernet controller PROset to assist with diagnostics, tests, and configuration. These modules plug into AcroPack® PCIe, VPX, and XMC carriers in any combination for embedded applications running on Linux®, Windows®, or VxWorks® operating systems. AcroPack AP580 modules start at less than $850 and carriers at $750.

Acromag offers C libraries for VxWorks® and other operating systems. The libraries provide generic routines to handle reads, writes, interrupts, and other functions. Demonstration programs enable the developer to quickly exercise the I/O modules before attaching the routines to the application program.

This COTS line of AcroPacks are SWaP-C optimized, ROHS compliant and designed for scientific development labs, military and aerospace applications and the defense industry.

The ePC-K7 is a usercustomizable, turnkey embedded instrument that includes a full Windows/Linux PC and supports a wide assortment of ultimate-performance FMC modules. With its modular IO, scalable performance, and easy to use PC architecture, the ePC-K7 reduces time-to- market while providing the performance you need.

Distributed Data Acquisition – Put the ePC-K7 at the data source and reduce system errors and complexity. Optional GPSsynchronized timing, triggering and sample control is available for remote IO. Limitless expansion via multiple nodes. Up to 4 HDD for data logging.

Uniquely customizable - Dual FMC IO module sites - add anything from RF receivers to industrial control modules. Userprogrammable FPGA for IO interfaces, triggering and timing control, USB ports.

Remote or Local Operation - Continuous data streaming up to 1000MB/s or 2 x Gb/s Ethernet. Optional, stand-alone, autonomous operation with GPS-synchronized sampling.

Rugged – SSD boot drive support in a compact, rugged 8x11” footprint that is ready for embedded operation.

8-36V DC-Only Operation - Designed for portable or automotive data loggers or waveform generators.

Acromag, Wixom, MI (248) 295-0880. www.acromag.com

Innovative Integration Camarillo, CA (805) 383-8994 www.innovative-dsp.com

1U Rackmount Networking System with Intel Xeon E5 processors The PL-81230 is a 1U rackmount, high-performance networking system. The device provides the features of the new Intel Xeon E5-2600 V3/V4 processors coupled with the Intel C612 series chipset. The Xeon processor delivers high performance with up to 22 processing cores. The CPU can support 55MB of cache and a total of 80 PCIe lanes. PCIe expansion provides support for up to 32 GbE LAN ports.

The platform supports networking functions, such Unified Threat Management, SPAM filtering, firewall, routing and switching.

The device features sixteen DDR4 ECC Register DIMM (up to 2400 MHz ) and a maximum memory capacity of up to 512 GB. It has 80 PCIe Express lanes and can support up to 4 NIC modules and multiple Ethernet module bays to provide flexible port configuration, such as 1/10/40/Gigabit fiber and Gigabit copper LAN ports with optional bypass function.

Strong IO elements of PL-81230 include two management Ethernet ports (one for management, another for optional IPMI function), a console port, two USB ports, a Graph LCD module with 5-key keypad, LEDs for power/ HDD / 2x GPO. In addition, the PL-81230 supports internal 2.5” SATA HDDs/SSDs and onboard Compact Flash™ m-SATA/M.2 2280 slot for basic network storage applications.

Win Enterprises, Andover, MA (978) 688-2000. www.win-ent.com

32

COTS Journal | September 2017

COTS PRODUCTS

Lightning Platform GVC2000 Rugged HPEC Display Computer Lightning-based systems are designed to be delivered to precise customer requirements in weeks rather than months with a high degree of I/O customization, resulting in significant cost and time savings. Systems based on the Lightning platform are available in a number of small form factors, and are designed to fulfill a broad range of mission requirements.

One of the first Lightning systems the GVC2000 Rugged HPEC Display Computer is an ideal mission or graphics computer that is mission-ready out of the box, reducing program risk and cost. Although it's highly configurable to specific requirements, it's also available on surprisingly short lead times.

The GVC2000 features Abaco’s expansion module to provide highly configurable I/O options. It is an optimum fit for symbol generation, mission computing, demanding graphics generation applications, and GPU-accelerated data processing.

An immensely robust prequalification testing program ensures the GVC2000 will meets tough requirements with little, if any, additional testing needed.

The Lightning platform provides a common, modular, scalable platform, enabling it to address numerous system needs and utilizing a standard footprint and connector to minimize design efforts. It leverages the capabilities of Abaco’s flexible and patented MMS I/O technology designed to accommodate most I/O requirements.

It enables easy upgradability via the simple exchange of individual subassemblies.

Systems based on the Lightning platform are designed to meet a rigorous qualification process based on select MIL-STD-461G, DO- 160G, MIL-STD-704F and MIL-STD- 810G standards. Customers can leverage the already-qualified subsystem in their system level qualification efforts to reduce their costs and schedule for qualification.

Abco Systems, Huntsville, AL (866) 652-2226. www.abco.com

Rugged Networking System Provides Higher Performance in Edge Computing. NetSys-5303 Provides Secure Data Communications Across Wireless Channels Elma Electronic has extended its NetSys-530x family of rugged, secure networking products with the NetSys-5303, which now adds edge computing capabilities on top of the rich Cisco-enabled routing functions of earlier NetSys systems. The model 5305 also incorporates the latest in Intel Core i7 CPU options, multi-terabyte data storage plus GigE ports expansion.

Based on Elma’s building block design concept for modular electronics, the NetSys-5303 is an extendable and configurable system enabling cost-effective upgrades for future expansion or system redefinition.

The new NetSys-5303 offers higher performance computing as well as secure routing connectivity to a wide range of applications in ground, ship and air defense equipment, drilling and mining operations, commercial air and ground transport infrastructure, energy distribution and homeland security and emergency services.

NetSys-5303 performs pre-processing tasks at the network edge, while bringing more secure data processing to in-the-field, remote and mobile applications.

In addition to a choice of Intel Core i7 CPUs, the system features dual routing ports, nine GigE and FE switching ports, a high capacity, multi-terabyte removable storage bay and optional

CANbus support.

Its modular design enables a host of I/O options including a full range of video, audio, USB, digital and GPIO connectivity.

Highly visible front LEDs indicate power and system status as well as link activity.

Routing is provided by integrated Cisco IOS Embedded Services Routing (ESR) software for secure data, voice and video communications across wired and wireless links. This dependable architecture provides secure connectivity for mobile and remote data applications.

The SWaP-optimized NetSys-5303 platform incorporates Elma’s extensive experience in rugged packaging design for harsh application environments. Features include an IP67 rating for ingress protection, MIL-STD 810 compliance for extended temperature, shock and vibration requirements, and a power supply that is MIL-STD-704F, 1275D and 461F compliant.

Elma Freemont, CA (510) 656-3400 www.elma.com

COTS Journal | September 2017

33

COTS PRODUCTS

Fanless 18.5" Wide Screen Panel-PC for Rugged Environments The silent, space-saving PANEL18 is a front-end interface for rugged, secure, or sensitive environments, where reliability and quality are important considerations.

The PANEL18 combines a 18.5” rugged display with excellent optical specifications, an optional touch screen, and a complete range of low power CPU based SBCs, from Single-Core Atom up to i7 Quad-Core.

The 18.5" LCD with LED backlight comes with 400 cd/m2, a contrast ratio of 1500:1, and an operating temperature of -20°C up to +70°C. The resolution is 1920x1080 with an angle of view in all four directions of 85°. Optionally, the display can be equipped with capacitive Touch Technology.

The utilized embedded board computers come from the CEC or PIP Family and are 100% designed and produced by MPL AG in Switzerland. It can be chosen from various low power Intel CPUs, from Atom single-core, or up to i7 quad-core. The CEC and PIP boards used, are equipped with embedded longterm available Intel CPUs and include features like; up to five GbE ports, up to seven USB (3.0 and 2.0), up to four serial ports (RS232/485), etc.. The “All-inOne“ Panel PCs can be expanded over the internal mPCIe slot with WLAN, Bluetooth, LTE, or any Fieldbus.

The front of the PANEL18 is an IP65 protected, powder coated aluminum frame. On the back are standard interfaces available (can be customized).

The Solution can be equipped with M12 to be used in Railways or Maritime application, other connectors are available on request. The standard supply power is 12VDC or optionally with 9-36VDC / 48VDC or 110VDC. Like all other MPL products, the PANEL18 does not require a fan, is very flexible, and can be adjusted to the customer needs and requirements.

MPL Scottsdale, AZ (480) 513-8979 www.mpl.ch

34

COTS Journal | September 2017

SyncServer S650 SAASM Time and Frequency Server Improves Immunity from GPS Jamming and Spoofing for Military Systems The modular Microsemi SyncServer S650 SAASM combines time and frequency instrumentation with flexibility and network/security-based features.

The base Timing I/O module with eight BNC connectors comes standard with the most popular timing I/O signals (IRIG B, 10 MHz, 1PPS and so on). When more flexibility is required, the Microsemi FlexPortTM Technology option enables six of the BNCs to output any supported signals (time codes, sine waves, programmable rates), all configurable in real time via the secure web interface. The BNC-by-BNC configuration makes very efficient and cost-effective use of the 1U space available. Similar functionality is also applied to the two input BNCs. Unlike legacy modules with fixed count BNCs outputting fixed signal types per module, FlexPort technology can allow up to 12 BNCs output in any combination of supported signal types.

This level of timing signal flexibility can eliminate the need for additional signal distribution chassis as there is no degradation in the precise quality of the coherent output signals.

For applications requiring superior low phase noise (LPN) 10 MHz signals, two different LPN modules are available. Each module has eight extremely isolated 10 MHz LPN outputs with each module offering excellent levels of LPN or Ultra LPN performance.

The GPS SAASM GB-GRAM MPE-S Type II PPS receiver coupled with Microsemi's patented active thermal compensation technology provides accuracy of <20 ns RMS to UTC (UNSO). This is in addition to a durable hardware design subjected to MIL-STD810G testing, high-reliability components extending the operating temperature range from -20°C to 65°C, and a dual power supply option. In addition, upgrading to a highperformance oscillator, such as a Rubidium atomic clock, keeps the S650 accurate for long periods in the event of a GPS service disruption.

The S650 SAASM utilizes several security features and protocols. Unsecure access protocols are deliberately omitted while remaining services can be disabled.

The four standard GbE ports accommodate more than 10,000 NTP requests per second using hardware time stamping and compensation. For more secure NTP operations, enable the optional security-hardened NTP ReflectorTM with line speed, 100% hardwarebased NTP packet processing.

The S650 SAASM includes additional built-in hardware features enabled through software license keys such as the security-hardened NTP ReflectorTMand IEEE 1588 PTP operations.

Microsemi Aliso Viejo, CA (949) 380-6100 www.microsemi.com

COTS PRODUCTS

Rugged Ethernet Switch and High-End Ethernet Switch Core Modules with PTP Support Kontron RES2404-PTP switch, ESC1600PTP and ESC2404-PTP with PTP clock synchronization for use in harsh environments The high-end Rugged Ethernet Switch (RES) is in a 19-inch 1U housing with two fully managed Ethernet Switch Core Modules (ESC). The RES2404-PTP switch as well as the ESC1600-PTP and ESC2404-PTP modules expand Kontron’s portfolio of rugged switching devices for harsh environmental conditions with Precision Time Protocol (PTP) enabled solutions. The PTP protocol for the precise synchronization of clocks throughout a computer network in accordance with the IEE 1588 standard is especially important for decentralized systems in automation technology. Control units in power distribution facilities, motion control systems, but also metrology devices that need to relay precise values over long distances, rely heavily on PTP. The RES2404 is a cost effective, fully managed 19 inch 1U Ethernet switch for industrial and military applications. The RES2404 can be monitored remotely via SNMP (Simple Network Management Protocol), command line or web interface. The L2/L3 switch with IPv6 support is available in two versions. The RES2404-PTP features 24 Gigabit Ethernet (1 GbE) and four 10 Gigabit Ethernet Ports (10 GbE), the RES2404-PTP-POE comes with additional 24 Power-over-Ethernet (PoE) ports with up to 150 watts in total, with a 30 W maximum per single port. Extremely robust mechanical design features make it suitable for use in production facilities, naval and military applications.

The RES2404 is highly resistant to shocks and vibrations, and suitable for use in a wide temperature range from -20°C to +50°C. The ESC1600-PTP and ESC2404-PTP L2/L3 1/10GB Ethernet Switch Core modules form a foundation for robust high-performance Ethernet switching devices. Due to the scalable number of interfaces, both boards provide a versatile feature set on a custom base board design. Both modules support the IEE1588v2 PTP standard for time-sensitive applications. The ESC1600-PTP and ESC2404-PTP feature up to four 10GbE and 24 1GbE ports, with the option of up to 32 1GbE ports on special request. Both modules are rugged, with high tolerance against shocks and vibrations, and are fully operational even in temperature ranges from -40°C to +80°C. Remote management is supported via SNMP, command line and web interface.

Kontron (800) 294-4558 www.kontron.com

Network Security TOE Module for Altera and Xilinx FPGAs for their 10G & 40G Full TCP & UDP Accelerators A full TCP and UDP Accelerator with Network Security capability which performs functions of firewall and other monitoring functions at full line rate. In addition to full TCP/UDP offloading, this security module performs port filtering, blocking, monitoring and related functions in FPGA hardware thereby relieving CPU from these tasks. They are performed in nanosecond speeds and with ultra precision. The fact that CPU which gets bogged down under high traffic rates and sometimes missing some events, can be used for other application functions.

Ultra-fast and precise processing time of around 100 nanoseconds for this module including TCP and UDP with thousands of sessions initially at 10G, sets the bar higher for speed and performance powered by a 7+ year mature and proven TCP Protocol Compliant architecture.

The architecture which implements Network Security module coupled with TCP and UDP Accelerators running at full 10G and 40G Line rate.

Working out of the box solutions with Choice of Cores implementing and this security module with 1K, 512, 256, 128, 32 and fewer concurrent TCP/UDP Sessions will be available in Q3 2016.

Santa Clara, CA (408) 496-0333 www.intilop.com

COTS Journal | September 2017

35

COTS

PRODUCT GALLERY AcroPack® APA7-200 FPGA PCIe-based Boards PRODUCT DESCRIPTION: • Low Cost: Under $1,000 USD • Conduction or air-cooled options • Low Power: +3.3V (±5%) 500mA Typical • Flexible I/O: RS485/422, LVDS, TTL, and more • COTS Designed • Superior Software Tools (Drivers & EDK) • PCI Express Generation 1 interface • Reconfigurable Xilinx® Artix-7® FPGA • VPX, XMC and PCIe Carrier Options The APA7-200 series provides a FPGA based user-configurable bridge between a host processor and a custom digital interface via PCI Express. These boards offer a low-cost, high-performance FPGA solution. Developed for adaptive filtering & processing applications.

Acromag

Phone: (877) 295-7084 Web: www.acromag.com/APA7

Small Form Factor (SFF) Solution 760-92 PRODUCT DESCRIPTION: • Received Gold Rating at the 2016 Military & Aerospace Electronics Innovators Awards • Enables Use of Commercial Mini-ITX Processor in Rugged, Deployed Applications • Rated for altitudes in excess of 50,000 feet • Highly optimized for size, weight, and power (SWAP) constrained applications

36

COTS Journal | September 2017

Atrenne Integrated Solutions Contact: Jim Tierney Phone: (800) 926-8722 Email: sales@atrenne.com Web: www.atrenne.com

Flash Storage Array with 200TB capacity in four removable canisters

50TB data in each 7 Lb. removable canister

• 100Gb Infiniband or Ethernet connections • MIL-STD 810 and 461 tested • Two versions: airborne and ground • 4U rackmount unit

(877) 438-2724

www.onestopsystems.com

POWER COMPONENT DESIGN METHODOLOGY

Solving the Power Challenges of SWaP-C Requirements for MIL-COTS Applications Application Examples using the Power Component Design Methodology See examples of how using Vicor components help meet SWaP-C requirements Avionics Computer Challenges Low profile components (8 mm), facilitate a redundant compact solution and meet high temperature (125°C) requirements.

Learn more about solving the challenges in Avionics Computer >

L1

28V

DCM

12V

ORing

12V

ZVS Buck

1V

28V

DCM

12V

ORing

12V

ZVS Buck

3.3V

28V

DCM

12V

ORing

12V

L2

L3 12V

Communications Equipment Challenges The DCMâ&#x20AC;&#x2122;s fixed switching frequency (750 kHz) enables a compact EMI filter to meet stringent conducted noise specifications.

L1

EMI Filter

28V

DCM

28V

48V

Learn more about solving the challenges in Communications Equipment > (8)

Airborne Equipment Challenges Scalable modular DCM based design, enables high power, regulated outputs with up to 200 mF of bulk capacitance.

L1

Custom DCM

220V

182A (2)

Learn more about solving the challenges in Airborne Equipment >

L2

Custom DCM

Jammers and Countermeasure Challenges

BCM

91A

(2) L1

High efficiency ZVS regulators (95%) enable high temperature operation with minimal power de-rating.

12V

Learn more about solving the challenges in Jammers & Countermeasure Equipment >

12V

3.3V

ZVS Buck (2)

L2 3.3V

ZVS Buck (2)

L3 12V

3.3V

ZVS Buck

UAV Challenges

L1 300V

DCM

24V

300V

DCM

24V

300V

DCM

24V

300V

DCM

24V

300V

DCM

24V

300V

DCM

24V

Lightweight DCMs (29.2g) enable a scalable high density power design.

Learn more about solving the challenges in UAV Equipment >

L2

L3

300V

Tether L4

L5

L6

Expanding the Family of MIL-COTS Products MIL-COTS Isolated Regulated Converter Modules

MIL-COTS Isolated Regulated Converter Modules

MIL-COTS DCM™ DC-DC Converter Modules in a ChiP Package >

MIL-COTS DCM™ DC-DC Converter Modules in a VIA Package >

Input Voltages:

Input Voltages:

9.0 – 50 VDC, 16 – 50 VDC, 160 – 420 VDC

Output Voltages: 3.3V, 5V, 12V, 15V, 24V, 28V, 48V Output Power:

3623 ChiP: Up to 320W 4623 ChiP: Up to 500W

Efficiency:

Up to 93%

Dimensions:

3623 ChiP: 38.7 x 22.8 x 7.3 mm 4623 ChiP: 47.9 x 22.8 x 7.3 mm

16 – 50 VDC, 160 – 420 VDC

Output Voltages: 5V, 12V, 15V, 24V, 28V, 48V Output Power:

3414 VIA: Up to 320W 3714 VIA: Up to 500W

Efficiency:

Up to 93%

Dimensions:

3414 VIA: 89.5 x 35.6 x 9.4 mm 3714 VIA: 95.3 x 35.6 x 9.4 mm

MIL-COTS PI31xx DC-DC Converter Modules > Input Voltages:

28 VDC (16 – 50 VDC)

Output Voltages: 3.3V, 5V, 12V, 15V Output Power:

Up to 50W

Efficiency:

Up to 88%

Dimensions:

22.0 x 16.5 x 6.7 mm

Point-of-Load Regulators (MIL-COTS Compatible) Cool-Power® ZVS Buck Regulators > Input Voltages:

12V nominal (8 – 18V) 24V nominal (8 – 36V) 48V nominal (36 – 60V)

Output Voltages: Wide output range (1 – 16V) Output Current: 8A, 9A, 10A, and 15A versions Efficiency:

Up to 96.5% Light load and full load high efficiency performance

Dimensions:

LGA SiP: 10 x 14 x 2.56 mm LGA SiP: 10 x 10 x 2.56 mm

MIL-COTS Filter Modules MFM DCM Filter > n Provides MIL-STD-461 EMI filtering and MIL-STD-704 and MIL-STD-1275 transient protection n For use with 28V and 270V nominal input voltage DCM products

MQPI Filter > n Provides MIL-STD-461 EMI filtering n For use with MIL COTS PI31xx regulators

Cool-Power® ZVS Buck-Boost Regulators > Input Voltages:

8 – 60V 16 – 34V 21 – 60V

Output Voltages: 10 –50V 21 – 36V 36 – 54V 12 – 34V Output Power:

Up to 240W continuous

Efficiency:

Up to 98% efficiency at >800 kHz FSW

Dimensions:

LGA SiP: 10 x 14 x 2.56 mm

Design your Power System in 90 seconds using the Power System Designer Tool.

Learn how to get to market faster with 4 easy steps: www.vicorpower.com/video/psd

COTS

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Index

intelligentsystemssource.com

Company Page# Website

Company Page# Website

Acromag, Inc........................................2............................ www.acromag.com

One Stop Systems...............................37................www.onestopsystems.com

AIM USA..............................................11........................ www.aim-online.com

Pentek..................................................5............................... www.pentek.com

Critical I/0...........................................23........................... www.criticalio.com

Phoenix International...........................4............................ www.phenxint.com

Dawn VME...........................................29.......................... www.dawnvme.com

Pico Electronics...................................13................. www.picoelectronics.com

Elma Electronics.................................17................................. www.elma.com

SkyScale........................................... 24-25.........................www.SkyScale.com

Intelligent Systems Source................7, 31..... www.intelligentsystemssource.com

Star Communications Inc....................18......................www.starcommva.com

Innovative Integration.........................21..................www.innovative-dsp.com

SynQor.................................................41...............................www.synqor.com

Meritec................................................42............................. www.meritec.com

Themis................................................27.........................www.hyperunity.com

MPL AG................................................22......................................www.mpl.ch

Vicor Corporation.............................38-39...................... www.vicorpower.com

New Wave DV.......................................19.......................www.newwavedv.com

COTS Gallery Ads..........................................................................................36

COTS Journal (ISSN#1526-4653) is published monthly at 940 Calle Negocio, Suite 230, San Clemente, CA 92673. Periodicals Class postage paid at San Clemente and additional mailing offices.

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40

COTS Journal | September 2017

Mil-Standard Compliant Highest Efficiencies Field Proven

Military-Grade Power Hi-Rel DC-DC Power Converters & Filters  Fixed switching frequency  No opto-isolators  Parallel operation with current share on MQFL  Remote sense  Clock synchronization  Primary referenced enable  Secondary referenced enable on MQFL  Continuous short circuit and overload protection with auto-restart feature

 Input under-voltage and over-voltage shutdown  Output voltage trim range (MQHL, MQHR and MQBL) +10% to -10%

 Full Power from -55°C to +125°C

Specification Compliance

Made in the USA

 MIL-STD-704 - Aircraft Electrical Power

 MIL-STD-461 - Electromagnetic Interference

 MIL-STD-1275 - Vehicle Electrical Power

 MIL-STD-810 - Environmental Engineering

1-978-849-0600

www.SynQor.com/C2

Innovative-Interconnect Solutions

®

Backplane-Cabling Backplane Backplan e -Cabling System

Solving the th OpenVPX OpenVPX Multi-gigabit I/O Problem ®

The success of Meritec’s VPX+® cabling system has spawned a new cabling system that replaces the need for the Multi-Gig (TE TM) connector and it is field deployable.

The new VPX+DA® (Direct Attach) cabling system (product currently in development) reduces weight and cost while improving performance. Preliminary VPX+DA® SI simulations are showing 25Gb/s performance. The VPX+DA® is an ideal solution for pulling various protocols from Slot to Slot and Backplane to I/O at higher speeds. VPX+DA® is the ideal SWaP solution.

For development and demonstration applications, VPX+® Cabling is the obvious solution for multi-gigabit OpenVPX® I/O

and custom slot-slot backplane interconnect in lieu of using one or more Rear Transition Modules (RTMs).

For rugged deployment applications, VPX+DA® Cabling is the rugged solution to solve trace loss issues for today’s newest multi-gigabit OpenVPX I/O. As compared to VPX+® cabling, VPX+DA® Cabling directly replaces both the RTM backplane connectors and mating VPX+® connectors for both cost and weight reduction while realizing increased performance.

Contact a MERITEC Solutions Specialist or visit MERITEC.com to see our proven array of interconnect solutions.

Meritec | 888-MERITEC (637-4832)

Contact: info@meritec.com Facebook: www.facebook.com/pages/Meritec/142140812492429 Linkedin: www.linkedin.com/company/meritec-inc.