RTC Magazine March 2009

The magazine of record for the embedded computing industry

March 2009

www.rtcmagazine.com

Getting the Most out of

MULTICORE PROCESSORS

Ethernet Beyond 10 Gigabits: Ready for Prime Time?

Speed Simulations with a Reflective Memory Network Build or Buy: The Case for Outsourcing ATCA An RTC Group Publication

Getting the Most out of

MULTICORE PROCESSORS

40 High-Density AC-DC Adapters for Medical Applications

42 Blue Lasers Target Micro-Projectors

TABLEOF CONTENTS

45 Digitizer Uses FPGA Technology, Multi-channel A/D and D/A

MARCH 2009

Departments

Technology in Context

system integration

Multicore Processors

Real-Time Software

5Editorial 10 The Taming of the Multicore Finding Fruit in the Economic Forest Insider Solutions Engineering 6Industry Latest Developments in the Embedded Marketplace Paul Fischer, TenAsys

8 40

Beyond 10 Gig Ethernet

Small Form Factor Forum Software Compatibility with the Flick of a Switch

16

Products & Technology Newest Embedded Technology Used by Industry Leaders

Industry Insight

Views & Comment 48News, Wine from Sour Grapes

40 and 100 Gigabit Ethernet: Ready for Real-Time?

Rob Kraft, AdvancedIO Systems

High-Speed Networking

When Do You Need Real 26Exactly Time?

Paul N. Leroux, QNX Software Systems

INDUSTRY WATCH

Solutions Enable Migration 30Silicon to Next Generation Networks Moshe De-Leon, Siverge Networks

vs. Buy: The Case for 36Make Outsourcing Complete ATCA Systems Brian Wood, Continuous Computing

up Your Real-Time Digital Simulation System 22 Speed

Herman Paraison, Dolphin Interconnect Solutions

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March 2009

3

MARCH 2009 Publisher

Embedded Super Power #102:

PRESIDENT John Reardon, johnr@r tcgroup.com EDITORIAL DIRECTOR/ASSOCIATE PUBLISHER Warren Andrews, warrena@r tcgroup.com

Super Small Board size: 1.85” x 1.75”

Editorial EDITOR-IN - CHIEF Tom Williams, tomw@r tcgroup.com CONTRIBUTING EDITORS Colin McCracken and Paul Rosenfeld MANAGING EDITOR Marina Tringali, marinat@r tcgroup.com COPY EDITOR Rochelle Cohn

Art/Production CREATIVE DIRECTOR Jason Van Dorn, jasonv@r tcgroup.com ART DIRECTOR Kirsten Wyatt, kirstenw@r tcgroup.com GRAPHIC DESIGNER Christopher Saucier, chriss@r tcgroup.com DIRECTOR OF WEB DEVELOPMENT Marke Hallowell, markeh@r tcgroup.com WEB DEVELOPER James Wagner, jamesw@r tcgroup.com

PIC32

INTERN Andrew Fuller, andrewf@r tcgroup.com PIC24

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To Contact RTC magazine: HOME OFFICE The RTC Group, 905 Calle Amanecer, Suite 250, San Clemente, CA 92673 Phone: (949) 226-2000 Fax: (949) 226-2050, www.rtcgroup.com EASTERN SALES OFFICE The RTC Group, 96 Dudley Road, Sudbury, MA 01776 Phone: (978) 443-2402 Fax: (978) 443-4844 Editorial Office Warren Andrews, Editorial Director/Associate Publisher 39 Southport Cove, Bonita, FL 34134 Phone: (239) 992-4537 Fax: (239) 992-2396

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March 2009

3/20/09 10:44:41 AM

Tom Williams, Editor-in-Chief 245-M Mt. Hermon Rd., PMB#F, Scotts Valley, CA 95066 Phone: (831) 335-1509 Fax: (408) 904-7214 Published by The RTC Group Copyright 2008, The RTC Group. Printed in the United States. All rights reserved.

All related graphics are trademarks of The RTC Group. All other brand and product names are the property of their holders.

MARCH 2009

EDITORIAL

Finding Fruit in the Economic Forest

by T om Williams Editor-in-Chief

W

hat is this elusive beast known as “the consumer” and how important is he/she to our daily lives in the embedded industry? As an OEM-oriented industrial trade publication, RTC does not directly address the consumer market.

That is, we seldom if ever deal with the design issues involving end-user consumer products—cell phones, TVs, audio systems and so on. Sometimes it seems like that might be a lot of fun, but it’s not our focus and rightly so.

Nonetheless, all the things that our market does address ultimately depend on the purchase decisions and purchase power of end users and consumers. I was recently in an upscale kitchenware store where I saw an interesting little gadget that was billed as a corer for chili peppers. It was a little green plastic gizmo with a strangely shaped blade on a card covered with shrink wrap.

For some reason the thought occurred that for that odd little item to get onto that pegboard, somebody started out with an idea and a sketch that led to a conversation and ultimately to a series of meetings, the assignment of some poor designer to come up with a prototype, marketing discussions and even perhaps some research, more meetings, budgeting, design and finally the scheduling of manufacturing, sales and distribution. It’s a good bet that the manufacturing involved the creation of injection molds and the programming of automated machinery for fabrication and packaging. This almost certainly required the use of embedded intelligence and the modification if not creation of software.

Now multiply that thought process by every gadget on the 18-foot-long pegboard, then out into the store and on to all the other stores on the street. At that point you are looking at a very large part of what drives the embedded industry—making things that people buy. Beyond making them, it includes transporting them and communicating information about them. But if an insensitive husband or a whimsical kitchen geek does not pick up that chili pepper corer and buy it, all of the other stuff does not happen.

Somewhere some industrial engineer sat through a sales presentation from an equipment manufacturer who had in turn listened to a pitch from a controller board salesperson about why their module was the right choice for the design of a new injection molder. The engineers at the board vendor had probably

never designed the module with a single thought to the needs of injection molding, but rather for the general requirements of a class of automated equipment. But the connection of their concerns to the person browsing a display of kitchen gadgets is direct and vital to success all along that chain. And if that chain breaks, then what?

In the current economic downturn, we hear that the driving force of the economy is consumer spending, and for that to happen there needs to be confidence so that there can be a return of lending, etc., etc. This applies not only to big-ticket items like cars and trucks, but also to things like chili pepper corers that ultimately wind up languishing in the back of a drawer. The question that should arise for our industry is: given the falloff in enduser consumer spending, which will bring with it an inevitable shrinking of revenues, what is the best focus for industrial use of embedded electronics and systems? Interestingly, there still appear to be opportunities.

For better or worse, it is now clear that there will be a large infusion of government money into areas involved with infrastructure, energy and data communication—both in medicine and in the general expansion of broadband. Although, somewhat ironically, these consumers of the technology do not reach all the way to the end-user consumer; the use of the technology to encourage job growth is part of an effort to restart consumer spending. Another obvious area is the military. I have spoken directly with a number of vendors who are excited by the announced plans for drawdown in Iraq because it means that the less money spent on boots and bullets frees up funds for equipment upgrades and replacement, which certainly involves electronics.

So while our industry is certainly not immune from the recession, it may be more advantageously positioned than others to survive it. By focusing on those areas (where there is at least some actual money available) that will consume embedded computing intelligence for the purpose of creating the material foundation and the job growth that may restart the economy—and hopefully put money back in the pockets of end-user consumers—we may be able to weather the storm, help a general recovery and ultimately return to our spoiled conception of prosperity.

March 2009

5

IndustryInsider MARCH 2009

Over $25 Billion: Total Size of the Embedded Software Engineering Market

Soft

Algor Engin ithm eers

Op Sy era ste tin ms g

A series of Embedded Systems Market Statistics reports Develo Model Tes pment ing To ting Tools ols too Th ls from Venture Development Corporation Research provides a tim ird p Spend on e s arty oft ru Commercial Embedded wa nSoftware Solutions detailed, vertical-by-vertical analysis of key embedded indusre tries. Within these reports, VDC provides estimates for the Spend on Embedded total market for embedded software engineering (TMESE), Software Engineering Labor which is believed to represent more than $25 billion worldHidden opportunity for commercial software solution providers wide.

B o Eng ard While spending on commercial software and tools for ine IC ers En /SoC Test ers gineer ine s Eng embedded software engineering represents a large portion of the TMESE, spending on engineering labor continues to represent a substantial piece of this market opportunity. VDC views this larger market size to be most representative of the total revenue opportunity for software vendors. Vendors who provide xploration solutions able to increase developer efficiency, improve time-to-market, and reduce labor costs can r your goal potentially capture a greater portion of the value of the engineering effort that the software they ak directly page, the provide replaces.

The TMESE calculation stems from recent upgrades to VDC’s Embedded Systems Market Staresource. hnology, tistics Model. This model also provides key metrics regarding the global engineering population and nd products embedded projects, with an emphasis on vertically, regionally and task-specific analysis. ngin

System

eers

Engineer s

E ware

vanced hardware acceleration, allows the companies to offer NEPs immediate solutions that support high-performance LTE networks. anies providing Continuous solutions nowComputing has Available now, this combination announced collaboration ation into products, technologies and companies.with Whether your goal is to research the latest from Continuous Computing and cation Engineer, or jumpNetworks to a company's page, the goal of Get Connected is to put you Cavium in a technical joint effort Cavium Networks solves critical ce you requirethat for whatever type of network technology,equipwill provide performance issues for NEPs as es and products you are searching for. ment providers (NEPs) with a well as reduces time-to-market, combined high-performance soproject risk and overall cost and lution that can support the comcomplexity. plete range of long-term evolution Continuous Computing’s (LTE) network elements, from Trillium LTE software—includLTE Base Stations (eNodeBs) to ing Diameter, S1-AP, eGTP, GTP, evolved packet core (EPC) deMAC, PDCP, RLC, RRC and vices, including mobility manX2-APsupports LTE Femtocells, agement entity (MME), serving macro/pico LTE base stations, gateway (SGW), packet data netand each of the network elements work (PDN) gateway and evolved within the EPC. All Trillium LTE packet data gateway (ePDG). protocols are compliant with the The combination of Conlatest 3GPP-defined LTE specifitinuous Computing’s Trillium Get Connected cations and are multi-threaded for LTE software and mentioned Cavium’s with companies in this optimized article. performance on multiOCTEONwww.rtcmagazine.com/getconnected multicore processor core processors. Trillium LTE family, which boasts a 16-core software also includes reference MIPS64 architecture with ad-

Continuous and Cavium Collaborate on Wireless Solutions for LTE Networks

End of Article

Get Connected with companies mentioned in this article. www.rtcmagazine.com/getconnected

6

March 2009

applications for relevant LTE interfaces such as LTE-Uu, S1, S5, S6, S7, S10, X2, etc.

Low-Voltage Motor Drives Market Expected to Grow During Downturn

According to the latest statistics from IMS Research, the worldwide market for low-voltage AC & DC motor drives experienced unprecedented revenue growth in 2007, increasing by 19.7% over 2006 levels. Data reported by leading drives suppliers indicate all regions and industry segments exhibited strong growth during the year.

The market is expected to continue performing well despite the global economic downturn, with positive growth forecast for both 2008 and 2009, when annual revenue growth should bottom out at 3.7%. High energy prices and an increased focus on energy efficiency will maintain posi-

tive growth of market revenues, which are expected to increase by an average annual rate of 10.4% throughout the forecast period to reach an estimated value of $13.6 billion by 2012.

Lead by infrastructure expansion in China and India, the Asia Pacific motor drives market experienced the largest amount of growth in 2007, and was the second largest regional market after EMEA. Valued at nearly $2.4 billion, the drives market in Asia Pacific is expected to continue growing at the fastest rate over the next five years. However, difficult economic conditions around the globe will slow growth across all regions, with most impact felt in the drives markets in the Americas and Japan. The success of recently introduced government stimulus packages will determine the severity of the market downturn. Positive growth in the utilities, food & beverage, chemicals & petroleum and renewable energy industries is expected to offset declines in the metal processing, mining, textiles and commercial HVAC industries.

Economic Downturn Speeding Trend toward Standards, COTS

In a new report tracking Advanced Telecommunications Computing Architecture (ATCA) adoption among Network Equipment Providers (NEPs), analysts from VDC Research Group predict an accelerated trend away from proprietary architectures developed in-house and toward open standards and Commercialoff-the-Shelf (COTS) building blocks. Analysts say the economic downturn is hastening a trend that was already well underway.

The new report “ATCA Adoption Trends Within The Network Equipment Provider Community,” predicts that 85% of Tier I

Industry Insider NEPs will be implementing the standard ATCA architecture by the end of 2010, and the percentage of those implementations using COTS building blocks will increase as NEPs look to prioritize their research and development budgets in the economic downturn.

VDC Research Group surveyed nearly 30 NEPs for the report and found that more than half of Tier I NEPs and more than three-quarters of Tier II and III NEPs are currently implementing ATCA. As standards like ATCA and MicroTCA have matured, many NEPs have shifted their competitive focus away from hardware and integration to the software layer.

“Service providers want options that include server-based, IP-centric platforms that are future-proofed for the continued evolution of their networks,” said Ron de Lange, executive vice president with Tekelec. “With open standards like ATCA, we minimize costs and deliver highquality multimedia session management products by leveraging a strong supplier ecosystem and the economies of scale that come with a common architecture and components across a broad range of network elements.” A case study on Tekelec’s implementation of ATCA is included in the report, which was commissioned by the Communications Platforms Trade Association (CP-TA).

National Instruments to Further Medical Device Development with Grants in 2009

National Instruments has announced it will continue its investment to further medical device development by offering software and training grants in 2009. As the global economic climate tightens, the medical device

industry continues to thrive. A recent study of more than 1,000 medical device manufacturers by medical device consulting firm Emergo Group, reported 61 percent of respondents expect sales for their companies to increase in 2009. To help medical device manufacturers meet this demand, NI is accepting applications for the 2009 Medical Device Grant Program, which provides startup assistance for those who are interested in using NI hardware as a component of their medical devices.

Because many of the innovative advances in medical technology over the past 20 years have been developed by small, entrepreneurial medical technology companies, National Instruments has created a grant program that awards up to $25,000 in software and services to start-up medical device companies that are evaluating NI hardware as a component of their devices. The goal of the grant program is to help startup companies reduce the cost and complexity of development by providing them with technology such as the easy-to-use NI LabView graphical system design platform. NI is accepting applications for the grant program until Nov. 30.

In 2008, National Instruments granted more than $340,000 in software and training to 21 medical device developers. Engineers use NI hardware and software solutions for medical devices to save time and money during medical device design, prototype and deployment.

Using NI hardware and software, domain experts can automate traditionally low-level implementation tasks with LabView and spend more time researching science and developing treatments. For example, with an arsenal of embedded electronics, 2008 grant recipient Quark Cybernetics and Fundamental Re-

search Laboratories is using LabView and NI hardware to create an advanced electrocardiogram, which aims to predict cardiac pathologies using advanced mathematical algorithms.

MIPS Technologies Joins the Linux Foundation

The Linux Foundation (LF), the nonprofit organization dedicated to accelerating the growth of Linux, has announced that MIPS Technologies has become a member of the Foundation. MIPS Technologies is a provider of industry-standard architectures, processors and analog IP for digital consumer, home networking, wireless, communications and business applications.

By joining the Linux Foundation, MIPS Technologies will help drive growth and promotion of Linux among its customer base and beyond. MIPS Technologies joins a leading group of companies who are experiencing business success and market expansion based on customer leverage of Linux and open source technologies.

“A large majority of MIPS developers are using Linux for product development,” said Udi Kalekin, vice president of software engineering at MIPS. “We are pleased to join the Linux Foundation as part of our commitment to maintaining and enhancing our contribution to the Linux community. We envision an evolution in consumer platform support on multicore systems powered by Linux, and our work with the Linux Foundation will accelerate this process.”

“Companies such as MIPS Technologies are making smart decisions in tough times,” said Jim Zemlin, executive director at The Linux Foundation. “The company’s work on Linux and desire to collaborate with its peers and the community will only help to

increase its already strong market position. We’re looking forward to MIPS Technologies’ contributions to the Foundation.”

Texas Instruments Acquires CICLON Semiconductor

Texas Instruments has acquired Bethlehem, PA-based Ciclon Semiconductor Device Corporation, a designer of highfrequency, high-efficiency power management semiconductors.

Ciclon Semiconductor Device Corporation is a fabless provider of high-frequency, high-efficiency power MOSFET and RF LDMOS and semiconductor solutions for high-performance applications.

The acquisition expands TI’s capability to improve energy efficiency in today’s end-equipment designs, including high-power computing and server systems.

Designers who incorporate Ciclon’s power management technology can double a power system’s operating frequency and achieve greater than 90-percent power efficiency in a footprint up to 20 percent smaller than today’s power supply. TI uses its application knowledge and high-performance analog manufacturing capabilities to provide discrete and integrated power management solutions for any portable or line-powered power design challenge—from cell phones and portable medical equipment to telecom, industrial and computing applications.

March 2009

7

SMALL FORM FACTOR FORUM

Software Compatibility with the Flick of a Switch

A

hhh, software. Can’t live with it, can’t live without it. Or so it seems during some projects. In this new world order of limited development budgets, it’s certainly the 800-pound gorilla in the room.

There was a time when hardware could be chosen first, then operating systems and development tools, and application software development occupied the rest of the project. In this highly evolved world of FAA, FDA, FCC, CE, EMI, UL, EN, NEMA, IP, MIL-STD and other regulations, certifications and compliance requirements, developers have a great deal of incentive to reduce and reuse. Just like a municipal recycling program.

Faced with extensive re-certifications, the clear choice is to ensure that new hardware maintains software compatibility at all levels. In some cases, certification filings themselves are drastically simplified if the code remains unchanged. Ever wonder about the 286-class system running the hospital equipment you’re hooked up to? Try implementing a memory hole, an A20 gate, assigning fixed IRQs, or initializing a PS/2 keyboard in the dawn of the UEFI BIOS era on a multicore low-power processor with dual PCI Express x1 lanes…a feast for a firmware king or queen if there ever was one. How about booting a custom OS for which the source code disappeared during the last millennium?

Job security for a contractor, or that old software guy that retired a few years ago.

The hardware designer gets to search the world over for that elusive legacy-friendly specification on a component or board datasheet, the proverbial needle in the haystack. For if such electronics cannot execute the 800-pound code properly, it’s back to the hardware drawing board. That code ain’t gonna change.

For those lucky enough to be working with application source code in a high-level language like C with a robust, industry-standard OS interface, life is easier. Not only is the migration from platform to platform less painful, but moving to a completely new CPU architecture and instruction set is within the realm of possibility. At worst, the software engineer rolls up his or her sleeves and plays around with a compiler switch or two—endianness, registers, not a big deal. There are always a few “gotchas,” and verification and field trials can be tall orders, but the application remains fundamentally intact. Compatibility with the “flick” of a compiler switch.

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March 2009

Suddenly, the enticing set of new low-power, small form factor components and boards can lead to stretching that ol’ code for one more generation. The software engineer insists upon four PCI bus masters, but that tiny 5-watt board comes with a “legacyfree” warning label. Tiny IC packages present several space-efficient, speedy PCI Express links instead of the legacy PCI bus.

Now the question becomes how to attach those four PCI-style (or worse, ISA-bus) devices.

For designers accustomed to maintaining ancient code along with the processors to which they are shackled, the term “PCI Express” may sound like massive overkill. At 2.5 times the bandwidth of parallel PCI, and duplex capability on separate transmit and receive differential pairs, each of the point-to-point PCI Express lanes has more than enough performance. Best of all, software protocols are preserved going from PCI to the equivalent PCI Express device.

But as a point-to-point bus, each of the four PCI devices would require a separate PCI Express lane. For new chipsets with only one or two PCIe x1 (“by one”) lanes, there is plenty of bandwidth to cover the four bus masters. Commercial PCI Express switches allow the mapping of one lane to multiple lanes, and the switches are smart enough to figure out where the data needs to go. This time, hardware saves the day, and software compatibility is maintained with the flick of an Express switch.

Modern chipsets offer plenty of new alternatives for attaching low-speed peripherals and I/O, although minor code changes are needed to make the connection (otherwise known as the “no free lunch” rule). For example, board-to-board communication over serial ports can be modified to ‘speak’ I2C, LPC bus, or even SPI. Some of these are processor-agnostic, and this type of code change is certainly simpler than converting to heavyweight, driver-intensive USB, Ethernet, or PCI Express communications.

Even ISA-bus-dependent code can be preserved with PCI-to-ISA or LPC-to-ISA bridges and ISA cores in FPGAs. New chipsets and programmable devices give hardware designers an “out.” After all, if the software engineer isn’t happy, nobody is happy.

Comments about this topic can be sent to sf3@rtcgroup.com.

Colin McCracken

& Paul Rosenfeld

Technology I n C onte x t

ploration your goal k directly age, the source. ology, d products

multicore processors

The Taming of the Multicore Using multicore CPUs to build asymmetric multiprocessing systems cuts costs and improves responsiveness in embedded systems. It even lets you mix DSP with general applications on a single multicore processor—just ask Shakespeare.

by P aul Fischer TenAsys

I

n the popular Shakespeare comedy, The Taming of the Shrew, Lucentio DSP VM Windows VM RTOS VM travels to Padua to attend school at the INtime Virtual Machine Manager local university. Upon his arrival he meets the beautiful Bianca and, smitten with GPOS GPOS RTOS DSP love, his priorities change instantly from CPU CPU CPU CPU Quad Core Processor attending to his studies to winning her hand. Unfortunately for Lucentio there are a few roadblocks: Bianca already has Figure 1 Consolidating three separate machines into one with a quad-core many suitors, and her father, the wealthy processor. old Baptista, has made it known that no nies providing now Bianca until her older sisonesolutions may court ion into products, technologies and companies.

Whether your goalthe is to research the latest I know it’s a stretch—had Lucentio not embedded system designer, could not ter, the ill-tempered Katharina (aka ation Engineer, or jump to a company's technical page, the goal of Get Connected is to put you been able to “change his priorities in- meet his goals of a system with “predictShrew), is married first. you require for whatever type of technology, stantly” he might have lost the race for able results.” Each suitor in the comedy The comedy and products you are searching for. continues with Lucentio Bianca’s hand; he had to make decisions played different roles but all of them and two other suitors disguising themin “real-time” and respond to actions by contributed to the final outcome. Modselves with the intent to trick Baptista and the other suitors in a “timely fashion.” ern embedded systems also have many win Bianca’s heart. The “Katharina probThe appearance of Petruchio and others roles to play: a GUI and enterprise netlem” is solved when Petruchio arrives in on the scene allowed for additional plots work interacts with the outside world, a Padua from Verona to find himself a rich to be played out “in parallel” with the real-time control loop works with mawife. In the end, three couples are married, but only one with “predictable re- plot to win Bianca’s heart. Without this chine-level I/O in a time deterministic “parallel processing” the comedy would manner, and analysis modules requiring sults” that you can “bank on.”

So what does Shakespeare have in have lost its pace and become nothing but numeric-intensive operations are needed to implement complex system functions. common with multicore and real-time? a forgotten story.

The same is true for embedded sys- Taking on all of these roles in an inextems. Without the ability to respond to pensive small form factor platform is the Get Connected inputs, control priorities and perform challenge faced by today’s embedded with companies mentioned in this article. tasks in parallel, our protagonist, the system developer. www.rtcmagazine.com/getconnected

End of Article

10

March 2009 Get Connected with companies mentioned in this article.

Technology In Context

Asymmetric Multiprocessing Meets the Challenge

Just like the multiple plots that operate in parallel in Shakespeare’s comedy, embedded developers can use the multiple cores available in today’s low-cost processors to implement parallel tasks. But rather than relying on a single operating system (OS) to arbitrarily assign those tasks to the processor cores based on a symmetric multiprocessing (SMP) scheduling algorithm internal to the OS, you can assign the cores to specific tasks using multiple operating systems and an asymmetric multiprocessing (AMP) solution.

Partitioning resources in a biased manner is a common design practice. For example, a DSP board or embedded processor card might be used for real-time data collection, processing and control; while a separate user-interface computer interacts with the outside world. In this case, expensive communication links are needed to coordinate the disparate realtime hardware with the high-level supervisory control computer.

Rather than allocating time-critical software to an expensive stand-alone processor or DSP board, you can run an RTOS on a dedicated processor core and use it to provide the same functions as an entire CPU board. The remaining core(s) can host your general-purpose operating system (GPOS), such as Windows. This lets you optimize the cost of your hardware and your software engineering resources.

Using shared memory to communicate between the RTOS and the GPOS (each OS resides on distinct cores of the same machine) provides for very low-cost and efficient transactions without the expense and complexity of extra hardware (Figure1).

Such a system is an asymmetric multiprocessing system because the processor cores are not being load-shared across a single OS but are dedicated to specific tasks, in this case simultaneously running multiple operating systems. You have ultimate control over the priorities and applications that run on each RTOS core, unlike the situation with a GPOS. Real-time application developers work with low-level hardware and need guaranteed access to I/O, timers, RAM and CPU cycles. User-interface, database and networking programmers must deal

with high-level APIs and complex data exchange protocols. By giving each discipline the best environment for their job—a real-time operating system (RTOS) for the former and a general-purpose operating system (GPOS) for the latter—and hosting both on a low-cost multicore platform, you can minimize your cost-of-goods, decrease your time-to-market, and maximize the use of your engineering resources.

DSP Replacement

Most modern general-purpose processors contain SIMD instructions (Single

Instruction, Multiple Data) designed to perform vector and matrix arithmetic. On Intel Architecture (IA) processors they are known as the MMX and SSE instructions. MMX instructions are limited to integer operands; SSE instructions accommodate floating point operands and vector arithmetic. These SIMD instructions are ideal for implementing digital filters, digital control loops, pattern recognition algorithms, and video streaming and mixing applications.

SIMD instructions have been a part of the Intel Architecture since the Pen-

450 400 350

Relative Determinism of IPP Functions On Windows (red) vs. INtime (blue)

300 250 200 150 100 50 6%

0

Figure 2

2%

1

12%

3%

11%

2

2%

3

14%

3%

14%

4

3%

7%

5

3%

26%

6

3%

7

Determinism comparison between Windows and the INtime RTOS.

Multi-OS Application RTOS Processes

GPOS Processes

RTOS Kernel and Drivers

GPOS Kernel and Drivers

Shared Memory

Dedicated GPOS Core

Dedicated RTOS Core

core 1

Inter-OS IPC

core 2

Dual-Core Processor

Figure 3

Shared-memory as an inter-process communication mechanism.

March 2009

11

Technology In Context

Video Decode/Encode

Audio Decode/Encode

JPEG/JPEG2000

Data Compression

Cryptography

Speech Coding

Speech Recognition

Image Processing

Image Color Conversion

Computer Vision

Signal Processing

Vector/Matrix Mathematics

String Processing

Data Integrity

Ray Tracing/Rendering

Table 1

IPP library application domains (see http://www.intel.com/software/ products/ipp).

conga-CAx

Industrial Temperature Range -40 to +85° C Onboard Flash Drive up to 4 GByte Intel® Atom™ processor Z520PT 1.3 GHz Intel® US15WPT System Controller Hub Intel® GMA 500 Graphics Engine Up to 2 GByte DDR2 onboard Memory COM Express Compact, 95 x 95 mm Pinout Type2 Advanced BIOS Features

congatec, Inc., 2187 Newcastle Ave, Suite 201, Cardiff by the Sea, CA 92007 USA Phone +1 760-635-2600, Fax +1 760-635-2601, sales-us@congatec.com, www.congatec.us 1 12Untitled-2 March 2009

3/20/09 10:49:34 AM

tium III. The instructions operate similar to those found on a DSP. In the latest IA processors the number of SIMD instructions available, with all their variations, is over 200! The instructions perform a variety of packed arithmetic, move, compare, conversion and logical operations, all designed to address the needs of digital signal processing algorithms.

Given the large number and complexity of the SIMD instructions, the notion of using SIMD to achieve DSP-equivalent functionality might feel overwhelming.

Fortunately, the Intel Integrated Performance Primitives library provides a relatively easy way to take advantage of SIMD instructions without having to be an SIMD expert.

The Intel Integrated Performance Primitives (the IPP library) is a collection of functions optimized for Intel Architecture SIMD instructions. The library takes full advantage of the advanced MMX and SSE instructions found on x86 processors without requiring that you be an expert at using the SIMD instruction set.

The library is divided into a number of functional groups, or application domains. These domains encompass a broad range of digital signal processing functions for handling tasks like matrix arithmetic, digital filters, audio, image and video encoding and decoding, and string processing. These application domains are summarized in Table 1.

For each application domain, the library provides function primitives that implement key algorithm and performancesensitive operations. These primitives perform single, specialized operations with minimal overhead and include the ability to control numeric precision and error handling. Variants of each primitive are optimized to specific data operand size and precision requirements.

When you read the literature for the Intel IPP library you will find that it is designed and sold only for use with the Windows, OS X and Linux operating systems.

No variants of the library are targeted for use with an RTOS. So how can an embedded developer take advantage of this tool to easily apply SIMD instructions to realtime applications on a dedicated core that is masquerading as a DSP replacement engine?

Technology In Context

Fortunately, the IPP library is OSagnostic; meaning it does not require an OS-specific API. And because the INtime RTOS utilizes the Microsoft Visual Studio compiler and integrated development environment (IDE) as its build and debug platform, real-time applications built for the INtime RTOS use the same calling conventions and library and object code file formats as those used by Windows applications. Thus, you can link the static edition of the IPP library file with your real-time application and utilize the SIMD-optimized IPP library primitives within your real-time application.

Applying the IPP library is a very time-efficient method by which to apply x86 SIMD instructions to a real-time application. It gives you the means to quickly and easily substitute a real-time application on a dedicated CPU core for an expensive DSP board, with the added benefit of avoiding the task of writing your own library of SIMD functions in assembly language.

when applied to a GPOS and an RTOS on a multicore machine, we measured the real-world variations in execution time of a JPEG test application. The test machine was “loaded” with multiple simultaneous system-intensive activities consisting of: a string search through all files on the local hard drive, viewing a small video in a continuous loop with a third-party video player, and continuously playing mp3 files in Windows Media Player while it gener-

ated a “visualization” display of the music being played. The results are shown in Figure 2.

The measurements shown in the chart tabulate the results of encoding seven uncompressed bitmaps into equivalent compressed JPEG files (1 7). Each red and green cluster contains six bars representing six successive encodings for an identical bitmap. The gray bars overlaying each cluster are the standard deviation of

Raw Performance and Determinism

The raw performance gains possible with the SIMD instructions are very appealing. Depending on the specific operations, speed improvements of more than 10x are possible, compared to the equivalent function performed using generalpurpose processor instructions. Your actual performance gains, of course, depend on the nature of the application and the mix of SIMD operations (or IPP functions) used.

If you compare the raw performance of an SIMD application on an idle machine running a GPOS, such as Windows, to that of the same application running on an RTOS, the numbers are virtually identical. But running an application on an idle machine that must perform many tasks in parallel is not a very good measurement of real-world performance. The difference between running an SIMD application on an RTOS and running it on a GPOS is not performance, but determinism. To successfully replace a DSP with a CPU core on a multicore processor, you need both raw performance and determinism In order to illustrate this difference in determinism for an SIMD application Untitled-24 1

March3/11/09 2009

13

1:34:47 PM

Technology In Context

the bars within that cluster, expressed as a percent of the mean execution time of the cluster. In other words, the red and green clusters over x axis label “1” represent the times to encode bitmap “1” over six successive runs: one set of six on the Windows OS and one set of six on the INtime RTOS, and so on.

Windows and INtime share a single multicore machine, therefore, activity on the Windows OS represents potential in-

terference to real-time applications on the INtime RTOS. However, INtime processes always have precedence over Windows processes, assuring control of priorities and real-time determinism for the real-time applications. This is illustrated by the green bars (the INtime measurements), which are consistently faster and more consistent in their execution times than the red bars (the Windows measurements).

In this example, on a busy system, a variation of 3% or less was measured when running the JPEG encoding application as a real-time process on a dedicated core.

Whereas the same application running as a Windows process runs longer and experiences variations in mean run times between 6% and 26%.

Consolidating two or more operating systems on a single platform requires a new form of inter-OS communication.

Shared memory is the logical choice, since each OS runs on one (or more) core of a single processor. Message signaling between cores can be facilitated using the Inter-Processor Interrupts (IPIs) built into the CPU cores. A shared-memory interface is capable of providing very highperformance communication (Figure 3).

More complex protocols may then be built on top of this base.

Virtual devices can be used as the interface for inter-OS protocols, especially for integration with existing legacy applications; for example, a virtual Ethernet or a shared-memory PCI device. In the case of a shared-memory PCI device, each guest operating system contains a virtual PCI device driver configured to point to the shared memory in which applications can post common data. After a virtual PCI device updates the shared data structure it signals the other virtual devices, using the IPI, to indicate that a data update has occurred.

The net gains from the application of multicore processor platforms to real-time embedded applications are the elimination of redundant computer and communication hardware, faster communication and coordination between RTOS and GPOS subsystems, improved reliability and robustness, reuse of proven legacy applications, and simplified development and debugging. Significant cost savings can be achieved by condensing systems comprised of separate GPOS, DSP and realtime hardware subsystems onto a single, multicore, hardware platform.

TenAsys Beaverton, OR. (503) 748-4720. [www.tenasys.com].

1 14Untitled-8 March 2009

3/19/09 10:26:22 AM

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solutions engineering

Beyond 10 gig Ethernet

40 and 100 Gigabit Ethernet: Ready for Real-Time?

With 10 Gigabit Ethernet just ramping up in deployment, the natural question is, “What about 40GbE and 100GbE?” In terms of real-time applications, the needed tweaks are being made to 10GbE, but for now 40 and 100GbE remain in the server space—for now.

by R ob Kraft AdvancedIO Systems

W

hile 10GbE is barely off the launching pad in terms of broad deployment in just about any market space, recent excitement has turned to 40GbE and 100GbE. It’s not a stretch to acknowledge that real-time embedded engineers, who are often also technophiles, are likely to be seduced by the allure of such high bandwidth technology.

So, the question is: should those of us in the real-time space shelve the just-ordered 10GbE technology and start designing 40GbE or 100GbE into our next-generation bandwidth-hungry applications?

Has 10GbE already become passé?

In December 2007, the IEEE P802.3ba 40 Gbit/s and 100 Gbit/s Ethernet Task Force was formed out of the High Speed Study Group (HSSG) that had been working since 2006. At the time of writing this article, the most recent release from the task force was P8023.ba Draft 1.2, on February 10, 2009.

The targeted date for a ratified standard is June 2010. Current predictions are that 100GbE will “take off” in 2013. 40GbE is expected to ramp up sooner. For reference, Table 1 shows how 10GbE rollouts compared to predictions and gives some data about 1GbE rollouts at selected points after the respective standards’ ratification dates.

Factors Driving 40GbE and 100GbE

Increases in Internet video traffic are driven by sources such as YouTube, highdefinition IPTV, video conferencing, and

16

March 2009

10GbE Physical Interfaces

Interface to External Time Lag

Modified Stack Behavior and Additional Application-Level Offload

Time Stamp Interface ApplicationOptimized Connectivity Engine

FPGA

Memory Control

Buffering For Line Input

Memory Host Fabric Interfaces

Figure 1

Elements of an FPGA-based solution that implements features required for real-time 10GbE connectivity.

enterprises migrating from private networks to Internet-based VPNs. To adequately service the increasing bandwidth demands of their customers, ISPs need to increase their backbone bandwidth at a ratio that may be 4x to 10x the customer’s needs. In addition, large search engine and social networking companies are eyeing 100GbE as a solution to their bandwidth needs for inter-data-center network aggregation.

Simultaneously, 40GbE (and good “old” 10GbE) are being driven by the growing needs for data movement between servers and other computing applications within data centers. The higher bandwidths not only solve data aggregation

and improve the flow of information, they also can reduce cabling infrastructure—a non-trivial problem given the number of servers in a data center.

A recent report cited the number of servers in 2007 to be 11.8 million in the U.S. and 30.3 million worldwide, up more than 4 times from a decade earlier. Analysts also predict that the U.S.’s 6600 data centers (where most servers are hosted) will need replacing or retrofitting in the next several years. Clearly, there are lots of servers to interconnect and lots of “voltage” behind the market force.

To support the 40GbE and 100GbE data rates, there have been several inno-

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SOLUTIONS Engineering vations. Some have been driven by the fact that current technology does not permit the transmission of 40 Gbits/s or 100 Gbits/s in a single stream over any optical fiber or copper wire. For instance, in the current baseline, 100GbE would be transported in parallel over cables consisting of 10 fibers, or 10 wires, or using 4 wavelengths in the case of single-mode fiber.

Except for increased data rate, there are no changes proposed at the Ethernet MAC layer (compared to 10GbE). Still, the base-

line has introduced the concept of multiple lanes and multi-lane distribution (MLD) at the Physical Coding Sublayer (PCS).

This was done to accommodate combinations of differing numbers and speeds of parallel electrical lanes and media lanes (fibers, wires, or light wavelengths), and to decouple those two numbers since electrical and optical technologies will develop at different rates.

Among other changes is an evolution of the now-familiar XAUI (10 Gigabit

Attachment Unit Interface), used for onboard signaling, into XLAUI (40 Gigabit) and CAUI (100 Gigabit). The ‘XL’ and ‘C’ correspond to Roman numerals for 40 and 100. To accommodate the higher rates (10.3125 Gbaud per lane, compared to XAUI’s 3.125 Gbaud per lane), XLAUI and CAUI use 64B/66B encoding, which has a reduced overhead (3%) compared to 8B/10B (20%) used in XAUI. 40GbE is handled in 4 XLAUI lanes, and 100GbE in 10 CAUI lanes.

Application-Level Characteristics

At the moment, the driving applications involve aggregation and distribution of data. But eventually, the data has to terminate at processors or other devices. The termination problem is challenging even at 10GbE (sometimes even at 1GbE), where processors get clobbered by the effort of running the protocol stacks. It stands to reason that the termination problem will be 4x to 10x worse for the case of 40GbE and 100GbE. In the commercial space, the solution at 10GbE typically involves forms of protocol offload, whereby some or all of the protocol processing elements are farmed out to a coprocessing ASIC. However, there are a variety of application characteristics unique to many real-time I/O applications that use 10GbE. These characteristics are not encountered in the server space, so server space solutions do not address them.

Real-time test and measurement, scientific, defense, hardware-in-the-loop simulation, and other multi-sensor systems rely on incoming data being accurately time stamped. The time-stamping aligns data arriving from multiple sources or sensors to permit detailed off-line analysis, as inputs into models in real-time processing, or to tightly control the release of data in complex simulation systems. At the higherperformance end, the CPU cannot time-tag data with accuracy and precision since, by the time the packets reach this point, they have gone through several non-deterministic interfaces. A solution is to stamp the packets at the 10GbE interface ingress point, before they ever get to the CPU. Most real-time applications begin as a stream of digitized analog real-world sensor signals in a control, automation, communications or measurement/analysis 1 18Untitled-5 March 2009

2/17/09 4:47:07 PM

SOLUTIONS Engineering system. The sampled data passes through signal processing algorithms such as filtering, FFT, decoding and many others, and is subsequently passed on to other processing functions. Many signal processing algorithms correct for or tolerate scattered errors and noise in the signal stream, but choke when faced with a consecutive stretch of missing data.

Ironically, the typical behavior of the standard Ethernet protocol stack can transform benign scattered errors into a swath of missing data that chokes signal processing algorithms. This occurs because the protocol will discard entire packets or messages, which could be 1500, 9000, or up to 64000 bytes long, if an error is detected in a checksum or if a message arrives incomplete. And yet the source of the checksum error may be just one or two data bytes, or in the packet header. The solution is to modify the stack behavior to avoid dropping the packets in

the presence of the CRC or checksum errors, and to allow them to pass to the signal processing stage.

High-throughput real-time instrumentation, communication and other sensor processing systems can receive multiple back-to-back packets burst at full line speed on a regular or even a sustained basis. In such cases, there are no spare cycles for flow control or retransmission requests when the receiving Ethernet interface is momentarily unable to access host system memory to store the incoming data. The result is unacceptable permanent packet loss. This characteristic is relatively uncommon in server systems that have much softer real-time requirements, thus giving opportunities for flow control or retransmission when required. Therefore, the cost-optimized solutions targeted at the server space do not have to be designed to accommodate these regular long-duration bursts.

Switch Port Shipments

Specification

Ratification Year (y0)

Year y0+3

10GbE (802.3ae) predicted from 2006

2002

10GbE (802.3ae) – actuals and 2008 predictions

2002

150K

1GbE actuals (1998)

1999

20M

Table 1

Figure 2

Year y0+4

Year y0+5

Year y0+7

1.8M 320K

Year y0+9 12M

<1M

7M 80M

The 10GbE switch port shipment predictions and actual shipments in January 2006, and revised predictions for 2011. The actual switch port shipments for 1GbE are also shown. Source: Dellâ&#x20AC;&#x2122;Oro, Infonetics

The AdvancedIO Systems V1120 Dual-port 10GbE conduction-cooled rugged XMC module, designed following the new VITA 42.6 standard, implements the architecture shown in the block diagram of Figure 1.

Untitled-7 1

March 2009

19

11/10/08 10:01:37 AM

SOLUTIONS Engineering

To address the requirements above, 10GbE technology must implement features including interfaces for precision time-stamping, local memory to accommodate large full-rate inbound bursts and outbound data staging, and the ability to customize stack behavior for receiving real-time sensor data (Figure 1).

These real-time adaptations will become even more complicated to implement for 40GbE and 100GbE and need

to be solved before solutions are matured.

Among the challenges: • Incoming buffers need to be larger— 4x to 10x the data arrives in the same time period as before.

• Likewise, external memory and controllers need to operate at a higher bandwidth.

• Interfaces like CAUI require 2.5x the number of high-speed pins of XAUI, increasing the number of high-speed

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Implications for Real-Time 40GbE and 100GbE

Because 40GbE and 100GbE technologies are currently driven by the massive server-type markets, the ASIC-based solutions, out of sheer volume necessity, will target those applications, just as they have in the 10GbE case. As pointed out, those applications have some fundamentally different requirements from the higherend real-time embedded applications. The latter will therefore need to use solutions based on programmable logic, which allows the solutions to be customized to the problems in the application space, while maintaining a standard external software interface for compatibility with the Ethernet ecosystem. Figure 2 shows one such solution for 10GbE systems: AdvancedIO Systems V1120 dual-channel conductioncooled 10GbE interface module, based on the Xilinx Virtex-5.

Without question, 40GbE and 100GbE will arrive in the real-time embedded space, but the arrival is still some years away and needs to be accompanied by the same kinds of innovation that make 10GbE suitable for the space. The good news is that, at 10 Gbits/s, Ethernet finally has sufficient bandwidth for most realtime high-speed applications, and there are real-time focused solutions existing today that you can use to get on board the Ethernet bandwagon. Once aboard, you can smoothly ride the Ethernet speed curve to 40GbE and beyond as your requirements scale, avoiding the software and architectural upheaval that resulted from previous iterations of integrating different high-speed technologies.

AdvancedIO Vancouver, BC. (604) 331-1600. [www.advancedio.com].

www.gocct.com email: info@gocct.com tel: (781) 933 5900 All trademarks acknowledged

I/O pins required in devices and complicating PCB routing.

• Internal processing bandwidth needs to increase correspondingly to realize protocol offload and other processing required for Ethernet termination.

The Intel® Processor Board Specialists

11/17/08 3:38:38 PM

INDUSTRY INSIGHT

High-Speed Networking

Speed up Your Real-Time Digital Simulation System A new higher-speed low-latency reflective memory solution to meet the needs of real-time digital simulation systems.

by Herman Paraison Dolphin Interconnect Solutions

I

n todayâ&#x20AC;&#x2122;s environment, companies There are several aspects to a realneed to review how they develop sys- time network that you must consider. First tems. For real-time digital simulation is the type of network structure supported. systems, they have trended toward off-the- Clusters, reflective memory or shared ploration shelf PC-based technologies. The main memory networks are all appropriate for your goal factors leading to this transition are the re- real-time networks. Second, you must not k directly duced cost, along with the huge improve- only consider bandwidth but more imporage, the source. ments in recent years in computer power tantly latency. Latency plays a key role in ology, and software sophistication. Concerns conducting complex high-performance d products have greatly diminished about the amount simulations. Latency requirements move of computation required to achieve a so- many system designers toward real-time lution, since computational elements are network solutions and away from comfaster and cheaper. Yet, a by-product of modity solutions such as Ethernet. Realthis increased computational capability time simulation of power electronic syshas been a significant increase in the com- tems can require the power electronic plexity of systems tackled by simulation. components to be simulated with frame nies providing solutions now For example, high-speed real-time times as low as 2 to 5 ms. The latency ion into products, technologies companies. Whether goal is to research the latest simulations ofand applications such your as power between components and subcomponents ation Engineer, or jump to a company's technical page, the goal of Get Connected is to put you electronics and automobile engine simu- plays a key role in achieving these types you require for whatever type of technology, demandfor.real-time execution with of frame times. and productslations, you are searching frame times of a few microseconds or less.

These frame times can only be achieved Network Solutions by using special purpose hardware and When we look at common network software. In many cases, even with the solutions for simulation, shared memory increase in local compute power, multiple or reflective memory, networks often meet systems are required for high-speed simu- the challenges. They have been used in lations and the data network is a critical various simulation environments in aircomponent in overall system performance. craft, ships, submarines and power plant So how do you pick the right network for simulators. Reflective memory networks your simulation environment? or replicated shared memory networks in particular have been an ideal data communication solution for high-speed simuGet Connected lation. These networks are deterministic, with companies mentioned in this article. high- performance, low-latency networks. www.rtcmagazine.com/getconnected

End of Article

22

March 2009 Get Connected with companies mentioned in this article.

They provide the framework to meet the low latency demands of high-speed realtime simulators.

What should you consider when implementing a hardware-based reflective memory solution? Most solutions share several common factors, even though each vendor may implement a different solution. Fundamentally, they are a shared data model. Data written to a reflective memory location by one processor is distributed to all nodes on the network where it appears as local memory. This provides high-speed access to data for each processor. The networks are deterministic and the availability of data is precisely known.

They are high-bandwidth implementations and the physical network is usually a ring configuration with updates done serially. Communication is achieved through a simple memory map of the global variables, and no processor intervention is necessary to move the data. There is no operating system or file system overhead for hardware-based reflective memory solutions. Network cards are installed in each host and these cards often have dedicated SRAM on them to store data.

The amount of SRAM is determined by the vendor and is fixed. This addition of SRAM tends to increase the cost of the solution.

A different approach to the standard reflective memory solution is a switch-

INDUSTRY Insight

User App on H1

Host 0

3. Broadcast write

Host 0 Memory Buffer

4. Incoming write to buffer offset “x” 2. Single write transaction 3. Broadcast write (loopback operation)

5. Read buffer (use virtual address) Dolphin API

Host 1 Memory Buffer Host 1

4. Incoming write to buffer offset “x”

Dolphin Driver DXH Adapter

4. Incoming write to buffer offset “x”

The Switch

3. Broadcast write

Host 2 Memory Buffer Host 2

3. Broadcast write

based reflective memory system. For realtime simulation, this approach provides higher bandwidth with a low-latency approach because it implements a data broadcast approach as a natural extension of the serial reflective memory networks of the past. Data broadcast is similar to the ring serial reflective memory networks, except that data is broadcast to all nodes simultaneously instead of serially.

This significantly lessens the time it takes for all nodes to have a new copy of the updated memory and reduces data delivery jitter. In simulation environments where data transfer speed is critical, such as power electronics, data broadcast provides speed. Thus, the data broadcast approach provides a path for expansion beyond serial reflective memory, enabling scalability and performance improvements with higher bandwidth.

Figure 1 illustates a data broadcast network. This network is built using Dolphin’s PCI Express-based switching network Dolphin Express. For this example four nodes are connected via a switch.

Each host has a host adapter installed and the host adapter has no onboard memory (Figure 2). Rather, this approach utilizes system memory, which is cacheable to implement its shared memory regions. This provides system engineers the flexibility to create the memory region of the size that their simulation requires. Most vendors place memory on their reflective memory board; access to this memory is not cacheable and has high latency compared to local main memory access. The elimination of onboard memory also lowers the cost of the overall solution since expensive onboard memory is not required.

This implementation provides a set of APIs for system setup, which is not required during system operation. Each host has the same size memory region marked as reflective write capable. A remote memory access transfer mode (either using CPU load/store or DMA) is used to store data on remote nodes. A hardware based multicast approach allows for lowcost multicasting of data, outperforming serial reflective memory solutions. All bus protocol handshakes and protocols are performed by hardware, while data is always pipelined to the next level. This approach is very low latency and flexible. For

Host 3 Memory Buffer Host 3

4. Incoming write to buffer offset “x”

User App on H0 Host 0 Dolphin API Mapped 1. Write to mapped remote location at offset X Remote Dolphin Driver Buffer DXH Adapter Mapped remote buffer address (using Dolphin API) is used for write operations

Figure 1

Switch-based reflective memory systems enable a single write operation to be simultaneously broadcast to all nodes in the switch topology and read locally by each node. A single write transaction to host 0 mapped remote location appears in local memory of hosts 1-3 as well as host 0, enabling fast read access by each host.

large datasets used in some simulations, DMA-based reflective memory can be used to distribute data in the background, improving overall performance.

The use of cacheable main memory provides a significant performance benefit. Remote interrupts or polling can be used to signal the arrival of data from a remote node. Since the memory segments are normal cacheable main memory, polling is very fast and consumes no memory bandwidth. The CPU can poll for changes in its local cache. When new data arrives from the remote node, the cache will automatically be invalidated by the I/O system and the new value will be cached. The hardware also supports remote PCI configuration cycles for initialization and set up of remote I/O systems that don’t have a processor. Remote initialization can be easily adapted to user-defined requirements.

The mapping address space is software configurable and very flexible. It can be mapped into a number of smaller address ranges. An address translation entry controls each of these ranges with mapping information that redirects the data to a remote machine and remote memory offset. Each of these mappings can be set up to not only map to any given address or machine in the system, but also to all machines in the system. After the memory size region is defined, a “write capable remote virtual address” is returned for the mapping. For example, a single write to host 0’s reflective write capable memory region is multicasted to the remote buffer of each host at the same offset within the remote buffer. Note that the buffer for the host performing the write operation can also be updated automatically by making use of the loopback capability of the switch.

March 2009

23

INDUSTRY Insight

The user application will use the actual virtual address of the buffer for “reads.” In other words, there will be two addresses where the application will use a mapped address for doing writes to remote buffers, and the virtual address of its own buffer to read the data. Independent “reflective memory regions” can be created. There are also other capabilities that the API can provide such as support for unicast, mechanisms for detection of transmission errors, and fail-over.

To create a higher available system, a second switch can be added. A connection can be made from each port of the host adapter to each switch. This is less complicated than in a ring topology where additional passive hubs need to be added.

Multicast groups can be created for both primary and secondary switch fabric topologies. For higher fault tolerance, the data link layer is designed with built-in CRC, 8b/10b encoding and the option to

Figure 2

The Dolphin DXH510 PCI Express host adapter supports fiber optical cabling of up to 100 meters and provides a high-speed interconnect for CPU to CPU with DMA capability.

communicate over both ports of the host adapter. What is the main advantage of this approach? Speed and performance.

The low-latency solution is especially effective on small packet transfers. At 1.3 Gbytes/s, a full remote memory write made up of a request/response pair typically takes 1.2 microseconds.

For real-time digital simulation systems, a switch-based reflective memory solution provides new levels of bandwidth and latency that software reflective memory solutions and other hardware reflective memory solutions can not obtain. The entire broadcast process is done in hardware. There is no processor overhead in moving the data except for the data store operation that equals a CPU-posted write to memory. Data of any size is transmitted to all nodes directly by functionality implemented in hardware. The data transfers are also deterministic. This fully hardware-based memory mapped data transmission doesn’t rely on any operating system service or kernel driver functionality.

The results are a bandwidth performance number of over 1.3 Gbytes/s and latency as low as 1.25 µs.

Dolphin Interconnect Solutions Marlborough, MA. (508) 786-9950. [www.dolphinics.com].

24

March 2009

SYSTEM ITNEGRATION

Real-time software

xploration r your goal ak directly page, the resource. hnology, nd products

Exactly When Do You Need Real Time?

Often, your system might have the right answer, but if it doesn’t execute in time it won’t matter. Weighing the differences between a general-purpose OS and a real-time OS, or a combination of the two, is critical for reliable operation in embedded applications.

by P aul N. Leroux QNX Software Systems

M

ost embedded systems today need some form of operating system. The question is, should it be a real-time operating system (RTOS) or a general-purpose operating system (GPOS)? In many cases, there is little argument.

When designing a flight control system, medical instrument, or process control application, for example, most system designers panies providing nowRTOS, simply because these systems must meet will solutions choose an ation into products, technologies and companies. your goal is to research latest absolute deadlines.

To quoteWhether software developer Billthe Gallmeister, cation Engineer, or jump to a company's technical page, the goal of Get Connected put you “...it doesn’t do you any good if the signal that cuts fuel istotothe jet ce you require for whatever type of technology, engine arrives a millisecond after the engine has exploded.” es and products you are searching for.

Sometimes, however, the answer isn’t so obvious. For example, do Internet routers, automotive infotainment systems, software defined radios and consumer appliances also need an RTOS? Often, the answer is yes, even though these systems can miss deadlines without causing loss of life or limb.

To understand why, consider a system that must satisfy quality of service requirements, such as a device that presents live video. If the device depends on software for any part of its content delivery, it can experience dropped frames at a rate that users perceive as unacceptable. Likewise, consider a system where users need or expect immediate response to input. Any delay will create user annoyance, loss of confidence in the manufacturer, Connected or, in theGet case of an in-car telematics system, driver distraction. with companies mentioned in this article.

By usingwww.rtcmagazine.com/getconnected an RTOS, the system designer can ensure that media rendering or user feedback executes in preference to other system activities.

End of Article

Get Connected with companies mentioned in this article. www.rtcmagazine.com/getconnected

26

March 2009

High

Priority

Job 1

Job 3

Priority Inversion

Preemption Low

Job 2

Time

Figure 1

Job 1 is waiting for Job 2 to complete an activity, when Job 3 preempts Job 2. This further delays Job 1 from executing.

Some would argue that faster processors and peripherals allow a GPOS to handle such timeliness requirements. However, for reasons of cost, power consumption or heat dissipation, many systems cannot use faster hardware. In systems that ship in the thousands or millions of units, for instance, even a small reduction in per-unit hardware costs can save the manufacturer a small fortune. Case in point: In the automotive telematics market, the typical 32-bit processor runs at about 600 MHz—far slower than the desktop-class processors for which most GPOSs have been tuned.

SMALL FORM FACTOR SHOWCASE Featuring the latest in Small Form Factor technology Processor AMCC-PPC 460 EX -1.0 GHz-ComExpress Module

ACTIS Computer Inc. Phone: (480) 838-1799 Fax: (480) 838-4477

x4 PCIe interface 32-bit,33/66MHz PCI 2GB DDR2 on SO-DIMM SDRAM on SO-DIMM and 1GB NAND Flash 16MB Boot Flash 8kB NVRAM One S-ATA II ports 2D/3D graphic controller Two Gigabit Ethernet ports Two USB 2.0 FS,HS,LS ports Extended Temp -40°C to + 85°C Linux and VxWorks BSP support E-mail: support@actis-computer.com Web: www.actis-computer.com

conga-CAx True -40C to +85C Extended TEMP Intel ATOM ComExpress CPU Module Industrial Temperature Range -40C to +85C Onboard Flash Drive up to 4 GByte Intel Atom processor Z520PT - 1.3 GHz Intel US15WPT Intel GMA500 Graphics Engine Up to 2 GByte DDR2 onboard memory Pinout - Type 2 Size 95 x 95 mm Advanced BIOS Features

congatec Phone: (760) 635-2600 Fax: (760) 635-2601

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Credit Card Size – 2.125”W x 3.375”L x 0.25”H FPGA - Xilinx® VirtexTM-5 FX70T or SX50T Advanced SoC Processing Architecture Memory – Three Banks DDR2 SDRAM up to 533 MHz Operating System – Linux 2.6 with Real Time Modifications

iVeia, LLC Phone: (410) 858-4560 Fax: (443) 557-1680

Radicom Research, Inc. E-mail: sales@iveia.com Web: www.iveia.com

Phone: (408) 383-9006 Fax: (408) 383-9007

EM-X270 Computer-on-Module

Phone: (905) 890-6400 Fax: (905) 890-6205

E-mail: sales@tracan.com Web: www.tracan.com

USB modems, in module or standalone form factor Linux, Windows and Mac O/S support -40C to +85C operating temperature (Module) Compact size: 1” x 1” x 0.2” (Module) USB 2.0 compatible up to 56K bps data rate, fax and voice AT command Transferable FCC68, CS03, CTR21 telecom certifications Global safety: IEC60950-1, IEC60601-1 (Medical) approved CE marking E-mail: sales@radi.com Web: www.radi.com

PCO-UIO48: Low cost, small size and stackable digital Pico-I/O

EM-X270 is a full-featured, selfcontained, computer board, for handheld & mobile “custom” implementations includes WiFi, Bluetooth, GPS and cellular Voice/GPRS modem 32-bit CPU, SDRAM, Flash Disk and vital computing peripherals Ready-to-run Windows CE and Linux packages on-board functional contents comparable to latest generation Pocket PC’s and smartphones

Tracan Electronics Corporation

E-mail: sales-us@congatec.com Web: www.congatec.us

48-Line digital I/O module for PicoITXe SBCs Each line programmable for Input, Output, or Output with read-back operation 24-Lines provide real-time event monitoring Pico-I/O, 60 x 72mm, module uses SUMIT™ connector Operational temperature -40° to +85°C

WinSystems, Inc. Phone: (817) 274-7553 Fax: (817) 548-1358

E-mail: info@winsystems.com Web: www.winsystems.com

SYSTEM Integration

High

Priority

Low

Job 1

Priority Inheritance (Job 2 = Job 1)

Job 3

Job 2

Time

Figure 2

Job 2 inherits Job 1’s higher priority, thereby preventing Job 3 from preempting Job 2. Job 3 no longer delays Job 1 from executing.

In any case, faster hardware doesn’t always guarantee predictable performance. It can improve overall performance significantly, but often fails to improve worst-case response times to events. As a further complication, most embedded systems are moving from single-purpose designs to multi-function designs, with more applications competing for resources and greater levels of concurrency and task interaction. This rising complexity makes it difficult to design systems that behave predictably under all usage scenarios and system loads.

Security also comes into play. Many people are familiar with the principles of security (for instance, complete mediation) formalized by Anderson, Saltzer and Schroeder in the 1970s. Since then, the security community has devised several enhancements, including the need to ensure that high-priority threads or operations proceed without undue delay caused by low-priority subjects or operations. Many RTOSs incorporate a strict protocol to ensure that, if system resources become sparse, only higher-priority requests float to the top of the processing queue. They also implement a prioritization protocol to ensure that higher-priority system-level requests never get “starved” out by lower-priority events.

Honor Thy Priorities

The need for predictable response times—and for RTOSs that enable them—remains common in embedded systems. The question is, what does an RTOS have that a GPOS doesn’t? And how useful are the real-time extensions now available for some GPOSs? Let’s begin with task scheduling. In a GPOS, the scheduler typically uses a “fairness” policy to dispatch threads and processes onto the CPU. Such a policy enables the high overall throughput required by desktop and server applications, but offers no assurances that high-priority, time-critical threads will execute in preference to lower-priority threads.

For instance, a GPOS may decay the priority assigned to a high-priority thread, or otherwise dynamically adjust the priority

28

March 2009

in the interest of fairness to other threads in the system. A highpriority thread can, as a consequence, be preempted by threads of lower priority. In addition, most GPOSs have unbounded dispatch latencies: the more threads in the system, the longer it takes for the GPOS to schedule a thread for execution. Any one of these factors can cause a high-priority thread to miss its deadlines, even on a fast CPU. In an RTOS, on the other hand, threads execute in order of their priority. If a high-priority thread becomes ready to run, it can, within a small and bounded time interval, take over the CPU from any lower-priority thread that may be executing. Moreover, the high-priority thread can run uninterrupted until it has finished what it needs to do—unless, of course, it is preempted by an even higher-priority thread. This approach, known as priority-based preemptive scheduling, allows high-priority threads to meet their deadlines consistently, even when many other threads are competing for CPU time.

Preemptible Kernel

In most GPOSs, the OS kernel isn’t preemptible. Consequently, a high-priority user thread can never preempt a kernel call, but must instead wait for the entire call to complete—even if the call was invoked by the lowest-priority process in the system.

Moreover, all priority information is usually lost when a driver or other system service, usually performed in a kernel call, executes on behalf of a client thread. Such behavior results in unpredictable delays and prevents critical activities from completing on time.

In an RTOS, on the other hand, kernel operations are preemptible. There are still windows of time in which preemption may not occur, but in a well-designed RTOS, those intervals are extremely brief, often in the order of hundreds of nanoseconds.

Moreover, the RTOS will impose an upper bound on how long preemption is held off and interrupts disabled; this allows developers to ascertain worst-case latencies.

To realize this goal, the RTOS kernel must be as simple and elegant as possible. The best way to achieve this simplicity is to design a kernel that only includes services with a short execution path. By excluding work-intensive operations, such as process loading, from the kernel and assigning them to external processes or threads, the RTOS designer can help ensure that there is an upper bound on the longest non-preemptible code path through the kernel.

In a few GPOSs, some degree of preemptibility has been added to the kernel. However, the intervals during which preemption may not occur are still much longer than those in a typical RTOS; the length of any such preemption interval will depend on the longest critical section of any modules (for instance, networking) incorporated into the GPOS kernel. Moreover, a preemptible GPOS kernel doesn’t address other conditions that can impose unbounded latencies, such as the loss of priority information that occurs when a client invokes a driver or other system service.

Mechanisms to Avoid Priority Inversion

Even in an RTOS, a lower-priority thread can inadvertently prevent a higher-priority thread from accessing the CPU—a con-

SYSTEM Integration

dition known as priority inversion. When an unbounded priority inversion occurs, the system can miss critical deadlines, resulting in outcomes that range from unusual system behavior to outright failure. Many examples of priority inversion exist, including one that plagued the Mars Pathfinder project in July 1997.

Generally speaking, priority inversion occurs when two tasks of differing priority share a resource, and the higher-priority task cannot obtain the resource from the lower-priority task. To prevent this condition from exceeding a bounded interval of time, an RTOS may provide a choice of mechanisms unavailable in a GPOS, including priority inheritance and priority ceiling emulation. We couldn’t possibly do justice to both mechanisms here, so let’s focus on an example of priority inheritance.

Let’s say two jobs are running, Job 1 and Job 2, and that the two jobs share a resource controlled by a mutual exclusion lock. If Job 1 is ready to execute, but Job 2 is using the resource, Job 1 must wait until Job 2 has unlocked the resource. The time required for Job 2 to unlock the resource can’t vary according to any parameter; it must remain bounded. Otherwise, Job 1 will fail to meet its deadline.

Now let’s introduce a third job—Job 3—that has a higher priority than Job 2, but a lower priority than Job 1 (Figure 1). If Job 3 becomes ready to run while Job 2 is executing, it will preempt Job 2, and Job 2 won’t be able to run again until Job 3 blocks or completes. This, of course, will further delay Job 1 from executing. The total delay introduced by the preemption is a priority inversion. In fact, multiple jobs can preempt Job 2 in this way, yielding an unbounded priority inversion and causing Job 1 to fail to meet any of its deadlines.

Priority inheritance prevents this scenario by allowing Job 2 to temporarily inherit the priority of Job 1. This mechanism prevents Job 3 from preempting Job 2 and thereby avoids the resulting priority inversion (Figure 2).

“Dualing” Kernels

GPOSs—including Linux, Windows and various flavors of Unix—typically lack the real-time mechanisms discussed thus far. Nonetheless, vendors have developed a number of real-time extensions and patches in an attempt to fill the gap. There is, for example, the dual-kernel approach, in which the GPOS runs as a task on top of a dedicated real-time kernel (Figure 3). Any tasks that require deterministic scheduling run in this kernel, but at a higher priority than the GPOS. These tasks can thus preempt the GPOS whenever they need to execute and will yield the CPU to the GPOS only when their work is done.

Nonetheless, tasks running in the real-time kernel can make only limited use of existing system services in the GPOS—file systems, networking, and so on. In fact, if a real-time task calls out to the GPOS for any service, it will be subject to the same preemption problems that prohibit GPOS processes from behaving deterministically. As a result, new drivers and system services must be created specifically for the real-time kernel, even when equivalent services already exist for the GPOS. Also, unlike most modern RTOSs, the real-time kernel doesn’t typically provide a robust memory-protected environment for real-time tasks. Instead, the tasks run unprotected in kernel space. Consequently,

User Applications

IPC

GPOS Kernel Real-Time Tasks

Real-Time Kernel

Hardware

Figure 3

In a typical dual-kernel implementation, the GPOS runs as the lowest-priority task in a separate realtime kernel.

a real-time task that contains a common coding error, such as a corrupt C pointer, can easily cause a fatal kernel fault. That is a problem, since most systems that need real time also demand a very high degree of reliability.

To complicate matters, different implementations of the dual-kernel approach use different APIs. In most cases, services written for the GPOS can’t easily be ported to the real-time kernel, and tasks written for one vendor’s real-time extensions may not run on another’s.

Such solutions point to the difficulty of making a GPOS capable of supporting predictable behavior. This isn’t a matter of “RTOS good, GPOS bad,” however. GPOSs such as Linux, Windows and the various Unixes all function extremely well as desktop or server OSs. They fall short, however, when forced into environments where users expect or need consistently predictable response times.

Still, there are benefits to using a GPOS, such as support for widely used APIs and, in the case of Linux, the open source model. With open source, a developer can customize OS components for application-specific demands and save considerable time troubleshooting. To maintain these benefits, the RTOS vendor should make its source code easily accessible, under commercial-friendly licensing terms. QNX Software Systems, for example, not only publishes its source code on a community portal, but also uses a transparent development model, in which source code to the QNX Neutrino RTOS and other software components is published as it is being developed.

QNX Software Systems Ottawa, Ontario.

(613) 591-0931. [www.qnx.com].

March 2009

29

industry watch

ploration your goal k directly age, the source. ology, d products

Silicon Solutions Enable Migration to Next Generation Networks Moving from the multiplicity of technologies and protocols that make up today’s telecommunications networks to the integrated next generation networks requires a transition technology in the form of a Universal Gateway that can bring any-to-any connectivity.

by Moshe De-Leon Siverge Networks

A

Universal Gateway is a logic so- Migrating to NGN: The Need & lution that can truly provide any the Challenges port, service, functionality and Figure 1 shows a high-level abinterworking/translation capability straction of a typical transport netfrom any protocol to any other proto- work. The figure demonstrates the col in layer one and two of the seven- major problems and shortcomings of layer model of communication. Such these transport networks and the exista Universal Gateway will provide the ing infrastructure, namely, complexity most efficient path to network, system and inefficiency. This complexity is the and linecard convergence/consolida- result of the transport infrastructure nies providing now tion,solutions thus enabling and paving the path which was built over years of changion into products, technologies and companies.

Whether your goal is to research the latest technologies, systems and of the migration to Next Generation ing services, ation Engineer, or jump to a company's technical page, the goal of Get Connected is to put you Networks (NGN). However, the related protocols. It was developed step-by-step you require for whatever type of technology, involved in such a Universal through years of constant (though slow) and productscomplexity you are searching for.

Gateway has made it impossible or at changes, which were trying to accomleast impractical to try and implement it. modate new requirements, growing On the horizon, a new VLSI archi- bandwidth, new customers and services tecture is paving the way for emerging while at the same time trying to reduce silicon solutions that are now capable cost (CAPEX and OPEX), space and of building this Universal Gateway. This power consumption. will have a major impact on the migraThese all lead to NGN, which is tion to NGN. all about convergence, consolidation and simplification. The main concept of NGN consists of moving away from today’s mixture of various transport networks into Ethernet and MPLS-based Get Connected transport networks. This also implies with companies mentioned in this article. moving away from all the legacy switchwww.rtcmagazine.com/getconnected ing systems (X25, FR, ATM) into a sin-

End of Article

30

March 2009 Get Connected with companies mentioned in this article. www.rtcmagazine.com/getconnected

gle system based on the same Ethernet and MPLS. While the concept may sound simple and straightforward, there are major challenges and obstacles. For one thing, there are many users who do not want to switch or compromise the existing services and interfaces they have today. Thus, any migration to Ethernet MPLS will have to support all the legacy protocols and interfaces of today’s layers one and two. And while any new network being installed might well be based on Ethernet and MPLS, it has to interconnect to the legacy network and support the same legacy services. And speaking of legacy in terms of existing lines and physical infrastructure, we would ideally have put fiber capable of at least 1GbE everywhere. The reality however is that T1 and E1 lines will be the major access infrastructure for years to come. There is also a technical need to compensate for the missing real time information (e.g. clocks) when serving applications like wireless backhauling, which need it.

Then, of course, there are the cost issues of migration. During transition, it is

INDUSTRY Watch

necessary to deal with the cost of supporting parallel networks and systems. And all of this will demand a huge amount of CAPEX & OPEX investment due to the need to purchase and install new systems and networks.

Given all these challenges, a new concept called â&#x20AC;&#x153;Universal Gatewayâ&#x20AC;? sounds like a solution, provided that it can be used to overcome these challenges. However, such a Universal Gateway has been considered not to be implementable by many experts.

Recent advances have shown how using a new VLSI architecture enables implementation of the Universal Gateway and one such implementation is now available for review and trial.

The Universal Gateway Framework

Figure 2 shows what we have in mind when discussing the desired solution. On the left side of the imaginary linecard or system shown in Figure 2, are the client or line side interfaces, while on the right side are the system or uplink network interfaces. This system

Business Access SONET/SDH/PDH Frame Relay or PPP

PTP & Voice

or line card enables any type of access interfaces that are used today in transport networks including SONET/SDH, PDH and Ethernet.

More than this, this logic and circuitry can be part of any type of system regardless of it being a TDM system (e.g. MSPP, ADM) or router, multi-service switch, aggregator, MSTP and the like.

It provides any type of relevant client side, functionality and any-to-any interworking between legacy and new protocols and services. The client side includes ports for Ethernet, SONET/SDH and PDH along with any channelization.

This side also has Layer 2 protocols including HDLC, PPP, LAPS, POS, ATM, GFP, PPP, Frame Relay and X.25 and bundles IMA, MLPPP, MLFR, VCAT and LCAS The concept of interworking here involves any-to-any protocol conversion and packet editing along with all encapsulation schemes, PWE3, CES (all flavors) and QoS and traffic engineering.

On the network and uplink sides there are Ethernet, SONET/SDH (any rate) and system interfaces that include a generic

SONET/SDH Transport

ATM

Ethernet Over TDM

Frame Relay or PPP

Obstacles & Challenges, Using the Universal Gateway

In the section above, we listed the major obstacles in migration to NGN. Assuming that the Universal Gateway functionality is implemented in whatever technology, one can easily see how these obstacles are overcome. Service continuation is trivially solved since we enable any legacy service to continue even if the whole transport network is changed from SONET/SDH to MPLS/ Ethernet using PWE3 (anything over MPLS).

The interworking of networks is also achieved since the Universal Gateway enables any interworking between any Layer 1/Layer 2 combinations. Thus, regardless of which side of the two networks implements it, the Universal Gateway enables this side to interwork with the other network seamlessly. When it comes to clock and time distribution, having the CES and clock distribution

Wireless RAN/UTRAN PDH/SONET/SDH (exc. RF) 2G TDM

PTP & Voice

ATM

switch fabric interface, Ethernet switch and TDM (e.g. STS-1 cross connect) switch.

3G ATM 2.5G FR/PPP

Ethernet Over TDM 3G ALL IP Wireless RAN/UTRAN Ethernet (exc. RF) 3G 2G ATM 3G TDM ALL IP 2.5G FR/PPP

Ethernet Over TDM

Business Access Ethernet Frame Relay or PPP

ATM

Ethernet/MPLS Transport

Ethernet

PTP & Voice ATM

Figure 1

Ethernet

PTP & Voice

Frame Relay or PPP

Typical Transport Network (high level).

March 2009

31

INDUSTRY Watch

SPI-4

10/100/1G/10G/40G/100G MAC

CES, NTP & 1588 OC768 <STM64> Down to OC3 <STMI> Framer & Mapper

Figure 2

DS3/E3 Framer

MI3

DS1/E1 Framer

HDLC FR/PPP (DS0)

MLPPP MLFR

ATM (DS0)

IMA

SAR

PDH VCAT & LCAS

GFP

MAC

Universal Gateway Functionality.

Extract Process Construct

Sync In/Out

On Chip Memory Buffering

External Memory Interface

Figure 3

Matrix High Level Block Diagram.

1 32Untitled-12March 2009

Ethernet

Processing

POS, ATM, GFP, LAPS, ETN Over SONET/SDH VT1.5 up to OC-192c

VT& VCAT+LCAS

L2.5 PWE3 ETN QoS TM LUT

GFP

VT & VCAT +LCAS

OC12/48 <STM16/4> Framer

mechanisms functionality in place, completely addresses this.

Next on our list is the issue of supporting multiple networks and systems.

Having this functionality between different transport networks solves it by providing seamless interworking (the networks can be considered as one system) between the various networks. Additionally, the need to continue and utilize the huge copper (e.g. T1/E1) installed lines is addressed by the Universal Gateway, which enables us not only to continue utilizing T1/E1 as in todayâ&#x20AC;&#x2122;s networks; it also enables us to move to Ethernet over T1/E1 using GFP and VCAT/LCAS. When it comes to multiple systems, it can be shown that a Universal Gateway, which supports any type of system backplane and internal interface, can easily be added to any type of system. This is true for any type of MSPP, MSTP, router, switch and multiservice switch. Therefore, assuming the system vendors add it to their existing and new systemsâ&#x20AC;&#x201D;any NGN can be built using minimal (ideally one) types of systems without compromising services and any interworking with legacy networks that might be required.

The same argument is also valid for the obstacle/challenge involving expenses. Given that this functionality can

3/11/09 11:09:39 AM

INDUSTRY Watch

be added to any type of system, this will significantly reduce the CAPEX/OPEX associated with migrating to NGN. The same systems used today can be utilized for building NGN, since if the Universal Gateway is added to them, the same system can be part of SONET/SDH legacy transport network and/or an NGN Ethernet/MPLS network. Therefore, a carrier can perform this transition without any investment in new systems just by adding Universal Gateway linecards to its already deployed systems.

If a carrier selects to buy new types of transport systems, having the Universal Gateway functionality as part of them will enable the carrier to continue the deployment of all its deployed systems and networks, while adding new systems (and networks) only where and when it makes sense for it.

Implementing the Universal Gateway Using Silicon

The problem with the Universal Gateway approach is that implementing

Channel Stream Context Selection

Layer 2 Machines

HDLC & POS IMA MLPPP ETHERNET GFP ATM COMMON

VCAT SONET SDH PDH PDH T1 E1 J1 PDH M13 PDH T3 E3 MAPPERS VC VT SONET SDH FRAMERS Layer 1 Machines

Figure 4

The Matrix in a Universal Gateway.

uP

OC48/ STM16 or 4x OC12/3/ STM4/1

OC48/ STM16 or OC12/ STM4

Mate I/F

Figure 5

Packet/Cell Memory POS & HDLC (2Kx)

STS-1 Frame. & VC/VT Map.

DS3/E3 Frame.

(48x)

M13 (48x)

DS1/E1 Frame.

(1344x)

ATM (2Kx) PDH & SONET & SDH LCAS+ VCAT

VCAT Memory (optional)

SP14

MLPPP Pre.Pr.

IMA

GFP (672 VCG)

Queuing & Buffering

ETN STS-1 Frame. & VC/VT Map.

OC48 / STM16 or OC12 / STM4

Control Memory (optional)

SV364x Universal Convergence Devices.

Untitled-1 1

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3/11/09 9:53:56 AM

INDUSTRY Watch

One Board.

All You Need.

so many protocols and functionality for large bandwidth is perceived as impractical and undoable by many. Indeed, we also believe that this is true when trying to apply conventional VLSI architecture and circuitry. New and out-of-the-box thinking is what’s needed to overcome this problem.

OC-48 <STM-16> 4xOG12 <STM-4> 4xOC-3 <STM-1>

SONET SDH PDH

Packet

NI Single-Board RIO with Processor, FPGA, and I/O g

g

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g

Embedded real-time processor for stand-alone and reliable operation Onboard FPGA for custom timing and signal processing Integrated analog and digital I/O for connecting to sensors/actuators NI LabVIEW graphical programming for rapid development

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the eval kit at ni.com/embeddedeval

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©2009 National Instruments. All rights reserved. LabVIEW, National Instruments, NI, and ni.com are trademarks of National Instruments. Other product and company names listed are trademarks or trade names of their respective companies. 2009-10798-305-101-D

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Untitled-1 1

March 2009

3/23/09 9:51:47 AM

Packets/Cells Interface

MLPPP/FR ATM SAR QoS & TM

TDM

SV34x0

Figure 6

it. Thus, if certain logic is better dealing with bits while another is better dealing with bytes or long-words—each gets what it needs. The Matrix is built around a content switching concept; therefore it may process any number of different (or similar) channels, thus enabling the processing of any channelization level.

CES & 1588

TDM Interface

FPGA

PWE3

Flexible Packets/Cells Interface SPI-4.2 SPI-3 nx1GE

Siverge Networks Universal Gateway.

One successful attempt was made by Siverge Networks when creating the Matrix architecture. This new architecture is a web of logic and memories that are connected to each other in a broadcast Matrix (Figure 3). The basic concept here is to create a very efficient memory structure in which data, control, status and block interconnect information can reside for all the functional blocks and interconnection between them.

Thus, a web of interconnects and logic is created, which broadcasts the content of the memory (one channel every cycle) to all functional blocks. Each logic unit can look for and modify any portion of the broadcasted bits. The Matrix provides many desirable features that differentiate it from all conventional VLSI architectures.

First is to maximize memory and logic sharing by having one memory for all the logic blocks, and also implementing logic such that any mechanism or circuitry that is the same or similar between any two (or more) functional units need be implemented only once. This also minimizes interconnectivity overhead because the only communication is done through the Matrix memory.

To further optimize connectivity, each unit gets the data path width ideal for

The logic is transparent such that one may decide to implement any protocol, service or functionality around it and the basic architecture stays untouched.

This enables the addition of protocols and functionality very easily. The architecture provides enormous flexibility because any number of bits processed by any unit can be modified and reassigned dynamically. So, if some changes and enhancements are needed in the field—it is easy to implement.

The architecture of the Matrix described above was used to implement the SV36x0, which provides in essence a single device implementation of the most difficult part of the Universal Gateway.

Figure 4 shows the needed logical units around the Matrix web of interconnects and memories. The red block shows the common logic that implements generic functions needed by two or more units.

Function-specific logic is implemented separately in the units surrounding the Matrix.

The logical units in Figure 4 include most of the protocols, channelization levels and functionality relevant to the Universal Gateway. Using Siverge’s Matrix it was possible to embed all of them in a single monolithic device. We believe that this was doable only through using

INDUSTRY Watch

the unique features and optimization provided by the Matrix and discussed above.

While Figure 4 is the real physical implementation of the SV364x device, a more conventional block diagram of this device when it comes to its functionality is given in Figure 5.

To complete the Universal Gateway functionality, a complementary FPGA is also provided that implements the interfaces to the Ethernet/MPLS world. The complete solution is shown in Figure 6.

Given the circuitry in Figure 6, the task of actually incorporating the Universal Gateway functionality in any type of system is now very easy if not to say trivial.

In a stand-alone system such as a pizza-box, we use the Ethernet interface on the left side and now this is a Universal Gateway that provides any possible interworking between any two networks and underlying protocols. In an MSPP/MSTP system, the left SONET/ SDH side can be connected to the TDM switch fabric while the left side can be connected to an Ethernet (MPLS) network and thus provide the any-to-any interworking between any TDM interface and a new Ethernet (MPLS) network.

Alternatively we can use it in a closed loop mode where it is a server card without external interfaces. In this mode we perform the Universal Gateway functionality between any two linecards that are connected to the TDM switch fabric of the system.

In all other systems, whether based on packets/cells or switch fabric, the right side is connected to the packets/cells switch fabric and the TDM side is connected to a SONET/SDH/PDH line. The Universal Gateway functionality is now provided between this linecard and any other linecard connected to the system and thus provides the complete interworking capability between any network and the SONET/SDH/PDH network.

Migration to NGN is probably the most important transition for most, if not all, carriers and service providers. This is what they are expecting will dramatically change their CAPEX, OPEX and revenues for years to come. Yet, this migration encounters many obstacles and challenges

that considerably slow it down and in some cases stop it altogether.

These obstacles can be completely overcome with the implementation of the Transport Universal Gateway, a functionality that enables interworking for any interface, protocol and service in Layers 1 and 2. While for many years it was considered impossible (or at least impractical) to implement, this

is no longer true. New breakthrough VLSI architecture enables building this type of functionality in a cost-effective implementation.

Siverge Networks Herzliya Pituah, Israel. +972 9 9526600. [www.siverge.com].

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3RU RES Servers - 1 or 2 AMD Opteron or Intel Xeon CPUs (quad-core processors) - Up to 32GB ECC SDRAM - Up to 5 removable HDD - Vibration – 0.9g from 10 – 2000Hz - Shock – up to 25G @ 20ms

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Themis’ new family of 1RU, 2RU and 3RU Rugged Enterprise Servers™ (RES) includes the latest quad-core processors from AMD and Intel, offering ruggedized systems with the fastest, widest range of performance options and scalability.

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Untitled-7 1

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industry watch

Make vs. Buy: The Case for Outsourcing Complete ATCA Systems The economics of the telecom infrastructure industry have evolved to the point where it makes financial and strategic sense for TEMs to source standards-based ATCA systems from the ecosystem while focusing their in-house resources on application development.

by B rian Wood, VP Marketing Continuous Computing

T

elecom infrastructure industry standards and our collective attitudes toward open systems have evolved to the point where it is no longer necessary for telecom equipment manufacturers (TEMs) to design, build, or even integrate carrier-class systems in-house.

With network element functionality progressing to the point of being innovative application software hosted on a standards-based, high-availability system, the strategic rationale for a TEM to build its own “plumbing” is actually declining by the quarter. Instead, TEMs should be focusing in-house resources on unique value add—in other words, on developing applications—and turn to the telecom ecosystem for complete, standards-based ATCA systems to run them.

Why Change?

Telecom infrastructure industry norms have evolved significantly over the past two decades. Back in the day, large Tier 1 TEMs developed proprietary systems completely in-house and had to recruit, train, manage and retain hundreds of thousands of employees in order to do it all. Industry economics and the regu-

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March 2009

Figure 1

High Cost, Slow TTM

Better TTM, But Costly & Difficult

Best TTM, Best ROI

Vertically Integrated Approach

Application Middleware OS HW HW HW

Vertically integrated, Proprietary platforms, In-house R&D + Integration

Horizontally integrated, Standards-based, “Plug-n-Play” integration

Application Focus, Standards-based, “Black-Box” platform APIs

36 Months

24 Months

12 Months

Application TEM Middleware Key OS Vendor Hardware

Fully integrated systems deliver the fastest time-to-market (12 months) vs. integrating COTS building blocks (24) or developing everything in-house (36).

latory environment helped facilitate this business model of old, and the barriers to entry for a non-incumbent were nearly insurmountable. Life was pretty good for a TEM, but much has changed since then.

Technology, competition and operator expectations today are such that it is no longer necessary, or even desirable, for TEMs to do everything in-house, regardless of whether they pursue proprietary or standards-based approaches. Market economics make it extremely difficult for a

“do-it-all-yourself” TEM to compete with other TEMs that leverage an ecosystem supplying standards-based solutions. The financial and innovative advantages of tapping into the hyper-competitive supplier ecosystem with highly skilled development and manufacturing resources in the most cost-optimized areas of the world cannot be ignored. Designing, building and owning the intellectual property of everything within a system is no longer feasible or profitable with open standards as part of

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INDUSTRY Watch

Build-Your-Own Approach Evaluate & Select

Develop & Integrate

Management

Application

• Hardware platform • Protocol Stacks • Line Cards • HA Software • Database

• Develop or Integrate 3rd party stacks onto hardware platform • Integrate Line Cards & Stacks • Develop or Integrate 3rd party database into HA Software • Integrate HA software with hardware • Integrate HA software with stacks

•M anage Hardware Platform •M anage Stacks •M anage Line Cards •M anage HA Software •M anage Database •M anage Application

• Develop & Integrate Application • N EBS Compliance Software • I nterop Testing • F ield Trials •D eploy

1-6 Months

6-60 Months

3-36 Months

3-6 Months

Figure 2

6-12 Months

Development and integration is hard! Even with COTS building blocks, it takes significantly longer than assumed to weave everything together into a unified whole.

the competitive equation—that’s a luxury that is now too expensive to afford.

As with the evolution of the personal computer (PC) industry, the way to succeed and make money in the business 10 or 20 years ago is clearly not profitable today. In the PC world, titans like IBM, HP and Dell have had to reinvent (or sell off) their PC businesses because of shifting marketplace realities. Likewise, the telecom infrastructure industry also faces unstoppable forces that compel TEMs to evolve and adapt or else go the way of Commodore, Gateway, Wang and dozens of other PC has-beens.

Why Outsource?

OK, so we’ve just convinced ourselves of the need for change. Now it’s time to make the case for a full step forward rather than just a quarter or half step. Knowing human nature and the corporate culture of large organizations, the tendency for TEMs will be to resist any more change than is absolutely necessary.

In this case, however, it’s a matter of, “Do it now—or else leave it to luck to see if you will still have the chance to do something about it later.”

Our thesis for action is this: It makes financial and strategic sense for TEMs to outsource the entire standards-based system “below the application” and focus in-house resources on application development. Such an approach requires two key changes by a TEM. The TEM must be willing to relinquish a proprietary design bias in favor of open standards, and must abandon a “do it yourself” bias in favor of outsourcing complete systems.

It is natural for TEMs to assume that buying a telecom system is more

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March 2009

expensive than developing one in-house; however, this is not necessarily the case.

In fact, the Make vs. Buy decision is not just about purchase price and operating expense, but also about profitability over the entire product lifecycle and long-term strategic advantage.

Continuous Computing’s market research indicates that it takes about three years for a TEM to build a complete system in-house, two years to integrate Commercial Off-the-Shelf (COTS) building blocks, and only one year to create and deploy an application on a fully integrated system—or much less time if the application already exists (Figure 1). These are big differences that impact product profitability and success, and could easily influence one’s career potential if the competition ends up running circles around you in the marketplace!

Why Systems?

Many TEMs miscalculate that it should be easy and fast to integrate COTS building blocks for their platform, but, time after time, the lesson is re-learned that integration of standards-based components is not simply a matter of “plug and play.” Far from it. The reality is that while each individual building block may conform to PICMG specifications for ATCA, AMCs, or MicroTCA, it’s extremely rare for separate building blocks to function fluently without some sort of integration, tweaking, or “shim” software in between, unless those building blocks were originally designed with the other(s) in mind or have already been integrated, tweaked, shimmed, etc.

And simply getting building blocks to interoperate isn’t really the point now, is

it? It’s like the difference between grunting a few sounds and singing an aria, or knowing enough of a foreign language to order some food and being fluent enough to discuss an important topic with insight, depth and conviction. So too are the differences of acquiring a collection of building blocks from disparate suppliers and making the pieces recognize and acknowledge one another, versus sourcing a fully integrated system that has been preconfigured, pre-tested and pre-certified.

In other words, integration makes all the difference, and integration takes time, money and expertise—things that TEMs no longer have on their side (Figure 2).

Why Hurry?

Time has value, and experience shows that getting to market 6, 12, 18, or 24 months sooner generates tremendous strategic and financial advantage, especially for Tier 2 and Tier 3 TEMs competing with (or planning to get acquired by) Tier 1 TEMs. These days victory goes to the swift, and our detailed financial modeling shows that TEMs can cut product delivery timeframes in half while achieving up to a 50 percent increase in product lifetime return on investment (ROI).

How? A TEM that delivers a solution to the market first gets to establish the value proposition for that set of features and benefits, and then defend it as new entrants try to claw their way to the top of the hill. In other words, the firstmover earns the benefit of setting market expectations and forcing competitors to react. The advantage is being on the offensive and setting the terms of engagement, whether in terms of price, performance benchmarking, service levels, goodwill,

INDUSTRY Watch

Protocol Software Carrier-Grade OS Redundant Device Drivers Switching I/O Storage CPU & Packet Processing System Chassis: Power, Alarming, Cooling HA Business Practices & Life Cycle Management

Ecosystem Value

Figure 3

Professional Services

Applications: Enhanced GGSN / Packet Data Gateway, Enhanced Node B, CSCF, MG / TG, MGC / Softswitch, etc.

TEM Value

By sourcing fully integrated ATCA systems, TEMs can focus on delivering unique application value and leave the rest of the “plumbing” to the ecosystem.

etc. Everybody loves a winner, and success tends to beget more success; playing catch-up-and-take-over is very hard to do (at least profitably) for the second, third and fourth entrants. It pays to be first.

Besides getting the revenue clock ticking, another perk of being first to market is that the volume clock starts ticking as well. This means that manufacturing costs start coming down sooner than if market entry was delayed. So, not only is there the market perception advantage, but also the benefit of increasing the gap of cost of goods sold (COGS). In other words, the COGS of the first-mover will be less than the COGS of the second-mover (and all others who follow), which is a competitive advantage that can be harvested by the leader in terms of higher margins, lower prices, or both.

Why Focus?

Besides time and money, there are other good reasons for TEMs to buy what they can and make what they must: organizational clarity and lower overhead.

The customer who focuses solely on application development while outsourcing the rest of the system needs far fewer inhouse resources for platform R&D, supply chain management, interoperability and regression testing, etc. Since the human resources necessary for these tasks cost money and their financial burden is spread across all projects, product profitability and operating margin can be higher with system sourcing. It’s basically a matter of shifting investment from R&D to COGS, which is more efficient financially over the life of the product.

It is also a matter of organizational effectiveness. Just as a successful product needs to target a well-defined market segment and deliver tailored benefits rather than employ a broad shotgun approach, a successful organization is one that concentrates on those attributes in which it possesses unique competencies and can deliver true (and strategic) value-add. With standards-based ATCA platforms, there is no compelling reason why a TEM needs to have R&D resources developing products and capabilities that already exist in the ecosystem. Instead, the smart choice is for TEMs to focus R&D budgets on application development, which is the true source of value in a standardsbased network element (Figure 3).

When factoring in direct and indirect costs, core competencies, organizational focus and the value of delivering a product early in the available market window, one can see why sourcing an entire system is actually quite smart. Being first carries with it compelling advantages that outweigh former top priorities like proprietary design, platform specialization and massive scale.

Today, being nimble, flexible and focused is the way to get and stay ahead. Rather than end up in the same historical dustbin as the PC vendors of yore, today’s TEMs need to have the courage and conviction to do what is needed to transform their business models in order to remain relevant for tomorrow’s telecom infrastructure needs, and well into the future.

Continuous Computing San Diego, CA. (858) 882-8800. [www.ccpu.com].

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&TECHNOLOGY

Products

High-Density AC-DC Adapters for Medical Applications

A series of wall mount switching adapters, designed specifically for medical and information technology equipment (ITE) applications, are high-density, single output power adapters capable of delivering 12V at 12W total power and feature a slim form factor— enabling the use of multiple adapters in dual wall outlet configurations. DA12-M series switching adapters from Emerson Network Power are suitable for non-patient contact and non-patient critical medical and dental devices, and feature universal 90-264 VAC inputs in four AC plug configurations (US, UK, EU and AU models), each specifically suited for the region of the world in which they will be used. In addition, all four adapter configurations are engineered to meet stringent Level V Efficiency standards and are fully certified by Energy Star 2.0 and CeC approvals.

To ensure best-in-class power reliability, DA12-M series adapters feature comprehensive protections against overvoltage, overtemperature and short-circuit/overload conditions up to 150% above their maximum rating. The flexible power adapters also support a wide range of ambient operating temperatures from 0 to 40°C, have a ground leakage maximum current of 100 μA at 50/60 Hz and provide constant voltage/current output. In addition, the adapters comply with rigorous EN55022-B and FCC part 15 Level B EMC standards for conducted noise, feature built-in EMI filtering (CISPR 22 Class B) and boast an extensive array of ITE and medical safety approvals including UL/cUL/TUV/AS 60950-1/60601-1 certifications. Pricing starts at $8.00 per unit.

Emerson Network Power, St. Louis, MO. (314) 553-2000. [www.emerson.com].

High Industrial Ethernet System Availability with Powerlink Stacks

A major safety feature for industrial communication is continuous system availability, even if failures in essential components occur, e.g. in the communication master or in network connections (cables). To ensure high system availability, the availability of the controller as well as of the network must be guaranteed. For this reason, a highly available controller solution was considered for Powerlink at a very early stage, and was now specified in EPSG WDP 302 A and implemented by IXXAT. Besides the primary Managing Node (MN), several redundant master devices can be operated in one network, which act like Controlled Nodes (CN). The MN transmits cyclic messages to the CNs, to ensure the reliable detection of a controller outage within one communication cycle. In that case, one of the redundant masters is activated by using a priority algorithm and immediately continues the tasks of the broken MN. The redundancy procedure is transparent for CN devices, so existing CNs can be used in highly available networks without adaptations.

Network redundancy is achieved by using two independent network cables. All messages are transmitted on both lines in parallel to enable the message reception by the network nodes even with one broken cable. The new version of the IXXAT Powerlink protocol software is implemented according to the Powerlink specification V 1.1.0 and is available as source code and as IP core for the development of highly performing Managing and Controlled Nodes based on an FPGA. The software is also implemented on the Industrial Ethernet Module from IXXAT. The extension package for the development of redundant managing nodes is optionally available.

IXXAT, Bedford, NH. (603) 471-0800. [www.ixxat.com].

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March 2009

Layer-2 Gigabit Ethernet Switch Features Front I/O Routing

Designed for demanding network switching applications in industrial, commercial, government, telecommunications and defense applications, a new 6U form factor switch provides support for 12 or 24 Gigabit Ethernet ports. The RM983RC from GE Fanuc Intelligent Platforms ships with GE Fanuc’s OpenWare Lite switch management environment,

providing customers with the flexibility to manage configuration of the RM983RC from a serial console or via the network.

Capable of Layer-2 switching at wire speed, the RM983RC’s 12 or 24 ports are routed to front panel I/O and can be 10/100/1000BaseT, 1000BaseSX or 1000BaseLX. Mixing and matching of fiber and copper media in groups of four is supported. The front panel I/O routing of the RM983RC extends the capability of the NETernity 6U VME product family by offering designers a choice of I/O routing; the recently announced NETernity RM982RC features rear I/O. OpenWare Lite, which is available on selected NETernity switches, is designed to be easy to deploy. Linux-based, the software allows faster implementation and easy updates to firmware. A familiar Linux command line interface and remote Telnet user interface support allows users to select how they interact with the switch. Management features include support for VLANs, MSTP, trunking, mirroring and limited SNMP. GE Fanuc Intelligent Platforms Charlottesville, VA. (800) 368-2738. [www.gefanuc.com].

Hybrid Ethernet-Terminal/Multiport Device Server

A Device/Terminal Server enables users to remotely access and manage up to 16 devices on a corporate network.

Using industry-standard management tools, the multiport EDSPS from Lantronix servers allows serial equipment, such as medical devices, kiosks and retail terminals, to be accessed and managed via the Internet.

The RoHS-compliant EDSPS includes strong SSH, SSL and AES-encryption, enterprise-level security, which is especially important in today’s corporate environment. Lantronix’ highly secure Evolution OS ensures data transported through the EDS is protected from denial of service, port mapping and other hostile Internet attacks. The data centergrade level of protection is easy to configure and allows organizations to attach multiple electronic devices to their corporate network.

Lantronix’ device servers also feature industry-standard management tools for easy configuration and monitoring, and email and RSS notifications for instant visibility of device activity. The EDS’ standards-based communications include a simplified, Cisco-like command line interface (CLI) to assist with set-up and control, in addition to XML-based and Web configuration tools.

Lantronix, Irvine, CA. (949) 453-3990. [www.lantronix.com].

User-Configurable FPGA-Based PMC Modules with Plug-In I/O

A powerful and flexible I/O processor module that is capable of executing custom instruction sets and algorithms, the PMCVFX70 board from Acromag features a reconfigurable Xilinx Virtex-5 FPGA enhanced with multiple high-speed memory buffers and a high-throughput PCI-X interface. Field I/O devices interface to the FPGA via the rear J4/P4 connector and/or with optional front mezzanine plug-in I/O modules.

The onboard XC5VFX70T FPGA with 71,680 logic cells has a hard core PowerPC 440 block to handle the most complex and memory-intensive computing applications such as offloading CPU-intensive operations like video and 3D data processing or fixed-point math for superior system performance. The PowerPC core also enables system-on-chip functionality with real-time processing capabilities.

64 I/O lines are provided via the rear (J4) connector. Additional I/O processing is supported on a separate mezzanine card that plugs into the FPGA base board. A variety of these external I/O cards offer an interface for your analog and digital I/O signals.

Large, high-speed memory banks provide efficient data handling.

Generous DDR2 SDRAM buffers store captured data prior to FPGA processing. Afterward, data is moved to dual-port SRAM for high-speed DMA transfer to the system. Our high-bandwidth PCI-X interface ensures fast data throughput.

Take advantage of the module’s support of conduction cooling for efficient dissipation of heat in environments with inadequate cooling air flow. The optional extended temperature VFX70E model operates from -40° to 85°C. Acromag’s Engineering Design Kit provides software utilities and example VHDL code to simplify your program development and get you running quickly. A JTAG interface enables onboard VHDL simulation. Pricing for the VFX70 is $5,250 and for the VFX70E $6,000.

2.7 Terabyte Rugged 6-Drive JBOD for HighAltitude Platforms

A rugged removable rotating media storage system for high-altitude applications is now available with up to 2.7 terabytes (TB) of hard drive storage. The SANbric from Curtiss-Wright Controls Embedded Computing deploys six 3.5”drives in a just a bunch of disks (JBOD) configuration supported by a dual high-speed Fibre Channel Storage Area Network (FC SAN) communications architecture.

SANbric is designed for use in the harsh environments typical of military aerospace intelligence, surveillance and reconnaissance applications such as ELINT, COMINT, SIGINT, SAR, MTI and SDR. SANbric enables system integrators to rapidly and easily deploy a high-performance, highcapacity storage system at a cost significantly less than that of solidstate flash memory-based alternatives.

SANbric, locked in its shock isolation unit (SIU), is designed to operate under shock and vibration conditions, over a wide temperature range and at high altitude. It uniquely deploys six FC disk drives in a single sealed cartridge, reducing system weight and simplifying cabling and connectivity between the drives. The isolation provided from harsh environments enables the use of standard FC disks in many applications previously considered too harsh for rotating media devices.

SANbric is available with a variety of SIU enclosure types and custom SIUs can be developed for program specific requirements. Each SIU is tested to RTCA DO-160 Curve C and T testing. In addition, all SIUs pass shock tests, modeled on the MIL810 standard, including crash shock. The unit can be connected to any standard FC adapter or switch for scalability in an FC SAN configuration and is an ideal complement to Curtiss-Wright’s family of 800 Mbyte/s Vortex Data Recording Engines.

Curtiss-Wright Controls Embedded Computing, Leesburg, VA. (703) 779-7800. [www.cwcembedded.com].

Acromag, Wixom, MI. (248) 295-0310. [www.acromag.com].

March 2009

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Products & TECHNOLOGY Blue Lasers Target Micro-Projectors

A new small blue laser diode could help bring the world one step closer to a vision of tiny projectors that can be integrated into mobile devices such as cell phones and digital cameras.

Lasers are the ideal choice as light sources for these micro-projectors, which convert the mobile devices into high-performance multifunctional devices that can not only record images but also present them in razor sharp detail. Mobile devices currently available on the market can produce and download high-quality photos and video clips. Integrated laser projectors will enable these devices to project this content in high quality on almost any surface.

The blue laser diode from Osram Opto Devices is delivered in a TO38 package and has a wavelength of 450 nm, output of 50 mW and voltage of 5.5V. It has all the important attributes required for micro-projectors such as small size (3.2 mm height), high efficiency (0.9 W/A) and excellent blue light visibility. As a ridge laser it also has an outstanding beam quality and therefore needs only relatively simple small optics to shape the beam.

Laser projection represents the next milestone in the development of mobile devices and has a promising future in terms of integrated projection modules.

End-users will appreciate the extremely low power requirements and compact dimensions offered by laser-based projection units. Lasers also offer exceptionally vibrant colors, high contrast and always produce sharp images irrespective of the distance over which the images are projected. Osram Opto Semiconductors is also developing red and green lasers for laser projection. The red laser, like the blue laser, will be designed as a direct semiconductor laser while green lasers will be implemented using a frequency doubling technique.

OSRAM Opto Semiconductors, Santa Clara, CA. (888) 446-7726. [www.osram-os.com].

Crystal Oscillator Family for Networking, Storage and Broadband Access

A family of low-jitter, low-power, high-frequency crystal oscillators developed using Pericomâ&#x20AC;&#x2122;s patented XP technology uses an industry unique quartz + silicon integration technology to offer very low-jitter, non-PLL-based oscillators covering the challenging 150 MHz - 220 MHz frequency spectrum.

The 2.5V/3.3V SX/SN series and 3.3V SD/SH series of XP crystal oscillators (XO) from Pericom Semiconductor feature the very latest in oscillator circuit design techniques. Based on a proprietary patented technology that combines Pericomâ&#x20AC;&#x2122;s IC silicon technology and Saronix-eCera quartz technology, the XP oscillators are designed for much improved reliability and lower phase jitter (0.25 ps rms typical) for high-frequency 2.5V & 3.3V CMOS/PECL clock applications. The product is drop-in compatible with existing Overtone, SAW and PLL-based oscillator solutions in 4-pin 5x7 mm (2.5V/3.3V SX CMOS Series), 6-pin 5x7 mm (2.5V/3.3V SN PECL) and 6-pin 3.2x5 mm (3.3V SD PECL Series) packages.

Pericom Semiconductor, San Jose, CA. (408) 435-0800. [www.pericom.com].

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March 2009

Low-Cost Brushless DC Motor Control Evaluation Board

A new low-voltage Brushless DC (BLDC) motor-control development platform supports the dsPIC33F family of motor control DSCs from Microchip Technology. It provides a costeffective method for evaluating and developing sensored or sensorless BLDC and Permanent Magnet Synchronous Motor (PMSM) control applications. The board contains a three-phase inverter bridge circuit. This circuit drives a BLDC or PMSM motor using different control techniques, without requiring any additional hardware. The dsPICDEM MCLV board is capable of controlling motors rated up to 48V and 15 amps, and supports multiple communication channels, such as USB, CAN, LIN and RS-232. It employs a processor-differentiated Plug-In Module (PIM) strategy to support a variety of dsPIC33F motor-control DSCs with different memory and pin configurations. A dsPIC33FJ32MC204 PIM (32 Kbyte flash and 44 pins) is included with the dsPICDEM MCLV Development Board.

Additionally, Microchip announced two new motor-control software solutions: one shows how Power Factor Correction (PFC) algorithms can be combined with sensorless motorcontrol algorithms on a single chip.

The second software solution demonstrates how to run an AC Induction Motor (ACIM) faster than its rated speed for a class of applications to lower cost, save space or reduce weight.

Both are available today for free at http:// www.microchip.com/DSCMOTOR The worldwide demand for improved power quality standards is driving the trend to add PFC to line-powered motor control applications. Power quality can be enhanced by implementing PFC, and efficient control of a motor can be realized using sensorless field oriented control (FOC) techniques. Both can be achieved by integrating PFC and sensorless FOC algorithms on a single dsPIC DSC. The dsPICDEM MCLV Development Board (part # DM330021) is available now for $150.

Microchip Technology, Chandler, AZ. (888) 628-6247. [www.microchip.com].

Software Defined Radio Now on Family of PCI Express Boards

A new family of software defined radio products features the PCI Express (PCIe) form factor with advanced connectivity options.

The 7700 family from Pentek is comprised of five products: the Models 7741, 7742, 7750, 7751 and 7752. Each offers a unique set of software radio features in a full-length PCIe board with the very latest Gen 2 PCIe x16 interface. This emerging standard for high-end PCs, blade servers and enterprise computers delivers fast interconnect links for economical, high-performance system solutions.

Each of the five software radio boards offers specific resources including channel count, bandwidth, FPGA population and more.

This allows customers to choose exactly what they need for very cost-effective, high-density solutions.

The Model 7741 includes up to four 125 MHz, 14-bit A/Ds and four 500 MHz 16-bit D/As. It features one or two TI/Graychip GC4016 quad digital down converters with output bandwidths up to 10 MHz, and one or two digital up converters that accept baseband real or complex data streams with signal bandwidths up to 40 MHz. One or two Xilinx XC2VP50 Virtex-II Pro FPGAs serve as control and status engines with data and programming interfaces to each of the onboard resources, including the A/D converters, digital down converters, digital up converters and D/A converters.

The Model 7742 includes up to eight 125 MHz, 14-bit A/Ds, two up converters and two 500 MHz 16bit D/As. The 7742 architecture also includes up to four Virtex-4 FPGAs. The Model 7750 includes up to eight 200 MHz, 16-bit A/Ds, up to 3 Mbytes of SDRAM, and up to four Virtex-5 FPGAs. The Model 7751 is a 512-channel digital down converter with up to eight 200 MHz A/Ds and up to four Virtex-5 FPGAs. This represents a tremendous amount of processing power in a single PCIe slot. It features independent tuning for each DDC channel and decimation from 128 to 1024 in steps of 64.

Finally, the Model 7752 is a 64-channel down converter with up to eight 200 MHz, 16-bit A/Ds and up to four Virtex-5 FPGAs. Each group of four A/Ds is supported by a high-performance 32-channel digital down converter. DDC decimation ranges from 16 to 8192 in steps of 8.

Another feature common to all the boards in the 7700 family is the 4-pin disk drive power connector to ensure that the boards receive ample power from the host computer or server. This augments the power supplied through the PCIe backplane connector.

The Models 7741, 7742 and 7750 have user-configurable FPGAs, and Pentek supports customers with the GateFlow Design Kits.

Because the Model 7751 and 7752 have reinstalled FPGA digital down converter IP cores, they do not require user programmability. ReadyFlow board support packages for Linux and Windows are available for all boards. Pricing for boards in Pentek's 7700 series begins at $13,490.

Pentek, Upper Saddle River, NJ. (201) 818-5900. [www.pentek.com].

Fully Integrated MIL-STD-1553 Terminal Speeds Integration

A fully integrated 1553 terminal consolidates all the necessary MIL-STD-1553 components within a single, small, cost-effective PBGA package. The BU-64843T Total-ACETM from Data Device Corporation comprises a complete interface between a host computer and a MIL-STD-1553 bus that simplifies design, procurement and qualification processes. The TotalACETM integrates dual transceivers, dual transformers, protocol engine and 4K words of internal RAM, and is fully software and hardware compatible with DDC’s Enhanced Mini-ACE series of devices. The BU64843T is powered entirely by +3.3 volts, and offers an extended -40° to +100°C industrial temperature range. Additionally, the Total-ACETM is DO- 254 certifiable, and is available in RoHS-compliant versions.

Data Device Corporation, Bohemia, NY. (631) 567-5600. [www.ddc-web.com].

Scientific and Medical Instrument Cabinet Enclosures

A cabinet enclosure for scientific and medical instrumentation applications from Optima EPS is designed with several features in mind for scientific and medical instrumentation. This includes a flexible, modular design that allows a wide range of shelves, rails, perforated panels, wiring duct, divider panels and ergonomics. DIN rails for mounting instrumentation are prevalent. The 14” shelves and 19” dividing rails are geared toward common equipment sizes for these applications. The enclosures come in standard 14U-24U heights and 32”, 34” and 36” depths. Widths range from 30-36”. With the enclosure line’s modular design, other sizes can easily be configured with little customization.

Other features for the enclosure line include a rearperforated panel for airflow, EMC shielding, and rear access. Various accessories are available such as castors, shelf options, mounting devices and more. Optima also offers painting/powder coating, silk-screening and customization services. Pricing is under $700 depending on volume, options and configurations.

Optima EPS, Tucker, GA. (770) 496-4000. [www.optimaeps.com].

March 2009

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Products & TECHNOLOGY New Automated Management of Software Requirements

A new software management technology automates the techniques and tools for the integration of requirements traceability with software testing and verification. On completion, the technology will be integrated into TBreq, the portion of the LDRA tool suite devoted to requirements-driven testing.

Automation of requirements-driven testing and traceability addresses an urgent need in safety- and mission-critical industries such as avionics, medical, defense and nuclear where requirements traceability and verification consume a significant portion of project budgets. The technology automatically captures requirement information for software development projects from a wide variety of sources and simplifies the construction of a requirements traceability matrix (RTM).

Building on proven technology that verifies software to exacting industry standards, LDRA has unveiled a solution for automating the construction of requirements traceability matrixes and enforcing the industryaccepted best practice of placing requirements as the focal point for software development and testing. The new technology enables developers to establish a baseline of selected software requirements from which development and testing will begin, and to delegate the tasks associated with each requirement to members of the development team.

The tool lets developers associate source code with each requirement, thereby automating the creation of trace relationships and also to refine source code mappings to the level of class or even individual functions. Requirements can be verified according to a wide variety of analyses and tests performed on the mapped code, and then requirements, test cases and code coverage results can be automatically linked in a unified view of all levels of testing LDRA, Wirral, UK. +44 (0)151 649 9300. [www.ldra.com].

Dial-Up Modems Specially Designed for Medical Apps

A complete family of external and embedded modems is specifically designed to meet the stringent requirements for the medical services industry. The Research Medical Modem family from Radicom is safety, emissions and telco compliant to meet most medical device requirements. These very small and versatile modems are available in both Serial TTL and the popular USB interfaces, capable of operating under Windows, Linux or Mac environments. The modems are designed to be suitable for x86 or other CPU-based Healthcare Home Monitoring Systems, Data Retrieval Devices using either Linux or Windows O/S that need to have reliable dial-up connectivity.

As well as compliance with IEC60601-1 for medical applications, 3KV breakdown is also available in both the USB and Serial versions. The certifications are transferable to allow easy integration into almost any platform. All Medical Modem versions are CCITT and Bell compliant for complete compatibility to existing and future installations. The family is also compliant to domestic and international Telco standards. Versions include 300 bits/s (V.21/Bell103), 1200/2400 bits/s (Bell212/V.22/V.22bis), 14.4 Kbits/s (V.32bis), 33.6 Kbits/s (V.34) and 56 Kbits/s (V.90/V.92).

All platforms are available with FAX, voice playback and record, as well as DTMF (SP) tone generation and detection. These versatile products can be provisioned for applications ranging from system monitoring and reporting to answering inbound calls with voice responses. Available in commercial and industrial temperature ranges, all versions are RoHS compliant.

Radicom, San Jose, CA. (408) 383-9006. [www.radi.com].

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March 2009

Core2 Duo-Based 6U VME SBC for Multiprocessor DSP Applications

Responding to customer demand for 6U VME solutions with increased processing performance, lower power consumption, extensive I/O capability and advanced graphics, GE Fanuc Intelligent Platforms has introduced it V7857 SBC. Featuring the Intel Core2 Duo T9400 processor—which was designed for mobile applications in which

power conservation is a key design factor—running at 2.53 GHz, the V7875 also provides up to 6 Mbytes of L2 cache.

This combination of high clock speed, large cache and fast front side bus, together with low heat dissipation, has been demonstrated to deliver exciting performance in multiprocessor DSP applications. Use of the Intel GM45 chip set provides fast access to up to 4 Gbytes of DDR3 SDRAM and a x16 PCI Express interface to deliver exceptional performance for demanding applications. VITA 41.3 (VXS) for Gigabit Ethernet across the backplane is also optionally available.

The V7875 also offers high I/O flexibility. Not only does it provide support for a PCI-X XMC/PMC site, but also a connector to the EXP237 mezzanine board to deliver an optional three additional XMC/PMC sites. The board can optionally include the ATI Radeon E2400 graphics processing unit—which features a x16 PCI Express interface and 1,920 x 1,080 (full HD) HDMI resolution—in place of one of the XMC/PMC sites, providing a powerful 2D, 3D and multimedia graphics capability.

Additional connectivity is provided by a dual SATA disk interface, two Gigabit Ethernet ports routed to the front panel, four USB 2.0 ports and two serial ports. For applications not requiring the XMC/PMC site, even further I/O—one eSATA port, one USB 2.0 port and two Gigabit Ethernet ports (when VITA 41 is not available)—can be provided via the front panel.

GE Fanuc Intelligent Platforms Charlottesville, VA. (800) 368-2738. [www.gefanuc.com].

Digitizer Uses FPGA Technology, Multichannel A/D and D/A

Targeted at high channel count signal processing for a wide range of applications such as RADAR, signals and electronic intelligence (SIGINT / ELINT), and Electronic Warfare (EW), a new 6U ANSI/VITA 41 (VXS)-compliant high-speed digitizer board combines high-density FPGA processing with six 16-bit A/D input channels at 185 Msamples/s along with a coherent 16-bit D/A output channel. The QuiXilica Tarvos-V5 VXS from TEK Microsystems employs three Xilinx Virtex-5 FPGAs. The Tarvos-V5 offers extremely high FPGA processing density per channel, along with a measured signal-to-noise ratio (SNR) of 72 dBFS and Spurious Free Dynamic Range (SFDR) in excess of 95 dB. Many advanced signal processing applications are based on antenna array processing and require large numbers of channels and distributed signal processing. The architecture of the TarvosV5 combines six analog input channels with three Xilinx Virtex-5 FPGAs, providing up to 2,336 DSP slices and 1.285 TeraMAC/s of

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CO C COT OTS OT OTS TS signal processing, equivalent to 61% of a Xilinx Virtex-5 SX95T device per input channel. For high channel count requirements such as beam forming, direction finding, jamming or anti-jam / interference cancellation, common in RADAR, SIGINT, communications, and EW applications, the Tarvos-V5 provides both the highest processing density per channel and per 6U slot, reducing total size, weight and power for many systems.

Each analog input channel uses a Linear Technology LTC2209 16-bit A/D converter, which is designed for digitizing high frequency, wide dynamic range signals within an analog input bandwidth of 700 MHz. A range of options is available for input signal conditioning to support different receiver applications.

The output channel uses a Maxim MAX5891 16-bit D/A converter that is synchronized to the input clock rate. The output is AC coupled with full scale output voltage of -2 dBm into a 50 ohm load.

The layout has been designed to ensure phase matching of the clock across all input channels and to minimize aperture jitter. Trigger input and output connections are also provided on the front panel to allow the hardware to be employed in a variety of scenarios.

RAID/SAN/NAS/VME

Phoenix International designs and builds rugged COTS Data Storage Systems that plug and play in any application -- from Multi-Terabyte Fibre Channel RAID and Storage Area Network configurations to plug-in Solid State Disk Drive VME/cPCI Storage Modules.

4FF VT BU XXX QIFOYJOU DPN PS DPOUBDU VT BU t JOGP!QIFOYJOU DPN An AS 9100 / ISO 9001: 2000 CertiďŹ ed Service Disabled Veteran Owned Small Business

TEK Microsystems, Chelmsford, MA. (978) 244-4112. [www.tekmicro.com].

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1/21/09 8:35:49 AM

Products & TECHNOLOGY 3.5” Single Board Computer Features LowPower Atom CPU

Focusing on innovative, revision controlled, long life cycle designs, Avalue has introduced a standard 3.5” form factor product featuring the Intel Atom N270 1.6 GHz CPU and support for up to 2 Gbyte DDR2 SDRAM. Video options include Dual Channel LVDS support along with DVI and TV-out support for HDTV applications. 5.1 Channel audio support allows for full multimedia application support. Dual Gigabit Ethernet interfaces and 6 USB 2.0 ports support a variety of add on devices for your application.

Targeted markets for this product include medical instrumentation, interactive kiosk designs, high-end digital signage applications and small footprint display applications. The Intel Atom N270 Processor and Intel 945GSE chipset were introduced during the second quarter of 2008 and have a manufacturing guarantee of 7+ years directly from Intel. By selecting these items Avalue continues to assure their customers of product longevity and support.

Series of PCI Express Frame Grabbers Spans Live and Still Applications

A new series of PCI Express frame grabbers ship with a number of different video inputs. Some models are available for low-profile PC cases. The Imaging Source frame grabbers are deployed for applications in which analog video signals (PAL, CCIR, NTSC, RS-170) need to be processed by a PC. In addition to cameras, such video input devices include ultrasound and x-ray machines. Analog cameras are not only used in legacy applications. Often they are preferred for price-sensitive projects, in which long cables are required.

The Imaging Source frame grabbers ship with drivers for Windows, the SDK ‘IC Imaging Control’ and the end-user application software ‘IC Capture’.

The latter is a powerful software that allows the setting of all frame grabber parameters, the display of live video stream and the acquisition of singular images and sequences.

The Imaging Source Europe, Bremen, Germany. +49 0421/33591-0 [www.theimagingsource.com].

Avalue Technology, Tinon Falls, NJ. (732) 578-0200. [www.avalue.com.tw].

INDUSTRIAL I/O via Ethernet Monitor position & speed | Regulate fluid levels Measure temperature | Control motors & solenoids

SENSORAY’s data acquisition applications range from controlling cranes at shipping ports to controlling water pressure at laser jet cutting factories. We specialize in the development of devices for industrial sdioincluding nelos & srotEthernet, om lortnoC PC/104, deeps &PCI, noitiand sop roPCMCIA. tinoM applications on several buses, We support operating slevel diuPocket lf etalugPC/Windows eR erutarepmCE, et eReal-Time rusaeM systems which include Windows, Linux, OSs and QNX. We offer off-the-shelf, custom or modified solutions, live technical support and evaluations.

To learn more visit: SENSORAY.com, email: info@sensoray.com or call: 503.684.8005 Model 2426 | Industrial I/O via Ethernet

1 46Untitled-3 March 2009

3/20/09 10:51:05 AM

INTO TECHNOLOGY COMING TO A CITY NEAR YOU rtecc.com

NEWS, VIEWS &

Comment MARCH 2009

Warren Andrews Associate Publisher

Wine from Sour Grapes

L

ast issue, Editor-in-Chief, Tom Williams accused me of being a Pollyanna—looking at the glass as ¼ full rather than ¾ empty. History may be proving him right. As I sit down to put this column together, it’s becoming increasingly difficult to find a lot of encouraging news. However, I’m sure it’s there, so here goes. Let’s try and make some wine out of sour grapes.

All reports from the embedded computer industry continue to be cautious, but optimistic. But for some, things are already starting to turn south. I spoke with a few companies that sell into the semiconductor equipment sector and they have already seen cancellations of orders and nothing new on their plate. Applied Materials—the world’s largest seller of chip-making tools—expects a 50% drop in spending on equipment this year. Applied reports that it is running its plants at 30% to 40% capacity. Others in the industry such as TLA Tencor, Lam Research, Novellus, Varian and others report similar results. The embedded-computer business supplies control and imaging equipment to these chipmaking equipment manufacturers.

The story has been much the same in other industrial automation areas. There remains a handful of bright spots as some companies shuffle to get into lower cost systems and higher productivity. And, needless to mention, retail and POS hardware and software is at a standstill.

And while this tells a dreary tale, there are some points of encouragement. In the public service and security sectors it seems activity has slowly been ratcheting up. Similarly, the medical instrumentation industry appears to be on the increase. Though the big imaging systems—CAT scanners, MRI, PET scanners, EBT and other systems suppliers are not expected to see much growth over the next few years, smaller portable and desktop systems are expected to grow as the healthcare system flattens out. This is likely to play out as new initiatives in healthcare are enacted and

48

March 2009

more monitoring and diagnostics are moved to a virtual world.

And new initiatives as part of the stimulus plan (see below) are expected to kick in next year.

Military: A Bright Spot, But Is There an Eclipse Coming?

And the other area that it appears may be salvaged—at least for the next year or so—is the military and defense industries.

The proposed Presidential budget for 2009/2010 actually shows an increase of some 4%. And if Congress continues on its spending spree, that amount might even be increased as special projects near and dear to the hearts of congressional supporters are revived and expanded.

The Navy is likely to see more new ships and planes, the Air Force will probably see a new salting of F-22 aircraft and other planes, the Army new and improved ground vehicles, and all the services, improved communications, training, simulation and services.

But there are clouds on the horizon. This year’s defense budget is larger in inflation-adjusted dollars than at any time since WWII. The Army has fewer divisions, the Navy fewer ships and the Air Force fewer planes. And, according to the CBO, what hardware we have is older than it’s ever been. And the list goes on and on. In spite of all the acquisition reform, cost overruns have been higher than ever measured: Further, no current system has been delivered on time, on cost and as promised for performance.

The fear is that this cloud over military acquisition is building, and simply throwing more money at the problem won’t make it go away. Sooner or later, the bubble is going to burst and we’re going to see some dramatic changes. The good news is for those in the embedded-computer business that will continue to sup-

ply upgrades and new technology insertion into older systems.

Granted, going forward I think we’ll see lower ASPs, but these retrofit programs will not only continue, but probably accelerate.

its joint-venture with Vodafone, expects to begin commercial service of the new technology in 2010. More information as it comes in.

Where There’s Light, There Is Competition

Obama’s Stimulus: Something for Every Techie

There continues to be some light at the end of the tunnel. As big buyers like banks and auto companies are on the spot these days, squeezing every penny, tech hardware makers are looking to win sales from smaller companies. This is particularly true in the embedded-computer business, however, larger companies and even some in the commercial laptop and Netbook business are scrambling for small customers since the bigger customers are “frozen up.”

There apparently is still some good news on the employment front also. A survey by TalentDrive reports that some 52% are investing in increased marketing efforts and a sales-force increase, 58% are implementing new services and repositioning their company to attract new clientele, 57% predict the staffing downturn will lighten by Q3 2009, and 65% of staffing firms find the over abundance and quality issues of resumes the number one concern for 2009. The survey looked at over 7500 staffing firms and independent recruiters. That’s the good news. However, when asked if new technology was being employed to assist with sourcing, 66% responded negatively.

Despite some setbacks, Intel is still upbeat over the future of WiMax. WiMax has had its difficulty in the U.S., primarily because Clearwire, the company building networks in the U.S. has been financially challenged and has managed to launch service in only two cities. However, Intel reports that networks based on WiMax now send their signals to 430 million people around the world and should cover 800 million people by the end of 2010.

The competition? While cellular 3G certainly has a leg up in acceptance, it’s nowhere near as fast. Other approaches include LTE (Long-Term Evolution—see below), which is expected to offer similar speeds to WiMax, but it’s not here yet. And it’s getting back to the chicken and egg problem, having the equipment to take advantage of the technology versus having the infrastructure to service the equipment. Embedded-computer technology is expected to take advantage of WiMax in a broad variety of applications once it becomes available.

And while on the subject of Intel, congratulations to our friends at PLX for being recognized by Intel for its contribution to advancing the PCI Express 2.0 interconnects on Intel microarchitecture, codenamed Nehalem, platforms. PLX’s switches were recognized for providing power and performance efficiency to the quad-processor platform.

And is 4G service just around the corner? At the Mobile World Congress, Verizon announced that it picked Ericsson and Alcatel-Lucent to build the first 4G Network. Often known as Long-Term Evolution (LTE), 4G technology will allow mobile access to features such as high-quality video previously available only through fixed-line broadband networks. Verizon, and

Such was the wording of a recent headline in a large national newspaper. While the article cited that the stimulus has many costly parts, some of which don’t seem to be fully baked, it said that the high-tech executive community probably wasn’t going to be complaining.

Let’s take a look at what’s in the stimulus plan for the techies. First there is some $19 billion allocated for automating healthcare facilities. That’s going to be fun. Intel and others have already gotten started here and it’s likely there will be a host of other embedded-computer applications forthcoming. It’s important to remember that the new breed of product (hardware and software) is going to have to carry FDA approval. That means specialized embedded computers that carry much higher margins and ASPs than we expect from cell phones and consumer products. Certainly in the capability range of many in the embedded-computer industry—particularly with the new generation of small, low-power, low-cost platforms. Everyone should be able to feed off that bandwagon from the semi makers right on through the embedded-computer makers and packaging experts.

Then, we’ve got $7 billion to broaden Internet access. Will Intel’s WiMax start to fit into this niche? At least part of the spending is intended to bring broadband networks to rural areas; this could directly impact WiMax. The embedded-computer market will obviously be one of the recipients of the infrastructure build out. How far will $7 billion go? My guess is quite a ways. However, not being able to access the whole stimulus bill, I don’t know what other special considerations/conditions were attached.

Then there’s the $3 billion going to the National Science Foundation, which grants money to Universities and companies for research projects that we hope will result in significant developments. While traditionally much of the creativity from Silicon Valley has come from creative entrepreneurship fostered by venture capital, it’s not certain that the NSF will function the same way. And when you start to take out the incentive—then add the burden of restricted option granting, higher taxes and the reduction of other incentives—perhaps the $3 billion could be better spent.

Now, add to the stimulus bill the proposed 2009/2010 budget, and hundreds of more billions of dollars will be available in areas such as healthcare, social services, security and other.

Perhaps the high-tech industry should indeed be looking up.

Until next month, Pollyanna

March 2009

49

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