New Se c t i o n : by RTC Media

New Se c t i o n :

Technology Focus

ESL TOOLS Come of Age

AUDIO CODECS MOBILE WiMAX SWITCH-MODE POWER SUPPLIES Featured Product: Sequoia SEQ7400

June 2007

www.portabledesign.com

MICROCONTROLLERS

Everything but the Kitchen Sink! Complete SoC for High-Precision Portable Instrumentation Applications • High-precision, battery-powered: Portable medical Portable industrial Low-power RF

Features • Up to 120KB Flash/8KB RAM • Ultra-low-power RTC operation • Zero-power brown-out reset • Complete system-on-chip: UART, SPI, I 2C, IrDA OPA-ADC-DMA-DAC-OPA • Voltage-programmable LCD driver • Trace buffer on chip • Easy to use

The World’s Lowest Power MCU With an extended 1MB memory model, the easy-to-use MSP430FG461x MCU series is designed for today’s larger system memory requirements and allows for the development of very sophisticated real-time applications. The extended memory model also enables faster code execution that results in up to 50% reduction in cycles for a full context store and up to 25% when addressing peripherals, Flash or RAM.

Device MSP430FG4616 MSP430FG4617 MSP430FG4618 MSP430FG4619 1USCI

16-Bit Program SRAM Timers Brown-Out (KB) (B) I/O A B Reset 92 4096 92 8192 80 3 7 116 8192 120 4096

SVS

USART LCD Temp ADC Additional UART/SPI USCI1 Segments DMA MPY Comp_A Sensor Ch/Res Analog

160

12/12 (2) DAC12, (3) OPAMP

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channel 1 supports UART/LIN, IrDA and SPI; USCI channel 2 supports I 2C and SPI.

Learn More and Take Home FREE Tools at 430 Day 2007 • FREE, three-hour lunch-and-learn • Register and attend to get your FREE MSP430 Collectors Kit, featuring the eZ430-F2013 tool, AND…

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1842A0

The 80/20 Power Problem: Major Productivity Drain

6 8 10 42 44

Block Architecture

RTL Level

RT Level

Synthesis

Gate Level

Iteration not possible so late in the design cycle

Physical Design

Layout

18 ESL tools

Design Time

editorial letter dave’s two cents industry news product feature products for designers

Power Gain

SoC Architecture

Weeks

departments

Architecture C/C++/SystemC

Days

System Architecture

Minutes

contents

Expensive, timeconsuming iterations

High-Performance Digital-to-Analog Converter

4.0

The Cost of Integration 26 in Audio Codecs

3.5 3.0

Robert Kratsas and John Tucker, Cirrus Logic

2.5

wireless communications Mobile WiMAX: 30 Gates The Evolution to Lower NAND Power

Allen Hill, Analog Devices, Inc.

.18

.25

2.0

1.0 64 pF of Capacitance 0.5

1 pF of Capacitance

portable power Designing Switch Mode 36 Power Supplies Daniel Wagner, Maxim Integrated Products, Inc.

2009/2010 (Projected)

2006/2007

1.5

30 WiMAX

Direct I/Q Transmitter

VGA

D/A

Polar Transmitter

More Effi

VGA

TXF

Linear Amps 2RF PLL

AM D/A PC

PC Div2 Mixers Generate Spurs

2RF Path Circuits Eliminated Current Reduced

TXF

PLL

D/A

42 product

90 nm

Analog Output

26 audio codecs

RF Transceiver

consumer electronics

Switched Capacitor Element Mobile WiMax Peak Power (No Assumption For Power Cycling)

Processor

Audio Port

24 bits @ 3 bits @ 24 bits @ 44.1 kHz Interpolation 2.822 MHz Multi-Bit 2.822 MHz Delta-Sigma Filter Modulator

WATTS

I²S Digital

JohnInput Donovan Serial

RF Transceiver

ESL Tools Come of Age 18

Processor

Analog Domain

Digital Domain

TOTAL

cover feature

One path for WEDGE

Polar Architecture Benefits • Simple RF System • Higher output power • Cleaner Spectrum • Maximum re-use • Lower power consumption feature

JUNE 2007

team editorial team

Editorial Director Editor-in-Chief Senior Editor Managing Editor Copy Editor

Creative Director Senior Graphic Designer Graphic Designer Director of Web Development

Web Developer

Associate Publisher Product Marketing Manager (acting) Advertising Sales Manager 6/15/07 10:14:46 AM Business Development Manager

Circulation

Chief Executive Officer Vice President Vice President of Finance Director of Corporate Marketing Director of Art and Media

Warren Andrews, warrena@rtcgroup.com John Donovan, johnd@rtcgroup.com Dave Cotton, davec@rtcgroup.com Marina Tringali, marinat@rtcgroup.com Rochelle Cohn

art and media team Jason Van Dorn, jasonv@rtcgroup.com Kirsten T. Wyatt, kirstenw@rtcgroup.com Christopher Saucier, chriss@rtcgroup.com Marke Hallowell, markeh@rtcgroup.com Brian Hubbell, brianh@rtcgroup.com

management team

Untitled-1 1

Marina Tringali, marinat@rtcgroup.com Aaron Foellmi, aaronf@rtcgroup.com Michael Bognacki, michaelb@rtcgroup.com Jessica Grindle, jessicag@rtcgroup.com Shannon McNichols, shannonm@rtcgroup.com

executive management

HOW WELL DO YOU KNOW THE INDUSTRY?

John Reardon, johnr@rtcgroup.com Cindy Hickson, cindyh@rtcgroup.com Cindy Muir, cmuir@rtcgroup.com Aaron Foellmi, aaronf@rtcgroup.com Jason Van Dorn, jasonv@rtcgroup.com

portable design advisory council Mark Davidson, National Semiconductor Doug Grant, Analog Devices, Inc. Dave Heacock, Texas Instruments Kazuyoshi Yamada, NEC America

WWW.EMBEDDEDCOMMUNITY.COM

home office

china sales office

The RTC Group 905 Calle Amanecer, Suite 250 San Clemente, CA 92673 Phone 949.226.2000 Fax 949.226.2050 www.rtcgroup.com

General Manager - China: Michael Tsui, michaelt@actintl.com.hk Phone 86.755.2598.8571.3 Fax 86.755.2598.8567

hong kong head office Publisher Director: Adonis Mak, adonism@actintl.com.hk

For reprints contact: Marina Tringali, marinat@rtcgroup.com. Published by the RTC Group. Copyright 2007, the RTC Group. Printed in the United States. All rights reserved. All related graphics are trademarks of the RTC Group. All other brand and product names are the property of their holders. Periodicals postage at San Clemente, CA 92673. Postmaster: send changes of address to: Portable Design, 905 Calle Amanecer, Suite 250, San Clemente, CA 92673. Portable Design(ISSN 1086-1300) is published monthly by RTC Group 905 Calle Amanecer, Suite 250, San Clemente, CA 92673. Telephone 949-226-2000; 949226-2050; Web Address www.rtcgroup.com. embeddedcommad_14v.indd 1 PORTABLE DESIGN

11/13/06 5:55:59 PM

Intersil Battery Authentication High Performance Analog

We’re On It.

Intersil’s ISL9206 FlexiHash+TM Engine delivers high-security battery authentication at a low cost. Intersil’s ISL9206 is an easy-to-use, robust, and inexpensive battery authentication solution for 1-cell Li-Ion/Li-Polymer or 3-cell NiMH series battery packs.

64-bit Secret 32-bit Hash Function 32-bit Hash Function

32-bit pseudo-random challenge word from host FlexiHash+ Engine

8-bit authentication code

ISL9206 Key Features: Challenge/response-based authentication scheme using 32-bit challenge code and 8-bit authentication code.

Oscillator

1-Wire Comm Interface

FlexiHash+ engine uses two sets of 32-bit secrets for authentication code generation.

16x8 OTP ROM

FlexiHash+ Engine

POR/2.5V Regulator

Control Register

16x8 one-time programmable ROM memory. Additional programmable memory for storage.

Go to www.intersil.com for samples, datasheets and support

Intersil – Switching Regulators for precise power delivery. ©2007 Intersil Americas Inc. All rights reserved. The following are trademarks or services marks owned by Intersil Corporation or one of its subsidiaries, and may be registered in the USA and/or other countries: Intersil (and design) and i (and design).

Patent pending FlexiHash+ engine consists of four separate programmable CRC calculators. Two sets of 32-bit secret codes are used for authentication code generation. XSD single-wire host bus interface communicates with all 8250-compatible UARTs or a single GPIO pin. Supports CRC on read data and transfer bit-rate up to 23Kbps. 16 bytes of one-time programmable ROM memory for storage of pack information and ID, device authentication secrets, device default settings, and factory-programmed trim parameters.

editorial letter

The number one problem facing Portable Design readers—or at least the most chronic—is adding functionality to a design while being under pressure to reduce power consumption at the same time. This is one area where it’s hard to have your cake and eat it, too. While stories of the death of Moore’s Law, in Mark Twain’s words, are greatly exaggerated, it is starting to run head on into some intractable laws of physics that are making lowpower designs increasingly difficult. The march from low power to ultra-low power is likely to involve some broken-field running. On the system level, new ESL tools (see this month’s cover story) have made it far easier to assess the impacts on power, performance and area that result from architectural decisions. These decisions have far more impact on the final power budget for a design than you can exercise after you’ve gone to RTL. On the chip level designers have a lot more tools in their toolkit than ever before. Dynamic frequency and adaptive voltage scaling are now

How Low Can You Go? john donovan, editor-in-chief

common, as are voltage islands that have their own power management systems associated with them, using ARM’s Advanced Power Controller (APC) and National’s PowerWise technologies, for example. Sections of chips can be shut off when not in use, with contexts being saved to onchip flash memory that enables nanosecond turnon times. Still, chip designers may be running low on tricks as line widths scale downward. Power conversion efficiency, for example, for switching regulators is now well over 90%, which doesn’t leave a lot of room for significant improvement. With deep submicron technology, static power becomes increasingly significant. Here the latest trick is threshold scaling, which reduces leakage by offsetting the N- and P- well bulk biases so that transistors are more effectively driven “off.” But there isn’t much room to play with the basic physics of CMOS transistors. When the junction doping of a 45 nm junction is off by a few atoms, it can cause a junction failure—which is why Design for Manufacturing (DFM) has become so critical, not to mention tricky. That’s were nanoelectronics comes in, offer

PORTABLE DESIGN

ing a way forward. New nanoscale technologies are moving from lab to fab, including silicon nanocrystals, carbon nanotubes, polymer and holographic memories. These have already been commercialized as FRAM, MRAM and Ovonic memories—but the most interesting applications are yet to come. Carbon nanotubes a few nanometers wide may replace the wiring in ICs, even building self-assembling structures. Freescale has demonstrated silicon nanocrystals as a replacement for on-chip flash at a fraction of the power consumption and a multiple of the speed. Zettacore has demonstrated multi-porphyrin nanostructures that use individual molecules for data storage. Can it get much lower power than that? We’ll go into that in more detail in next month’s cover story on nanoelectronics. While a lot of work has gone into power conservation and energy management, a new approach called “energy harvesting” is starting to emerge. At the recent NanoPower Forum, a wide range of approaches was presented for converting mechanical, thermal, RF and chemical energy into electricity to power ultra-low-power devices. Thermoelectric junctions cannot only deal with heat dissipation problems, they can also generate sufficient energy to enable self-powered wireless sensors, for example on the fuselage of a plane or a boiler in a factory. Piezoelectric transducers work well for vibration and motion sensing, generating enough power to power a small wireless sensor; these might be attached to motors to monitor bearing wear or to a floor plank for intrusion detection. And flexible solar panels that might be used to house ultra-low-power devices should come as no surprise to anyone. Many energy harvesting devices are targeted not at your MP3 player but at low-power wireless sensor networks, an area that has been receiving a lot of attention of late. Zigbee, of course, was designed for ad hoc wireless mesh networks. The duty cycle of the chips is very low, often transmitting only a few milliseconds every second; and transmitting power can be kept low—a few microwatts—since each node in the network acts as a relay for nearby nodes. Also on the ultra-low-power wireless front, the Bluetooth Special Interest Group (SIG)—of which Zigbee was a low-power spin-off—recently agreed with Nokia to make the Wibree specification part of the Bluetooth specification as an ultralow-power Bluetooth technology for ultra-lowpower, low-data rate wireless human-interface devices (HID) such as wireless keyboards and mice—a very different market from Zigbee. So how low-power can you go in portable designs? Well, there are some serious barriers out there but also some seriously smart engineers. Stay tuned.

Intersil Handheld Products High Performance Analog

We’re Hip to Handheld.

Improve your performance in portable media players with Intersil’s high-performance analog ICs.

Analog Mixed Signal: Amplifiers DCPs Light Sensors Real-Time Clocks RS-232 Interface Sub Ohm Analog Switches Switches/MUXes Video Drivers Voltage References

Go to www.intersil.com for samples, datasheets and support

Intersil – An industry leader in Switching Regulators and Amplifiers. ©2007 Intersil Americas Inc. All rights reserved. The following are trademarks or services marks owned by Intersil Corporation or one of its subsidiaries, and may be registered in the USA and/or other countries: Intersil (and design) and i (and design).

Power Management: Backlight Drivers Battery Authentication Battery Chargers Fuel Gauges Integrated FET Regulators LCD Display Power LDOs Memory Power Management Overvoltage and Overcurrent Protection Voltage Monitors

dave’s two cents

I usually arrive at work at what many, including my wife, consider a ridiculous time of day—around 5 a.m. During my commute, I get to listen to the news of the day. Last month, one of the news promotional announcements was, “Cell phones fight terror.” The actual story was broadcast about 30 minutes later, so I had time to wonder about what I would hear. Would cell phones have weapons installed like TASERs or pepper spray? I guess “fight” makes me think of weapons. The story was eventually broadcast and I was a little surprised at the “terror-fighting” cell phones. The Department of Homeland Security is considering a program called “Cell-All.” This would allow cell phones to autonomously report detection and location of threats from various radiological, chemical and biological agents. They could be outfitted with detectors for sensing the agents. The cell phone would then use its internal GPS to determine the location, and then

dave’s two cents on ...

Is Your Cell Phone Your Big Brother?

call in the threat. Many of today’s cell phones have built-in GPS receivers to meet the E911 requirements. In 1996, the Federal Communication Commission (FCC) started hearings on wireless 911 initiatives. The goal is that the telephone number and location of the caller would be provided to a Public Service Answering Point (PSAP). The cell phone location would be accurate to within 50 to 300 meters. I used to buy wristwatches based on how many other things they could do, in addition to giving the time and date. So having a cell phone that could detect hazards would be a good thing. I think I would extend this to other reporting that might be simpler. For example, weather information would be nice. The cell phone could report barometric pressure at the current location, as well as temperature. The density of lightening strikes could also be detected and reported along with location. I would probably get a new phone more often than the current three or more year schedule that I am currently on, if it had these types of technical features, although I am not sure the rest of the public would be that motivated.

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There are issues with determining locations based on GPS indoors, but these challenges could be worked around. The phone could always be fitted to remember just the last rational position that it sensed. The location could also be reconciled by base station ID. By combining GPS with other information, the location could be determined within a useful range. However, there may be those who would not want their location known. Including GPS in a cell phone has also opened up new business opportunities. For example, monitoring the location of a child carrying a cell phone is a service that is currently being offered on some cellular systems. I am not sure, though, that the child would always want this level of parental monitoring. There are also business services that deem cell phone tracking as mobile resource management. There is even a social aspect to the business where a person can list a group of friends who can locate them through their GPS-enabled phone. In this case, you would not even have to know where you are or how you got there, but your friends could find you. The privacy advocates certainly are not in favor of any involuntary location determination such as might be the case in Cell-All. There are also concerns that there may be some level of self-incrimination due to the association of your phone as your person and the expectation of privacy. These concerns need to be addressed even though the public safety aspects are surely important. Indeed a voluntary election to be part of hazard grid detection would be good as well. The combination of cell phone with mobile sensing is very intriguing. Adding still and video cameras has definitely expanded the use of the cell phone. Entertainment and games have given us a cellular-based pacifier. In the effort to solve the location problem for 911 responses, location determination features were added to our cell phones. When more than half of 911 calls now come from cell phones, the location problem deserves to be solved. It is unlikely that only one solution like GPS or terrestrial triangulation solves the problem for all cases, but the combination comes close. For my two cents, I would definitely enable my cellular GPS for public service use. I guess I am not that concerned about the Paparazzi using my cell phone GPS to find out which high-end shopping mall I frequent. I am also not that concerned if anyone finds out exactly where I am stuck in traffic, but telling someone the air quality at that location just might help others. Dave Freeman, Texas Instruments

Cool & Compact 2A Charging Efficiency vs Battery Voltage 100

SENSE

PVIN

BAT

PGND

LTC4001

NTC

LTC4001

4.2V Li-Ion/ Polymer

Efficiency (%)

5V VIN

Higher Efficiency = Less Heat

80 70

Linear Charger VIN = 5V ICHARGE = 1A

EN PROG

TIMER

GNDSENS

3.2

3.4

3.6

3.8

4.2

VBAT (V) 9mm 14mm Actual Size Demo Circuit

Less Heat & Higher Current than Linear Chargers Is too much heat from your high current linear regulator-based battery charger killing your system? If so, try our new LTC ®4001, a monolithic synchronous switching step-down Li-Ion/Polymer charger, capable of delivering 2A of charge current with over 90% efficiency. The highly integrated LTC4001 includes on-chip MOSFETs and current sense resistor. With its 4mm x 4mm QFN package and 1.5MHz switching frequency operation, only five external components are needed for a simple, compact and cost-effective solution.

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news High Sensitivity Image Sensor

Kodak has developed a new approach for determining color information on image sensors that it claims provides a 2x to 4x improvement (from one to two photographic stops) in the sensitivity of the sensor compared to current designs, which will improve performance when taking pictures under low light and reduce motion blur when imaging moving subjects. In addition, this technology enables the design of smaller pixels (leading to higher resolutions in a given optical format) while retaining imaging performance. Today, the design of almost all color image sensors is based on the “Bayer Pattern,” an arrangement of red, green and blue pixels that was nd first developed by Kodak Scientist Dr. Bryce Bayer in 1976. In this design, er exploration ether your goal half of the pixels on the sensor are speak directly used to collect green light, with the ical page, the ght resource. remaining pixels split evenly between technology, sensitivity to red and blue light. After es and products exposure, software reconstructs a full ed color signal for each pixel in the final image. Kodak’s new proprietary technology builds on the existing Bayer Pattern by adding panchromatic, or “clear” pixels to the red, green and companies providing solutions now pixels already on the sensor. exploration into products, technologies and companies. Whether your goal is to research the latest blue datasheet from a company, mp to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever Since these pixelslevel areofsensitive to all gy, Get Connected will help you connect with the companies and products you are searching for. wavelengths of visible light, they colonnected lect a significantly higher proportion of the light striking the sensor. The remaining red, green and blue pixels are then used to record the color information of the scene. Initially, Kodak expects to develop CMOS sensors using this new technology for consumer applications such as digital still cameras and camera phones. Since the technology is appropriate for use with both CCD and CMOS image sensors, however, its use can be expanded across Kodak’s full portfolio of image sensors, includGet Connected with companies mentioned in this article. ing products targeted to applied imaging marwww.portabledesign.com/getconnected kets such as industrial and scientific imaging.

End of Article

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The first Kodak sensor to use this technology is expected to be available for sampling in the first quarter of 2008. Eastman Kodak Company, Rochester, NY. (585) 477-1470. [www.kodak.com].

Chartered, Tezzaron Team Up to Deliver Ultra High-Speed Memory Solution

Chartered Semiconductor Manufacturing and Tezzaron Semiconductor have announced that Chartered is beginning to ramp production of Tezzaron’s unique ultra high-speed memory chips. In addition, the two companies are working on the manufacture of Tezzaron’s 3D devices and hope to see them become the first 3D ICs to be manufactured in volume. The promise of 3D ICs is the potential to improve performance, density and error resistance capabilities over traditional two-dimensional methods. With Tezzaron’s FaStack technology, device circuitry is divided into sections that are built onto separate wafers using standard processing. Chartered enables 3D stacking of these wafers by building hundreds of thousands of Tezzaron’s embedded thru-silicon interconnections, called SuperContacts, into the circuitry on each wafer. The wafers are then aligned with a precision of 0.5-micron, bonded, thinned, and diced into individual devices. Unlike many 3D solutions that connect only at the I/O pads, a FaStack chip functions as a single device due to its abundant internal Super-Contacts. The first products manufactured at Chartered using this approach will be the proven 72 Mb memory device, currently in production, which will be double stacked to create a 144 Mb SRAM replacement product. The increased density of this product will allow system developers to use fewer components, create simpler designs, reduce cost and power requirements, make testing easier, and still keep pace with the ever-accelerating demand for more computer memory. Tezzaron plans to offer many types of 3D IC memories in

june 2007

two, three and even five layers, using their NanoTSV (nanoscale thru-silicon via) technology to enable ultra-high capacity devices and chips with built-in repair capabilities. Chartered Semiconductor Manufacturing, Milpitas, CA. (408) 941-1100. [www.charteredsemi.com]. Tezzaron Semiconductor, Naperville, IL. (630) 505-0404. [www.tezzaron.com].

New Chip Material Addresses Power Leakage, Scaling for 45-nm and Beyond

Texas Instruments has announced plans to integrate a “high-k” value material within the transistors in its most advanced, high performance 45-nanometer (nm) chip products. For years, high-k dielectrics have been under consideration to address leakage, or power drain, which has become increasingly problematic as transistor dimensions continue to shrink. Through its approach, TI claims it can reduce leakage by more than 30 times per unit area as

while reducing power consumption by 40 percent. TI plans to sample a 45-nm wireless product in 2007, with qualified production starting by the middle of 2008. High-k dielectrics will be added in later versions of the 45-nm process for TI’s highest performance products. TI will leverage a chemical vapor deposition (CVD) process to deposit Hafnium Silicon Oxide (HfSiO) followed by reaction with a downstream nitrogen plasma to form HfSiON. While the benefits of Hafnium-based dielectrics have been widely recognized for the impact on leakage, implementation has previously presented several hurdles. Issues include electrical compatibility with standard CMOS processes, as well as challenges in matching the carrier mobility and threshold voltage stability that SiO2-based gate dielectrics have previously delivered. However, by implementing the nitrided CVD technique, TI is able to solve the leakage issue without degradation of the other key parameters that customers have come to expect from SiO2-based gate dielectrics. TI’s approach reduces leakage significantly over any of the SiO2-based material options. Texas Instruments Inc., Dallas, TX. (800) 336-5236. [www.ti.com].

compared with commonly used silicon oxide (SiO2) gate dielectrics. In addition, TI’s high-k choice offers the compatibility, reliability and scalability to continue delivery of high-volume, high-performance and low-power semiconductor solutions through the 45-nm and 32-nm process nodes. Last June, TI unveiled details of its 45nm process that will double output per wafer through use of 193-nm immersion lithography. Through a number of techniques TI also expects to achieve a 30 percent increase in performance of its SoC processors,

Bluespec, Eve Create Platform for ESL Verification, Modeling, Architectural Design

Bluespec Inc. and EVE today announced immediate availability of an integrated solution of electronic system level (ESL) synthesizeable transactors and models that run directly on EVE’s hardware-assisted verification platforms. The link between Bluespec’s ESL synthesis and EVE’s ZeBu hardware-assisted verification platform of accelerators, emulators and field programmable gate array (FPGA) prototypes offers high simulation speed with hardware accuracy early in the development cycle for architectural exploration, virtual prototyp-

ing, modeling and verification. The result is a single development environment for models, transactors, implementations and synthesizable verification testbenches, and a rich foundation library of IP. Typically, the trade-off between simulation speed and hardware accuracy hinges on the availability of a register transfer level (RTL) model that is usually available late in the development cycle. Additionally, RTL simulation speed is slow, except when emulation, hardware acceleration or FPGA prototyping is used, but these are only effective with mature, relatively bug-free RTL code. High-level functional models may be relatively fast, but typically aren’t hardware accurate. Normally, transactors, models and implementations are handled by three separate environments. Transactors and models are usually not synthesizable. Models running on emulation, hardware acceleration or prototyping platforms require RTL implementations and require mature, relatively bug-free RTL code to be effective. Bluespec, Inc., Waltham, MA. (781) 250-2200. [www.bluespec.com]. EVE, San Jose, CA. (408) 881-0440. [www.eve-team.com].

Image Sensor Market Passes $6 Billion but Market Shares Are Shifting

The image sensor market reached $6 billion in 2006, a jump of over 30% over 2005, with sales expected to grow another 14% in 2007, according to a new market report from Strategies Unlimited. The market will gradually slow in the next several years, but the year-over-year growth will still provide large opportunities and challenges as the leading players jockey for position. While the overall market is becoming more predictable, camera phones and digital cameras continue to exceed expectations. Strong growth is also expected in security cameras and in digital radiography. Automotive appliJUNE 2007

news cations are moving slowly but steadily into production, but the segment remains small for now. The top five suppliers continue to hold about 2/3 of the total market share, but membership in the top five has changed. Sony and Micron are nearing $1 billion each in annual revenues. Overall, there are about 50 suppliers, about twice the number in 1997, but unchanged in the last few years. That is, for every Atmel or ESS Technology that sells or closes its image sensor business, there is a Planet82 or a ProMOS Technologies that enters. CMOS image sensors now dominate both unit and revenue share, mostly owing to the continued rise of the camera phone market. Micron has shot to the top position in CMOS arrays, with other semiconductor manufacturers such as ST and Samsung also showing strong gains. While CCDs continue to grow in dollar value, there is some consolidation in the market share, with the possibility that Sanyo Electric will exit the business.

er exploration ether your goal speak directly ical page, the ght resource. technology, es and products

Strategies Unlimited, Mountain View, CA. (650) 941-3438. [www.strategies-u.com].

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Mobile Handsets Positioned to Radically Change the Navigation Device Market

Mobile phone from operators now have the abilexploration into products, technologies and companies. Whether your goal is to research the latest datasheet a company, mp to a company's technical page, the goal of Get Connected is to put you in touchity withtothemarket right resource. Whichever level ofnavigation apa downloadable gy, Get Connected will help you connect with the companies and products you areplication searching for. that is just as good as, if not better

onnected

End of Article Get Connected

with companies mentioned in this article. www.portabledesign.com/getconnected

than, personal navigation devices (PNDs), reports In-Stat. As a result, handset-based mapping and navigation applications could cause a major change in the overall navigation market, which is now dominated by relatively expensive stand-alone devices, the high-tech market research firm says. Recent research by In-Stat found the following: • C ellular operators whose service is based on CDMA (and iDEN) have an advantage over other mobile operators in nearly every region of the world, largely because of the A-GPS technol-

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ogy originally driven by mandates to support E911 services. • In-Stat surveys of U.S. subscribers find navigation applications have a strong ability to draw subscribers from other operators and keep them loyal. • The total number of mapping and navigation mobile phone subscribers could exceed 42 million worldwide by 2012. In-Stat, Scottsdale, AZ. (480) 483-4440. [www.in-stat.com].

Energy Harvesting Competitive Analysis Released

Most of the companies getting a jump on “the next big thing” in power management are not well-known in the power supply industry. Many are start-up companies, and many are based in Europe. With potential unit sales in the billions, however, these companies have targeted the low-power sensor and device market. Many of the energy harvesting companies have found it useful to partner with IC companies. IDS Microchip has a near-field communications solution they did for Texas Instruments, for example. EnOcean is working with the Fraunhofer Institute. Perpetuum is working with Dust Networks. Many of these companies are members of the ZigBee Alliance, as well. The IEEE 902.15.4 standard ensures that ZigBee will co-exist with competing standards such as Z-Wave, Insteon, LonTalk and others. The most established companies offering wireless sensor network and energy harvesting solutions are the power management IC companies. Texas Instruments, Nordic Semiconductor, STMicroelectronics—these manufacturers and more have a variety of products targeted at ultra-low-power applications. Some, like Advanced Linear Devices, have specific modules for energy harvesting. These products are expected to help drive down costs, since high volumes are necessary to achieve market penetration. Radiocrafts, for instance, is “aiming for

june 2007

Darnell Group Inc., Corona, CA. (951) 279-6684. [www.darnell.com].

China’s Chip Market to Rise 20 Percent in 2007

Despite uncertainties regarding the technology sector and the overall economy, China’s semiconductor market growth is expected to accelerate in 2007, according to iSuppli Corp, who predict that semiconductor shipments in China will rise to $51.7 billion in 2007, up 20 percent from $43 billion in 2006. This compares to 15 percent revenue growth in 2006. While such accelerated growth may seem to be positive, there are some concerns that the Chinese technology industry and the overall economy are entering a stage of unsustainable hyper-expansion that could generate a market bubble. However, iSuppli doesn’t considers these factors to represent a major risk for the semiconductor industry, where growth has actually decelerated compared to a few years ago. After expanding by 39.8 percent in 2004, China’s semiconductor industry has settled into a more sustainable average growth rate ranging from 10 to 20 percent. This year will represent the cyclical peak for China’s market, with growth expected to cool in the coming years. Hot segments of China’s electronics market include flat-panel televisions, digital set-top boxes, 3G mobile phones and so-called Digital Multimedia Platforms (DMPs). DMPs are converged personal multimedia products that combine functionality found in varying products including Personal Media Players (PMPs) and mobile televisions, PMPs and global positioning systems, and Digital Still Cameras (DSCs) and digital camcorders. iSuppli Corporation, El Segundo, CA. (310) 524-4000. [www.isuppli.com].

China’s Annual Semiconductor Revenue Growth Forecast Millions of U.S. Dollars

high-volume manufacturing.” Most companies see commercial adoption of ZigBee products and related energy harvesting solutions in two to three years.

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Sidense Qualifies 1T-Fuse in UMC’s 130-nm Process

Sidense announced that it has qualified its logic non-volatile memory (NVM) intellectual property (IP) in UMC’s 130-nm standard logic CMOS process. By qualifying the NVM IP, a valuable memory addition to the foundry’s IP Alliance Program, UMC’s customers now have access to a low-cost, highly secure embedded NVM for applications such as electrical fuse replacement, flash and mask-programmable ROM replacement, code storage, RFID, unique ID, encryption, key storage, HDMI and digital rights management (DRM). Sidense’s 1T-Fuse Logic NVM IP is based on a one-time programmable (OTP) technology that is one of the smallest and fastest in the industry. It requires no additional mask layers or process steps and is portable across several different technology nodes and foundries. Furthermore, the OTP can be programmed in the field, during wafer or production testing. Sidense’s products are targeted to standard logic digital CMOS processes that are 180 nm, 130 nm, 90 nm, 65 nm and smaller at several well-known foundries. Ideal applications include electrical fuse replacement, flash and mask-programmable ROM replacement, code storage, RFID, unique ID, encryption, key storage, HDMI and digital rights management (DRM). Sidense Corp., Ottawa, Ontario Canada. (613) 287-0292. [www.sidense.com].

JUNE 2007

High-Performance Energy-Efcient Processors for Embedded Market Segments Intel® Core™ Microarchitecture-based Processors for Embedded Designs Balancing embedded design challenges is complex. That’s why Intel now offers a variety of Intel® Core™ microarchitecture-based dual-core processors for a broad range of demanding, low-power embedded applications, including: • Medical Imaging, Communication servers, and Storage subsystems • Interactive Clients (ATMs, point-of-sale devices, gaming); Industrial Control and Automation Systems; and Military, Aerospace, and Government • Infotainment, Print Imaging, Ruggedized Mobile Devices and Tablet PCs Our new Intel Core microarchitecture-based processors deliver high efciency and value, so you can deliver more advanced products to your customers. And, as part of our embedded program, we provide 5 to 7 year life-cycle support for both processors and chipsets to help ensure longevity and stability for your designs and bolster your customers’ assurance in your products.

Intel Core microarchitecture enables new levels of performance and power efciency through a combination of unique processor technology advancements only from Intel.

Choices in Performance, Efciency, and Value Intel’s new embedded processors, all produced on our 65 nm advanced process technology, let you match performance, efciency, and value to your embedded design targets. • Best Performance+: Dual-Core Intel® Xeon® processors (5140,¨ 5130¨ and LV 5148¨) for compute- and I/O-intensive designs. • Best Energy Efciency+: Intel® Core™2 Duo processor T7400¨ for high-performance, low-power applications. • Best Value Performance+: Intel® Core™2 Duo processor E6400¨ for optimal price-performance.

Intel Core microarchitecture enables new levels of performance and power efciency through a combination of unique processor technology advancements only from Intel, enabling you to integrate more capabilities into more power-efcient designs. • Intel® Wide Dynamic Execution: Execution pipelines are 33 percent wider in each core than previous generations, allowing each core to simultaneously fetch, dispatch, execute, and retire up to four instructions. • Intel® Advanced Smart Cache: A multi-core optimized cache that signicantly reduces latency to frequently used data, thus improving performance and efciency by increasing the probability that each execution core of a multi-core processor can access data from a higher-performance, more efcient cache subsystem. • Intel® Smart Memory Access: Improves system performance by optimizing the use of the available data bandwidth from the memory subsystem and hiding the latency of memory accesses. • Intel® Advanced Digital Media Boost: Enables 128-bit Streaming SIMD Extension (SSE/SSE2/SSE3) instructions to be completely executed at a throughput rate of one per clock cycle, effectively doubling, on a per clock basis, the speed of execution for these instructions as compared to previous generations. • Intel® Intelligent Power Capability: Better power-control efciency with micro-gating of processor circuitry, which de-energizes inactive portions of the processor with ner granularity than other processors. + Relative to the three Intel Core microarchitecture products presented in this brochure.

Industry-Leading Embedded Processors In performance/watt, Intel Core microarchitecture-based processors for embedded designs beat competitive offerings, enabling more compute density for demanding applications and higher efciency for long life designs. As shown below, Intel offers better value as measured by performance/watt/dollar. Dual-Core Intel® Xeon® processor LV 5148 Our most powerful embedded processor, the Dual-Core Intel Xeon processor LV 5148,¨ offers outstanding scalability and headroom for added functional density in demanding dual-processor embedded applications. 1.9x better

4.5x better

• •

AMD Opteron* 275 HE2 2.20 GHz, 2 MB cache, 90 nm process, 55 watts, MSRP $10513

Dual-Core Intel® Xeon® processor LV 51484 2.33 GHz, 4 MB cache, 65 nm process, 40 watts, MSRP $504

Efciency1 Perf/watt

“The combination of two Dual-Core Intel® Xeon® processors 5140 with the Intel 5000X chipset in our latest RMS4205000XI Server provides roughly 100% performance improvement over a similar server... for certain imaging applications and also provides PCI-Express x16 connectivity to support high end graphics cards. – Wade Clowes, General Manager, Commercial Segment, RadiSys

Value

Efciency/$

Intel® Core™2 Duo processor T7400 The ultimate in low power and high performance, the Intel Core 2 Duo processor T7400¨ optimally balances energy efciency and performance for your thermally constrained applications. 6.6x better

3.9x better 3.20

• •

1.31 0.82

Single-Core Freescale MPC7447A5 1.42 GHz, 512 KB cache, 130 nm process, 30 watts, MSRP $2456

Intel® Core™2 Duo processor T74007 2.16 GHz, 4 MB cache, 65 nm process, 34 watts, MSRP $411

0.20

Efciency1 Perf/watt

Value

“Intel’s continued innovation in multi-core processors delivers the increased performance and capabilities needed by our customers for distributed real time systems. With the new Core 2 Duo processor platform, Intel has taken another step forward in delivering high performance... that are critical to the digital factory.” – Dr. James Truchard, National Instruments president, cofounder and CEO

Efciency/$

Intel® Core™2 Duo processor E6400 Combining dual-core performance with low cost, the Intel Core 2 Duo processor E6400¨ enables enhanced capabilities in embedded designs without a price penalty. 2.2x better

6.4x better 3.00

0.68 0.30

Efciency1 Perf/watt

• •

0.47

Value

Efciency/$

AMD Athlon* 64 X2 Dual Core 4800+8 2.4 GHz, 2x 1 MB cache, 90 nm process, 110 watts, MSRP $6459

Intel® Core™2 Duo processor E640010 2.13 GHz, 2 MB cache, 65 nm process, 65 watts, MSRP $224

“...The increased performance and lower power consumption delivered by the Intel® Core™2 Duo processor E6400... ideal for these markets.” – Hannes Niederhauser, CEO of Kontron

Value beyond “the Numbers” Intel Core microarchitecture-based processors deliver the best performance and overall efciency of today’s embedded processor offerings. But there’s still more to think about when making the right choice. Consider: • Intel delivers long life-cycle support for both the processor and chipset together, making it the only company that ensures you can continue to support your products with the most advanced platform foundation available. • Intel advanced platform technologies are specically designed into our processors and chipsets to enable you to integrate more capabilities, such as virtualization and manageability, while conserving power. • Intel’s global capacity capabilities provide the agility required to serve your manufacturing demands. • Intel’s world-leading 65 nm process technology enables greater energy efciency and more cores for higher performance, resulting in fewer cooling challenges and greater functional density for all design footprints. • The Intel® Communications Alliance, a community of embedded developers using technologies, processors, products, and services from Intel help you balance price and performance today, with the headroom and scalability for next-generation solutions tomorrow. The Alliance platform solutions approach combines a multi-core architecture with complementary technologies to deliver scalable, power-efcient processing for a wide range of applications. Visit www.intel.com/go/ica to learn more. With high performance, energy-efcient processors available for embedded designs, broad design support, and global manufacturing capacity, Intel embedded processors are your best choice for your next-generation, emerging applications. For more information about Intel’s embedded products, please visit www.intel.com/go/embedded.

Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/ processor_number for details. “Efciency” measured as a simple ratio of SPECint_rate_base2000 performance ÷ Watts consumed by the processor. Products selected for benchmarking against Intel’s were determined based on competing comparable embedded products which had published test results. 2 AMD - SPECint*_rate_base2000 (4 copies) for AMD Opteron* 275 HE (2.2 GHz & 2MB L2) based on published results (December 2005) on PRIMERGY RX220 with 16GB DDR1 using Windows* Server 2003 Enterprise + SP1, Intel C++ Compiler 8.0 Build 20040318Z, Microsoft* Visual Studio* .NET 7.1.3088 (for libraries), MicroQuill SmartHeap Library Version 8.0 http://www.spec.org/osg/cpu2000/results/res2006q1/cpu2000-20051223-05318.html. AMD performance score = 64.3. 3 AMD Opteron* 275 HE conguration and pricing from www.amdcompare.com/us-en/opteron/details.aspx?opn=OSK275FAA6CB and www.amd.com/pricing. 4 Intel - SPECint*_rate_base2000 (4 copies) for Two 2.33 GHz Dual-Core Intel® Xeon® processors 5140 (2.33GHz & 4 MB L2) with Intel® 5000X chipset, 1333 MHz FSB based on published results (May 2006) on Dell PowerEdge* 1950 with 8 x 1GB 667MHz ECC CL5 DDR2 FB-DIMM. Software: Microsoft Windows Server 2003 Enterprise x64 Edition + SP1 (64-bit), Intel C++ Compiler 9.1 for IA32(20060323Z), Microsoft Visual Studio .NET 2003(7.1.3088), MicroQuill SmartHeap Library 8.0 http://www.spec.org/osg/cpu2000/results/res2006q3/cpu2000-20060626-06254.html. Intel performance score = 101. 5 SPECint*_rate_base2000 for Freescale’s MPC7447A* from Apple’s website using a shipped version and PowerPC* optimized compiler from IBM: http://www.apple.com/macmini/. Freescale performance score = 6. 6 Freescale’s “MPC7447A* RISC Microprocessor conguration and pricing from “MPC7447A* RISC Microprocessor Hardware Specications” http://www.freescale.com/les/32bit/doc/data_sheet/MPC7447AEC.pdf and press release 7 SPECint*_rate_base2000 (2 copies) for Intel® Core™2 Duo processor T7400 (L2 Cache 4096KB & 2.167 GHz) performed on Cappel Valley Reference Platform with Mobile Intel® 945GM Express chipset, 667MHz FSB, and 512MB DDR2 SO-DIMM in July, 2006. Software: Linux RedHat 9.0, Kernel 2.4.20-SMP, Intel Compiler 9.0, SPEC CPU2000.1.2. Intel performance score = 44.7. 8 SPECint*_rate_base2000 (2 copies) for AMD Athlon* 64 X2 Dual Core 4800+ (939-pin, 2.2 GHz, & 2 x 1MB L2) based on published results (February 2006) on Gamer’s Edge DualX with 2x512MB, Mushkin DDR400 CL2 using Microsoft* Windows* XP Home Edition SP2, Intel® C++ 9.0 build 20050912Z for IA32, Microsoft* Visual Studio* .NET 7.0.9466 (libraries) MicroQuill Smartheap Library 7.0: http://www.spec.org/osg/cpu2000/results/ res2006q1/cpu2000-20060209-05550.html. AMD performance score = 33.4. 9 AMD Athlon* 64 X2 Dual Core 4800+ conguration and pricing from www.amdcompare.com/us-en/desktop/details.aspx?opn=ADA4800DAA6CD and www.amd.com/us-en/Corporate/VirtualPressRoom/0,,51_104_609,00. html. 10 SPECint*_rate_base2000 (2 copies) for Intel® Core™2 Duo processor E6400 (2.13 GHz & 2 MB L2) based on published results (June 2006) on Precision Workstation 390 with 4x 1024MB 533MHz non-ECC CL4 DDR2 SDRAM using Windows XP Professional SP2, Intel C++ Compiler 9.1 for IA32(20060519Z) Microsoft Visual Studio .NET 2003(7.1.3088) MicroQuill SmartHeap Library 8.0: http://www.spec.org/osg/cpu2000/results/ res2006q3/cpu2000-20060705-06411.html. Intel performance score = 44. Performance tests and ratings are measured using specic computer systems and/or components and reect the approximate performance of Intel® products as measured by those tests. Any difference in system hardware or software design or conguration may affect actual performance. Buyers should consult other sources of information to evaluate the performance of systems or components they are considering purchasing. For more information on performance tests and on the performance of Intel products, reference http://www.intel.com/performance/resources/limits.htm or call (U.S.) 1-800-628-8686 or 1-916-356-3104. Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to tness for a particular purpose, merchantability or infringement of any patent, copyright, or other intellectual property right. Intel products are not intended for use in medical, life-saving or life-sustaining applications. Intel may make changes to specications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undened.” Intel reserves these for future denition and shall have no responsibility whatsoever for conicts or incompatibilities arising from future changes to them. *Other brands and names may be claimed as the property of others. Copyright © 2006 Intel Corporation. All rights reserved. Intel, the Intel logo, Intel. Leap ahead., Intel. Leap ahead. logo, Intel Core, and Xeon are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. Printed in USA 0906/KAK/OCG/PP/2K Please Recycle 315336-001US ¨

cover feature ESL tools

ESL Tools Come of Age Full ESL-to-GDSII automation isn’t here yet, but the tool flow is getting a lot more robust.

by John Donovan, Editor-in-Chief

Even though the phrase “electronic systemlevel design” (ESL) is only a few years old, the promise of being able to do high-level design, push a button and output both the system software and a gate-level netlist has been the siren song of designers for at least a decade. We’re definitely not there yet, but we’re closer than you may realize. Every year at the Design Automation Conference (DAC) there’s another ESL panel that sounds a lot like the one from the previous year. This year things were different. All the panelists agreed that (1) available ESL tools have gotten quite capable and robust, even if the overall flow isn’t smooth; and (2) companies doing complex designs—at both the chip and board level—have reached a pain point where moving their design methodologies over to ESL is no longer optional. Last July Portable Design did a cover story on Electronic System-Level Tools for

PORTABLE DESIGN

Portable Design. The consensus then was that ESL held a lot of promise but there were a lot of holes in the tool flow. For this story we asked some of the same ESL gurus how much things have progressed in the intervening year and how the tools are shaping up. What is the current state of ESL, and what are the main impediments holding it back? Long story short, there have been some major breakthroughs, though the whole tool flow is yet to be fully automated.

What Is ESL?

First, let’s try again to define ESL. Even though ESL techniques are becoming increasingly commonplace, there still isn’t one clear definition. Many designers think of ESL as a mixture of hardware and software design. Others think of it as something the system architect does that will later have to be handcoded in RTL before it can be usefully imple-

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ÂŠ2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners.

cover feature

Power Gain

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with companies mentioned in this article. www.portabledesign.com/getconnected

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90%

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mented in hardware. An old joke has it that ESL is design at one level above wherever you’re designing now. EDA analyst Gary Smith originated the figure 1 term ESL three years The 80/20 Power Problem: ago, defining it as Major Productivity Drain the “concurrent design of hardware and Architecture System Architecture C/C++/SystemC software.” Smith sees ESL as consisting of SoC Architecture a behavioral level— Iteration not possible so design done prior to RTL Level Block Architecture late in the design cycle hardware/software Synthesis RT Level partitioning; an architectural level—design Gate Level Gate Level done after partitioning; and platform-based Physical Design Layout design, which makes Expensive, timeconsuming iterations extensive reuse of exnd isting IP, usually in the form of RTL. Many er exploration ether your goal designers consider the Power is best addressed at the system level. speak directly task of ESL as endical page, the ght resource. ing at the RTL level, technology, where traditional EDA tools can kick in. To es and products date that has most often been the case, but it no ed longer needs to be. One reason that ESL is hard to define is that it takes many forms. An ESL flow can be topdown, starting with algorithmic exploration. It can be bottom-up, leveraging legacy IP. Or it can be middle-out when called upon to excompanies providing solutions now tensively modifyfrom existing functionality. There exploration into products, technologies and companies. Whether your goal is to research the latest datasheet a company, mp to a company's technical page, the goal of Get Connected is to put you in touchiswith right resource. Whichever levelor of tool flow that no the one language, approach gy, Get Connected will help you connect with the companies and products you areexclusively searching for. defines ESL. And those languages onnected that do serve the ESL market—notably ANSI C/C++, SystemC, and to some extent SystemVerilog—are also competing, evolving and developing more functionality.

The State of Play

Gary Smith, while bullish on tools from some smaller vendors, is frustrated by a perceived lack of support for ESL from the major EDA vendors. “We’re seeing a lot of rewrites of old tools, we’re seeing a lot of integration of tools, we’re seeing design kits—but we still haven’t seen much movement out of the big three with

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the exception of Mentor,” who makes a C/C++ development suite. Actually, Cadence and Synopsis were early converts to—and competitors in—ESL; both made significant contributions to the development of SystemC. Cadence developed its Virtual Component Co-Design (VCC) and Signal Processing Worksystem (SPW) in the late 90s. Synopsis developed System Studio to compete against VCC. However, in recent years neither company has put much effort into ESL. That has now changed. Cadence recently announced a system-to-silicon design solution based on CoWare’s Platform Architect and LISATek system-level design products and the Cadence Incisive functional verification platform. Aside from linking their tools, the two companies are working with SoC design leaders such as ARM to ensure this unified flow is supported by interoperable IP. Ran Avinun, the marketing group director for the Incisive Platform at Cadence, assured Portable Design that Cadence takes ESL quite seriously and is expending considerable energy in that direction, though details outside of the CoWare effort are to follow. For its part, Synopsis acquired Virtio last year. Virtio brought along virtual system prototype (VSP) technology and C/C++ models of microprocessors and peripherals that Synopsis integrated into its Systems Studio for mixed-level modeling. Texas Instruments used Systems Studio to develop its OMAP processors. Shay Benchorin, director of business development solutions group at Synopsis, was the founder of Virtio. He explained to Portable Design that his team’s work on virtual platform technology continues at Synopsis, which is increasingly focused on ESL. “Right now the big problem with ESL is a software issue,” continued Smith. “The software problem is all about multicore chips—we can’t program those things. I checked with my clients going to DATE and the problems they complained about were software, software, software, DFM and power. The three software problems were heterogeneous computing, homogeneous computing and hardware/software

cover feature partitioning. We don’t have the tools for any of those.” What’s the current state of ESL? According to Smith, “It’s growing, though it certainly hasn’t hit the knee of the curve yet. Everyone in the power user community is using it. A lot of it is for verification. On the design side they’re using mostly internal tools, though we’re expecting to see some commercial tools come out. It’s pretty solidly accepted now that we just can’t keep going the way we’ve been going. All of the customers are there, and they’re basically asking the EDA community, ‘Where are the tools?’” If the concurrent software infrastructure gets built, and if it doesn’t go open source, Smith projects that the TAM for ESL will rise from $1.7B to $4.2B by 2010. ESL is currently the fastest-growing segment in the EDA space. Actually, commercial ESL tools are more widely available than Smith implies. ARM’s RealView SoC Designer (formerly Axys’ MaxSim) is probably the best-known ESL architectural workbench, followed by CoWare’s Platform Architect (formerly ConvergenSC), CoFluent’s CoFluent Studio, IBM’s RightStart, Poseidon’s Triton Tuner, Summit’s Visual Architect and Panorama (acquired by Mentor) and Synopsys’ System Studio. VaST, Virtio and Virtutech all offer non-SystemC behavioral modeling and simulation tools. Working from SystemVerilog inputs, Silistix’ CHAINworks designs and synthesizes customized on-chip interconnects using selftimed (clock-less) circuits. Part of the problem impeding the wider acceptance of ESL is cultural—hardware and software are separate disciplines with different approaches and concerns. Typically hardware design engineers work in RTL; their responsibility is hardware and their main problem is functional verification. The system architect’s job is to find the most efficient algorithms to do what the specification requires; making sure that the chip is functionally correct isn’t an immediate concern. If one designer is to do both of those jobs, you have to teach the system engineer about hardware and the hardware designer

about the software. That’s a cultural issue in most organizations. The most important thing that design teams are finding is that if you take some time up front you can write a model that’s good enough for verification and runs fast enough to do hardware/software prototyping. It’s still high-level enough to do algorithmic exploration, power management and all the other things that the system architect does.

High-Level Design

There is no lack of tools for doing high-level design. The most popular tool for algorithmic modeling has long been MATLAB, which provides a high-level language and development tools that let designers quickly develop and analyze algorithms and applications; MATLAB then works with Simulink to enable multi-domain simulation and model-based design. MATLAB converts system requirements into an executable specification of the system, which is then used for verification. Once satisfied with their MATLAB models, designers have traditionally used the program to output C/SystemC code that they can then synthesize to RTL to carry their designs forward; the C code is especially useful for embedded software development. In the past year The MathWorks has opened an alternate path, introducing the Simulink HDL Coder, which generates bit-true, cycle-accurate, synthesizable Verilog and VHDL code from Simulink models and Stateflow diagrams for both the datapath and control sections of a design. The HDL code can be used to verify existing HDL code using formal or functional verification tools before being mapped directly onto an FPGA or ASIC. Simulink HDL Coder can work with Link for ModelSim and Link for Cadence Incisive, enabling designers to incorporate existing HDL code and IP blocks into their Simulink models. “The virtual platform tools allow you to model an architecture, but there’s still the problem of mapping an application onto that architecture,” explained Ken Karnofsky, director of signal processing and communications at The MathWorks. “So it really takes JUNE 2007

cover feature

a combination of a behavioral tool and an architectural modeling tool to be able to do that. Right now there’s not a completely automated process for doing that.”

When you’re developing a design using ESL tools, you can always generate an RTL model and use that model to estimate a performance and power envelope, even if you intend to go back later and do further optimizations.

ESL models today are usually developed using C/C++ or SystemC, though SystemVerilog—which Bluespec supports—is making some inroads on the verification side. SystemC has pretty well established itself as the de facto standard for ESL, since it enables designers to ed model hardware—including concurrency—at an early stage. Still, ANSI C/C++ has a strong proponent in Mentor graphics, whose CatapultC competes with Forte’s SystemC offering. For a detailed account of the arguments on either side, please refer to our earlier (July, 2006) companies providing solutions now ESL article. exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, mp to a company's technical page, the goal of Get Connected is to put you in touch with the right Whichever levelaofC/C++ or SysThere areresource. tools that convert gy, Get Connected will help you connect with the companies and products you aretemC searching for. model into RTL. But how do you know onnected that the resulting RTL accurately reflects the C model? That is the issue that Calypto addresses with its System Level Equivalence Checking (SLEC) tools. SLEC SYSTEM proves functional equivalence or locates differences between system-level models written in SystemC / C++ and RTL design descriptions independent of sequential differences. SLEC RTL verifies functionality by comparing a RTL design specification against a “golden” reference design. Some tool manufacturers are beginning to Get Connected with companies mentioned in this article. work together and to address discontinuities www.portabledesign.com/getconnected in the tool flow. For example, a recently an-

er exploration ether your goal speak directly ical page, the ght resource. technology, es and products

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nounced link between Bluespec’s ESL synthesis tools and EVE’s ZeBu hardware-assisted verification platform of accelerators, emulators and field programmable gate array (FPGA) prototypes offers high simulation speed with hardware accuracy early in the development cycle for architectural exploration, virtual prototyping, modeling and verification. The result is a single development environment for models, transactors, implementations and synthesizable verification testbenches based on a foundation library of IP. Design teams can now synthesize complex ESL models at hardware speeds. On the input side you might drive high-level synthesis from MATLAB; from SystemC using the Forte tools; SystemVerilog using the Bluespec tools; or ANSI C/C++ using the Mentor Catapult tools. ESL output is almost invariably RTL.

The ESL-to-RTL Flow

Mitch Dale, director of product marketing for Calypto, questions the quality of available functional synthesis tools to provide useful code that can be integrated with IP from a variety of vendors into a complex system. “Part of the problem is that you need to integrate a lot of disparate IP and it’s in RTL format. And part of the problem is that you have these behavioral synthesis tools out there, but it’s still an immature market. These tools have to output RTL at the back end and come out with good quality results. You can be more productive using these tools, but can you use the results?” Tensilica’s chief scientist Martin makes an important point: “What will come out of the ESL process, if taken all the way to RTL and characterization, represents a worst-case performance and power envelope. You know you can do at least that well using a fully automated flow.” The RTL designer may be able to hand optimize the code and achieve better performance, but in the process you lose the ability to move back up past the RTL level to make architectural changes, at least for that particular function. So the onus remains on the ESL tool vendors to provide the most highly optimized RTL, based on the tradeoffs that they make at the system level.

figure 2

EDA - ESL & SDA WALLCHART 2007 SYSTEM DESIGN AUTOMATION ELECTRONIC SYSTEM LEVEL EDAptive

ESL VERIFICATION

PLATFORM-BASED DESIGN

ARCHITECTURAL DESIGN

BEHAVIORAL

ALGORITHMIC METHODOLOGY

PROCESSOR/MEMORY METHODOLOGY

Telelogic CONTROL LOGIC METHODOLOGY

Algorithmic Architect’s Workbench MathWorks Catalytic CoFluent Concurrent EDA CoWare - Cadence - Comdisco MLDesign Mentor - Summit Synopsys - Cadis

Processor/Memory Architect’s Workbench Mentor - Summit Mirabilis Space Codesign

Control Logic Architect’s Workbench MathWorks Mentor - Summit Telelogic - iLogix

Algorithmic Design & Entry Celoxica (Embedded Solutions) CoFluent Poseidon Design Systems

Processor/Memory Design & Entry CoWare Mimosys Mirabilis Virtual Computer Corp.

Control Logic Design & Entry Mentor

Algorithmic Synthesis Celoxica (Embedded Solutions) Mentor Forte - Chronology/Cynapps Synplicity Catalytic Concurrent EDA Impulse Accelerated Technologies MathWorks NEC Y Explorations Application Engine Compiler Synfora Tensilica

ESL Synthesis Bluespec ESL Target Compiler Arteris Denali Mirabilis Sonics Silistix

ESL Synthesis Bluespec MathWorks Control Logic ESL Power Analysis Sequence

Application Engine Compiler Synfora Tensilica

Algorithmic Power Analysis ChipVision Entasys

Processor/Memory Power Analysis Mirabilis Sequence

Algorithmic Platform Design & Entry CoWare - LisaTek Synopsys Prosilog

Processor/Memory Platform Design & Entry ARM - Axys Mentor VaST

Process Engine Compiler CoWare - LISATek ARC BINACHIP Critical Blue Poseidon Stretch Synfora Target Compiler Technologies Tensilica

Processor/Memory Modeling ARM - Axys VaST

Control Logic Platform Design & Entry Esterel Technology PolyCore Software

Algorithmic Modeling Mentor - SpiraTech Prosilog

Intelligent Test Bench Cadence - Verisity - Inspec Mentor Breker Certess NuSym ESL Formal Veriﬁcation Calypto

Concurrent Software Compiler Imperas ESL Compiler ACE Spiral Gateway

OTHER ESL

SDA Design & Simulation MathWorks

Software Virtual Prototype VaST Virtutech Synopsys - Virtio ARM Carbon Design Systems CoWare Mentor - Summit TenisonEDA Silicon Virtual Prototype ENTASYS Javelin (Icinergy)

ESL Test & Veriﬁcation Cadence - Verisity - Inspec Avery Beach Systems Diagonal Systems (DS) JEDA Levetate Design Systems Mentor Novas Prolog Source III Structural Design Veriﬁcation Synapticad Temento TransEDA

ESL Co-Veriﬁcation Cadence Mentor Tarek

ESL Design & Entry HyPerformix (SES) Actis Aldec Beach Solutions Bellum Easics Expressive Systems MataiTech S2C

Temporal Analysis Forte - Chronology/Cynapps Gigascale (InTime) Synapticad Time-Rover

Processor/Memory Test & Veriﬁcation IBM Transaction-Based Acceleration & Emulation Cadence EVE Mentor

ES Level RF Design Applied Wave Research Agilent - Eagleware - Elanix Ansoft - Simec (Germany)

ESL Simulation Synopsys Mentor ARM Bluespec Carbon Mesquite Software Simantix

ESL tool topology.

JUNE 2007

cover feature

ESL vendors have long been challenged to provide synthesizable RTL that doesn’t require extensive optimization in order to meet area, performance, power and timing requirements at the gate level. This is one area where ESL vendors have made major strides in the past year. Part of the problem has been solved by IP vendors. According to Martin, “If you are using cycle-accurate models, you can get pretty good estimates out of ESL/SystemC-type simulations, with cycle-accurate ISS models being plugged in for processors. Those models are becoming more and more available at the ESL level.” When you’re developing a design using ESL tools, you can always generate an RTL model and use that model to estimate a performance and power envelope, even if you intend to go back later and do further optimizations. The models supplied by IP vendors enable you at that point to get a fairly accurate performance estimate regarding that IP even while you’re still considering architectural changes. Most IP vendors work closely with library providers, who try to characterize their libraries for the most advanced processes. Since that process information is available to ESL tools, system architects can fairly accurately estimate the power requirements of the final design.

er exploration ether your goal speak directly ical page, the ght resource. technology, es and products

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Designing for Low Power

Low power hasfrom become the number one probexploration into products, technologies and companies. Whether your goal is to research the latest datasheet a company, mp to a company's technical page, the goal of Get Connected is to put you in touchlem with for the right resource.Design’s Whichever level of Portable readers. According gy, Get Connected will help you connect with the companies and products you areto searching for. Gary Smith, “Eighty percent of power prob-

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lems are caused by poor partitioning.” Power is best addressed at the architectural level (Figure 1); the closer you are to implementation, the less impact design changes will have on power consumption. How—and how well—do ESL tools address the power problem? Calypto’s SLEC CG functionally verifies register transfer level (RTL) power optimizations without requiring the creation of specific test benches or running days of simulation regressions. SLEC CG enables designers to aggressively reduce power through RTL clock gating changes by iden-

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tifying whether clock gating changes have introduced functional errors. PowerPro CG (for PowerPro Clock Gating) is an Automated RTL Power Optimization Solution that the company claims can reduce power by up to 60% in RTL designs. Power savings from PowerPro are complementary and cumulative to downstream tools that operate at the combinational gate level. Thomas Blaesi, president & CEO of ChipVision, contends that “Power consumption is the most limiting fact in chip design. We believe that Moore’s Law is in trouble because power is limiting the level of integration of modern SoC designs.” ChipVision demonstrated its new ESL power optimization tool at DAC, one that the company claims can result in pre-RTL energy savings of up to 75 percent, shorten time-to-results by a factor of 60 and create code that is 9x more compact than that generated by current tools. ChipVision’s pending product lets RTL designers work interactively with system-level descriptions to generate power-optimized RTL code in the form of synthesizable Verilog. According to Blaesi, ChipVision’s power estimation tool takes ESL (C/C++/SystemC) inputs; lets designers perform interactive synthesis, graphically trading off power, area and timing; and outputs an optimized RT architecture, along with CPF and UPF power constraint files that downstream tools can utilize. The ChipVision tool—which goes on sale later this year—also implements leakage strategies, using technology-driven modeling for process, temperature and voltage variations. Work is under way to support power gating and dynamic frequency and voltage scaling.

The ESL-to-GDSII Flow

Forte Design Systems raised numerous eyebrows at the recent Design Automation Conference (DAC) claming to have completely automated the ESL-to-GDSII design flow. Version 3.3 of their Cynthesizer SystemC synthesizer tool completes the path from SystemC to GDSII by generating command files that feed into Magma’s Blast Create logic synthesizer and Blast Fusion place-and-route tools.

cover feature According to Brett Cline, Forte’s VP of marketing and sales, Cynthesizer takes SystemC input, converts it into synthesizable Verilog output, and uses that to launch Blast Create with default scripts. The designer can then automatically view the results from the Magma tool and change the tradeoffs in Cynthesizer before making additional synthesis runs. Cynthesizer 3.3 also includes an IP library and a graphical analysis environment. The CynWare SystemC IP library includes a variety of synthesizable building blocks, including AMBA AHB master and slave bus interfaces, memory and streaming data interfaces and fixed-point datatypes.

Are We There Yet?

After a decade of steady development, ESL is finally starting to deliver on its promise. For the first time you can do architectural exploration doing algorithmic and transaction-level models; then generate cycle-accurate, process-specific synthesizable RTL that reflects the tradeoffs you made at the ESL level for power, performance and area—the point where you can make the greatest impact on power consumption. A wide range of existing EDA tools can then take you the rest of the way to GDSII. You may need to stitch together tools from a variety of vendors to pull this off, so the ESL flow isn’t yet fully automated, but it’s getting close. One problem holding back widespread adoption of ESL is the fact that many high-level tool vendors are small enough and their tools new enough to make corporate buyers reluctant to re-engineer their entire design process around “unproven” tools, not to mention companies. The ESL panelists at the latest DAC agreed that even if the ESL flow isn’t fully automated yet, ESL tools are finally robust enough to be trusted. They also agreed that companies won’t switch over to ESL technologies until it becomes just too painful to stick with current design techniques. The panelists whose companies were involved with 90- and 65-nm complex SoC designs argued strongly that the inflection point has arrived.

ARM Inc., Sunnyvale, CA. (408) 734-5600. [www.arm.com]. Bluespec, Inc., Waltham, MA. (781) 250-2200. [www.bluespec.com]. Cadence Design Systems Inc, San Jose, CA. (408) 943-1234. [www.cadence.com]. Calypto Design Systems, Santa Clara, CA. (408) 850-2300. [www.calpyto.com]. ChipVision Design Systems Inc., San Jose, CA. (408) 449-4550. [www.chipvision.com]. CoFluent Design, Inc., San Jose, CA. (408) 573-6172. [www.cofluentdesign.com]. CoWare, Inc., San Jose, CA. (408) 436-4720. [www.coware.com]. EVE, San Jose, CA. (408) 881-0440. [www.eve-team.com]. Forte Design Systems, San Jose, CA. (408) 487-9340. [www.forteds.com]. Gary Smith EDA, Santa Clara, CA. (408) 985-2929. [www.garysmitheda.com]. IBM North America, White Plains, NY. (800) 426-4968. [www.ibm.com]. Magma Design Automation, Inc., Santa Clara, CA. (408) 565-7500. [www.magma-da.com]. Mentor Graphics Corporation, Wilsonville, OR. (503) 685-7000. [www.mentor.com]. Poseidon Design Systems, Inc., Atlanta, GA. (770) 937-0611. [www.poseidon-systems.com]. Silistix, San Jose, CA. (408) 436-1656. [www.silistix.com]. Synopsis, Inc., Mountain View, CA. (650) 584-5000. [www.synopsis.com]. Tensilica Inc., Santa Clara, CA. (408) 986-8000. [www.tensilica.com]. The MathWorks, Inc., Natick, MA. (508) 647-7000. [www.mathworks.com]. VaST Systems Technology Corporation, Sunnyvale, CA. (408) 328-3300. [www.vastsystems.com]. Virtutech, Inc., San Jose, CA. (408) 392-9150. [www.virtutech.com].

JUNE 2007

consumer electronics audio codecs

The Cost of Integration in Audio Codecs Portable Applications Benefit When Analog Features Remain in Dedicated Silicon

by Robert Kratsas, Portable Audio Product Line Manager and John Tucker, Portable Audio Analog Design Manager, Cirrus Logic

Feature integration on silicon is generally accepted as the natural evolution in the semiconductor market. Nowhere else is silicon integration more anticipated than in the portable electronics segment. The explosion of the mobile handset and portable entertainment markets has created a very competitive playing field that is driven by increasing consumer demand for a more aggressive formfactor, higher audio performance and longer battery life. Within IC vendors in the portable market, there is a natural silicon divide forming between analog audio and digital processing integration. On one side, traditional analog ICs such as audio codecs are increasingly becoming integrated within digital SoC processors, creating truly integrated audio systems for products such as MP3 players. While this integration may at first appear a logical marriage of system function, the truth is that it more often makes

PORTABLE DESIGN

sense for portable system designers to continue to adopt stand-alone analog audio codecs for their portable products. The reality is that designing with digital SoCs that integrate audio codecs are typically more costly, leading to higher product costs. Keeping analog components separate from their digital brethren also has other advantages: it simplifies the design process, allows for more flexibility, minimizes risk and production delay factors and ensures faster design cycles. Also, increasingly important, stand-alone codecs are more likely to produce better audio quality and lower battery consumption, enhancing the productâ&#x20AC;&#x2122;s overall consumer appeal. While digital SoC solutions have made some inroads in the portable market, they tend to be more accepted within lower-end applications. Further, the continued existence of discrete audio converters in market-leading MP3 players,

Cost Issues

Two very large hurdles present themselves when considering between stand-alone analog codecs compared to integrated digital SoCs. The first is most assuredly cost. The system architects of todayâ&#x20AC;&#x2122;s portable audio products are fairly savvy and demanding of their audio chips. It is not uncommon for an MP3 player to require audio codecs with full 24-bit conversion capability, and integrating items such as programmable gain amplifiers (PGAs), analog mixers, microphone pre-amplifiers, headphone, line and even speaker drivers is fairly common. These items are all of course analog and dominate the architecture of a low-power audio codec. High transistor counts are not as customary in this type of chip either. Most codecs use tens of thousands of transistors, which is a far stretch from the millions of transistors used in larger DSP or even larger portable processor chips. Typically, chips with high transistor count benefit from smaller geometry fabrication technologies, such as 90 nanometers (nm) and even smaller 65 nm processes. Converters with less than a tenth of the transistor count found in processor chips do not benefit from smaller geometries. In fact it is quite the opposite. To illustrate, consider a currently available low-power audio codec from Cirrus Logic. This product is manufactured in 0.25 micrometer (Âľm) technology and is about 9 mm2 in size. To port this product to a cutting-edge processor technology of 90 nm, the die would shrink to about 5.15 mm2, but the overall cost of the die would increase by 24 percent (Table 1)! One lesser known item about analog audio design is that it often requires multiple revisions. There is a very simple reason for this, and that is a lack of 100 percent functional and performance verification on analog chips. Conversely, digital chips can achieve close to 100 percent verification prior to the first tapeout. It is currently expected for all large digital chips to make it to market with only a small metal

consumer electronics

portable media players (PMP) and high-end handsets sends a very clear message that analog audio and digital integration is not currently the expected standard.

revision. An analog audio chip can see two or three full layer revisions followed by a few metal revisions. Using Table 1 as a guide, one can see how research and development costs can quickly spiral out of control for an audio codec developed in a smaller geometry, and those costs ultimately get passed on to manufacturers and consumers. Moreover, in 90 nm geometries, mask costs can exceed $1.4 million prior to achieving final silicon on an audio codec, if one is not careful during the analog verification and validation process.

figure 1 High-Performance Digital-to-Analog Converter Analog Domain

Digital Domain IÂ˛S Digital Input

Serial Audio Port

24 bits @ 3 bits @ 24 bits @ 44.1 kHz Interpolation 2.822 MHz Multi-Bit 2.822 MHz Delta-Sigma Filter Modulator

Switched Capacitor Element

Analog Output VQ

90 nm

.18

.25

NAND Gates

1 pF of Capacitance

64 pF of Capacitance

High-performance digital-to-analog converter.

Achieving final silicon on a first pass of an audio codec design is a significant task when considering the complex features such as amplifiers, analog volume controls, charge pumps and the converters themselves. Any single missed specification from any of these above features can mandate a full layer revision. Furthermore, product designers have been known to request specific feature changes or additions after having delivered what was thought to be the final silicon. If the analog audio and digital chips are combined, there is a very good chance that JUNE 2007

consumer electronics

the development costs will exceed what is normally expected by the silicon developer’s management. Revising the design to try and obtain an increase in the dynamic range of the DAC or shaving a few unwanted milliwatts off the quiescent playback power consumption may not be acceptable to the financial arm of a design company. This is especially true if the finance or management team is accustomed to the digital chip’s high success rate on the first or second try. A good analog design manager will go through a similar analysis and quickly determine the cheaper geometry process (i.e., 0.25 µm) is best suited to design their converters. This same design manager will want to limit the R&D costs on the masks, which will have

dynamic range, and THD+N better then -90 dB. With significant advances in converter technology, analog companies are able to achieve these performance requirements while still meeting the power constraints placed on them by the system designers. Achieving this performance comes at a cost, due to increased die size. To better understand how die size plays into the design of a Delta-Sigma converter, one must understand its construction. For example, the architecture of a Delta-Sigma design with a simple three-bit (a.k.a multi-bit) switched capacitor digital to analog converter can be used to achieve performance levels near 100 dB dynamic range. In this design (Figure 1) the input signal is interpolated from the com-

table 1 Transistor Size

Average Costs

Average Wafer Cost

CODEC Die Size

Gross Die / Wf

Die Cost

.25 um

$68,321

$885

9 mm

3190

$0.28

90 nm

$700,000

$5,045

5.15 mm

13543

$0.37

Die cost for an audio codec.

the added benefit of allowing more money to be spent on good solid analog design engineers. This in turn benefits the system design architect with more creative products that have a lower average sale price.

Average Selling Price Impact

The current state-of-the-art technology for precision audio converters is multi-bit DeltaSigma (ΔΣ) architecture. It is generally accepted by audio system and silicon designers that multi-bit Delta-Sigma architecture can achieve equivalent in-band dynamic range performance with a lower system clock rate and lower silicon area then earlier single-bit solutions. This lower clock rate translates into lower power consumption for the codec as well as the overall system. It makes sense that a discerning audio consumer who is in the market for a new MP3 player would want the best audio quality available. So it becomes clearer to see why portable codecs have converged on the use of this technology. MP3 players have not quite achieved the performance required by home theater enthusiasts, but high-end MP3 audio designers are now requiring companies to supply converters capable of achieving 100 dB 28

PORTABLE DESIGN

mon MP3 sample frequency of 44.1 kHz to 2.822 MHz. The signal is then processed by a Delta-Sigma modulator to convert the 24bit data into noise-shaped three-bit data. At this point we transition from the digital to the analog domain by sending the three-bit data stream into the DAC. In this design, eight-capacitor elements are used to recreate the analog signal and filter out the quantization noise from the Delta-Sigma modulator. While these digital signal processing techniques have relaxed the analog design requirements, the analog design time and area are still not trivial. The capacitors used in the analog domain typically require values in the 50 pF to 100 pF per audio channel. These capacitors are used in the switched capacitor elements, switched capacitor filter and operational amplifier compensation. Capacitor integration does not scale with smaller geometry processes and transistor logic scales. For example, the area needed for a 100 pF capacitor is the same for a 0.35 µm and 90 nm process at about 0.1 mm2. On the other hand, a NAND gate in 90 nm is approximately 15 times smaller than the same gate in a 0.35 µm process. Nearly 2.4 thousand 0.35 µm NAND gates or 36 thousand 90 nm NAND gates can fit in 0.1 mm2.

Time-to-Market Delays

Getting the next generation portable product into the market as fast as possible is critical for system designers. This ensures continued or growing market share in their particular segment. When deciding to choose an integrated audio solution, a system designer can easily quantify the ASP of that product compared to a discreet solution. What the designer cannot quantify easily is the potential delays incurred by choosing an integrated digital SoC. The complexity of an integrated chip tends to create unforeseen problems not readily apparent to the portable system design community. Trying to debug an integrated chip takes time, especially if there is a parallel effort to review and debug the processor software. One would expect a semiconductor company who creates this type of integrated chip to oversee digital silicon validation, analog performance validation and software testing all at the same time. Experience dictates that a company may be good at one of these items, and maybe two, but not all three at the same time. So this leaves the portable system designer with an unknown: can the silicon be trusted and will the overall system meet the standards set for the product? Once designed in, any major feature bugs could delay the delivery of the final product by months. Once a problem has been isolated and fixed it still has to be fabricated. Cycle time for a 90 nm process can be 50 percent longer than a .25 μm process. This can be devastating for companies that are pushing for a product release in the fall prior to the holiday season. The market release of the product could be delayed until after the most profitable season. One other non-quantifiable advantage of having stand-alone audio codecs in the market is the leverage that a product design purchasing department is afforded. Having several standalone codecs and processor options available allows the design team to choose the best solution for their system based on performance. It

consumer electronics

At 90 nm pricing this 0.1mm2 worth of capacitors translates into about a $.01 die price increase over the 0.25 µm process. This is only for the caps used in the DAC. Then one has to start looking at the other analog elements such as resistors and capacitors used in the analog features such as mixers, PGAs and charge pumps. Integrating all of these products translates into a higher die cost and eventually a higher average selling price (ASP) for the end user.

also gives the purchasing department leverage during the cost negotiation process. This allows the design and purchasing team to work in unison to choose the best overall solution. It also decreases the risk of dependence on one particular silicon vendor.

Analog Integration Is the Key for Success

A company that specializes in digital signal processor design may not have the audio background or historical skill to integrate a complex mixed signal converter system. This dissociation of resources creates a situation where processor companies may take shortcuts when designing their integrated codecs. The historical expertise at that company will focus on and do a good job in areas that they are familiar with and can solve readily. However, they may not have the expertise to lower their analog converter’s power consumption. They may not be able to hit the analog specifications generally excepted as cutting-edge, and they definitely will view the analog portions of the chip as ancillary. The conclusive key to a portable system’s success is specialization. Allow the digital companies to integrate as many digital components as possible and have the analog companies integrate analog. Trends in the market seem to support this premise. Analog companion chips that integrate audio converters, amplifiers and even power management are commonplace in mobile handsets. For portable high-end entertainment, complete audio integration of converters and amplifiers on one chip is now expected. Companies that specialize in portable converters can concentrate on items such as lowering power consumption while simultaneously squeezing every decibel of performance out of their silicon. Analog audio companies also have years of experience developing line drivers, headphone and speaker amplifiers, so it also makes sense that they can more efficiently integrate these items into their converter line. Integration of components on silicon does make sense, but only along a certain divide. Separation of features by process technology and design expertise is intuitive for the silicon designer. From the system designer’s perspective, designing in chips that separate functionality across the lines of digital and analog makes sense, especially when one wants a lower risk solution with a higher potential of completing the design on time. Cirrus Logic, Austin, TX. (512) 851-4000. [www.cirruslogic.com].

JUNE 2007

wireless communications WiMAX

Mobile WiMAX: The Evolution to Lower Power Mobile WiMAX applications can deliver very high data rates with modest power consumption—if you design them right.

by Allen Hill, Analog Devices, Inc.

WiMAX (Worldwide Interoperability for Microwave Access) is the latest “next-generation” wireless telecommunications standard making its way to the marketplace. Based on the IEEE 802.16 air interface standard, WiMAX is a broadband wireless solution offering high data throughput, efficient data multiplexing and low data latency. The two versions of WiMAX that are being deployed are aimed at different market segments. The first, fixed WiMAX (802.16d), is primarily utilized in fixed locations. It competes with cable and DSL to provide the public with high speed Internet access. The second, mobile WiMAX (802.16e), is aimed toward Mobile Internet, which provides users the convergence of broadband wireless connectivity in handheld devices. WiMAX is based on OFDM (Orthogonal Frequency Division Multiplexing). High order modulation schemes and wide bandwidths allow high throughput but require

PORTABLE DESIGN

high linearity and low noise for proper operation. Present profiles support up to 64 QAM (Quadrature Amplitude Modulation) in bandwidths up to 10 MHz, putting tremendous pressure on system designers to meet conformance specifications.

Power Issues

As a relatively infant technology, mobile WiMAX faces challenges in reducing size and power consumption to meet customer expectations for mobile devices. Mobile WiMAX is in its first generation. Functionality and interoperability have thus been the highest priorities for system designers. As future generation devices are contemplated, smaller size and lower power consumption will be required to ensure market acceptance. Today’s solutions use modem processors that consume up to 1 watt or more. Add the RF transceiver, with power as high as 750 mW, and transmit power

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TOTAL

RF Transceiver

Processor

TOTAL

RF Transceiver

Processor

WATTS

amplifiers (PA) that consume above 1.5 watts, and the task of designing mobile devices that aren’t hot to the touch is daunting. Figure 1 shows where the mobile WiMAX platforms stand in 2006/7 with expected improvements for 2009/10. As specifications unify, one of the first ways to reduce power in any developing technology is to utilize more efficient design philosophies. figure 1 WiMAX has started down this path as the Mobile WiMax Peak Power (No Assumption For Power Cycling) tasks of functionality 4.0 and interoperability 3.5 are now accepted as “givens.” WiMAX 3.0 profiles driven by in2.5 dustry organizations 2009/2010 ensure acceptance of 2.0 nd 2006/2007 (Projected) the technology within 1.5 the marketplace, but er exploration ether your goal provide only a small 1.0 speak directly subset of what the ical page, the 0.5 ght resource. full 802.16 standard technology, allows. This enables es and products 0 both system and chip ed designers to narrow their focus to meet realistic overall requirements. As an example, 802.16 specifies chanMobile WiMAX Peak Power. nel bandwidths from companies providing solutions now 1.25 MHz up to 28 exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, mp to a company's technical page, the goal of Get Connected is to put you in touchMHz with the resource. Whichever level of inright FDD (Frequency Division Duplex), gy, Get Connected will help you connect with the companies and products you areHFDD searching(Half for. Frequency Division Duplex) and onnected TDD (Time Division Duplex) modes. Wisely, the industry has narrowed the scope by limiting initial mobile WiMAX profiles to channel bandwidths in the range of 5 MHz to 10 MHz, and restricting modulation to TDD modes. The implications of this narrowed scope are tremendous for WiMAX system and chip designers. The fact that all mobile profiles presently defined are TDD means that the device can either transmit or receive at any time, but not both. This allows chip designers Get Connected with companies mentioned in this article. to optimize their devices to handle only this www.portabledesign.com/getconnected condition. Limiting the channel bandwidth

also improves efficiency, allowing designers to optimize filters and data converters to a set of bandwidths rather than having to scale multiple octaves. Although narrowing the scope of the 802.16 standard reduces some of its flexibility, it ensures that the industry will follow a course where price, power and size can be reduced over time, while also ensuring functionality and interoperability. This allows a better chance that mobile WiMAX will meet its overall market potential.

Partitioning

The second method of power reduction involves utilization of more optimum IC (integrated circuit) processes and system partitions. This has already begun with second and future generations of chips. Most existing WiMAX processor designs started with FPGA verification, migrating to single chip devices that are fabricated in stable and mature IC processes. All these devices are fabricated in CMOS technology with geometries ranging from about 90 nm to 180 nm. Obviously, next-generation processor designs will explore using smaller geometries (65 nm and below), following the economies of the CMOS lithography progression and capitalizing on the inherent power reduction provided by smaller gate sizes that consume lower currents. Some of these processors are now starting to appear in the market, with power supply current that is one half to one quarter of first-generation devices. System partitioning also plays a large part in power reduction. Most existing WiMAX processors contain an applications processor, DSP, fixed engines and signal path data converters. The applications processor contains the MAC (media access control), as well as high-level software. The DSP and fixed engines, which perform the modem functions, include encoders, decoders, correction algorithms and FFT blocks. The data converters are included as part of the signal path to convert digital signals to analog and analog signals to digital for use by RF transceiver chips.

wireless communications

The placement of the data converters on the processor chip leads to an inefficient partition. Mixed signal components, such as data converters, tend to be one or more lithography step sizes behind digital functions.

vantages to placing the data converters on the RF transceiver include allowing all real-time loops, such as AGC (automatic gain control) on Rx and power control on Tx, to be integrated on one chip, thus minimizing software overhead between the transceiver and proces-

figure 2 Analog Partition

Most existing WiMAX

ADC Applications Processor DSP Modem Engine

ADC

processors contain an

DAC

applications processor,

DAC

DSP, fixed engines

Mobile WiMax RF Transceiver

and signal path data

Mobile WiMax Processor

JEDEC JESD207 Digital Partition

converters.

AD9352 ADC ADC DAC

This is based on the fact that linear circuits require much more process verification and modeling than digital. With data converters contained on the processor chip, the smallest CMOS lithography will generally not be used, thus forfeiting minimum die size and minimum power dissipation. A better partitioning choice is to place the data converters on the radio transceiver chip. This allows the processor to be designed in the smallest digital CMOS process node, with no extra (expensive) process steps that may be required for linear circuits. An added benefit to this partition is that all interfaces are digital, so no sensitive analog signals are routed on PC boards. A JEDEC specification (JESD207) has been approved that aims to unify the digital interface between the RF transceiver and the digital processor for mobile WiMAX and other high data rate applications. Other ad-

Applications Processor DSP Modem Engine

DAC

Mobile WiMax RF Transceiver

Mobile WiMax Processor

WiMAX Partitioning Schemes.

sor chip. Figure 2 shows the differences between the two partitions. One of the largest consumers of power in the system is the power amplifier. Based on the higher order modulation and narrow subcarrier spacing utilized by mobile WiMAX, the PA has to be linear and low noise over the transmit power range. To meet these attributes, the PA consumes quite a bit of power. The good news is that the mobile WiMAX data link is generally asymmetric, downloading data approximately 70% of the time, versus 30% transJUNE 2007

wireless communications

mitting with an active PA. Additionally, PA designers are working to achieve the required linearity and low noise with advanced processes (GaAs HBT), and design techniques such as linearization. Even with the efforts underway, the PA will be a big

Mobile WiMAX supports a wide range of smart antenna technologies. All of these are aimed at enhancing system performance and reducing overall system power.

er exploration ether your goal speak directly ical page, the ght resource. technology, es and products

power consumer in mobile WiMAX systems for the next generation.

Advanced Features

Mobile WiMAX is a very flexible communications standard that includes features to support high data rates, high QoS (Quality of Service), scalability and security. Additional companies providing solutions now advanced features ofa company, mobile WiMAX aim to exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from mp to a company's technical page, the goal of Get Connected is to put you in touchimprove with the right resource. level of and reduce data linkWhichever performance gy, Get Connected will help you connect with the companies and products you arepower searchinginfor.the mobile handset. Most advanced onnected features are not available in fixed WiMAX, and are yet to be deployed in mobile WiMAX due to their complexity, but the improvements gained by their use will dictate that they be added. Mobile WiMAX supports a wide range of smart antenna technologies. All of these are aimed at enhancing system performance and reducing overall system power. The smart antenna technologies include multiple transmit and receive antenna paths. Get Connected with companies mentioned in this article. Beamforming is one supported technol-

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ogy that uses multiple antennas to transmit and receive signals. For receive, the device uses different algorithms to combine multipath versions of the received signal to increase signal level and improve signal quality. For transmit, the power savings is seen by running multiple power amplifiers at lower output levels, combining their signals by beamforming. This targeted approach consumes less power than using a single PA at higher output power levels. Also on the transmit side, mobile WiMAX uses OFDMA (Orthogonal Frequency Division Multiple Access), an optimized version of OFDM. The mobile terminal uses subchannelization where a limited number of subcarriers can be transmitted and the RF energy is concentrated in a narrower band. This improves signal strength for a given RF power, allows less power to be transmitted in many cases, and reduces overall transmit power. In summary, mobile WiMAX technology is in its relative infancy. A natural maturation will occur, as with any developing technology, and will include more efficient design philosophies as the specifications unify. As they develop, WiMAX solutions will also transfer to smaller, lower-power IC processes and to newer system partitioning schemes. Additionally, the WiMAX standard is one of the most flexible the wireless industry has seen, with advanced features that will offer power-saving attributes as they become available and mainstream. Analog Devices, Norwood, MA (781) 329-4700 [www.analog.com].

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portable power power supply topologies

Designing Switch Mode Power Supplies Choosing the right SMPS topology requires a careful analysis of your portable application.

by Daniel Wagner, Associate Member of the Technical Staff, Applications, Maxim Integrated Products Inc.

With the multiple DC voltage levels required by a wide variety of electronic gadgets, it is only necessary that there be an effective means of converting standard power source potentials into the voltages dictated by the load. Doing so must be versatile, efficient and reliable. Switch mode power supplies (SMPS) are frequently used to provide the various levels of DC output power needed for modern applications, and are indispensable in achieving a highly efficient and reliable DC/DC power conversion system.

Why SMPS?

The majority of electronic DC loads are supplied from standard power sources. Unfortunately, that standard source voltage may not match the levels required by microprocessors, motors, LEDs, or other loads, especially when the source voltage is not regulated. Batterypowered devices are prime examples, where 36

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the typical voltage of the standard Li+ cell or NiMH stack is either too high or too low, or drops too far during discharge, to be used in common applications. Fortunately, the problem of converting a source voltage into a usable, specified output voltage is solved by the versatility of the SMPS. There are numerous SMPS topologies, but classified into fundamental categories, these power supplies are capable of stepping up, stepping down, inverting, or even stepping up and down the input voltage. Unlike linear regulators, which can only step down an input, SMPS are attractive in the fact that a topology can be selected to fit just about any output voltage needed. Additionally, modern SMPS ICs are designed with varying levels of integration, allowing the engineer to choose from a wide array of topologies with more or less of the standard SMPS circuit brought into the IC. In doing

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so, manufacturers are able to ease the design burden for commonly used, application-specific power supplies, or offer the engineer barebones SMPS ICs for custom projects, thereby enhancing the versatility of these widely used devices. One commonly encountered problem that an engineer must face is efficiently stepping

figure 1 L1 2.2uH VIN=3.6V

VOUT=1.8V

IN_P C1 2.2uF

MAX8640YEXT18+

GND

OUT C2 2.2uF

er exploration ether your goal speak directly ical page, the ght resource. technology, es and products

/SHDN\

tion, and here is where the switch mode power supply shines. Due to its nature, a well-designed SMPS can achieve 90% efficiency or more, depending on load and voltage levels. From the previous example, using the step-down SMPS such as the version shown in Figure 1 instead of a linear regulator, delivers an efficiency of 90%, which is an improvement of 40% over the linear regulator. By direct comparison, the efficiency advantage of the step-down SMPS is apparent. Similar or better efficiencies are observed in other SMPS topologies. Although high efficiency is the dominant advantage with SMPS designs, other benefits naturally occur as a direct result of minimizing power loss. For example, a reduced thermal footprint is observed in the SMPS when compared to its less efficient counterparts. This equates to reduced thermal management requirements, and, more importantly, an increased lifetime due to improved reliability, since components are not subjected to excessive heat as they would be for a lessefficient system.

SMPS Topologies and Conversion Theory

ed Simple Step-Down SMPS Circuit IC.

down an input voltage to achieve a lower output voltage. A simple solution is to implement a linear After all, it requires only a exploration into products, technologies and companies. Whether your goal is to research the latestregulator. datasheet from a company, mp to a company's technical page, the goal of Get Connected is to put you in touchfew withcapacitors the right resource. levelthermal of andWhichever adequate managegy, Get Connected will help you connect with the companies and products you arement. searching for. But where simplicity ends, inefficiency onnected beginsâ&#x20AC;&#x201D;even to unacceptable levels if the voltage differential is large. Efficiency of a linear regulator is directly related to the power dropped across its pass transistor, which can be significant since dissipated power = ILDO x (VIN -VOUT). For example, when stepping down a 100 mA load from a 3.6V battery to a 1.8V output, 0.18W is dropped across the linear regulator. This yields a low 50% efficiency, which reduces battery longevity by 50% (assuming ideal operation). Get Connected with companies mentioned in this article. In light of this efficiency penalty, the dutiful www.portabledesign.com/getconnected engineer is driven to achieve an improved solu-

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As mentioned above, SMPS are capable of converting a DC input voltage into a different DC output voltage, depending upon circuit topology. While there are numerous topologies used in the engineering world, a few are fundamental and most often seen being classified according to their conversion function: step-down (Buck), step-up (Boost), and stepup/down (Buck/Boost or Inverter). These three fundamental topologies are depicted in Figure 2. Current paths are included on the diagrams and the current flows will be discussed as each topology is analyzed. All of these topologies include a MOSFET switch, a diode, an output capacitor and an inductor. The MOSFET, which is the actively controlled component in the circuit, is interfaced to a controller (not shown) that applies a pulse-width-modulated (PWM) square-wave signal to the MOSFET gate, switching the device on and off. To maintain the output volt-

portable power age constant, the controller senses the SMPS output voltage and varies the duty cycle (D) of the square-wave signal, dictating the amount of time that the MOSFET is on during each switching period (tS). The value of D, which is a ratio of the square-wave’s on-time and period (tON/tS), directly affects the voltage observed at the SMPS output, as will be shown below. The state of the MOSFET divides the SMPS circuit into two phases, a charging phase and a discharging phase, both of which describe the energy transfer of the inductor (see loops in Figure 2). Energy stored in the inductor during the charging phase is transferred to the output load and capacitance during the discharge phase. The capacitor supports the load while the inductor is charging, and sustains the output voltage. This cyclical transfer of energy between the circuit elements maintains output voltage at the proper value, according to topology. The inductor is central to the energy transfer that exists from source to load during each switching cycle. Without it, the SMPS would not function as the MOSFET is switched. Energy (E) stored in an inductance (L) is dependent upon its current (i):

1 × L ×i 2 2

Therefore, energy change in the inductor is gauged by the change in its current (ΔIL), which is due to the voltage applied across it (VL) over a specific time period (Δt):

∆I L =

To be in steady state, a variable that repeats with period tS must be equal at the beginning and the end of each period.

During the charge phase, the MOSFET is on, the diode is reverse-biased, and energy is transferred from the voltage source to the inductor. Inductor current ramps up since VL is positive. Also, the output capacitance transfers the energy it had stored from the previous cycle to the load, in order to maintain output voltage constant. During the discharge phase, the MOSFET turns off, and the diode becomes forward-biased and conducts. Since the source is no lon-

figure 2

VIN +

VOUT < VIN + Load -

V L × ∆t L

The change in current is a linear ramp, since a constant voltage is applied across the inductance during each switching phase (Figure 3). The inductor voltage during the switching phase can be determined by performing a Kirchoff’s voltage loop, paying careful attention to polarities and VIN/VOUT relationships. For example, inductor voltage for the step-up converter during the discharge phase is (VOUTVIN). Since VOUT > VIN, the inductor voltage is negative.

VIN

VOUT < VIN + Load -

STEP-DOWN (BUCK) VIN +

STEP-UP (BOOST)

Load

STEP-UP/DOWN (BUCK/BOOST OR INVERTER)

|VOUT| > |VIN| |VOUT| < |VIN| Inductor Charging Path Inductor Discharging Path

Fundamental SMPS Topologies: The Buck, Boost and Buck/Boost.

JUNE 2007

portable power

er exploration ether your goal speak directly ical page, the ght resource. technology, es and products

ger charging the inductor, the inductor’s terminals swap polarity as it discharges energy to the load and replenishes the output capacitor. The inductor current ramps down as it imparts energy, according to the same relationship given above. The charge/discharge cycles repeat and maintain a steady-state switching condi-

table 1

Topology

Voltage Conversion Ratio

Current Conversion Ratio

Step-Down

VOUT/VIN=D

IIN/IOUT=D

Step-Up

VOUT/VIN=1/(1-D)

IIN/IOUT=1/(1-D)

Step-Up/ Down

VOUT/VIN=D/(1-D)

IIN/IOUT=D/(1-D)

SMPS Conversion Ratios

tion. During the circuit’s progression to steady state, inductor current builds up to its final level, which is a superposition of DC current and the ramped AC current (or inductor ripple current) developed during companies providing solutions now thethetwo phases (Figure 3). The DC exploration into products, technologies and companies. Whether your goal is to research latest circuit datasheet from a company, mp to a company's technical page, the goal of Get Connected is to put you in touchcurrent with the right resource. Whichever of current, but level is related to level output gy, Get Connected will help you connect with the companies and products you aredepends searching for. on the position of the inductor in onnected the SMPS circuit. The ripple current must be filtered out by the SMPS in order to deliver true DC to the output. This filtering action is accomplished by the output capacitor, which offers little opposition to high-frequency AC current (X C= 1/(2*pi*f*C)). The unwanted output ripple current passes through the output capacitance and maintains the capacitor’s charge as the current passes to ground. Thus, the output capacitance also stabilizes the Get Connected with companies mentioned in this article. output voltage. In real applications, howwww.portabledesign.com/getconnected ever, Equivalent Series Resistance (ESR) of

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the output capacitor causes output voltage ripple proportional to the ripple current that flows through it. So, in a nutshell, energy is shuttled between the source, the inductance and the output capacitance to maintain the output voltage constant and to supply the load. But, how does the energy transfer of the SMPS determine its output voltage and conversion ratio? This is easily calculated by understanding steady state as it is applied to periodic waveforms. To be in steady state, a variable that repeats with period tS must be equal at the beginning and the end of each period. For the inductor, since its current is periodic due to the charge and discharge phases described above, inductor current at the beginning of the PWM period must be equal to the inductor current at the end. This means that the change in inductor current during the charge phase (ΔICHARGE) must equal the change in inductor current during the discharge phase (ΔIDISCHARGE). Equating the ΔI equations above, an interesting result is achieved, which is also referred to as the voltsecond rule: ÄI CHARGE = ÄI DISCHARGE

V L(CHARGE) × D × t S L

V L (DISCHARGE ) × (1 − D) × t S

V L(CHARGE) × D × t S = V L(DISCHARG

L E)

× (1 − D) × t S

Simply put, the inductor voltage-time product during each circuit phase is equal. This means that by observing the SMPS circuits of Figure 2, the ideal steady-state voltage and current conversion ratios can be found with a little work. For the step-down circuit, a Kirchhoff’s voltage loop around the charge circuit reveals that inductor voltage is (VIN-VOUT). Likewise, inductor voltage during the discharge phase circuit is –VOUT. Using the volt-second rule, the voltage conversion ratio is found:

V IN - V OUT × D = − V OUT × (1 − D) V OUT =D V IN

portable power Further, input power is equal to output power in an ideal circuit. Thus, the current conversion ratio is found:

PIN = POUT I IN × V IN = I OUT × V OUT I IN I OUT

V OUT =D V IN

From these results, it is seen that the stepdown converter reduces VIN by a factor of D, while input current is a D-multiple of load current. Table 1 lists the conversion ratios for the topologies depicted in Figure 2. All SMPS conversion ratios can usually be found with this method, although complex topologies can be more difficult to analyze.

Disadvantages and Tradeoffs

Of course, the high efficiency afforded by the SMPS is not without its penalties. Perhaps the most often cited issue with switch mode converters is their propensity to radiate electromagnetic interference (EMI) and conduct noise. EM radiation is caused by the fast transitions of current and voltage switching waveforms that exist in SMPS circuits. Rapidly changing voltages at the inductor node cause radiated electric fields, while fast switching currents of the charge/ discharge loops produce magnetic fields. Conducted noise, on the other hand, is propagated to input and output circuits when SMPS input/output capacitances and PCB parasitics present higher impedances to switching currents. Fortunately, good component placement and PCB layout techniques go a long way toward combating EMI and reducing noise. Other issues include the fact that SMPS require additional external components and can be quite complex to understand. Fortunately, most SMPS IC manufacturers write their literature to the extent that not only gives the customer enough details about operation, but also explicitly gives direction in choosing correct external components. Also, the high

figure 3

+VL

VL(CHARGE)

-VL CHARGE PHASE

VL(DISCHARGE)

DISCHARGE PHASE

∆ICHARGE

∆IDISCHARGE

IL_DC

(1-D)XtS OA

DXtS

IL_DC

{

IOUT (STEP-DOWN) IIN (STEP-UP) IIN + IOUT (STEP-UP/DOWN)

Steady-State Inductor Voltage and Current Characteristics.

levels of integration seen in modern SMPS ICs can reduce the number of external components required. However, additional complexity and parts can equate into increased cost of the power supply. Despite these issues, however, SMPS are widely used in numerous applications. The disadvantages can be dealt with, and the efficiency and versatility gained from their use is very desirable and often required. Maxim Integrated Products, Inc. Sunnyvale, CA (408) 737-7600 [www.maxim-ic.com].

JUNE 2007

product feature Single-Chip, 7-Band, Polar HEDGE RF Transceiver Self-Calibrating Multi-Mode Transceiver Chip Enables Reduced BOM Cost, Improved Battery Life by John Donovan, Editor-in-Chief Sequoia Communications has announced sampling of the SEQ7400, which it claims is the industry’s first singlechip, polar transmit, seven-band, HEDGE (HSDPA/WCDMA and EDGE/GPRS/GSM) RF transceiver. The chip supports WCDMA, HSDPA, EDGE, GPRS and GSM modes across seven frequency bands simultaneously, making it applicable to major networks worldwide. Portable Design would have appreciated this capability when attending 3GSM in Barcelona with a highend but CDMA-only phone. Chips such as Sequoia’s are just what international road warriors have been waiting for. More than annoyance is at stake here. Deutsche Bank Securities estimates that the 3G handset market will reach 680

transmitter architecture comparison Direct I/Q Transmitter

Polar Transmitter

VGA

D/A

More Efficient Amps

VGA

TXF

D/A Linear Amps 2RF

PLL

PC Div2 Mixers Generate Spurs

2RF Path Circuits Eliminated Current Reduced

AM D/A PC

PA TXF

PLL RF

One path for WEDGE

Polar Architecture Benefits • Simple RF System • Higher output power • Cleaner Spectrum • Maximum re-use • Lower power consumption

million WCDMA units in 2010, with HSPA accounting for 310 million of those units; improvements in battery life, form-factor and cost are critical to both users and carriers in order to enable this growth. The SEQ7400 includes tri-band WCDMA/HSDPA capability on a highly integrated device designed to be used across a wide range of 42

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handsets. Sequoia believes that the resulting small footprint, reduced bill of materials (BOM) cost and low power consumption make this chip an attractive choice for multi-band, multi-mode 3G handsets. The SEQ7400 is the first transmitter to use polar modulation for both EDGE and WCDMA modulation. Polar modulation splits the signal into its phase and amplitude components, and is the basis for most GSM and EDGE phones. By extending the polar architecture to WCDMA, it is possible to eliminate the redundancies within the transceiver chip inherent to today’s approaches, which require completely separate transmit paths for WCDMA and EDGE. In addition, a polar modulation system allows the use of highly non-linear power amplifier architectures such as Class E and Class F, which are far less power-hungry than standard linear PAs. The opportunity for reducing current consumption increases with higher peak-to-average ratio envelope variations, which occur in WCDMA and OFDM systems such as WiFi and WiMAX. To date, polar modulation has bedeviled engineers trying to get it to behave in WCDMA circuits—the chief problem being “calibration issues,” according to Sequoia CEO Dave Shepherd. Shepherd claims that the SEQ7400 is self-calibrating, with a simple interface that enables handset manufacturers to customize the architecture for a variety of platforms. The integrated SEQ7400 receiver includes all LNAs, eliminating the need for external WCDMA SAW filters. In addition, the low-noise polar modulation transmit architecture eliminates the transmit SAW filters for GSM/EDGE. The integration of LNAs and filters significantly reduces the RF bill of materials and board layout complexity. The SEQ7400 comes in an 8 mm x 8 mm BGA package. Samples and complete RF evaluation boards are available now. Volume production is anticipated in the second half of 2007.

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