Industry News: breaking News in the Industry and by RTC Media

Industry News: Breaking News in the Industry and around the World

MEMORY Interfaces WIRELESS COMMUNICATIONS:

Ultra-wideband CONSUMER ELECTRONICS:

HANDHELD GAMING DEVICES PORTABLE POWER:

PARTITIONING for POWER

Featured Product:

Texas Instruments TMS320DM355

Digital Media Subsystem

September 2007

www.portabledesign.com

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PORON® URETHANES FILL THE GAP IN HANDHELD DESIGN APPLICATIONS

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Capacity

contents

128MB

DDR3 16bit

LPDDR1 16bit

32MB

departments

editorial letter dave’s two cents industry news analysts’ pages products for designers product feature

6 7 8 12 46 50

8MB <8MB

High-Performance, Low-Power, 16 Low-Cost Off-Chip DRAM: Can I Use it in My Portable Design?

Marc Greenberg, Denali Software, Inc.

ECMA-368 (PHY)

FEC

Mapper

Peak Bandwidth Frequency Synthesiser Transmit AFE and DAC

IFFT

DAC PA DAC

AES Decryption

FEC

De-Mapper

Receive AFE and ADC

FFT

ADC

VGA

ADC

VGA

LNA

Power consumption independent of data rate 30 ultra-wideband Power consumption proportional to data rate

Charles Ng, Kilopass Technology, Inc.

The Impact of Make vs. Buy 24 Decisions for Memory Interface Solutions Jai Iyer, Virage Logic

wireless communications

PSRAM

MAC

Leverage Embedded Non-Volatile 20 Memory to Improve Yield and Enhance System Options

LPSDR 32bit

AES Encryption

LPSDR 16bit

16 memory interfaces

cover feature

DDR2 32bit Future LPDDR1 32bit

Future LPDDR1 16bit

16MB

ECMA-368 (MAC)

LPDDR1 32bit

64MB

VDD

VTRIPENTRY VTRIPEXIT 1.0V VSS VDDLeakage Power asRST tRSTD a percentage of total tRSTD power for various process technology nodes tvTRIPENTRY VSS VTRIPEXIT

Designing for Ultra-Low Power: 30 90 Ultra-Wideband in Handheld 80 Devices

36 handheld gaming devices

Mark Moore, 70 Artimi 60

50 consumer electronics 40

Supervisor Solutions for Handheld 36 30 Gaming Applications

Mark Palmer, Microchip Technology, 20Inc. 10

0 portable power

130nm

Partitioning for Power Management 40

Bhanu Kapoor, Ph.D., Mimasic

90nm

65nm

45nm

30nm

20nm

40 partitioning for power

SEPTEMBER 2007

Gbit/s

team editorial team

Editorial Director Editor-in-Chief Managing Editor Copy Editor

Creative Director Art Director Graphic Designer Director of Web Development

Web Developer

Associate Publisher Product Marketing Manager (acting) Advertising Sales Manager

Warren Andrews, warrena@rtcgroup.com John Donovan, johnd@rtcgroup.com Marina Tringali, marinat@rtcgroup.com Rochelle Cohn

art and media team Jason Van Dorn, jasonv@rtcgroup.com Kirsten T. Wyatt, kirstenw@rtcgroup.com Christopher Saucier, chriss@rtcgroup.com Marke Hallowell, markeh@rtcgroup.com Brian Hubbell, brianh@rtcgroup.com

management team

Untitled-1 1

6/15/07 10:14:46 AM

Circulation

Marina Tringali, marinat@rtcgroup.com Aaron Foellmi, aaronf@rtcgroup.com Michael Bognacki, michaelb@rtcgroup.com Shannon McNichols, shannonm@rtcgroup.com

executive management

HOW WELL DO YOU KNOW THE INDUSTRY?

Chief Executive Officer Vice President Vice President of Finance Director of Corporate Marketing Director of Art and Media

John Reardon, johnr@rtcgroup.com Cindy Hickson, cindyh@rtcgroup.com Cindy Muir, cindym@rtcgroup.com Aaron Foellmi, aaronf@rtcgroup.com Jason Van Dorn, jasonv@rtcgroup.com

portable design advisory council Mark Davidson, National Semiconductor Doug Grant, Analog Devices, Inc. Dave Heacock, Texas Instruments Kazuyoshi Yamada, NEC America

corporate office

WWW.EMBEDDEDCOMMUNITY.COM

The RTC Group 905 Calle Amanecer, Suite 250 San Clemente, CA 92673 Phone 949.226.2000 Fax 949.226.2050 www.rtcgroup.com

For reprints contact: Marina Tringali, marinat@rtcgroup.com. Published by the RTC Group. Copyright 2007, the RTC Group. Printed in the United States. All rights reserved. All related graphics are trademarks of the RTC Group. All other brand and product names are the property of their holders. Periodicals postage at San Clemente, CA 92673. Postmaster: send changes of address to: Portable Design, 905 Calle Amanecer, Suite 250, San Clemente, CA 92673. Portable Design(ISSN 1086-1300) is published monthly by RTC Group 905 Calle Amanecer, Suite 250, San Clemente, CA 92673. Telephone 949-226-2000; 949226-2050; Web Address www.rtcgroup.com. embeddedcommad_14v.indd 1 PORTABLE DESIGN

11/13/06 5:55:59 PM

Intersil Battery Authentication High Performance Analog

We’re On It.

Intersil’s ISL9206 FlexiHash+TM Engine delivers high-security battery authentication at a low cost. Intersil’s ISL9206 is an easy-to-use, robust, and inexpensive battery authentication solution for 1-cell Li-Ion/Li-Polymer or 3-cell NiMH series battery packs.

64-bit Secret 32-bit Hash Function 32-bit Hash Function

32-bit pseudo-random challenge word from host FlexiHash+ Engine

8-bit authentication code

ISL9206 Key Features: Challenge/response-based authentication scheme using 32-bit challenge code and 8-bit authentication code.

Oscillator

1-Wire Comm Interface

FlexiHash+ engine uses two sets of 32-bit secrets for authentication code generation.

16x8 OTP ROM

FlexiHash+ Engine

POR/2.5V Regulator

Control Register

16x8 one-time programmable ROM memory. Additional programmable memory for storage.

Go to www.intersil.com for samples, datasheets and support

Intersil – Switching Regulators for precise power delivery. ©2007 Intersil Americas Inc. All rights reserved. The following are trademarks or services marks owned by Intersil Corporation or one of its subsidiaries, and may be registered in the USA and/or other countries: Intersil (and design) and i (and design).

Patent pending FlexiHash+ engine consists of four separate programmable CRC calculators. Two sets of 32-bit secret codes are used for authentication code generation. XSD single-wire host bus interface communicates with all 8250-compatible UARTs or a single GPIO pin. Supports CRC on read data and transfer bit-rate up to 23Kbps. 16 bytes of one-time programmable ROM memory for storage of pack information and ID, device authentication secrets, device default settings, and factory-programmed trim parameters.

editorial letter

Tell the truth: isn’t it a bit humorous—possibly even a little painful—to watch a 200-lb. man trying to answer his e-mail on his handheld wireless messaging device by typing with his thumbs? It wasn’t enough that computers forced a generation of adults to learn to type in order to escape becoming techno-relics. Now we have to type with our thumbs? Interacting with digital devices has always been a stretch for humans—OK, except maybe for Unix programmers, who can so relate. Humans remain stubbornly analog, and their input devices—mainly fingers and now thumbs—are the main limiting factor in designing interactive electronic systems. Today you could design a cell phone the size of a credit card, but no one could use it. Ergonomics may be the last frontier for electronics, but it’s a tough one. The keyboard remains our main input device. The QWERTY keyboard was patented in 1878 by C. L. Sholes, who built the prototypes of

Human-Interface Devices john donovan, editor-in-chief

the first commercial typewriter in a Milwaukee machine shop in the 1860s. The first keyboards were alphabetical, and the first machines were clunky. If you pressed two characters in rapid succession, the keys would lock up. Sholes solved this problem by making sure that the most common combinations required two hands to input. He created an illogical input device to accommodate the needs of the machine. In the 1960s, Xerox PARC did pioneering work on graphical input systems, inventing the graphical user interface (GUI) and the mouse, which were a huge step forward over typing arcane commands into a computer (Unix programmers notwithstanding). Add touch screens, and you have the main input systems we still use today.

PORTABLE DESIGN

But these human-interface devices (HIDs) are being stretched as portable products get both smaller and more interactive. You can’t really type on a keyboard that’s only a few inches wide. I’ve tried in vain to write with a script shorthand on the screen of my PDA, but the error rate is too high. The fallback is a “soft keyboard” on the touch screen on which you “type” with a stylus. Workable, if neither fast nor elegant. Star Trek may once again point the way forward. I’m thinking of the episode in which the crew of the Enterprise goes back to a time when Earthlings still used classic Apple McIntosh computers. Scotty picks up the mouse, holds it in front of his mouth, stares at the screen and says, “Computer?” Voice recognition systems have made great strides in the last several years. When properly trained to a person’s voice, they can give the user complete control over complex electronic systems. Most people can talk an order of magnitude faster than they can type. While not useful for all applications, voice recognition systems work well to control computers, toys and a potentially wide range of embedded systems. I’ve been trying voice recognition software for over a decade, and it’s always been more frustrating than useful. But more recently I was sent a leading software package to evaluate— and I’ve been using it daily ever since to write stories, send e-mail and make notes to myself. After a half hour of training, the program easily hits 95% accuracy and can be further trained on the fly. I can start up my e-mail program, look up addressee names, compose the message and send it, all without touching the keyboard. Voice recognition holds a lot of promise for a wide range of embedded devices, and it’s one area that portable designers—who have rightly ignored it to date—should investigate. Unless, of course, you really like typing with your thumbs.

dave’s two cents

Making a prediction and having it come true can be very rewarding, for example picking the winning lottery numbers. However, just predicting everyday events like sport scores and the best route past a traffic jam can also make you feel special. Predictions coming true are special mostly because they are such rare events. Certainly some things are more predictable than others. My wife feels that she can predict what I will do within the first five minutes of arriving home after work. She says it’s like predicting that the sun will rise tomorrow; after about 1.6 trillion times in a row—it is not much of a prediction. Out of the twenty-plus flights I took this summer, I only arrived once at my destination within 10 minutes of the initial predicted arrival time. The interesting thing is the number of predictions that occur during a flight. They usually are kicked off by the first announcement of a late departure. This prediction usually is followed by predictions of an even later departure. On one flight we ended up with a boarding delay of over three hours. Once everyone was on board, an equipment problem was identified. This resulted in three more predictions of how long it would take to fix it. In many ways predictions are like trying to find a lost object. It is always in the last place you look when lost becomes found. Similarly, predictions are most accurate when the future becomes now. In July, the FCC announced a ruling on the 700 MHz band auction [1]. Prior to this ruling, Google had proposed that the FCC include provisions for the auction that promoted a high degree of openness for part of the available spectrum. Google proposed four conditions of open access: open applications, open devices, open services and open networks. If these conditions were met, then they would bid $4.6 billion for the band. So what was Google’s prediction of the outcome? Only Google actually knows, but some predict that if Google did not get their four conditions, they would not bid. The FCC ruled that the conditions of open applications and open devices would be applied to a 22 MHz band. The open services and open network requirement was rejected. The FCC also set a minimum bid of $4.6B for this band. If the minimum bid was not reached, the conditions would be removed, and bidding would be restarted. This is truly material for lots of predictions. Some suggest that Google predicted that they would only be granted some of the conditions. This is like predicting what predictions might be. The FCC must be predicting that Google will

join the auction and make their $4.6B bid and afterwards, if they so desired, could provide open services and networks. It is interesting that the FCC set the minimum bid to what Google had offered. While Google, in making the request for openness and offering $4.6B, said what they

dave’s two cents on...

Can Anybody Predict What the Predictions Might Be? would do, did not say what they would not do. Open devices will allow consumers to pick their preferred wireless device to be used on the new band. Consumers also will be able to pick their favorite wireless applications. All of this picking still has conditions. The devices can not interfere with the general use of the network or security, and the network must be able to support the applications. The consumer still will pay for access to the network. In 1968, the FCC ruled that any compliant device could be connected to the telephone network. I am not sure anyone could have predicted the number of different devices that would use the phone lines, answering machines, FAX machines and even security monitors. This is probably the same for the open 700 MHz bands. It may start with just cell phones, but the predictions are much more. For my two cents, I predict our 10-digit phone numbers may be replaced by a 12 hexadecimal digit MAC or an even longer MAC. I also predict that I will never be able to remember that many characters in a row. Tonight, I am going to show my wife that I am not predictable. I’ll use my notebook on batteries while sitting in the recliner instead of on the couch with the adapter plugged in. Yes, just call me “Mr. Unpredictable.” Dave Freeman, Texas Instruments

http://hraunfoss.fcc.gov/edocs_public/ attachmatch/DOC-275669A1.pdf 1

SEPTEMBER 2007

news QuickLogic Is Now a “CSSP” Vendor

At a press event last month, QuickLogic CEO Tom Hart announced that QuickLogic is dealing itself out of the FPGA market and now wants to be thought of as a vendor of “customer-specific standard products,” or CSSPs. The company will continue production of its PolarPro and ArcticLink products, customizing them for the burgeoning mobile handset market. Since its founding in 1988, QuickLogic has struggled in the shadow of Altera and Xilinx in what Hart described as a “Coke and Pepsi” market. It’s done well in military markets—as has Actel—arguing the reliability of its products vs. the SRAM-based architectures used by its bigger competitors. But in consumer markets, where being “rad-hard” isn’t often important (one can only hope), it’s had trouble nd gaining traction. The CSSP approach is a radical new direcer exploration ether your goal tion for a programmable logic company. Hart speak directly makes the case that ASSPs are the most ecoical page, the ght resource. nomic solution to most design problems, if they technology, happen to suit your needs—which they rarely es and products will, at least completely. The low-cost, noed NRE and “quick time-to-market” arguments are hurdles that will always dog ASICs; as for structured ASICs, in Hart’s words, they’re “the last dying gasp of the ASIC industry,” requiring additional processing that is neither fast nor cheap. According to Hart, CSSPs are platforms companies providing solutions now developed for specific markets—smart phones exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, mp to a company's technical page, the goal of Get Connected is to put you in touchbeing with the right resource. target numberWhichever one. level of gy, Get Connected will help you connect with the companies and products you are searching for. QuickLogic’s two main products are Polaronnected Pro and ArcticLink. Aside from performance and non-volatility, PolarPro has one outstanding feature—extremely low power consumption; QuickLogic claims that PolarPro draws the same active current as a comparable CPLD, 1/10 the static power and 1/1000 the current in “inactive” mode (10 μA). This makes it well suited to mobile handsets, if QuickLogic can find the right socket for them. QuickLogic is supplying both PolarPro and ArcticLink with a wide range of interfaces alGet Connected with companies mentioned in this article. ready instantiated (USB 2.0 OTG, SD, SDIO, www.portabledesign.com/getconnected MMC, CE-ATA, managed NAND, etc.).

End of Article

PORTABLE DESIGN

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They’re supplying software drivers for most standard CPUs and graphics processors as well as support for Windows Embedded and Linux. Customers can buy these chips with, say, 90%

of the capability they need already programmed in—the other 10% being “customizable building blocks” of custom logic and GPIO. The standard products then become “customer specific.” ArcticLink is now a “programmable connectivity solution platform.”

From FPGA to CSSP

The change to CSSPs for QuickLogic has more to do with marketing positioning than technology. ArcticLink, introduced last March, already contains all of the capabilities just mentioned burned into silicon. But FPGA companies don’t get in the front door with handset vendors. However, if you’re selling a multimedia bridge chip that also promises to solve all your I/O and interface problems, that’s another matter. This refocusing makes a great deal of sense for QuickLogic, particularly since they already have the parts in production. How effectively they can grab some notably sticky handset sockets remains to be seen. In some ways it’s ironic to see a programmable logic vendor move from selling large blocks of blank logic to almost fully programmed devices—the domain of their arch-enemy ASICs, which are not so much “application specific” as “customer specific.” Competitive reasons aside, QuickLogic’s move seems a natural outgrowth of the path that FPGA companies have traveled over the last 10 years. In the days when programmable logic was

simple, vendors initially competed to see who could put out chips with the most gates. But as applications became more complex, FPGA vendors started to work more closely with their customers to be able to design chips that would meet their increasingly demanding requirements. This led to more and more inhouse systems expertise, increasing libraries of soft cores and industry-specific “ecosystems” to fill in the technology gaps. FPGA vendors started developing devices customized for specific applications. QuickLogic’s decision this week to reposition their devices as “customer specific” follows that path to a logical conclusion.

Congratulations to Ubiquiti and the Italian hams. Obviously, don’t expect this system to arrive in your local Best Buy any time soon. Ubiquity Networks, Inc., Milpitas, CA. (408) 942-3085. [www.ubnt.com].

MIPS Acquires Chipidea

MIPS Technologies, Inc. has announced that the company has acquired privately held Chipidea Microelectrónica S.A, a leading independent supplier of analog and mixed signal intellectual property (IP) for the wireless, digital

Bothered that your home Wi-Fi signal gets weak when you want to do email from your back deck? Maybe what you need is a highpowered transmitter and a 35 dBi parabolic dish on both ends! Ubiquiti Networks and the Italian Center for Radio Activities (C.I.S.A.R), an association founded by a group of Italian radio amateur operators, today announced the new world record for a 5 GHz Wi-Fi link achieving a distance of 304 km (188.89 miles) across land and sea. The link was established using Ubiquiti’s XtremeRange5 High-Power Carrier Class mini-PCI radio modules—rated at 28 dBm output for a 6 Mbit/s data rate—and 35 dBi 5 GHz parabolic dish antennas. The link extends from Sardinia Island to Central Italy achieving data-rates of about 5 Mbits/s. It allows ham operators on Sardinia Island to stay in touch with their community on the Italian Peninsula. The first alignment was made by providing a beacon through a semi-directional antenna (short-backfire 17 dBi, 25°V, 25°H) on the Sardinia Island and one of the two 35 dBi antennas on Monte Amiata (Amiata Mountain) about 5,220 feet (1,740m) above sea level.

MIPS Technologies, Inc., Mountain View, CA. (650) 567-5000. [www.mips.com].

Ericsson and Texas Instruments to Co-Develop 3G Solutions for Handset Manufacturers

–John Donovan QuickLogic Corporation, Sunnyvale, CA. (408) 990-4000. [www.quicklogic.com].

World Wi-Fi Distance Record— 190 Miles

nesses. Chipidea will become a newly formed business group within MIPS Technologies, with its complete product portfolio continuing to be sold under the Chipidea brand. Jose Franca will assume the role of president and general manager for the new business group and has been appointed a member of the board of directors for MIPS Technologies. Currently, Chipidea has more than 310 employees worldwide, including design centers in Portugal, France, Belgium, Poland, China, Norway and Macau.

consumer and connectivity markets. The combined entity becomes the second largest semiconductor design IP company and the number one analog IP company worldwide, based on Gartner, Inc.’s recent 2006 rankings. According to MIPS, the acquisition creates a unique technology portfolio and delivers a powerful value proposition to customers as they gain access to a broad array of leading analog IP that fuels next-generation SoC (system on chip) designs. Within the last five years, Chipidea has grown its customer base from 20 to more than 150— including 13 of the world’s top 15 semiconductor companies. Gartner consistently ranks Chipidea either first or second in design IP for A/D and D/A converters, wireless interfaces and connectivity solutions—which today includes USB and in the future will address HDMI and other emerging high-speed interface standards. The worldwide semiconductor IP market grew 24% to $1.8 billion in 2006, according to Gartner, Inc. Today, the analog and mixedsignal IP market represents the fastest growing segment in the semiconductor IP market. Following the transaction, MIPS intends to quickly integrate the two companies and busi-

Ericsson and Texas Instruments have announced that the companies will form a strategic technology engagement to develop custom solutions for new Open OS-enabled 3G devices. Solutions from the technology created by the two companies will combine 3G modems from Ericsson Mobile Platforms with OMAP applications processors from TI. Solutions from the joint engagement will include OMAP, custom basebands and connectivity technologies and will be capable of supporting the major Open OS, which offers easy access to a rich array of applications and services. The result of this joint effort will enable all device manufactur-

ers to offer advanced Open OS handsets for both the high-end and the rapidly growing midrange market. Ericsson’s access technology, current HSPAenabled platforms and future HSPA evolution and LTE technologies, combined with the mulSEPTEMBER 2007

news timedia performance enabled by TI’s OMAP 2, OMAP 3 and future generations of OMAP processors, are intended to push the performance boundaries of mobile devices and mobile entertainment features. By leveraging TI’s OMAP platform with Open OS support for Windows Mobile, Symbian S60, Symbian UIQ and Linux, these solutions will provide OEMs and operators with a robust and flexible architecture for applications and services deployment. This will enable handset manufacturers and mobile operators to differentiate their products through easy-to-use and customizable user interfaces, and through a robust and flexible application architecture. Handsets based on these solutions are expected to be available on the market in the second half of 2008.

Texas Instruments Inc., Dallas, TX. (800) 336-5236. [www.ti.com].

er exploration ether your goal speak directly ical page, the ght resource. technology, es and products

Intel to Move NOR Flash Memory Products for Embedded to 65 nm Process Technology

Intel Corporation has announced its plans to extend its embedded NOR flash products to the 65 nanometer (nm) generation. According to the company, the move to 65 nm process technology will provide price/performance balance and ensure support for extended product life cycles, both important factors to original companies providing solutions now equipment manufacturers (OEMs) designing exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, mp to a company's technical page, the goal of Get Connected is to put you in touchfor withembedded the right resource. Whichever level of Intel’s 65 nm market segments. gy, Get Connected will help you connect with the companies and products you areproducts, searching for. which are typically used in consumer onnected electronics devices, wired communications equipment and industrial applications, are expected to start sampling to customers in the first half of 2008. Intel NOR wireless products are already being manufactured in high volume on this leading-edge process. The move to 65 nm process for embedded will enable Intel to support the longer product life cycle, as well as offer enhanced product features and cost efficiencies. Intel NOR product offerings for embedded market segments Get Connected with companies mentioned in this article. include both parallel and serial solutions. Intel www.portabledesign.com/getconnected StrataFlash Embedded Memory (P30/P33) is

End of Article

PORTABLE DESIGN

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Intel’s lowest cost-per-bit, high-density, highperformance single chip code and data solution. Intel Embedded Flash Memory (J3 v.D) offers drop-in compatible upgrade paths for legacy designs. Its enhanced features support mainstream embedded applications that need

value and scalability. The industry-standard Intel Serial Flash Memory (S33) simplifies board design and saves board space with a low pincount interface and smaller package for a range of applications such as TVs, DVDs, PCs, modems and printers. Intel Corporation, Santa Clara, CA. (408) 765-8080. [www.intel.com].

Accellera Approves Functional Design Verification Standard

Accellera, the electronics industry organization focused on Electronic Design Automation (EDA) standards, has announced that its Board of Directors, representing semiconductor, Intellectual Property (IP), EDA companies and systems houses, approved Accellera’s Open Verification Library (OVL) 2.0 as an Accellera verification standard last month. OVL improves electronic design quality and supports Assertion-Based Verification (ABV) with Verilog, SystemVerilog, VHDL and the Property Specification Language (PSL). The Accellera OVL standard includes a library of assertion checkers provided as an open standard. It improves electronic design verification when using Hardware Description Languages (HDLs) and results in better quality designs by enabling effective use of ABV methodologies. The Open Verification Library 2.0 standard is an open source version of assertion checkers, allowing reuse in various verification environments.

The Accellera Standard OVL 2.0 is available now for download at the Accellera Web site. More information and examples are available at a users’ site: www.eda-stds.org/ovl. Accellera Organization Inc., Napa, CA. (707) 251-9977. [www.accellera.org].

What’s New

“OVL has been used for five years as a vendor-neutral and language-independent assertion methodology to functionally verify designs in simulation and formal verification environments. OVL version 2.0 represents a major step forward for users, while still being fully backward compatible with earlier versions,” according to Mike Turpin, Accellera OVL technical subcommittee chair. A powerful new feature in OVL is the ability to synthesize assertions into emulators, accelerators and FPGA prototyping environments, extending assertion-based verification with OVL to support the full verification flow, with simulation, formal verification, hardware-assisted verification and FPGA prototyping. Version 2.0 adds synthesizable checkers that include “enable” and “fire” ports for additional control of the checkers when used in hardware flows including emulation, FPGA prototyping or ASIC error detection. There are also 17 new and more advanced checkers, taking OVL to a total of 50 assertion checkers that cover many of the common properties that engineers check during functional verification. There is now a VHDL implementation of the 10 most popular checkers, and finer control of X checking on a per-instance basis. Version 2.0 is backward compatible with previous versions of Accellera OVL. Accellera OVL technical committee was formed in early 2005 and the first OVL standard was announced in August 2005. In addition to creating more checkers and maintaining the standard, the committee plans to add features and welcomes new members and contributions.

Need for Interoperable Radio Communications in U.S. Public Safety Sectors

Hurricane Katrina and the terrorist attacks of 9/11/01 have called considerable attention to the need for enhanced radio communications in the public safety sector. In both cases, first responders’ operational capacity was compromised by their inability to communicate with each other in real time. But this lack of interoperability is not just a technology problem but one also related to such factors as intellectual property rights, standards and marketing, according to a new study commissioned by the Software Defined Radio (SDR) Forum (www.sdrforum.org), a nonprofit international industry association for reconfigurable wireless technology, and prepared by Jim Gunn, a noted market research and technology consultant specializing in digital wireless communications and multimedia communication systems. The 84-page study (“The U.S. Public Safety Market”), which involved interviews with public safety communication officials from around the country, provides a comprehensive look at a very fragmented market consisting of a multitude of federal, state and local agencies; city, county and regional jurisdictions; and police, fire and emergency medical functions. It points out that, historically, each of these diverse organizations has independently procured, operated and maintained its own public land mobile radio (PLMR) communication system but that these functions are not usually a focus for senior public officials with other professional experiences and priorities. “PLMR is usually delegated to communication professionals,” the report says, “which appears to have created an environment with

generally good local coordination and information, but less than desirable state, national and international coordination, visibility and general market information.” Among the study’s findings is that without consistent and adequate policies, standards and guidelines regarding public safety communication systems, first responders sometimes lack the means to coordinate their routine activities, let alone communicate effectively in stressful emergency situations. The report goes on to cite five key challenges (identified by the National Task Force on In-

teroperability) to interoperability of public safety communication systems: incompatible and aging communication equipment; limited budgets and funding; fragmented planning and coordination; insufficient spectrum; and inadequate equipment standards. Some of these challenges, the study notes, fall within the realm of SDR’s potential. For example, recent advances in semiconductor, RF and data acquisition technologies provide imminent market opportunities for SDR to extend programmability for more transceiver algorithms and to more extensively achieve the technology’s long-verified benefits, such as lower development costs and enhanced flexibility in developing, customizing and deploying fielded products. SDR Forum, Denver, CO. (303) 628-5461. [www.sdrforum.org].

SEPTEMBER 2007

analysts’ pages Real Men Are Fabless; Qualcomm Enters Semiconductor Top-10 in Q2

According to iSuppli Corp., it’s time to add the phrase, “Real men have fabs” to the list of laughably outdated clichés, along with classics like “If man was meant to fly, he’d have wings” and “The world needs only five computers.” That’s because Qualcomm Inc., a company that

Q1-07 Rank

Q2-07 Rank

Intel

7,868

7,728

-1.78%

12.25%

Samsung Electronics

4,835

4,716

-2.46%

7.48%

19.73%

Texas Instruments

2,900

3,030

4.48%

4.80%

24.53%

Toshiba

3,109

2,510

-19.27%

3.98%

28.51%

STMicroelectronics

2,276

2,418

6.24%

3.83%

32.35%

Renesas Technology

1,948

1,985

1.90%

3.15%

35.49%

Hynix

2,539

1,963

-22.69%

3.11%

38.61%

NXP

1,427

1,472

3.15%

2.33%

40.94%

Qualcomm

1,259

1,367

8.58%

2.17%

43.11%

Infineon Technologies

1,282

1,363

6.32%

2.16%

45.27% 100.00%

er exploration ether your goal speak directly ical page, the ght resource. technology, es and products

Company Name

Q1-07

Q2-07

% Change

% of Total

All Others

35,975

34,519

-4.05%

54.73%

Total Market

65,418

63,071

-3.59%

100.00%

Cumulative Percentage

Quarterly Semiconductor Market Shares--Q1-’07 Through Q2-’07 (Ranking by Revenue in Millions of U.S. Dollars) Source: iSuppli Corp. August 2007

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doesn’t own a single semiconductor production factory, ascended to the Top-10 ranks of the global chip industry in the second quarter, marking the first time a fabless company has achieved such a distinction. Qualcomm, a U.S.-based fabless semiconductor supplier, rose to the ninth position among global semiconductor suppliers in the second quarter, up from 13th in the first quarter. The seller of communications chips in the second quarter achieved revenue of $1.4 billion, up 8.6 percent from $1.3 billion in the first quarter. On its way from 13th to ninth place,

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Qualcomm surpassed companies with considerable manufacturing assets, including Infineon Technologies AG, Qimonda AG, Freescale Semiconductor and NEC Electronics Corp. Qualcomm now stands shoulder-to-shoulder with chip manufacturing powerhouses including NXP Semiconductors and Hynix Semiconductor Inc. The table presents iSuppli’s ranking of the Top-10 semiconductor suppliers in the second quarter of 2007.

Qualcomm’s Coups

Recent headlines covering Qualcomm’s legal troubles notwithstanding, the company achieved stellar results in the second quarter. The company’s 8.6 percent increase represented the highest growth rate of any Top-10 semiconductor supplier in the second quarter—and marked a significant accomplishment amid a decline in overall chip revenue. Global semiconductor revenue declined by 3.6 percent to $63.1 billion in the second quarter, down from $65.4 billion in the first quarter. The company in the first quarter replaced Texas Instruments Inc. as the world’s top supplier of semiconductors for wireless applications. This marks the first time that Texas Instruments has not occupied the leadership position in this area, at least since iSuppli began tracking such market share in 2004. With its valuable intellectual property, Qualcomm is capitalizing effectively on the transition to 3G technology in the mobile handset market. iSuppli doesn’t expect the International Trade Commission’s (ITC’s) decision to ban U.S. imports of some mobile phones that include certain Qualcomm chips to significantly damage the company’s third-quarter results. iSuppli Corporation, El Segundo, CA. (310) 524-4000. [www.isuppli.com].

Video-Enabled Portable Media Players Will Outsell Audio-Only Models by 2009

Driven by increased broadband penetration, declining price points and a growing catalog of online audio and video content, the market

In-Stat, Scottsdale, AZ. (480) 483-4440. [www.in-stat.com].

DRAM Price Downturn to Arrive a Month Early

Following a brief respite, iSuppli Corp. predicts that market conditions for DRAM suppliers are set to take a turn for the worse in September. iSuppli previously forecasted that DRAM prices would undergo a downward correction in October, following the current period of relative strength that brought an end to a phase of severe erosion in the second quarter. However, iSuppli now believes the DRAM prices will begin to decline one month earlier, in September. Near-term market conditions remain in a state of flux with a great deal of uncertainty in the

Percentage Annual Revenue Growth

for MP3 players and portable media players (PMPs) will remain strong over the next five years, reports In-Stat. Nevertheless, according to In-Stat’s latest primary research, the main reason consumers are purchasing portable MP3 players and video-capable PMPs today is for the devices’ audio playback capability, the high-tech market research firm says. “Only 11% of survey respondents say they will purchase a PMP primarily for its video playback function,” says Stephanie Ethier, InStat analyst. “Still, the cost of incorporating video into portable devices continues to decline. As a result, In-Stat expects shipment growth of video-enabled PMPs to outpace that of audioonly MP3 players by the end of 2008.” Recent research by In-Stat found the following: • Worldwide unit shipments for audio-only MP3 players and PMPs combined will reach 275 million units in 2011, up from 182 million in 2006. • Of the 2,408 respondents to In-Stat’s latest survey of U.S. consumers, 52% own an MP3 player or PMP. • In-Stat does not expect music-enabled cell phone shipments to displace dedicated PMP/ MP3 player shipments any time soon, but there is an opportunity for cell phone manufacturers to capture those consumers who are considering cheap, audio-only MP3 players.

25% 20% 15% 10% 5% 0% -5%

2007

2008

2009

2010

2011

-10% -15%

Annual Global DRAM Market Revenue Growth Forecast Source: iSuppli Corp. August 2007

supply chain as suppliers and distributors continue to work off a glut of DRAM inventory. Furthermore, sales momentum is waning in the DRAM spot market, as rising prices and falling supply of LCD panels cut into the available budget for memory in some PCs. This is bad news for memory suppliers, which had been basking in the present period of relative pricing strength. Weak pricing in September will set the stage for further erosion in the fourth quarter. iSuppli now foresees the possibility of doubledigit sequential price declines in the fourth quarter, erasing any increases that aided suppliers in the third quarter. Because of Untitled-2 1

SEPTEMBER9/21/07 2007 10:52:58 13 AM

analysts’ pages this, DRAM suppliers’ profitability will dwindle in the fourth quarter compared to the third, iSuppli predicts. Amid signs of improvement in pricing, iSuppli in July upgraded its rating of nearterm market conditions for DRAM suppliers to “neutral,” up from “negative.” OEM DRAM prices increased in the first half of July after the market hit bottom at the end of

2006 Market Share

Revenue ($ Millions)

Rank

Company Name

2005

2006

Percentage Change

Percentage

Toshiba

5,336

6,131

14.9%

11.6%

Sony

4,012

4,838

20.6%

9.1%

Samsung Electronics

2,617

3,033

15.9%

5.7%

er exploration 4 ether your goal speak directly 6 ical page, the ght resource. technology, es and products

Matsushita Electric

2,425

2,398

-1.1%

4.5%

Hynix

1,569

1,913

21.9%

3.6%

Others

30,645

34,746

Total

46,604

53,059

13.9%

100.0%

2005

2006

Top-5 Suppliers of Semiconductors to Consumer Electronics Applications in 2006 and 2005 (Ranking by Revenue in Millions of U.S. Dollars) Source: iSuppli Corp. August 2007

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June. The main reason for the price increases

was reduction exploration into products, technologies and companies. Whether your goal is to research the alatest datasheet in fromproduction a company, among DRAM mp to a company's technical page, the goal of Get Connected is to put you in touchmakers, with the right resource. Whicheversupply level of and demand which brought gy, Get Connected will help you connect with the companies and products you areback searching for. into balance.

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“By reducing their output, DRAM suppliers have helped bring about higher pricing in the third quarter,” said Nam Hyung Kim, director and chief analyst for memory ICs/storage systems at iSuppli. “But OEMs and the channel are still working off the inventory oversupply left over from January, which will make it a difficult fourth quarter for memory manufacturers. Furthermore, the shortage of LCD panels is preventing white-box PC makers from purchasing more DRAM. Increasing panel prices also are slowing DRAM content growth in PCs in the third quarter.”

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However, suppliers’ efforts to cut production starting in the third quarter will play an important long-term role in strengthening the DRAM market. Global annual bit growth in 2008 will amount to less than 60 percent, compared to the explosive 97 percent bit growth expected in 2007. This will help rebalance supply and demand in the market. Because of this, iSuppli remains optimistic about DRAM market conditions in 2008. iSuppli still anticipates that NAND flash will undergo a downward price correction in September. Despite all this, iSuppli is not reducing its rating of DRAM market conditions to “negative” at this time. iSuppli predicts global DRAM revenue will rise by 17.5 percent in 2008, following weak growth of less than 2 percent in 2007. iSuppli Corporation, El Segundo, CA. (310) 524-4000. [www.isuppli.com].

Ultra Mobile Device Market Will Be Defined by Multiple Forms

The ultra mobile device market, initially defined by the ultra mobile PC, is evolving to become a family of devices that will compose the “ultra mobile device (UMD) paradigm,” reports In-Stat. One ultra mobile device will not be able to meet all of the different UMD usages/applications, the high-tech market research firm says. Three key features differentiate UMDs from products like PDAs and smart phones. First, UMDs must run a full operating system. Second, they must run any application as originally developed and compiled for PCs or notebooks. Third, UMDs must run full Web pages unmodified (including flash and java applets) to provide complete Internet experiences. “The new paradigm also requires specific market inflection points in the mass availability of anytime/anywhere wireless communications, as well as new business models for application programs for widespread adoption,” says Ian Lao, In-Stat analyst. “Many of these requirements are already in the late stages of development or roll-out.”

Recent research by In-Stat found the following: • The UMD worldwide forecast is for more than 8 million units in 2011. • 2008-2010 will be key years for the development of a market inflection point of anytime/ anywhere wireless connectivity that is necessary for widespread adoption of the UMD paradigm. In-Stat, Scottsdale, AZ. (480) 483-4440. [www.in-stat.com].

Hynix Advances in 2006 Consumer Electronics Chip Rankings

Riding a surge in demand for Portable Media Players (PMP)/MP3 players, Hynix Semiconductor Inc. in 2006 posted a standout performance in the global consumer-electronics chip business, according to iSuppli Corp. Hynix of South Korea in 2006 advanced one position in iSuppli’s ranking of top consumer-electronic chip suppliers, displacing Renesas Technology Corp. of Japan to take fifth place. The rise was due to Hynix’s strong sales of NAND-type flash memory for PMP/ MP3 products. Total PMP/MP3 unit shipments surged to 178.1 million in 2006, up 38.4 percent from 128.7 million in 2005. Hynix expanded its PMP/MP3 revenues to $831 million in 2006, up 42.9 percent from $582 million in 2005. That increase was the highest among the three key suppliers to the PMP/MP3 market: Samsung Electronics Co. Ltd. of South Korea, Japan’s Toshiba Corp. and Hynix. These three companies together accounted for more than 97 percent of global PMP/MP3 NAND flash memory revenue in 2006.

Market Stability

“Hynix’s performance was particularly notable given the relative stability of the overall rankings in 2006,” said Chris Crotty, senior analyst for consumer electronics at iSuppli. “The Top-10 ranked suppliers for total consumer-electronics semiconductors remained the same from 2005 to 2006,

despite some shifts in positions compared to 2005.” Large, vertically integrated manufacturers continued to dominate the $53.1 billion consumer electronics semiconductor market in 2006, with Toshiba, Sony, Samsung and Matsushita retaining their first through fourth positions, respectively. Renesas of Japan fell three positions in the global ranking, declining to 8th place, down from 5th in 2005. As a whole, the Top-10 suppliers accounted for nearly 50 percent of all consumer-electronics semiconductor revenue during 2006.

PMP/MP3 Market Machinations

Meanwhile, nVidia Corp. of the United States—due to its acquisition of PortalPlayer Inc.—passed fellow American firm SigmaTel Inc. to take the top spot for PMP/MP3 controller chips. nVidia’s PMP/MP3 revenue reached $173 million in 2006, despite the earlier loss of the Apple iPod nano design win to Samsung. China’s Actions Semiconductor Co. Ltd., which also moved past SigmaTel to take the No. 2 spot, actually shipped the most controller units by far, at 75.3 million in 2006. But just as Actions arose in 2005 and 2006 to challenge the market pioneers PortalPlayer and SigmaTel, a new wave of competitors emerged in late 2006 and early 2007 to confront Actions. These new competitors include startups such as Rockchip, Taiwanese fabless suppliers like Silicon Motion Technology Corp. and Sunplus Technology Co. Ltd., and even broad-line suppliers like Analog Devices Inc. and Texas Instruments Inc. of the United States.

from integration trends and new Bluetooth standards hitting the market, the high-tech market research firm says. The market for Bluetooth chips is also in flux. “The Bluetooth silicon market is beginning to see some consolidation, as larger silicon vendors add new capabilities, such as Wi-Fi and GPS, to their chip portfolios, either by internal development or acquisition,” says Brian O’Rourke, In-Stat analyst. “The goal is to create combined radio silicon that is being demanded by mobile phone vendors.” Recent research by In-Stat found the following: • Growth of Bluetooth devices will increase by 34% in 2007, slowing from the recent past. • Wireless chip companies are seeking to offer integrated radio chips with Bluetooth, Wi-Fi, GPS, and FM. • New low power and high data rate Bluetooth standards will emerge over the next two years. • According to recently conducted In-Stat surveys, France, Germany and the UK have the highest percentages of those extremely or very familiar with Bluetooth. Korea and Japan had the lowest percentages, while the U.S. was in the middle. In-Stat, Scottsdale, AZ. (480) 483-4440. [www.in-stat.com].

iSuppli Corporation, El Segundo, CA. (310) 524-4000. [www.isuppli.com].

Bluetooth Market Continues Growth, but Rate Is Slowing

Bluetooth had another successful year in 2006, and it will have continued success in 2007, led by its increasing penetration into mobile phones, reports In-Stat. However, market growth for Bluetooth products is beginning to slow, and it will see some complications arising SEPTEMBER 2007

cover feature memory interfaces

High-Performance, Low-Power, LowCost Off-Chip DRAM: Can I Use it in My Portable Design? The answer is yes, if you choose wisely from among a wide range of options.

by Marc Greenberg, Technical Marketing Manager, Denali Software, Inc.

Consumer demand for more features and higher performance from their portable electronic devices is driving significant change in the memory requirements for these products in terms of speed, capacity and overall system architecture. A few years ago, a small amount of embedded memory or a small off-chip SRAM was sufficient for a typical portable device such as a mid-range cell phone. The feature set for todayâ&#x20AC;&#x2122;s portable electronics is much different, requiring significantly greater capacity and performance capabilities to satisfy advanced media storage and playback requirements. Fortunately, there is a host of new and emerging memory technologies to address these growing requirements, such as Low-Power SDRSDRAM, PSRAM, LPDDR1 and LPDDR2. In some cases, even DDR2 or DDR3 may be used for the highest bandwidth requirements. This article will discuss some of the new and emerging devices and memory system archi-

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tectures that can be applied to idealized portable devices, and how DRAM can be efficiently incorporated into these system designs. The article also addresses design for power savings, and the future of Low-Power DRAM.

How Is Memory Used in Portable Devices?

In contrast to non-portable designs, a large number of different portable devices use Dynamic Random Access Memory (DRAM)â&#x20AC;&#x201D;for example, cellular telephones, Personal Media Players (PMPs), Personal Digital Assistants (PDAs), Ultra-Mobile PCs (UMPCs), Global Positioning Systems (GPS) and video cameras. These systems tend to have powerful Central Processing Units (CPUs) that require more memory than what is economically feasible in embedded memory, and hence, these systems typically use off-chip DRAM. A common thread among portable devices

cover feature using off-chip DRAM is that these are rapidly changing technologies, where new features are introduced frequently to entice consumers into buying the latest product—and not a competitor’s product. The addition of larger amounts of fast memory typically allows devices to operate faster, carry more applications, run more powerful applications, provide better graphics and support fast off-chip interfaces. There are a number of possible memory architectures for portable devices, however. These can be broadly grouped into “execute-in-place” and “store-and-download” architectures. Execute-in-place architectures are often used when NOR Flash memory is present in the system. A particular feature of NOR Flash is that it allows program instructions to be executed directly from the NOR Flash device without first having stored the program instructions in DRAM. Another property of NOR Flash devices is that they adhere to a similar memory protocol as Static RAM (SRAM) or Pseudo-Static RAM, and therefore NOR Flash and SRAM/PSRAM are often found sharing the same memory bus, for example in 2G cell phone systems. When more DRAM bandwidth or more memory capacity is needed, we see a shift to the store-and-download architecture where program code is stored in Non-Volatile Memory (NVM) that does not support random access at high speed, for example NAND Flash. In this case, program code is downloaded from NVM into DRAM when the portable device is booted, and the CPU fetches its program code from the DRAM in normal operation. New techniques allow boot from NAND Flash without the assistance of another flash device or ROM in the system. There are also some “Managed NAND” devices, Samsung’s OneNAND for example, that may allow execute-in-place even if using NAND Flash devices. While some people may worry about power consumption and boot time of the store-anddownload method, very often our recommen-

table 1 Feature

DDR1

LPDDR12

I/O Pad Type

SSTL_2

LVCMOS_18

I/O Voltage and supply voltage

2.5V

1.8V

I/O Switching Voltage

Based on input reference voltage

Based on absolute voltage level

DLL used for timing?

DLL Used

No DLL in memory

tAC timing

+/- 0.75 ns (1.5 ns window)

+2 to +6 ns (4 ns window)

Current used in self-refresh mode at 70c

4 mA (10 mW)

300 uA (540 uW)

Current used on read commands (IDD4R)

185 mA (463 mW)

95 mA (171 mW)

Idle Standby Current (IDD2F/ IDD2N)

45 mA (113 mW)

20 mA (36 mW)

A comparison between DDR1 and LPDDR1 memories. (1 MT46V16M16BG-75 2 MT46H16M16LFBF-75)

dation is to download the necessary data from NVM into LPDDR-SDRAM at boot-up and then leave the SDRAM in Self-Refresh mode when the device is off. A full reboot would only be necessary when the battery is completely drained or removed, or if the user requests a hard reset. With a typical self-refresh current, an average cell phone battery can keep the SDRAM refreshed for more than a month. In the future, LPDDR-SDRAM and LPDDRNVM will share the same bus and provide more bandwidth and capacity than the previous generation technology of sharing NOR Flash and PSRAM on the same bus.

Low-Power Memory Features

DRAM devices can be considered to have three major parts: The memory array where data is stored, including its associated control logic; the I/O pads of the memory devices; and the physical layer (PHY) that allows the memory array to interface to the Input/Output (I/O) pads. SEPTEMBER 2007

cover feature

A low-power DRAM array typically starts its life as the memory array used in one of the mainstream technologies such as Personal figure 1 Computers (PCs) or servers; later the same memory array Capacity is adapted for use in low-power memory 128MB DDR3 16bit systems. When the arLPDDR1 ray gets migrated from DDR2 32bit 64MB 32bit Future LPDDR1 LPDDR1 mainstream to low32bit 16bit 32MB power use, the array might stay relatively Future LPDDR1 16MB 16bit the same, with the typical addition of new LPSDR LPSDR 8MB 16bit 32bit Self-Refresh features. DRAM devices rePSRAM <8MB quire periodic refresh nd 16 Gbit/s cycles to keep the con2 4 8 tents of the memory er exploration Peak Bandwidth ether your goal array from deterioratspeak directly ing. During normal ical page, the ght resource. read/write operation, Off-Chip Low-Power DRAM Choices technology, the refresh cycles are es and products inserted into the comed mand stream by the memory controller. There is another refresh mode, Self-Refresh mode, where most parts of the memory are turned off and the memory array is refreshed by a self-timed circuit within the memory. Self-Refresh is a DRAM feature companies providing solutions now that implemented both Double-Data Rate exploration into products, technologies and companies. Whether your goal is to research the is latest datasheet from in a company, mp to a company's technical page, the goal of Get Connected is to put you in touch(DDR) with the and right resource. Whichever level(LPDDR) of Low-Power DDR memgy, Get Connected will help you connect with the companies and products you areory searching for. families. onnected Low-Power memories typically add two new features to the memory array. TemperatureCompensated Self Refresh (TCSR) allows the memory to determine how often to refresh its internal array while in Self-Refresh mode by sensing the temperature of the device; power usage in refresh is then optimally matched to the temperature requirements of the device. The other new feature, Partial-Array Self-Refresh (PASR), allows the user to specify which parts of the memory array to refresh during Self-ReGet Connected with companies mentioned in this article. fresh mode; other parts of the memory are not www.portabledesign.com/getconnected refreshed, saving power. TCSR and PASR are

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features of LPDDR memory technologies, as well as DDR3 and some DDR2 devices. The next noticeable change on low-power DDR memories is that they use CMOS signaling instead of the Stub-Series Terminated Logic (SSTL) I/O pads common in mainstream technologies. This typically results in a substantial reduction in the current used in Low-Power memory I/Os, although at a cost of worse timing margins. The third noticeable change between mainstream memory and Low-Power memory is a change in the PHY. Mainstream DDR memory uses a Delay-Locked Loop (DLL) to control output data timing from the memory; in LPDDR the DLL is not present. Again, this power reduction has the cost of worse timing margins. We can see the effects of these changes to LPDDR memories in Table 1, which compares two similar DDR1 and LPDDR1 devices. Table 1 lists the access time of the memory (the time at which data appears after the clock) that is significantly degraded by the change in the I/Os and removal of the DLLs. This makes data capture more difficult in LPDDR devices than in equivalent DDR devices. The benefit is almost a 3X reduction in power on reads and in the idle state. Finally, a cautionary note: Although the I/O pads used for LPDDR devices are typically of the LVCMOS type, it is not always possible to reach the rated speeds of the memory with all LVCMOS pads. Taking this into account, care should be taken to review the specification of the LVCMOS pad used on your chip to make sure it is compatible with the highest speed that you wish to operate your LPDDR memory.

Memory Selection

Memory selection for portable devices is based on a number of factors: cost, capacity/density, performance, power, availability, past experience and availability simulation models and IP such as memory controllers, physical layer interfaces (PHYs) and I/Os for the chosen memory technology and chip production technology.

cover feature Cost-per-bit is usually lowest for the newest and highest density technology, as long as it is not so new that the memory device attracts a premium because of its newness. The challenge then for the portable designer is to find a memory that meets all of the goals above. A particular problem for many portable and embedded devices is that the newest memory types are often too large for the application—a consequence of the memory arrays having been developed for the PC market, where bigger is always better. In the embedded case, if you select a memory type X with 40% lower cost per bit than memory type Y, but the smallest capacity of memory type X is twice as large as what your product needs, then you may have made your end product more expensive than it needs to be. Another problem that sometimes faces the designers of embedded products is the availability of memory devices of the correct width for the memory bandwidth that is needed by the system. While DDR2 and DDR3 memories are only available in maximum 16-bit widths, most Low-Power DRAM technologies are available with a 32-bit memory data width on a single die. Figure 1 displays recommended off-chip DRAM choices for a range of memory densities and system bandwidths. Note the logarithmic scales. Data is approximate.

Effective DDR Memory Power Saving Techniques

Table 1 showed us about a 3X reduction in power in some of the common operation modes of the memory that is achieved by changing from a standard DDR to LPDDR memory. But the number is still high, and the devices do still use a significant amount of a battery’s power if they are left inactive. Clearly, it’s desirable to have the memory in the lowest power mode possible. DDR and LPDDR devices are provided with three main power-saving modes: • Active Powerdown, where the I/Os are disabled. • Precharge Powerdown, where the device pre-

viously had the memory array returned to the idle state before entering Powerdown. • Self-Refresh, as described previously. It should be noted that the DLL in DDR devices is turned off in this mode to save power, it must be re-enabled before using the memory after exiting self-refresh, which can take over 100 ns. Additionally, system power can be saved by gating clocks, power gating and other techniques in the memory controller and PHY. An advanced memory controller design will enable smart power management within the memory controller itself, the PHY, the ASIC I/Os and the memory by detecting the system demands for memory access and selecting the appropriate power modes, driving the memory into the lower power modes as soon as it is practical to do so after a memory access.

The Future

The future direction of Low-Power DRAM is LPDDR2, a standard that is under development at JEDEC. Denali Software is an active participant in the LPDDR2 committee, and while confidentiality obligations prevent the disclosure of detailed specifications, it can be assumed that LPDDR2 devices will be faster and lower voltage than LPDDR1. Look for announcements from JEDEC and from Denali Software in the near future. Memory selection for portable and embedded systems is a challenging task because of the wide choices of memory available and the trade-offs between performance and density. We hope this article has served as a useful memory selection guide, and that you now have the knowledge to select Low-Power DRAM memory for your next design. Denali Software, Inc. Palo Alto, CA. (650) 461-7200. [www.denali.com].

SEPTEMBER 2007

cover feature memory interfaces

Leverage Embedded Non-Volatile Memory to Improve Yield and Enhance System Options Including non-volatile memory in your ASIC can supply the flexibility you might otherwise have lost.

by Charles Ng, Vice President of Sales, Kilopass Technology Inc.

In the world of portable and even line-operated consumer products, the large quantities of systems sold—MP3 players, digital still cameras, cell phones, global positioning systems, etc.—and the low cost of those systems, leads many vendors down the path to develop an application-specific integrated circuit. And to amortize the development cost of that ASIC, many designers will make that ASIC configurable so that with a few register settings the chip can be reused in a different product, thus saving the cost of developing a second ASIC. The configuration storage can be off-chip using a flash memory or other means to load the data into the ASIC, or it can be on-chip, in the form of embedded non-volatile memory. For high-volume products, an ASIC reduces system cost by keeping the component count to a minimum, thus simplifying the bill of materials. Employing an ASIC also protects the system from competitors who might otherwise

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reverse-engineer the product and bring a competitive solution to market, greatly impacting the original vendor’s profit margins. By embedding non-volatile memory (NVM) on the ASIC, designers can perform trimming or final device configuration well after the chip comes off the fabrication line. The embedded NVM also permits post-manufacture trim capabilities or even the ability to bypass a faulty element or switch off or on a function, thus improving manufacturing yield. The key to a costeffective solution is to select the best embedded NVM for your system application.

Many Trade-offs to Consider

There are many trade-offs designers can make between aspects such as reprogrammability, process compatibility, density, programming performance and still other factors. Table 1 lists many of the aspects for some popular non-volatile memory cell types and

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cover feature

figure 1 Calibration/Trimming of Temperature Sensor

Temperature Sensor

ADC

NVM

Temperature Valve Register

I2C Interface

In an analog/mixed-signal design, embedded non-volatile memory can be used to trim values, set reference voltage levels and allow vendors to customize the compensation curve, such as in this temperature sensor application.

provides a simple decision matrix to help point designers in the best direction based on their application requirements. Designers have a choice of several types of embeddable NVM technologies that include multitime reprogrammable flash memory, multitime reprogrammable electrically erasable PROM (EEPROM), and various one-time programmable schemes based on flash-like storage cells, electrical fuses and antifuse programming schemes. Some of these approaches require extra process steps and can thus incur a significant adder to the chip manufacturing cost. As the table shows, antifuse one-time programmable cells offer many positives, but depending on the application, may have an issue with reprogrammability since each cell can only be programmed once. To get around this issue, designers can often integrate many times the amount of memory needed to hold the desired data since the cells permit a high bitdensity per unit area. The larger memory array is then divided into pages, and each time new

table 1 Fuse OTP

Floating Gate (EPROM)

Floating Gate (Flash)

Antifuse OTP

Re-Programmable

+/-

DRC Violations Required

No Extra Mask/Process Steps

Low Power

Physical Security

Small Die Area / High Density

Manufacturing Yield

Data Retention

Radiation Tolerant (Neutron)

Advanced Process Node Scalability

Read Performance

+/-

Program/Write Performance

+/-

Comparison of various embedded non-volatile memory technologies.

PORTABLE DESIGN

data must be stored, the data is written to a new page and a pointer reference is updated. This paging approach provides limited reprogrammablity. The limit, of course, is determined by how many extra pages are allocated. For instance, if 128 bits are needed to hold a security key or configuration data, a 1-Kbit memory array could hold ten 128-bit pages (10 reprogramming cycles) while an 8-Kbit array could hold eighty 128-bit pages or eight 1024bit pages if more data must be stored in each page. In many consumer applications, just a few reprogramming cycles are usually needed, so the â&#x20AC;&#x153;limitedâ&#x20AC;? reprogrammability should be sufficient for many applications. To keep the chip count low, many consumer products employ a single ASIC that integrates both analog and digital functions. Or, in some cases companies may use a two-chip solution, with one chip mostly analog and a second ASIC that may be mostly digital. Alternately, that digital chip could be an application-specific standard product (ASSP) such as an 8- 16- or 32-bit microcontroller available from many companies, or a programmable multimedia processor such as the OMAP or DaVinci processors from Texas Instruments, the i.MX series from Freescale Semiconductor, or the Nexperia media processor from NXP Semiconductors.

Trim Analog Levels with Embedded NVM

In an analog chip, embedded NVM can be used to trim offsets, set voltage reference levels, control analog switches and perform still other functions. This capability allows both the chip manufacturer and the system vendor to optimize chip yield to recover some chips that may initially have been out-of-spec. Although the digital portion of the chip may not need trimming, embedded non-volatile memory can also be leveraged to do final chip configuration before the end system is shipped from the factory, turning on or off certain features. Additionally, the NVM can hold security information or digital-rights management data, or even program code with areas reserved to hold code patches.

cover feature By allowing the chip to be configured in several ways, designers can save the cost of multiple chip implementations. This allows the system vendor to develop a single ASIC that can be used in multiple systems just by turning on and off several options by programming a few configuration registers. Thus one chip could serve an entire family of products, from a low-cost minimal feature set device, to a top-of-the-line system resplendent with many bells and whistles. Additionally, the embedded NVM can also be used to hold code patches. These patches can be used to fix a bug in the system’s program, add a new feature or enable a “hidden” feature when the customer orders an upgrade. For applications such as these, the system software development team must work hand in hand with the ASIC designer to determine the size of the patch space, the number of times patches can be used, and account for the extra program execution time when executing the patched software. For reprogrammable applications, flashbased storage is the most desirable, but also can potentially have the highest manufacturing cost since flash processes often add multiple process steps in the fabrication sequence. Since cost is often an overriding concern for high-volume consumer products, a non-volatile memory technology that fits in the standard CMOS manufacturing flow is the ideal solution.

Make Sure You Have a Migration Path

Although there are a few flash cell structures that don’t require additional process steps, these structures do not offer high packing densities and are usually not available on the latest process nodes such as 180, 130, 90 and now 65 nm. In contrast, non-volatile OTP structures can deliver high bit densities and many are available in the more advanced process nodes, thus providing easy integration into today’s 180, 130 and 90 nm ASIC design flows, and in the near future into 65 nm design flows. Many of the applications that need non-volatile memory don’t require reprogramming once the initial data is stored on the chip. Additional applications may need just a few updates over the life of

the product. For both of figure 2 these application needs, Digital SoC Applications for NVM one-time programmable memory can be used to System Bus handle both one-time and limited multi-time programmable requireMCU SRAM ments. Let’s take a look at a few simple examples of how the embedded Security Logic NVM OTM memory can be used in some consumeroriented applications. Application Application In a mixed signal Function 1 Function 2 ASIC such as shown in Figure 1, the embedded Configurable I/O Interface NVM array can be used to provide correction coefficients or trim values for the temperature Multiple uses for embedded non-volatile memory are possible in an all-digital ASIC—the NVM can hold security keys, program patchs, or even control sensor to ensure that which functions on the chip are enabled. the sensor readings are accurate and within the desired range. Since an on-chip sensor’s accuracy may vary due to process variations, this would permit chips with sensors that are out of the desired range to be brought back into range. Or, the NVM can be used to set different temperature ranges, thus allowing one chip to serve different applications. An all-digital ASIC that includes a variety of functions can also leverage NVM in several areas—security, program storage, configuration parameter storage and software patches to name a few (Figure 2). The block diagram of processor-based ASIC shows the NMV memory linked to all the sections of the chip so that it can hold security keys for the security logic firmware for the MCU, configuration bits for the various special function blocks and the I/O channel. This allows the system to be configured in multiple ways thus permitting a single chip to deliver multiple solutions. Kilopass Technology Inc. Santa Clara, CA. (408) 980-8808. [www.kilopass.com]. SEPTEMBER 2007

cover feature memory interfaces

The Impact of Make vs. Buy Decisions for Memory Interface Solutions Licensing a proven memory controller core can reduce the risk associated with timing closure, verification and changing functionality requirements. by Jai Iyer, Senior Director, Virage Logic

Memory controllers are vital subsystems in a variety of SoC/ASIC designs. Whether in low-power consumer electronics where MobileDDR memories require power-efficient, but also high-bandwidth access; or in highperformance low-latency data communication applications where cutting-edge DDR3 memories are required, the design of an efficient memory controller has become very complex and time-consuming. The analysis of whether to design a portion of an ASIC or SoC product or purchase an IP core from a third-party is challenging. While the cost of purchasing the IP core is usually simple—you just get a quote from a vendor. The cost of developing the IP core internally is much more complicated. Direct and indirect costs, risks, support, staffing and a variety of other, sometimes hidden costs, can dominate the project. This article will review many of the com-

PORTABLE DESIGN

plexities associated with memory controller designs and will explore how a third-party IP core can lower cost, improve profitability and reduce risk in SoC/ASIC design.

Overview of Memory Controller Requirements

Today’s memory controllers are key to just about every SoC/ASIC design. The right memory controller can reduce the amount of memory required, lowering cost, power and board space—or it can improve the performance of the system by ensuring that critical data is available at the right time for the application to process data with the highest possible performance. In high-performance applications, the right memory controller can improve bandwidth without the need for additional memory banks, thus freeing expense, board space and power to be used in other ways.

cover feature

Developing an optimal memory controller is a complicated design and verification task that requires an in-house expert. There are a variety of standardsâ&#x20AC;&#x201D;DDR, DDR2, DDR3, MobileDDR, GraphicsDDRâ&#x20AC;&#x201D;that must be considered. Access priority, error checking and correcting (ECC), read-modify-write support, byte-write implementations, out of order access support, FIFO options, latency and bandwidth trade-offs are just a few features that must also be studied, and the ability to support the wide-ranging memory de-

figure 1

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80% 70% 60% 50% 40% 30% 20% 10% 0% 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38

Company X Profit ($M)

Company Y Profit ($M)

Gross Margin

Comparison of Profit: Company Y with a Three-Month Schedule Slip

companies providing solutions now

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Feature and System Optimization

End of Article Get Connected

with companies mentioned in this article. www.portabledesign.com/getconnected

Itâ&#x20AC;&#x2122;s critical to optimize the in-house controller design during system integration. As it can be difficult to model the complete behavior of the system during design, modifications and what-if scenarios must be created, entailing design changes and experimentation. Trade-offs for latency, performance and features that impact system bandwidth and cost must be explored to identify the mix that meets design requirements. These capabilities must be examined during verification as well. A variety of test benches

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Get Connected with companies mentioned in this article.

and regression suites may be required to ensure that system design space is free of bugs and incorrect assumptions. Tests also need to mimic the system access patterns of the final system if benchmarks and other goal-measuring metrics are to produce valid results. Verification of the controller itself can also be very complex, requiring deep knowledge of the corner cases for each standard and feature to obtain the coverage required to create a robust solution, as well as requiring memory-vendor-specific tests. Beyond controller design, the physical layer (PHY) interface must also be considered. If an analog approach is taken, a completely new skill set and new tools and test methodology are required. Cell libraries and processes need to be verified as well. If a digital design is used, it simplifies some of the tool, process and design experience issues, but specifics of how to design the digital phase locked loop and delay elements needed to ensure that data recovery is robust, that jitter is minimized and that process, temperature and voltage variations are accounted for remain critically important. A third-party PHY could be used instead of designing one internally, which may be a good alternative assuming the PHY vendor has a proven track record and will support development, verification, test development, system integration and bring-up.

Impact of Schedule Slips to Profitability and Cost

There are a variety of factors that cause a project schedule to slip. Several were discussed above. Schedule slips dramatically impact product profitability, as several studies have shown. Consider an example from the cell phone market, where two silicon vendors, Company X and Company Y, introduced similar products, but Company Y suffered a three-month schedule slip, as illustrated in Figure 1. Since Company X launches product a full three months earlier than Company Y, its profit starts sooner and climbs to a higher level than Company Y. Note that the Gross

cover feature Margin is higher during the early portion of the sales cycle, providing Company X with a profit boost over Company Y. Late in the sales cycle Company Y shows slightly higher profit that Company X. This is deceiving, since Company X is introducing a new product, with higher margin that accounts for significant additional profit not shown on the single product comparison chart. If Company X leverages its three-month advantage to create another new product before Company Y it will again obtain higher profit. Additionally, if Company Y is late again, this delay will compound the schedule slip (in the case of a single design team working on both projects) and now Company Y is 6 months behind. Over time, Company X’s competitive edge could become disastrous for Company Y. The impact of the profit from sales is one major component of the economics of a schedule slip, but development costs are also impacted, boosting project costs and further reducing overall profitability. If a schedule slips three months, engineering costs are that much higher; for a yearlong project, three months becomes 25% of the overall cost. In some cases, engineering loading increases toward the project’s end and costs may actually be greater than 25%. If the SoC or ASIC requires a respin, manufacturing costs must be paid again as well. Other costs—material costs for scrapped wafers, testing expenses, EDA license costs, computer time or equipment rental—add up. In total, a three-month schedule slip with a respin could easily cost $5 to $10M. Amortized over the project sales cycle and subtracted from profitability for Company Y, the result is shown in Figure 2.

Key Sources of Risk in Memory Controller Design

The potential sources of slips—design risks that can turn into schedule delays and requirements to re-spin a SoC/ASIC design—are numerous, but for memory controller design there are three main areas to consider.

figure 2 $8.0 $7.0 $6.0 $5.0 $4.0 $3.0 $2.0 $1.0 $-

80% 70% 60% 50% 40% 30% 20% 10% 0% 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 Company X Profit ($M) Company Y Profit ($M) Gross Margin

Comparison of Profit: Company Y with a Schedule Slip and Increased Costs

The first schedule risk is that functionality requirements for the memory controller can grow over the course of the project. Because memory bandwidth is so key to performance, functionality, power and cost, the memory controller is often treated as the “go-to” portion of the design when these metrics are at risk, while the schedule impact of making feature changes can be difficult to estimate and resource when done late in the development cycle. Conversely, an IP core with a robust set of features and expert support from the vendor provides an experience-based schedule and feature set, dramatically reducing schedule risks. Once the feature set is finalized and verified, timing closure—the second key source of risk—becomes critical. The memory controller has a variety of critical design areas, primarily due to the importance of the physical layer interface timing between the controller and the external memory. And, unless great care is taken in the design of the scheduling logic, logic levels can become too deep and timing difficult to achieve. Register retiming can help, but at the risk of increasing latency, which can then reduce overall bandwidth. Because the memory controller is so central to the system design, there can also be numerous critical paths beSEPTEMBER 2007

cover feature

er exploration ether your goal speak directly ical page, the ght resource. technology, es and products

tween various functional blocks in the design and the controller. The optimization of critical timing within the memory controller block and between other key system blocks can turn into a tugof-war, putting schedules at risk and mak-

figure 3 $8.0 $7.0 $6.0 $5.0 $4.0 $3.0 $2.0 $1.0 $-

80% 70% 60% 50% 40% 30% 20% 10% 0% 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 Company X Profit ($M) Company Y Profit ($M) Gross Margin

Comparison of Profit: Company Y with a Schedule Slip, Increased Development Costs and Opportunity Costs

ing it nearly impossible to find a workable solution, even for an experienced designer. In contrast, an IP core has a proven set of constraints that has been used in a variety of applications and, with a small amount of companies providing solutions now vendor support, much more easily inexploration into products, technologies and companies. Whether your goal is to research the latest datasheet can from abe company, mp to a company's technical page, the goal of Get Connected is to put you in touchtegrated with the right resource. Whichever level of into the design. gy, Get Connected will help you connect with the companies and products you are searching for. significant area of risk in an inThe third onnected house development is verification. A memory controller must operate under a variety of different conditions, and to verify all combinations and sequences of access patterns is impossible. The verification approach must use intelligent, knowledge-based traffic patterns and access sequences that exercise the key elements of the design. Pure pseudo-random approaches will not converge on a useful coverage metric. Without detailed knowledge of the controller boundary conditions, enabling Get Connected with companies mentioned in this article. command and state conditions, it is difficult www.portabledesign.com/getconnected to predict with any certainty how long it will

End of Article

PORTABLE DESIGN

Get Connected with companies mentioned in this article.

take to reach coverage metric that will reduce risk to a tolerable level. An IP core that is part of a complete solution will come completely verified using a wide variety of corner cases, conditions and target applications. Furthermore, test suites included with the IP core allow bandwidth estimates using example application-specific access sequences, avoiding any last-minute surprises that can also impact schedules and covering a broad array of memory vendors’ products.

Long-Term Costs for Memory Controller Support

Once the design is completed and the new product rolled out, work on the memory controller is far from finished. The memory controller will need support during code development, feature enhancements, customerspecific enhancements, test coverage enhancement and all other engineering support required for a complex system. Test coverage enhancement is an excellent example of this support: As production ramps up, more becomes known about the bottlenecks of test time, yield loss and reliability—issues often linked to the memory subsystem. Vendors’ memory products can change from vendor to vendor, or even between wafer lots when vendors migrate processes and timing characteristics, reliability and sensitivity to noise and voltage variation. When yield crashes halt production or key customers find bugs previously masked, support from the designer becomes critical. If a product is successful, a follow-on product is called for; if it’s in a new process, the memory controller will need to be ported to it and another set of complexities emerges. New library elements need to be tested and optimizations for power, performance and die size may need to be complete redone. New memory technology must be taken into account as well as potential new vendors, memory features and characteristics. And, if a process-sensitive PHY needs to be ported,

cover feature it is often faster—and easier—to create a new design from scratch.

Opportunity Cost

When engineering resources are spent designing a memory controller, they are not being used to differentiate the core technology of the system. Though often overlooked, this “opportunity cost” can allow a competitor to do a better job of adding compelling features, pushing performance or lowering cost. When memory controllers are developed using an IP core instead of an in-house effort, engineering resources can be applied to counter competitors’ moves and enhance the product line’s core technology—investments that carry forward into future designs and enhance profitability on multiple product generations. Because they can pay off over multiple product developments (a 2 to 3x advantage over non-core investments) and can provide compelling advantages over the competition (another 2 to 3x advantage), investments in core technology can deliver a 4 to 9x return on investment. Contrast this to an investment in non-core technology where the return is 2x at best and it is clear that opportunity costs should be included in any detailed cost estimate.

Overall Profitability Result

We have seen the significant cost associated with designing a memory controller inhouse instead of sourcing the controller from a third party. If these additional costs are factored into the project profit projection we saw in Figure 2 and amortized over the project sales cycle, Figure 3 is the result. Company Y—burdened with a 3 month schedule slip, the additional engineering costs associated with the slip, the costs for spinning the SoC/ASIC, the additional engineering costs for designing, verifying, supporting and testing the memory controller, and the opportunity cost of missing features and capabilities in the current project—has a dramatically

lower profit curve. In fact, this range of profit may not be sufficient to keep the company viable depending on the other costs associated with selling and supporting the product line. For products with smaller sales and profit potential, it’s clear that even small impacts to overall profitability can mean the difference between a company staying in business and closing shop.

Conclusion

The design, verification and support for a memory controller are complex tasks. It is also costly, risky and in most cases unnecessary to do in house. Purchasing a memory controller as an IP core avoids a host of problems and allows the company to focus on its core competency and differentiate its offering from its competition. The resulting increase in profitability can make a tremendous difference in a product line’s impact on the company bottom line. The author wishes to acknowledge Warren Miller’s contribution to the development of this article. Virage Logic Corporation Fremont, CA. (510) 360-8000. [www.viragelogic.com].

SEPTEMBER 2007

wireless communications ultra-wideband

Designing for Ultra-Low Power: Ultra-Wideband in Handheld Devices When measuring the power consumed for a given transfer, UWB is the most power-efficient radio yet conceived. by Mark Moore, Chief Technology Officer, Artimi

Ultra-wideband (UWB) is promoted as a very low-power technology, even more power efficient than the best of current Bluetooth radio implementations. However, currently available UWB chipsets appear to be anything but low power, with peak power consumption sometimes measured in the range of watts rather than milliwatts. A WiMedia-based UWB radio spreads its signal over 1.5 GHz, delivering a total maximum transmit power of around 0.1mW. This is significantly less than for comparable radios such as Bluetooth, which has a typical transmit power of between 10 and 100 mW. This low transmit power combined with wide bandwidth means that the UWB radio is very fast, but relatively short range. Compared to other radio technologies, a WiMedia UWB radio design offers very high performance, 480 Mbits/s, while operating at a range of just a few meters. To take advantage of the very fast throughput

PORTABLE DESIGN

of UWB in portable product designs, particularly with battery-powered handheld devices, there are a number of design and application options to help optimize power. When planning UWB implementations, power utilization can vary depending on the chipset, use case and application service.

Chipset Power Management

Since the UWB transmission power is very low, a complete WiMedia radio might be expected to consume relatively little power. However, the very high data rates, high RF frequencies and wide bandwidths mean that power consumption is not dominated by the transmission power but by the radio front-end analog and digital signal processing blocks. Surprisingly, many of the most power-hungry circuit blocks have a power consumption that is largely independent of the application data rate, as shown in Figure 2.

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PHY power consumption can be as much as ten times the MAC, particularly if using a radio with a diversity receiver or a MIMO implementation. Fortunately, not all of this circuitry

figure 1

Performance (Mbits/s)

500 UWB

400 300 200 100

802.11g 5

Range (m) UWB Range vs. Performance

table 1

State

Power Examples Consumption

Active

~750 mW

This is typical for a single-channel receiver. MIMO designs can consume several times this level. Receive processing typically consumes more than transmit, but again this is very implementation-dependent (for example, a diversitybased receiver).

Sleep

~100 mW

The actual power consumed varies greatly with implementation and the duration of the sleep interval.

Hibernation

< 5 mW

This may be dominated by silicon leakage power, especially from memory devices since the high data rates supported by UWB typically require more on-chip RAM than comparable Bluetooth or Wi-Fi solutions.

Typical in use

~500 mW

Supporting a 480 Mbit/s Certified Wireless USB data stream with a single channel, non-MIMO receiver.

active all ofStates the time. Power Consumption at DifferentisOperational

The WiMedia MAC is designed to maximize

PORTABLE DESIGN

the opportunity for PHY power management. Transmissions are broken into superframes, which in turn contain 256 possible transmission slots. Each superframe begins with the transmission of beacon information used to manage the wireless network, followed by actual application data transfer, as in Figure 3. Mechanisms are provided for the MAC to schedule data transmission using a distributed reservation protocol (DRP). This allows the MAC to predict when the radio will be inactive and hence power down sections of the PHY circuitry whenever possible to minimize the average power consumption of the radio. Depending on the length of the gap and the particular PHY implementation, different sections of PHY circuitry can be shut down. Typically, digital circuitry can be clock-gated for arbitrarily short periods of time to save power, while analog circuitry must be powered down and may take a significant time to recover when power is restored. Although most PHY power management capabilities are implementation-dependent, the WiMedia specifications effectively provide both short and long duration power saving states. The longest state, termed hibernation, can span several complete superframes and is designed to allow complete shutdown of the entire PHY circuitry. Significantly, this includes the ability to shut down the PHY’s frequency synthesizer circuitry, which may account for as much as 30 percent of the total radio’s power consumption during data transfer. This ability ensures that a good WiMedia implementation offers extremely low power consumption when idle. Table 1 illustrates typical power consumption in the different states. While these figures may appear to be high, the data rate supported in these modes is also very high. The typical figure quoted above corresponds to drawing of approximately one mW per Mbit/s of throughput. First-generation UWB devices can be almost 10x more power efficient than 2.4 GHz Bluetooth for a given data transfer—and this will only improve as UWB implementations evolve. This efficiency only applies while the radio is performing a data transfer. Standby and idle power states consume more power than existing 2.4 GHz Bluetooth or WiBree solutions.

Fast Is Efficient

Since the power consumption of many radio blocks is largely independent of the application data rate, the best power efficiency for a given transfer (measured in battery energy consumed for a given data exchange) is obtained at the highest data rate. The most power efficient way to use a UWB radio is to run it at the highest usable data rate, allowing the task to either complete as quickly as possible, or allowing the MAC to place the radio into its lowest power states whenever possible. For example, a Certified Wireless USB bulk file transfer from a PC to a portable media player is likely to be limited by flash memory performance, with a sustainable application throughput perhaps half that supported by the WiMedia radio architecture. A good UWB implementation will try to run the radio at the highest PHY rate while grouping the data transmissions into bursts and thereby maximizing the opportunity to keep the PHY in its lowest power saving state.

wireless communications

This is partly due to the need for the radio to periodically monitor beacon transmissions even if there is no data transfer occurring, and partly due to the increased leakage power associated with the larger RAM buffers needed to handle UWB data rates (the WiMedia radio is 150 times faster than the current fastest 2.4 GHz Bluetooth standard). For this reason additional techniques may be needed to deliver the absolute lowest power system solutions.

vide an always-on wireless USB host mode to which the camera can be connected. In contrast, the more limited battery capacity of a handheld device means that the camera will normally leave its radio completely powered down until the user presses a button on the camera to initiate a download to the PC. When the task is

table2

Radio

Power Consumption

PHY Rate

Power efficiency

802.11g

250 mW

54 Mbit/s

5 mW/Mbit/s

WiMedia UWB

500 mW

480 Mbit/s

1 mW/Mbit/s

Power Efficiency Comparison for Wi-Fi and WiMedia UWB

figure 2

ECMA-368 (MAC) AES Encryption

Frequency Synthesiser

ECMA-368 (PHY)

FEC

Mapper

IFFT

Transmit AFE and DAC DAC PA DAC

MAC AES Decryption

FEC

De-Mapper

FFT

Receive AFE and ADC ADC

VGA

ADC

VGA

LNA

Power consumption independent of data rate Power consumption proportional to data rate

Always-On vs. On-Demand

Application services using UWB can be classified as always-on or on-demand. On-demand services leave the UWB radio completely powered down for most of the time: the UWB radio is powered on only to perform a specific, finite task, and is powered off as soon as it has been completed. In contrast, always-on services are typically used for service provision or for permanent connections. An example application for UWB is the use of Certified Wireless USB to download pictures from a digital camera to a desktop PC. Most PCs can accommodate the standby power consumption of a WiMedia radio and will pro-

WiMedia Radio Blocks and Power Consumption

completed, the UWB radio is once again shut down so that no power at all is drawn. Most handheld device synchronization tasks fall into this category. While this model works well for some applications, other applications may benefit from a genuine always-on model on the handheld device. This can be provided by a second radio that provides an always-on control channel that automatically enables and disables the UWB connection as required. SEPTEMBER 2007

wireless communications

One possible always-on control channel is an ISO14443 Near Field Communication (NFC) radio. This can be utilized to trigger operation of the UWB radio based on proximity, such as placing two devices next to each other. For example, the camera could be placed on a

figure 3 Beacon Slots

Slots with data Idle slots

Idle Superframe

existing 2.4 GHz radio. The 2.4 GHz radio will provide a well-proven low-power always-on connection. When two UWB-enabled Bluetooth devices are in range, the 2.4 GHz radio acts as a control channel that enables or disables the UWB capability transparently based on application needs. Such an approach gives best in class standby power consumption, while also offering UWB data rates of up to 480 Mbits/s with the lowest possible power consumed per bit transferred.

Conclusion

1 slot, 256Âľs

superframe n

superframe n+1

256 slots. 64ms

superframe n+2

WiMedia MAC Transmission Timing

figure 4

ECMA-368 (MAC) AES Encryption

Frequency Synthesiser

ECMA-368 (PHY)

FEC

Mapper

IFFT

Transmit AFE and DAC DAC PA DAC

MAC AES Decryption

FEC

De-Mapper

FFT

Receive AFE and ADC ADC

VGA

ADC

VGA

LNA

Able to power down only over long time periods (typically 65mS or more for deepest hibernation states) Able to power down for intermediate time periods (typically a few 100 microseconds or more) Able to power down for very short time periods (typically a few microseconds)

Power management capabilities

compatible printer to automatically enable the UWB radio link and trigger printing of the currently selected picture. The radio is shut down automatically when the action completes. Another example is the proposed next generation of the Bluetooth standard that is currently under development. This will utilize a WiMedia UWB radio to provide a high-performance data channel that complements the 34

PORTABLE DESIGN

When measuring the power consumed for a given transfer, UWB is the most power efficient radio yet conceived. However, the lowest power applications for UWB are for shortrange, bulk transfer applications so the radio is only enabled when needed. This makes UWB ideal for file transfers and file exchange between handheld devices, or between a handheld device and a PC. Utilizing a MAC that can optimize power consumption within the PHY during various states certainly helps lower power consumption. Understanding the realities of peak power consumption is critical when selecting chipsets for handheld applications. Peak power figures can be up to 50 percent higher than quoted average figures, potentially posing difficulties for some power supplies. UWB can also be successfully combined with existing technologies for an always-on connection, such as Bluetooth. This delivers both the best performance and the lowest power consumption in use cases. Ultimately, the most power efficient way to run UWB is as fast as possible. Even with todayâ&#x20AC;&#x2122;s UWB power consumption advantages, it will only improve in future implementations. Artimi, Inc. Santa Clara, CA. (408) 348-0288. [www.artimi.com].

Dream of Darkness,

Wasteman!

consumer electronics handheld gaming devices

Supervisor Solutions for Handheld Gaming Applications By using voltage supervisory circuits, designers can better protect these demanding designs from a variety of low powerrelated problems. by M ark Palmer, Principal Application Engineer, Analog and Interface Products Division, Microchip Technology Inc.

In handheld gaming applications, like most portable electronic applications, low-power conditions can wreak havoc and cause much annoyance to the user. The most common lowpower condition is the brownout state, where the system supply drops below the minimum operating voltage. This could be a momentary drop, due to the additional load on the power rail, or the drop could be due to a slowly decaying power supply (such as in a battery-based system). In either of these cases it is possible for the microcontroller (MCU), ASIC or state machine to operate improperly, leading to improper program flow and data computations.

Handheld Gaming Applications— Why Use a Supervisor?

At the heart of most portable electronic systems is most likely an MCU. Some MCUs do not offer supervisory functions, however some do in the form of an on-chip brownout circuit. 36

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An integrated brownout circuit may not be suitable for every application due to its trip-point selections, the trip point minimum/maximum voltage range and the additional current required to enable this feature. In these cases, the use of an external voltage supervisor or voltage detector may be preferable. The wide range of these available devices allows greater flexibility to match the handheld system’s requirements for the trip point’s minimum/maximum voltage range, current consumption and time that the reset signal is asserted after the system has returned to the valid operating voltage (for the system to stabilize). Figure 1 shows a power-up sequence, followed by a momentary brownout condition. The tRSTD time is the delay that the supervisor forces after the device voltage has returned to the valid voltage range (VDD > VTRIPEXIT). Holding the reset signal low allows the system to stabilize before the reset signal is released or

Features Available on Voltage Supervisors

Advanced voltage supervisors may provide additional functions. Some of these functions include an external reset input pin and a watchdog function. The external reset input may also be called a manual reset. This allows an external switch to be directly connected without the need for additional components. This could be used as the handheld gaming system’s hard reset switch. It could also be used to indicate an on/off condition for the system.

Importance of Watchdog Input

The watchdog function monitors an input pin that we will call WDI. If that pin does not change state within the specified time, the supervisor will force the RST pin low. Normally, this function is used to monitor the MCU to ensure that proper code execution is occurring. It is assumed that the MCU program was written to toggle the WDI pin within the minimum specified time. If the pin is not toggled, then it is assumed that the MCU has a problem and needs to be reset. Depending upon how the supervisor device is being used, this watchdog function could be implemented as a wake-up from a low-power mode. While the MCU is operating, it toggles the WDI pin. When the MCU wants to enter its low-power mode, it toggles the WDI pin to reset the watchdog timer and then enters sleep. This allows the device to be in sleep mode for the watchdog timeout time. Some devices offer watchdog timeouts up to 25 seconds. This technique could help significantly lower the aver-

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system operation starts again. A voltage detector has a tRSTD time of zero. The tRSTD delay can be also thought of as a time-based hysteresis. We can look at the waveform as the device powers down or browns-out (Figure 2). The voltage (VDD) falls from a voltage above the devices trip point (VTRIP). The device’s actual trip point voltage (VTRIP) will be between the minimum trip point (VTRIPMIN) and the maximum trip point (VTRIPMAX). Once the device voltage (VDD) goes below this voltage, the reset pin(s) will be forced to the active state. There is a hysteresis on this trip point.

age system current consumption, which means longer life for the batteries or the use of fewer batteries in the system.

Choosing Voltage Trip Points Based upon Application Requirements

There are two conditions of VDD activity that need to be explored (Figure 3). The first

figure 1

VDD VTRIPEXIT

1.0V VSS VDD

tRSTD

VTRIPENTRY

VTRIPEXIT

RST

VSS

tRSTD

tvTRIPENTRY

Power-up and brownout waveforms.

figure 2 VDD

VTRIPMAX

VTRIP + VHYS

VTRIPMIN

VTRIP

VTRIP 1V

RST tRPD

<1V is outside the device specifications.

tRST

tRPD

Reset operation timing as determined by VTRIP and VHYS.

is where VDD is rising from a voltage below the trip point of the device to above the trip point. This may also be a result of a power-up state. The second condition is where the voltage was in the normal operating range, and then power is lost and the VDD decays below the device’s trip point. From the first case, as the power is rising, what you need to be concerned about is the voltage level, where the device no longer detects the reset condition—that is when it exits SEPTEMBER 2007

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the reset condition. This could be referred to as VTRIPEXIT. From the second case, as power is falling, the voltage level that is of interest is when the device enters the reset condition. This could be referred to as VTRIPENTRY. Now, as there is variation from device to device with respect to these VTRIP levels, it is important to understand that as the voltage is falling from the normal operating range, voltages above VTRIPENTRY(MAX) will never cause the RST pin to be forced active, while voltages below the VTRIPENTRY(MIN) will always cause the RST pin to be forced active. Somewhere in between these two voltages is where the supervisor figure 3 will detect the change in conditions and force VREG (MAX) the RST pin active. VREG (typ) +2.5% or +5.0% Desired Regulated Voltage Range For the VTRIPEXIT -2.5% or -5.0% VREG (MIN) voltage, it is most imVTRIPEXIT (MAX) VDD portant to understand V , +2.0% VTRIP (MAX) HYS (MAX) the VTRIPEXIT(MAX). VTRIP (typ) +1.5% Trip Point Voltage Range The system’s reguVTRIP (MIN) -1.5% lated voltage range nd must be above the VTRIPEXIT(MAX) voltage, er exploration ether your goal or the system may not speak directly exit the reset state. Trip-point specification values with respect to the system’s regulated voltage. ical page, the ght resource. This would occur technology, when the system’s reges and products ulated voltage is below that of the supervisor ed VTRIPEXIT(MAX). Depending upon how a device is specified, VTRIPENTRY(MIN) may be indicated as VTRIP(MIN); VTRIPENTRY(MAX) may be indicated as VTRIP(MAX); and VTRIPEXIT(MAX) may be indicated as VTRIP(MAX), or VTRIP(MAX), plus some hysteresis (VHYS). companies providing solutions now From can see that the reguexploration into products, technologies and companies. Whether your goal is to research the latest Figure datasheet3, fromwe a company, mp to a company's technical page, the goal of Get Connected is to put you in touchlated with the right resource. Whichever of voltage should not belevel outside the VREG gy, Get Connected will help you connect with the companies and products you arerail searching for. range. At the VTRIPEXIT(MAX) point, the reset onnected signal will not be driven active for any voltage above this level. Between the trip point voltage ranges, as VDD falls, the voltage above VTRIP(MAX) will never force the reset signal active, and the voltage below VTRIP(MIN) will always force the reset signal active. These trip-point specifications can be calculated based upon the desired regulated voltages and the maximum error for the voltage regulation (2.5% and 5%). VTRIPEXIT(MAX) was specified as VREG(MIN) 0.001V. From this value, VTRIP(MIN, TYP, AND MAX) Get Connected with companies mentioned in this article. can be calculated based upon VTRIP(MAX) error of www.portabledesign.com/getconnected +-1.5% and VHYS(MAX) of 2.0%.

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Power-Down/Brownouts

During a brownout condition, the supply voltage dips or “sags” down to a low end of the safe operating level before returning to a normal level. Many factors such as inadequate power regulation, system devices turning on or off or system malfunction contribute to the brownout condition, which remains undetected during the system development stage. When the production run begins, the condition may rear its ugly head. Some of today’s MCUs cannot fully guard against certain system failures. One possible system problem can occur when the supply voltage is ramped down very slowly, such as in the decay of a battery supply (Figure 4). In this state, many MCUs begin to execute the code in an arbitrary manner. This is because the program memory fetch has a corrupted read, due to the MCU’s frequency of operation and the low voltage of operation. Additionally, if the voltage is low enough, then RAM locations may become corrupted as well. This issue could manifest itself in some gaming handhelds as gibberish on the display, or the handheld may simply hang. With some memory devices such as serial EEPROMs operating down to 1.8V and responding to commands as low as 1.2V, there is a strong probability that random data will be written into the memory device. Here is how it plays out: data is written into the EEPROM and the system is certified good and switched off. Down the production line, it is discovered that the EEPROM data has been corrupted. Now, there may be calls to the EEPROM vendor with complaints on data retention, when in fact it was the MCU that sent write commands to the EEPROM during power down.

Reset Delay Timer

Based upon the value of the reset delay timer, the voltage supervisor can be selected so as to hold the handheld system in reset until the system voltage has stabilized. Voltage supervisor manufacturers offer several time-out options to help designers meet the requirements of a wide range of applications. For example, the standard offering time-out is typically 200 ms on Microchip Technology’s MCP131X/2X supervisors. However, supervisors with times up to 1.6s (typical) and down to 1.2 ms (typical) are also available.

figure 4

Microcontroller ‘loses control’ here

~4V Supply Voltage

The reset delay timer starts after the device voltage crosses above the actual exit trip point (VTRIPEXIT). When the reset delay timer times out, the reset output pin (RST/RST) is driven inactive. The system must be designed so that the TRSTD(MIN) time is adequate for all system components to stabilize, and so that a delay of TRSTD(MAX) will not cause any system issues. Voltage supervisors on handheld gaming devices offer a manual reset pin (Figure 5) that allows a push button switch to be directly connected to the system. This enables the handheld to be easily reset. Filter circuitry on this pin handles noise that may be present on the manual reset signal. Typically, the manual reset pin is active-low and has an internal pull-up resistor. Although voltage supervisors have fixed voltage trip points, for the sake of design flexibility, sometimes custom adjustments are necessary. On the MCP131X/2X devices, this can be accomplished by connecting an external resistor divider to the MCP131X/2X VDD pin. This causes the VSOURCE voltage to be at a higher voltage than when the MCP131X/2X input equals its VTRIP voltage. To maintain detector accuracy, the bleeder current through the divider should be significantly higher than the 10 µA maximum operating current required by the MCP131X/2X. A reasonable value for this bleeder current is 1 mA (100 times the 10 µA required by the MCP131X/2X). For example, if VTRIP = 2V and the desired trip point is 2.5V, the value of R1 + R2 is 2.5 kΩ (2.5V/1 mA).

DANGER ZONE

~1.5V

Time MCU loses control with slowly decaying power supply.

figure 5

Graphics Display

Keyboard or Touchscreen

Microchip Technology Inc. Chandler, AZ (480) 792-7200. [www.microchip.com].

Backlit Control

+3V

SD or Mini SD Card

VDD

Conclusion

More often than not, low-power conditions in handheld gaming devices result in problems that are hard to detect, and that cause operational problems like hanging up and unpredicatable behavior. Therefore, it is very useful to add an external voltage supervisor to the handheld system. This article provided some guide¬lines on how to avoid these intermittent problems related to low-power conditions. By using voltage supervisory circuits, designers can better protect their portable systems from a variety of low-power-related prob¬lems.

Other components in system may work down to here

MCU Sensor Interface

I/O

RESET

Ethernet

+5V RST VDD WDI

MCP13XX MR

VSS

Block Diagram of a Handheld Gaming Device Under Voltage Supervisor Control

SEPTEMBER 2007

portable power partitioning for power

Partitioning for Power Management Power is a critical metric for many high-performance embedded designs, and effective system partitioning is key to achieving power goals of the design. by Bhanu Kapoor, Ph.D., SoC Power Management Consultant/Founder, Mimasic

Over the past few years, the popularity and growth of portable consumer devices has exploded. These consumer devices include battery-powered mobile phones, digital cameras, MP3 players, personal digital assistants (PDAs) and smart phones that include all or most of these applications. These products rely on high-performance and low-power embedded systems. Power consumption has become one of the most important differentiating factors for semiconductor products due to a major shift in the market toward these handheld consumer devices. The advances in semiconductor manufacturing process technology have also led to power becoming a key issue in the chip design process. This is due to rapidly increasing power density and leakage current in smaller geometry devices. Power is shaping key product decisions. This is reflected in Steve Jobs’ comment (Wall Street

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Journal, June 6, 2007) on Apple’s decision to not use 3G in the initial version of the iPhone: “When we looked at 3G, the chipsets were not quite mature, in the sense that they’re not low-enough power for what we were looking for. They were not integrated enough, so they took up too much physical space. We cared a lot about battery life and we cared a lot about physical size.”

Partitioning—The Fourth P

The three Ps of embedded designs are Price, Performance and Power. And a fourth P, called Partitioning, is a key to achieving these embedded design goals. In particular, it plays a significant role in meeting the low power goals of the system. Power is a primary design criterion for the bulk of semiconductor designs now. Power is also a key reason behind the shift toward multicore designs; power consumption limits our

Power Sources

There are two types of power consumption in a semiconductor device: Dynamic and

portable power

ability to simply increase clock speed, the traditional way to increase performance. Power can be managed through the clock and the supply voltage. Voltage is the strongest handle for managing chip power consumption. Dynamic power is proportional to the square of supply voltage, and leakage power has a linear relationship with it. In addition, leakage power has an exponential relationship with the threshold voltage of the device. This implies that if voltage can be controlled to optimally meet the performance, then there can be much to be gained in terms of power savings. Until recently, most applications used a single always-on supply voltage for a chipâ&#x20AC;&#x2122;s operation. Initially, laptop chips started employing voltagebased power management techniques to manage leakage and dynamic power. Many wireless and handheld applications now extensively deploy such power management techniques. Leakage in standby mode is the prime concern for extending battery life in many applications. A single handheld device can now host multiple consumer electronic applications such as phone, camera, video, TV, 3D graphics, high-fidelity audio, gaming and high-speed wireless communication; the need to aggressively manage both dynamic and leakage power has become essential. Leakage accounts for most of the power in standby mode; powering off appropriate portions of the chip helps mitigate the issue effectively. Leakage in active mode of operation has grown from less than 20% at 130 nm to nearly 60% at 45 nm. Leakage also grows quickly with increasing temperature. Figure 1 shows the ITRS projected trend of growth for active leakage power as a fraction of total power. This clearly shows the growing importance to manage leakage power in embedded systems. In this article, we will first take a quick look through the origins of power consumption in embedded systems. Hardware consumes power and appropriate mechanisms need to be built into hardware to support power management at the system level. An overview of power management techniques follows next. We will then look into system-level partitioning and software aspects of power management in the context of embedded system design.

Leakage. The dynamic power consumption is a result of switching activity, i.e., device state transitions from a 0 to a 1 and vice versa. Leakage power consumption is static in nature and a device dissipates leakage even while maintaining a given state.

Dynamic Power

Dynamic power depends linearly on switching activity as determined by the clock frequency and the amount of switched load or capacitance. It also has a squared dependence on the supply voltage of the device. Clock frequency depends upon the supply voltage as higher voltage allows for higher frequency of operation. This implies that there is much to be gained in terms of power savings if voltage can be scaled down to meet performance goals.

figure 1 Leakage Power as a percentage of total power for various process technology nodes 90 80 70 60 50 40 30 20 10 0

130nm

90nm

65nm

45nm

30nm

20nm

Leakage Power as a percentage of total power for various process technology nodes.

Leakage Power

The leakage power component is a product of leakage current and supply voltage giving it a linear relationship with the supply voltage. However, the leakage current itself has an exponential dependence on the deviceâ&#x20AC;&#x2122;s threshold voltage; it increases exponentially with decreasing threshold voltage. As supply voltage is scaled down, threshold voltage has to be reduced to meet performance goals. However, decreasing threshold voltage significantly increases leakage power. In designing embedded systems, two types SEPTEMBER 2007

portable power

of leakage are to be considered: Standby and Active. Many applications spend considerable time in standby and special attention must be paid to this mode in designing power management architecture, as leakage will be the dominant source of power consumption here.

Power Management Techniques

The availability of power management features impacts partitioning of the system to reach power goals. The parameters on which power depends directly imply the types of features that can be used for power management. Switching off and scaling clocks to reduce dynamic power, switching off and scaling supplies to reduce dynamic power and leakage to a small extent, and switching of supplies and

figure 2

Core1

Core2

PMIC

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Acceltr1

Acceltr2

Interconnect Power & System Control

On-Chip Memory Subsystem

Example of a power-managed chip architecture.

scaling threshold voltage to reduce leakage power are among the key techniques to manage power. Some of the key power management companies providing solutions now techniques are described next. exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company,

mp to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of gy, Get Connected will help you connect with the companies and products you areClock searching for. Gating and Scaling

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(CG)

Clock gating is one of the power-saving techniques used on many synchronous circuits. To save power, clock gating refers to adding logic to a circuit to prune the clock tree, thus disabling portions of the circuitry where flipflops do not change state. Clock frequency can also be scaled per performance requirements. A chip can have multiple clock domains each operating at a clock frequency as required to meet application schedule. Clock synchronization will be needed on signals that cross these clock domain boundaries.

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Power Gating (PG)

Power gating (PG) is a technique for eliminating leakage power consumption of unused blocks in certain modes of chip operation. The power supply to the power-gated block is cut off via the use of a power switch thus almost entirely eliminating leakage. The outputs of a block float as a result of power gating. PG can be either carried out on large functional areas of the chip or it can be implemented on smaller blocks of logic. These are known as the coarse-grain and the fine-grain PG techniques, respectively.

Power Gating with Retention (RPG)

Power gating is a time-consuming process; power up and down process can take up a large number of clock cycles in high-speed applications. Power up is followed by a system reset. Resuming the operation, from the state where the system was prior to power down, requires the system state to be stored and re-loaded upon power up. A system stores its state in registers and memory blocks. The combinational logic present in between the registers provides a means for state propagation. In standby or idle mode, the clock is gated and registers simply save the state. The combinational logic part consumes significant leakage power while doing no useful work. State retention power gating (SRPG) is an approach for retaining states while avoiding unnecessary leakage power consumption.

Multiple Supply Voltages (MSV)

Different blocks of a chip can operate at different voltages based on performance requirements; voltage supplies can be always-on or turned off. Each partition is associated with a fixed operating voltage. There may be an application specific accelerator on the chip that needs to operate at much higher frequency whereas the rest of the chip can operate at a lower frequency. Most of the chip can make use of a lower voltage compared to the accelerator part and reduce dynamic power consumption significantly. Even the leakage in active mode will be reduced due to the use of a lower supply voltage on the majority of the chip. The maximum frequency at which the design can run safely decreases with decreasing voltage. Thus, the system can reduce processor

Dynamic Voltage Scaling (DVS)

Different applications that run on a processor may have varying performance requirements. These applications can be effectively run at different voltages in various modes of the chip operation. Appropriate voltage can be determined through a frequency-based voltage lookup table. PMIC can be directed by the power controller to provide the appropriate supply. DVS is also known as dynamic voltage and frequency scaling (DVFS). DVS requires additional design considerations compared to MSV. For example, the use of voltage scaling in conjunction with the frequency scaling requires that clock switching happens at a safe voltage level for the new clock.

portable power

energy consumption by reducing design voltage, but this necessitates running the system at a slower speed. This implies that voltage can also be scaled to meet performance needs.

If the leakage increases with age, temperature or other conditions, changes in bias supply can be used to compensate. Compensation is required for process variations also; ABB is likely to become a necessity at 45 nm and below.

Implications of Power Management Design Techniques

The clock and voltage-driven design techniques described here help mitigate leakage and dynamic power issues. Table 1 summarizes the targeted issues for each of these techniques. The targets are standby leakage power, active leakage power and dynamic power reduction. Green indicates primary effect and yellow indicates a secondary effect of the technique. White space indicates either little/no effect or an existence of an alternate method to have the same primary effect. For example, PG cuts off dynamic power too, but clock gating can be

figure 3

Adaptive Voltage Scaling (AVS)

From a power management concept standpoint, AVS is similar to DVS. However, unlike DVS, which uses table lookup, AVS is a closed loop system and the power controller interfaces with a monitor in the scaled block to determine frequency needs and then directs the system to provide appropriate voltage.

Core1

Core2

PMIC

Acceltr1

Acceltr2

Interconnect Power & System Control

On-Chip Memory Subsystem

Multi-Threshold CMOS (MTCMOS)

Sub-threshold leakage increases exponentially with decreasing threshold voltage (Vth). The performance of the device is dependent upon the differences between the supply voltage and the Vth; lower Vth implies higher performance. A foundry will typically provide two or three libraries with different Vths that can be effectively used to optimize leakage; in case of two Vths, lower Vth devices are used on the critical paths and higher Vth elsewhere.

Active Back Bias (ABB)

Active back bias (ABB) voltage, applied to wells of N-MOS and P-MOS transistors, is used to set the threshold voltages and leakage currents precisely in order to improve speed and at the same time control device sub-threshold leakage. The active back bias applies a voltage to the well of devices and this voltage can be generated by a PMIC.

Parts (Core1, Core2 and Accltr2) of the chip are power gated during one mode of operation.

used to have the same effect on dynamic power. But standby leakage remains an issue in presence of clock gating.

System Power Management

A typical embedded system consists of heterogeneous components such as programmable processors (CPUs and DSPs) and hardware blocks (ASICs and FPGAs). These components are connected through communications links and form a distributed architecture. In addition, components such as Analog-to-digital converters (ADCs), Digital-to-analog converters (DACs) and Input/Output Ports (I/O) make communications with the external world feasible. SEPTEMBER 2007

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A complete embedded system will also contain application software that is run on this underlying distributed architecture. Effectiveness of an embedded system in meeting its market goals is determined by how well both the hardware and software aspects have been optimized in the system context. First, as part of the architecture allocation task, the application has to be partitioned into hardware and software tasks to meet application schedules. Hardware is designed to provide power management capabilities as required by the application, and software has to be able to orchestrate the application to effectively use these power manage-

And on the two extremes, either the application can be fully implemented as software on a fast programmable processor or it can be implemented as a dedicated hardware ASIC solution. And there are a large number of possibilities in fragmenting the application to hardware and software implementation subsets. Each of these choices has a cost and power implication, assuming that performance goals are met by all of the possible solutions. And, as a result, system partitioning has a first order impact on partitioning. Unfortunately, design tools to help with the partitioning tasks that take power estimations

table 1 Power/Technique

RPG

MSV

DVS

AVS

MTCMOS

ABB

Standby Leakage Active Leakage Dynamic

er exploration ether your goal speak directly ical page, the ght resource. technology, es and products

Voltage-based PM techniques and their primary and secondary impacts.

ment features. Finally, the pure software part of the application can be optimized for power while ed meeting the performance goals. We will use a system-on-a-chip (SoC) example, as shown in Figure 2, to support explanation of the discussions here. This is a simplified view of a chip architecture used in smart cell phone platforms. Such systems will contain companies providing solutions now several peripherals, exploration into products, technologies and companies. Whether your goal is to research the latest datasheet fromconverters a company, and I/Os in admp to a company's technical page, the goal of Get Connected is to put you in touchdition with the resource. Whichever of This SoC has toright components shownlevel here. gy, Get Connected will help you connect with the companies and products you aretwo searching for. cores, an ARM CPU and a DSP; two accelonnected erators, a video/imaging accelerator and a 3D graphics accelerator; a power controller that communicates with an external power management IC (PMIC) to supply various blocks with different voltages; and a memory subsystem with on-chip SRAM. Even in this simplified view of a system, there are several options and each option has a different power and cost implication. For example, one can use two CPU cores, a fast and a slow CPU, instead of a DSP and a CPU. As another Get Connected with companies mentioned in this article. option, one or both of the accelerator ASICs can www.portabledesign.com/getconnected be implemented on programmable processors.

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into account are mostly lacking at this stage. There are ways to model and simulate performance goals of the system but system partitioning remains a manual task that is mainly application specific and platform-driven. Application modes are central to optimizing power goals. For example, such a smart cell phone will also have several modes of operation. Each mode dictates possibilities for power management. When a phone is switched on, it initializes into a Network Search (NS) mode. The system will stay in this mode until a suitable network is found and then switches into what is known as a Radio Link Control mode where it maintains the network connection. An incoming or outgoing phone call switches the phone into GSM Coding/Decoding mode (GSM) while maintaining the RLC mode. Speech coding, decoding, transmission and reception occur in this mode. Additional modes could include the use of the phone as an MP3 player (MP3), as a digital camera, as a digital video recorder and for reading/writing emails.

portable power

Statistics plays an important role in power optimization. In a typical scenario, a smart cell phone may be in the RLC mode 80% of the time, in the GSM and RLC combined mode 10%, 1% in the NS mode, and the rest of the time using the remaining features. Leakage power reduction is extremely important for battery life; the fact that the phone is in standby RLC mode most of the time can be leveraged effectively by turning off the supply to portions of the chip that are not used in this mode. Figure 3 shows an example of a chip mode where some parts of the chip can be power gated to reduce leakage and dynamic power during mode. The system has to have the ability to detect this mode and instruct components via system software to apply appropriate power saving modes. Similarly, in one of the modes, Accelerator 2 may have to operate at a higher frequency to achieve performance goals and uses a higher voltage as a result. In other modes, it can either be shut off or operate at a lower voltage. Power management architecture should ensure that processing elements and communication links are put into standby or sleeping modes whenever they are idle. The reactivation of components takes finite time and energy. As a result, the components should only be switched off and set in standby mode if the idle periods are long enough to avoid deadline violations or increase power consumption. State retention power gating (SRPG) helps mitigate some of the deadline issues in these situations. The clocks to the powered-down regions can be gated prior to switching off the supply to avoid wasting power consumption of the buffers associated with the clock tree. The scaling of voltage and frequency, on the other hand, exploits slack time by reducing clock frequency and voltage simultaneously. It adapts the component performance to the actual requirement of the system. All of this is possible only through an effective orchestration of power management states by the system software. Hardware techniques are useless unless system software effectively utilizes them. In addition to the system-based orchestration of power management techniques, the pure software part of the embedded application running on the processor cores can also be optimized for power.

For example, video codecs contain computation-intensive algorithms that can be implemented in a variety of ways to optimize for power. Some critical loops can also be written at the assembly level to optimize for performance and power. Code generation by compilers is not power aware. As a result, the choice of algorithms to implement your application can impact power significantly. Importance of software power optimization is underlined in a Wall Street Journal article, July 18, 2007, titled “Batteries in Gadgets Can’t Support All The Gee-Whiz Adds.” After Apple announced its new iPhone in January, for example, its engineers went to work looking for places in the device’s software that could be tweaked to cut back battery usage, said Greg Joswiak, an Apple vice president who handles iPhone marketing. The result was a boost in the talk time of the device. From the beginning, said Mr. Joswiak, design decisions were made with the battery in mind. Apple picked the video-playing software programs known as codecs because they used the least power. The design of low-power and high-performance embedded systems requires power considerations throughout the design process. The most important decisions are the ones that are made at the system level and have the most profound impact on power. The partition of the system into hardware and software components and the resulting architecture allocation determine the overall power landscape. Mode-specific power reductions are the most important and these modes are determined and orchestrated by software at the system level. Hardware techniques provide the necessary means to achieve these savings. Software running on the programmable core of an embedded system can also be optimized for power through the use of algorithmic changes and processor targeted implementations. Mimasic, Richardson, TX. (214) 336-4973. [www.mimasic.com].

SEPTEMBER 2007

products for designers Power Management Fuel Gauge Accurately Predicts Battery Life in Smart Phones and Other Handhelds

New SMD Rotary DIP Switches Offer Design Flexibility

How much battery life do I really have left? Texas Instruments Incorporated (TI) answers the question by introducing its system-side fuel gauge integrated circuit (IC) with Impedance Track technology for smart phones and other handhelds. The 2.5 mm x 4 mm gauge predicts battery life with 99-percent accuracy to extend run-time, protect data and provide a better user experience for mobile handheld users. The bq27500 system-side battery fuel gauge with TI’s patented Impedance Track technology accurately measures data from a device’s single-cell Li-Ion battery in order to predict remaining battery capacity under all conditions, even as a battery ages. The tiny IC analyzes precise state of charge by correlating between a battery’s voltage and cell impedance, or resistance, and its current integration to adjust remaining state of charge up or down the predicted discharge curve. The bq27500 directly measures the effect of a battery’s discharge rate, temperature, age and other factors to accurately predict remaining life within one percent error. By measuring and storing real-time battery impedance values, the IC automatically adjusts to changes in full capacity as a battery ages. State of charge and full capacity are calculated from the voltage and impedance measurements, eliminating the need to re-learn from a charge and discharge cycle. The bq27500 is implemented on the host system’s board, and can support an embedded or removable battery. System-side implementation allows a handheld manufacturer to save cost by designing an end-equipment that does not need extra electronics added to the battery pack. As batteries continue to shrink in size, integration of electronics on the battery becomes more of a challenge. System-side implementation of the bq27500 can control and manage other main battery management functions, such as battery pack authentication. The bq27500 is available today in volume in a space-saving 12-pin, 2.5 mm x 4 mm SON package. The device’s suggested retail pricing is $0.95 in 1,000-piece quantities. Evaluation modules of the bq27500, design application notes, user guides and TI’s software design tool are available through power.ti.com.

Omron Electronic Components LLC has announced the availability of the new A6RS series of gull-winged terminal surface mounted (SMD) rotary DIP switches for static function-select settings on control boards. These top-actuated switches are available with flat or extended shafts, 10 position (decimal) or 16 position (hexadecimal) outputs and terminal arrangements of 4 x1 and 3 x 3, which allow for flexibility in circuit design. They all have highly visible legends with an arrow on the actuator to aid in proper code setting. These RoHS-compliant switches are designed to withstand peak reflow temperatures of 260°C and are perfect for use in applications that are commonly found in HVAC, Medical and Security equipment. The A6RS has a contact rating of 25 mA @ 24 VDC. It operates in an ambient operating temperature range of -25° to +80°C, and can be supplied in tubes or tape and reeled. MSRP for the A6RS-101RF-P 10 position top-actuated flat actuator in a 4x1 terminal arrangement is $1.69 each for a 750-piece reel. MSRP for the A6RS-161RS-P 16 position top-actuated extended shaft in a 4x1 terminal arrangement is $2.51 each for a 250-piece reel. Delivery is stock to 8 weeks.

Texas Instruments Inc., Dallas, TX. (800) 336-5236. [www.ti.com].

Omron Electronic Components, Schaumburg, IL. (847) 8822288. [www.components.omron.com].

New Kit Cuts Risk and Time for Adopting Functional Verification Methodology Cadence Design Systems, Inc. has announced a comprehensive verification kit for wireless and consumer system-on-chip (SoC) design, enabling engineers to adopt advanced verification techniques with reduced risk and deployment effort and meet time-to-market requirements. The Cadence SoC Functional Verification Kit provides a proven end-to¬-end methodology that extends from block-level verification to chip- and system-level advanced verification and includes automated methodologies for implementation and management. The kit provides complete example verification plans, transaction-level and cycle-accurate models, design and verification IP, scripts and libraries—all proven on a wireless segment representative design and delivered through applicability consulting. The new kit addresses key challenges engineers face when designing and verifying SoC designs: ensuring comprehensive verification of the design, enabling re-use, managing low-power modes typical in today’s SoCs, ensuring hardware-dependent software coverage, and accomplishing the verification within very stringent time-to-market timelines. The applicability consulting included with the kit provides complete and interactive guidance for performing predictable and repeatable verification of blocks, clusters, full chips and SoCs, and enables design teams to quickly and easily adopt the Cadence Incisive Plan-to-Closure Methodology. The SoC Functional Verification Kit includes design and verification IP from Cadence and third parties, including an accurate high-speed model of the ARM968E-STM processor, AMBA PrimeCell IP including interconnect and peripherals, and the ARM RealView Development Suite debugger, USB 2.0 from ChipIdea and 802.11 from WiPro. The kit includes three main flows: architectural, RTL block to chip and system-level. Users can implement the entire kit as an integrated flow, or may select flows individually. Also included are 13 workshop modules and over 40 hands-on labs, which engineers can use to incrementally improve their verification productivity. The Cadence Incisive Plan-to-Closure Methodology will support the Open Verification Methodology or OVM in Q4 this year. The OVM is based on Cadence’s Incisive Plan-to-Closure URM module and Mentor’s Advanced Verification Methodology module. Cadence Design Systems Inc, San Jose, CA. (408) 943-1234. [www.cadence.com].

PORTABLE DESIGN

Linear Technology Corporation introduces the LTC2308, a 12-bit analog-todigital converter (ADC) that measures eight single-ended input channels, four differential input channels, or combinations of both for digitizing multiple data acquisition signals with a single chip. The LTC2308 features an internal 8-channel multiplexer and communicates via an SPI-compatible serial interface at throughput rates up to 500 ksps. With the combination of an internal reference and a tiny 4 mm x 4 mm QFN24 package, the LTC2308 provides a high level of integration to reduce board area and total system cost, making it ideal for portable instruments and space-constrained designs. The LTC2308 operates from a single 5V supply, drawing only 17 mW at the 500 ksps throughput rate. Power dissipation can be further decreased with two shutdown modes. Nap mode reduces the power to 1.15 mW at 1 ksps, and sleep mode shuts down all internal circuitry and reduces the power to 35 uW. The LTC2308 measures unipolar or bipolar input signals, achieving excellent DC specifications, including +/-2 mV(max) zero-scale error and +/-4 LSB(max) full-scale error. The LTC2308 excels when digitizing AC input signals, measuring 73 dB SINAD and -88 dB THD at 1 kHz. A separate digital output supply voltage (OVDD) allows users to configure the serial data output for power supplies ranging from 3V to 5V logic. The LTC2308 is available today in both commercial and industrial temperature grades. The LTC2308 is competitively priced, beginning at $2.95 for 1,000-piece quantities. Linear Technology, Milpitas, CA. (408) 432-1900. [www.linear.com].

First Low-Frequency Filter Based on Analog Signal Processor (dpASP) Technology Anadigm has introduced AnadigmFilter1, the first in a family of chipsets using its dynamically programmable dpASP and a state machine. This dynamically programmable ASP incorporates a universal analog filter architecture that provides the designer with frequency options from DC to 600 kHz, using a 6th order filter. Low-pass, band-pass, high-pass or band-stop circuits can be quickly implemented, without the usual digital-to-analog conversions or writing DSP or microprocessor programming code. The designer simply selects from the comprehensive library of pre-sets available within AnadigmFilter1. The onboard filters can be selected to emulate Butterworth, Bessel, Chebyshev and inverse Chebyshev filter approximations. AnadigmFilter1 is the first low-frequency filter to provide the designer with breakthrough design simplicity—enabling selection of one of four types of filters—frequency and gain control using a simple 16-bit control interface, DIP switches or hard wired pull-up and pull-down resistors. The chipset input consists of a choice of one or two fixed input stages (which can be summed), each of which can be configured using external resistors and capacitors to provide gain or attenuation, level shifting, single-ended-to-differential conversion and 1st-order low-pass and high-pass filtering. Gain and stop-band frequency can be dynamically controlled in real time without interruption to the signal, allowing filter gain and frequency to be swept across one full octave of the frequency spectrum. Large changes in filter frequency are realized by adjusting the internal clock dividers, or external reference clock frequency changes to the clock. Summing stage input connections and filter circuit architecture or approximation can also be realized in real time when these parameters are changed, although there will be a momentary break in the circuit connections and step response settling time. Filter gain and corner frequency settings are typically better than 1% accurate; these settings are very stable over the entire industrial temperature range—with almost no temperature drift. Chipset power consumption is typically 200 milliwatts. Low-current standby mode/sleep mode is also available. Samples and production quantities of the new AnadigmFilter1 AN236K04 chipset, which consists of the AN231E04 dpASP and AN236C04 State Machine, are available now from distributor Nu Horizons (www.nuhorizons.com) and Anadigm, at a suggested resale price for U.S. delivery in 1000-piece quantities at $11.28 each. In addition, the AN236K04-EVAL2 AnadigmFilter1 evaluation board, which includes the AN236K04 chipset, is available at a suggested resale price of $199. Anadigm, Inc., Oak Park, CA. (480) 422-0191. [www.anadigm.com].

White LED Step-Up Converter Integrates Schottky Diode Semtech Corp. has announced the SC4509, a step-up converter for white LED backlight applications with an integrated Schottky diode in a 2 x 2 x 0.8 mm package. The SC4509 can drive up to five white LEDs in series to provide a tiny solution for small LCD displays. The device’s built-in Schottky diode saves board space and reduces costs while still providing efficiencies of over 80%, which is better than most competitive devices with integrated Schottky and similar to many that require an external Schottky. To simplify control of the backlight, the device features a combination enable and PWM dimming pin that allows the user to turn the device on and off, or to apply a PWM dimming signal of up to 10 kHz to control the output current level and dim the LEDs. This pin can also provide a soft start capability to reduce in-rush current at start up. The SC4509 features extensive protection capabilities including over-voltage protection, current limit, thermal shutdown and open LED protection. The input voltage range for the SC4509 is 2.7V to 10V, and the device can output up to 20V at 30 mA. The device operates with a 1.2 MHz constant switching frequency. The SC4509 is available in either an MLPD-8 or SOT-23 package, both of which are RoHS-compliant. Both packages ensure a small overall footprint and cost-effective solution. The SC4509 is available immediately in production quantities and is priced at $0.37 in 1,000-piece lots. Semtech Corporation, Camarillo, CA. (805) 498-2111. [www.semtech.com].

SEPTEMBER 2007

products for designers

12-Bit, 8-Channel 500 ksps SAR ADC Features Compact Solution Size and Low Power

products for designers

Green Laminate System In response to global demand for environmentally friendly solutions, Rogers Corporation has developed a halogen-free, transparent epoxy polyimide laminate system that is safe for the environment and delivers superior performance in an all-inclusive package for flexible circuit designs. An extension of the Rogers R/flex CRYSTAL product line, the new R/flex JADE A epoxy adhesive system is ideal for a wide range of applications including hard disk drives, cellular phones, laptop computers, personal digital assistants and semiconductor packaging applications. Rogers’ R/flex JADE A series products are RoHS-compliant and are UL 94 V-0-classified for flame retardant performance. Outstanding thermal stability enables R/flex JADE A laminates to withstand multiple passes through a lead-free soldering process. R/flex JADE A materials’ excellent dimensional stability and adjustable squeeze-out control results in increased yields and better results in fine-line, tight tolerance design applications. Like the R/flex CRYSTAL line of products, the R/flex JADE A series features a transparent adhesive system that simplifies optical inspections. Available in bonding film, coverlayer and copper clad laminate constructions, the R/flex JADE series of products are manufactured under rigorous process controls that continuously monitor physical performance properties such as peel strength, squeeze-out control and dimensional stability. Rogers Corporation, Rogers, CT. (860) 774-9605. [www.rogerscorporation.com].

Freescale Adds 2 Mbit Devices to Growing MRAM Portfolio Freescale Semiconductor has introduced a series of 2 Mbit magnetoresistive random access memory (MRAM) devices, providing designers a broader portfolio of MRAM products for a range of commercial, industrial and automotive applications. Freescale’s 4 Mbit MR2A16A device, announced in 2006, is the world’s first commercially available MRAM product. The 2 Mbit MRAM replaces two current 1 Mbit nvRAM parts with a single device designed to help reduce system cost and board area. The 2 Mbit devices round out Freescale’s MRAM family of products with a choice of commercial, industrial and extended temperature ranges (operating from -40° to 105°C). MRAM devices are well suited for a variety of applications, such as networking, security, data storage, gaming and printers. The extended temperature version is suitable for use in rugged application environments, such as military, aerospace and automotive designs.

MRAM uses magnetic materials combined with conventional silicon circuitry to deliver the speed of SRAM with the non-volatility of flash in a single, unlimited-endurance device. MRAM devices offer industry-leading price/performance within the high-density non-volatile RAM market and can be used in applications that require speed, endurance and non-volatility. Freescale’s MRAM devices are designed to combine the best features of non-volatile memory and RAM to enable “instant-on” capability and power loss protection in new classes of intelligent electronic devices. The 2 Mbit MRAM device (MR1A16A) is in volume production and available at a suggested resale price of $12.50 in 10,000-unit quantities. Initial shipments are planned to begin in September 2007. Freescale Semiconductor, Austin, TX. (800) 521 6274. [www.freescale.com].

PORTABLE DESIGN

Industry’s Smallest Supervisory Circuits to Offer Battery Backup, Chip-Enable Gating and Power-Fail Warning for Power-Supply Monitoring Maxim Integrated Product introduces the MAX16033MAX16040 low-power, microprocessor supervisory circuits with precision power-supply monitoring and battery control functions. Optimized for performance in space-saving 2 mm x 2 mm microDFN packages, these supervisory circuits offer a variety of features, including a microprocessor reset, battery-backup switchover, power-fail warning and chip-enable gating, thereby reducing the complexity and number of components for power-supply monitoring. The small size and high integration of the MAX16033-MAX16040 make them ideal for a wide variety of applications, including point-of sale equipment, industrial equipment, fax machines, computers and set-top boxes. The MAX16033/MAX16040 automatically switch the RAM to the backup battery when Vcc falls below either the reset threshold or Vbatt. These devices also assert a reset when Vcc is below the reset-threshold voltage for at least 150 ms after Vcc returns above its threshold. The MAX16033/MAX16037 feature a manual-reset input, and the MAX16036/MAX16040 feature an auxiliary user-adjustable reset input for monitoring a second voltage. The MAX16034/MAX16038 include a watchdog function that triggers a reset pulse whenever WDI remains high or low for longer than the watchdog timeout period. The MAX16035/ MAX16039 feature a battery-on output during battery-backup mode. The MAX16033-MAX16036 provide internal gating of the chip-enable signals to prevent erroneous data from corrupting the CMOS RAM. Each device offers either an active-low, push-pull reset or an active-low, open-drain reset, and includes a power-fail comparator that signals an interrupt when Vpfi falls below 1.235V or when Vcc falls below the reset threshold. The MAX16033/MAX16040 consume only 13 microamps of quiescent current and operate from as low as 1.2V. Fully specified over the -40° to +85°C extended temperature range, they are available in 8- or 10-pin microDFN packages. Pricing starts at $1.98 (1000-up, FOB USA). Maxim Integrated Products, Inc., Sunnyvale, CA. (408) 737-7600. [www.maxim-ic.com].

Vishay Intertechnology, Inc. has announced the industry’s first power MOSFETs with onresistance ratings at a 1.2V gate-to-source voltage, a move that will help designers simplify power management circuitry while extending battery run-times in portable electronic systems. The new 1.2V-rated Vishay Siliconix TrenchFET devices bring the MOSFET turn-on voltage into alignment with the 1.2V to 1.3V operating voltages of digital ICs used in mobile electronics, enabling safer and more reliable designs. As the first power MOSFETs that can be driven directly from 1.2V buses, the new TrenchFETs provide the additional potential benefit of eliminating the need for an extra conversion stage in battery-operated systems with a core voltage lower than 1.8V. In MOSFETs for which 1.5V is the lowest rating, on-resistance tends to increase exponentially at lower, unspecified gate-to-source voltages such as 1.2V. By contrast, these new 1.2V TrenchFETs offer guaranteed n-channel on-resistance as low as 0.041 ohms and p-channel onresistance as low as 0.095 ohms at a 1.2V gate drive. On-resistance performance at a 1.5V gate drive is better than in devices for which 1.5V is the lowest gate-to-source specification: as low as 0.022 (n-channel) and 0.058 (p-channel). The devices released today (and their package types) are the n-channel SiA414DJ (PowerPAK SC-70), Si8424DB (MICRO FOOT), and SiB414DK (PowerPAK SC-75), and the p-channel SiA417DJ (PowerPAK SC-70), Si8429DB (MICRO FOOT), and SiB417DK (PowerPAK SC-75). The previously released p-channel Si1499DH in the SC-70 package completes Vishay’s 1.2V power MOSFET offerings. Typical applications for the new devices include load, power amplifier and battery charger switching in cell phones, PDAs, MP3 players, digital cameras and other portable systems. In addition to saving on battery power with their low on-resistance, the new devices will save on space with package dimensions as small as 1.5 mm by 1.5 mm. Samples and production quantities of all seven 1.2V devices are available now, with lead times of eight to 10 weeks for larger orders. Pricing for U.S. delivery starts at $0.15 each in 100,000-piece quantities. Vishay Intertechnology, Inc., Malvern, PA. (402) 563-6866. [www.vishay.com].

Open Source RTOS Targets Microchip Technology’s 16-bit dsPIC DSCs and PIC24 MCUs RoweBots Research Inc. today announced the launch of DSPnano Version 2 for the 16-bit dsPIC Digital Signal Controller (DSC) and PIC24 microcontroller (MCU) families from Microchip Technology. DSPnano is an open source RTOS and Eclipse-based tool set that increases small embedded signal processing system development productivity and reliability. OEM users can develop faster and better applications in less time to meet stretch market goals using these off-the-shelf products. From Microchip’s PIC24 16-bit MCUs through the dsPIC 30 30 MIPS DSCs to the dsPIC 33 40 MIPS DSCs, DSPnano offers seamless support including a C/C++ integrated development environment (IDE) based on Eclipse with a highly productive user interface; DSPnano operating system level simulator; seamless integration with Microchip’s MPLAB IDE for instruction-level simulation, compiling and debugging; integrated DSP RTOS with full POSIX capabilities and a tiny foot print to minimize training time and processor size; DSP libraries with 650 functions for off-the-shelf tried and proven processing; complete I/O minimizing development and integration; integrated with MPLAB IDE to use the MPLAB ICD 2 and MPLAB REAL ICE debugging and emulation hardware development tools. DSPnano V2 is hosted on Windows XP and Vista for x86 platforms. Support for the entire dsPIC DSC product line and the PIC24 MCU line is available. DSPnano V2 will begin shipping in Q3, 2007. It is priced from $499 for a single user. Open source royalty-free licenses start at $3,999. RoweBots Research Inc., Waterloo, Ontario. (519) 208-0189. [www.rowebots.com].

Low-Current Oscillators Extend Battery Life in Portable Applications Fox Electronics now offers two upgraded lines of SMD oscillators with reduced power consumption that provide an extended usable battery life for portable and battery-powered applications. Fox’s RoHS-compliant F330A and F530LA oscillators offer reduced heat generation to prolong battery life, which is paramount in offering a viable portable product. Fox’s new oscillators, which are low current versions of the popular Series F330 and F530L, are ideal for use in computers, cell phones, AM/FM Radio, CD/DVD players, MP3 players, satellite radio, tools, test equipment, scanners and bar code readers. The compact F330A, measuring 3.2 mm x 2.5 mm, and the F530LA, measuring 5 mm x 3.2 mm, are ideal for any portable application where an oscillator is required. In addition to the oscillators’ 1.800-50.000 MHz frequency range and 3.3V operation, the Series F530LA is available in a 5.0V (F550L) version for select portable applications. The oscillators also offer HCMOS output and a standby current of 1 μA, which reduces the production of heat and extends the product’s battery life. The oscillators’ lower current draw and reduced heat generation eliminate the need for cooling fins and fans as well. The Series F330A and F530LA have a storage temperature of -55° to +125°C and are conveniently packaged on tape and reel in 2,000 pcs. STD. Pricing for the F330A, 40 MHz, 2 Kpcs oscillator is $1.70 and the F530LA, 125 MHz, 2 Kpcs oscillator is priced at $1.31. Delivery is 10 weeks ARO. Fox Electronics, Ft. Meyers, FL. (239) 693-0099. [www.foxonline.com].

SEPTEMBER 2007

products for designers

Power MOSFETs Specifying On-Resistance at 1.2V Gate-to-Source Voltage

product feature Video Subsystem Targets LowCost, Portable Digital Video Devices Digital media processor provides HD video performance and double the battery life of today’s HD products. by John Donovan, Editor-in-Chief Considering the rapid market acceptance of Texas Instruments’ DaVinci line of digital video systems, it was inevitable that TI would turn its attention to the high end of the portable video market. This month TI announced the availability of a new embedded DaVinci processor with ARM host control and complete development tools. At a price of less than $10, TI claims its new TMS320DM355 digital media processor provides HD video performance and double

the battery life of today’s HD products. Target applications include digital cameras, IP video cameras, ultra low-cost video recorders and portable test equipment. The TMS320DM355 consists of an integrated video processing subsystem, an MPEG-4JPEG coprocessor (MJCP), an ARM926EJ-S core and peripherals. The processor is available in clock speeds of 216 MHz or 270 MHz, which

PORTABLE DESIGN

allows for a scalable line of products. The MJCP provides HD MPEG-4 SP encode or decode at 720p and 30 frames per second and JPEG encode or decode at 50 MegaPixels per second. The video processing subsystem integrates a preview engine, histogram, resizer and on-screen display all in hardware. The MJCP provides the equivalent of 400 MHz of digital signal processing (DSP) to achieve HD video, while the video processing subsystem tasks equate to approximately 240 MHz of performance on a DSP. Combined, the MJCP and video processing subsystem provide the equivalent of up to 640 MHz of DSP processing performance, leaving up to 270 MHz of ARM processing capabilities still available for product differentiation. The DM355 also includes a suite of peripherals, including high-speed USB 2.0 On-The-Go, three UARTs, two audio serial ports and a range of external memory interfaces (Async SRAM, mDDR, DDR2 SDRAM, OneNAND, NAND Flash, SmartMedia/xD). An integrated 10-bit D-A converter and video encoder are also included. On the power front, the DM355 consumes approximately 400 mW during HD MPEG-4 encoding and only 1 mW of stand-by power. This means that consumers using DM355-based digital cameras in video mode can expect to record 80 minutes of HD video while using just two AA batteries. It’s hard for Portable Design to think of TI’s characterization of nearly a half an amp as “ultra low power,” but considering that this is high-speed HD encoding, the results are impressive nonetheless. TI also provides a corresponding development tool, the DM355 Digital Video Evaluation Module (DVEVM), which takes advantage of the application programming interfaces (APIs) common across DaVinci offerings. The DVEVM includes optimized MontaVista Linux, an uboot loader and drivers for the complete peripheral set. Rounding out the DVEVM are the JPEG, MPEG-4 SP and G.711 codecs plus Video Input/Output, Audio In/Out, an external EMAC, USB 2.0 On-The-Go and JTAG for test. ORCAD schematics are also available at no charge. Support for Windows CE and other OSs is available from third parties. The DaVinci TMX320DM355ZCE216 processor is now sampling. The 216 MHz version will be priced in volume production at $9.75 in 50 ku and the 270 MHz version will be $11.49 in 50 ku. The highly integrated device is packaged in a 13 x 13 mm, 329 pin, 0.65 mm-pitch BGA package. The TMDXEVM355 Digital Video Evaluation Module is now available for $495. Texas Instruments Inc., Dallas, TX. (800) 336-5236. [www.ti.com].

advertiser index Amphenol Mobile Consumer Products/T&M Antennas www.ampphenol-tm.com

event calendar 10/02-04/07

ARM Developersâ&#x20AC;&#x2122; Conference & Design Pavilion Santa Clara, CA www.arm.com/developersconference 10/03-04/07

Atmel www.atmel.com

Portable Design Conference & Exhibition (PDCE)

CEVA wwwceva-dsp.com

10/11/07

Santa Clara, CA www.portabledesignconference.com

Real-Time & Embedded Computing Conference

EmbeddedCommunity.com www.embeddedcommunity.com

Intersil Corporation www.intersil.com

Linx Technologies, Inc www.linxtechnologies.com

Mouser Electronic www.mouser.com

National Semiconductor www.national.com

Tysons Corner, VA www.rtecc.com/tysons 10/16-18/07

AdvancedTCA Summit Santa Clara, CA www.advancedtcasummit.com 10/17-18/07

AFCEA Fall Intelligence Symposium Chantilly, VA

www.afcea.org

10/22-25/07

10th Annual Systems Engineering Conference San Diego, CA www.ndia.org 10/29-31/07

MILCOM Orlando, FL

Rogers Corporation www.realporon.com

www.milcom.org

11/05-08/07

TechNet Asia-Pacific Honolulu, HI

www.afcea.org

11/06/07

Real-Time & Embedded Computing Conference Detroit, MI

www.rtecc.com/detroit

11/06/07

Real-Time & Embedded Computing Conference Toronto, ON

www.rtecc.com/toronto

If you wish to have your industry event listed, contact Sally Bixby with The RTC Group at sallyb@rtcgroup.com

Reduce Energy Consumption with PowerWise Technology ®

Digitally-Programmable LP5552 Energy Management Unit Extends Battery Life and Enables New Features PWI 2.0 Bus PWI 2.0 Slave ENABLE RESETN PWROK

Adaptive Voltage Regulator

Processor Core

Adaptive Voltage Regulator

GPO Control

LP5552

PWI 2.0 MASTER

Hardware Accelerator

Advanced Power Controller

DSP (Adaptive Supply Voltage)

Programmable LDO

GP01 GP02 GPO3

(Adaptive Supply Voltage)

Programmable LDO

VPPLL/Analog

Programmable LDO

VIO

Programmable LDO

V Peripheral

Programmable LDO

V Memory

Embedded Memory TCM Cache Dual Core System-on-Chip IC

Ideal for use in dual core processors, cellular handsets, handheld radios, PDAs, battery powered devices, and portable instruments Product ID

# of Outputs

Output Voltages and Current

VIN Range

Interface

Package

LP5550

1 Buck: 0.6V to 1.2V, 300 mA 3 LDOs: 0.6V to 3.3V, up to 250 mA

3V to 5.5V

PWI 1.0

LLP-16

LP5551

2 Bucks: 0.6V to 1.2V, 300 mA 4 LDOs: 0.6V to 3.3V, up to 250 mA Nwell bias: -0.3 to +1V (to supply) Pwell bias: -1V to +0.3V (to GND)

2.7V to 5.5V

PWI 1.0

LLP-36

NEW LP5552

2 Bucks: 0.6V to 1.235V, 800 mA 5 LDOs: 0.6V to 3.3V, up to 250 mA

2.7V to 4.8V

PWI 2.0

micro SMD-36

For FREE samples, datasheets, and more information on PowerWise technology contact us today at: powerwise.national.com Or call 1-800-272-9959