featured product:

featured product:

Altera MAX IIZ CPLD

January 2008

www.portabledesign.com

Dealing with the Limitations of

Flash Memory

wireless communications: Mobile WiMAX consumer electronics: Mixed-Signal SoC Verification portable power: Programmable Clocks / Lower Supply Voltages An RTC Group Publication

CEO Interview:

Ray Zinn Micrel

Worldwide Semiconductor Revenue Forecast (Revenue in Millions of U.S. Dollars)

contents

380,000 361,379

Millions of U.S. Dollars

360,000

wireless communications

291,360

280,000

5260,000 6 8240,000 220,000 12 40 200,000 42 44

260,222

270,930

12 analysts’ pages 2006

2007

Frank Ferro, Sonics, Inc.

CPU

DSP

CPU

(MAC)

(PHY)

(MAC2)

consumer electronics

Karen Chow, Mentor Graphics Corp.

portable power

RTL

RTL Simulation

Chip-Level Memory Top-Level Testbench 20 mobile WiMax I/O CTL

Schematic Capture

Extend Battery Life Using 30 Simulation Programmable Clock Technology Custom Layout

Synthesis

Mixed-Signal Simulation

Static Timing Analysis

Chip-Level Assembly

Place and Route

DRC/LVS

DRC/LVS

Extraction

Extraction

Extraction

Static Timing Analysis

Post-Layout Simulation

Post-Layout Simulation

Greg Richmond, SpectraLinear, Inc.

Lower Supply Voltages Enable Low-Power 34

Portable Electronic Devices

Digital Design

BUS

Analog Design

2011

2010

Mobile WiMax: How to Make Mobile 20 WiMax Consumer Devices a Reality

Applying an Integrated Approach to 24 Mixed-Signal SoC Verification

2009

16 flash memory

2008

Dealing with the Limitations of 16 Flash Memory Xerxes Wania and Steven Cliadakis, Sidense

303,492

300,000

cover feature

320,000

departments

dave’s two cents editorial letter industry news analysts’ pages product feature design idea products for designers

334,061

340,000

Aditya Rao, Microchip Technology, Inc.

ceo interviewNo

Ray Zinn 48

Micrel

Design Meets Specs?

Yes

Yes Tapeout!

Design Meets Specs?

No

Yes

24 mixed-signal design

Design Meets Specs?

JANUARY 2008

No

team editorial team

Editorial Director Editor-in-Chief Managing Editor Copy Editor

Creative Director Art Director Graphic Designer Director of Web Development

Web Developer

Warren Andrews, warrena@rtcgroup.com John Donovan, johnd@rtcgroup.com Marina Tringali, marinat@rtcgroup.com Rochelle Cohn

art and media team Jason Van Dorn, jasonv@rtcgroup.com Kirsten T. Wyatt, kirstenw@rtcgroup.com Christopher Saucier, chriss@rtcgroup.com Marke Hallowell, markeh@rtcgroup.com Brian Hubbell, brianh@rtcgroup.com

management team

9/21/07 10:52:58 AM

Untitled-2 1

Associate Publisher Product Marketing Manager (acting) Western Advertising Manager Western Advertising Manager Eastern Advertising Manager Circulation

Marina Tringali, marinat@rtcgroup.com Aaron Foellmi, aaronf@rtcgroup.com Stacy Gandre, stacyg@rtcgroup.com Lauren Trudeau, laurent@rtcgroup.com Nancy Vanderslice, nancyv@rtcgroup.com Shannon McNichols, shannonm@rtcgroup.com

executive management

HOW WELL DO YOU KNOW THE INDUSTRY?

Chief Executive Officer Vice President Vice President of Finance Director of Corporate Marketing Director of Art and Media

John Reardon, johnr@rtcgroup.com Cindy Hickson, cindyh@rtcgroup.com Cindy Muir, cindym@rtcgroup.com Aaron Foellmi, aaronf@rtcgroup.com Jason Van Dorn, jasonv@rtcgroup.com

portable design advisory council Ravi Ambatipudi, National Semiconductor Doug Grant, Analog Devices, Inc. Dave Heacock, Texas Instruments Kazuyoshi Yamada, NEC America

corporate office WWW.EMBEDDEDCOMMUNITY.COM

The RTC Group 905 Calle Amanecer, Suite 250 San Clemente, CA 92673 Phone 949.226.2000 Fax 949.226.2050 www.rtcgroup.com

For reprints contact: Marina Tringali, marinat@rtcgroup.com.

Published by the RTC Group. Copyright 2007, the RTC Group. Printed in the United States. All rights reserved. All related graphics are trademarks of the RTC Group.

All other brand and product names are the property of their holders. Periodicals postage at San Clemente, CA 92673. Postmaster: send changes of address to: Portable Design, 905 Calle Amanecer, Suite 250, San Clemente, CA 92673.

Portable Design(ISSN 1086-1300) is published monthly by RTC Group 905 Calle Amanecer, Suite 250, San Clemente, CA 92673. Telephone 949-226-2000; 949226-2050; Web Address www.rtcgroup.com. Ride along enclosed. embeddedcommad_14v.indd 1 PORTABLE DESIGN

11/13/06 5:55:59 PM

dave’s two cents

H

Happy New Year! I cannot believe 2008 is already upon us. Early each year I draft a list of New Year’s resolutions. It is important to do them early so I can forget them early. This year I resolve to be more organized, learn more Chinese and, of course, live healthier. With any luck I will have eliminated all but one by February.

Another annual event of mine is to predict what may happen during the incoming year. There are easy predictions. For instance, portable devices will have more features at lower prices. And there are tougher predictions—like the total time I sit on the ground in an airplane.

Mixed predictions already exist about the electronics industry for 2008. Last October, EE Times reported that “Japan’s IC execs see 2008 upturn.” [1] They went on to report that NEC and Toshiba projected growth of 10 percent or more for 2008. However, not everyone agrees with the rosy outlook. In December, EE Times reported, “Gartner pulls down chip forecast.” [2] It’s not that there won’t be growth; it’s just that the expectations for growth are less—down from 8.2 to 6.2 percent. In another article published by Forbes, [3] a 50 percent probability of a recession is predicted for 2008.

Generally, economic predictions are like weather forecasts. For example, a 30 percent chance of rain means that rain is likely to fall on 30 percent of the region covered by the forecast.

While some analysts say they have not forecasted a recession for the U.S., they have increased the probability from 10 to 35 percent, [2] or up to as much as 50 percent. How should these numbers be interpreted? If they are like weather predictions, then that percentage of the economy could feel like it is in a recession. Or it could just be the probability of a recession, meaning that under the predicted circumstances, that percentage of the time we could enter a recession. If the U.S. does enter a recession, the analysts predict that growth for the electronics industry will be further reduced.

Unlike weather forecasting, economic predictions can influence the probability that the predictions become reality. With weather, predicting rain may make people carry an umbrella—but carrying an umbrella does not make it rain.

However, predicting an economic downturn can cause our industry to enter a hibernation mode, which in turn really can cause a downturn. Subsequently, those forecasting the downturn will have been correct.

I prefer information rather than forecasts and opinions. For example, inventories of DRAM and flash devices are building. The average unit price (AUP) of these devices is falling at some rate. This is usable information. We can use either the same amount of memory and move the

money to other valued functions, or we can use more memory. For example, “Kindle,” a wireless E-Book reader recently introduced by Amazon, reportedly sold out in less than six hours. It has only 256 Mbytes of memory. This is small in today’s portable memory standards. With memory inventory growing, maybe this device’s memory could be bigger? However, this shows that even in a soft market and with gloomy predictions that novel products can sell.

dave’s two cents on...

My Forecasts for 2008 For another example, an Olympic viewer could record his favorite sport while off doing other things. This may be an extension of the SlingPlayer™ Mobile. The sport could be viewed later on the portable device, or upon arrival at the hotel for a bigger screen. There are plenty of good ideas to drive our industry. We should not let the “gloomers” distract us.

I am not sure which is more complex—the economy or the weather. But what I do know is that reporting is more accurate than predicting for either one. All in all, 2008 presents another year for opportunities. We can both get busy and have a great year, or we can take a nap. Either one will make time go by. For my two cents, I predict a good year for 2008 with continued innovations and opportunities for all. I also predict that my resolutions have a 30 percent probability of lasting more than three months, unless I win the lottery by finding the winning ticket.

Dave Freeman, Texas Instruments EE Times: Semiconductor News, “Japan’s IC exces see 2008 upturn,” Mark LaPedus http://www.eetimes.com/showArticle.jhtml?arti cleID=202200193.

[1]

EE Times: Semiconductor News, “Gartner pulls down chip forecasts,” Rick Merritt http://www.eetimes.eu/semi/204701202.

[2]

Forbes: AFX News Limited, “Leading economists tell Congress recession dangers rising,” Thomson Financial News Limited 2007, URL: http://www.forbes.com/afxnewslimited/feeds/ afx/2007/12/05/afx4409040.html [3]

January 2008

editorial letter

N

Navigating CES is all about logistics and comfortable shoes. Thanks to days of planning, countless Frappuccinos and a new pair of Rockports, I managed to surf the hype, skim at least the highlights and discover a few hidden gems.

Still, with 2700 companies displaying their wares for the benefit of almost 150,000 attendees, even hitting the highlights is an endurance contest.

CES is all about generating buzz—or, worst case, trying to convince people that you have it. Nobody cranked up the buzz machine louder than Intel, starting with Paul Otellini’s opening day keynote. Otellini’s entertaining presentation focused on how the Internet has changed the world—and how much more it will change it once everything goes wireless. Otellini continued to beat up on cell phones as a highly inferior way to access the Internet, which they surely are.

His solution, most recently promoted at IDF, is Mobile Internet Devices (MIDs), all of which he expects to be powered by Intel’s pending Menlo chips. According to Otellini, the impact of MIDs will be nothing less than the advent of television.

Come on, Paul, get a grip.

Leaving Las Vegas

john donovan, editor-in-chief

Portable Design blog For more detailed coverage of the Portable Design industry, including videos and podcasts, check out my new blog at: www.portabledesign.blogspot.com.

PORTABLE DESIGN

Still, with Intel planning on pumping billions of dollars into promoting MIDs, only a fool would bet against them, especially when they’re addressing an admitted problem whose solution could open up a huge market—not coincidentally, an embedded market in which Intel has been a marginal player to date. Plenty of traditional handset makers are already jumping on the would-be bandwagon. Lenovo, AsusTek, Toshiba and Samsung all showed off MID prototypes that could browse the Web, send emails, play music, take pictures and work on office documents—and possibly even make a phone call.

Consumer acceptance of MIDs is anything but a given. Why would I want to spend $500+ to carry around yet another gadget that does very little beyond what my cell phone already does? The lack of infrastructure is another major problem. Cell phone service isn’t up to full video streaming; Wi-Fi access is too spotty; and WiMAX networks are a long way off. Everyone would welcome better mobile Internet access, but MIDs aren’t the obvious answer. By the time the infrastructure problems are solved, cell phone makers will no doubt be able to show much improved Internet-surfing capabilities, which will

undercut the main argument for MIDs. Besides, the first-generation MID is already here. It’s called the iPhone.

Not to belabor the point, but in an inadvertently related keynote, Jerry Yang of Yahoo showed off the new Yahoo! Go 3.0, which offers “a better Internet experience,” as the marketers say, on the current crop of cell phones. It’s a handsome GUI that Yahoo is opening to third-party developers, perhaps as a counter to Google’s Android efforts. Whatever, it’s a lot easier to use than the frustrating menu structure that afflicts most cell phone browsers.

One standing-room-only SuperSesssion was titled, “The Top Ten Technologies You’ve Never Heard Of.” They’re all wireless technologies that our readers have heard of (NFC, WiMAX, etc.), but not the mainstream press, apparently.

The panel concluded that in the near future almost all products will be completely wireless, including power cords. In case anyone missed it, the “next killer app” is already here: it’s wireless connectivity.

The ZigBee Alliance proudly displayed a range of wireless thermostats, power meters and other devices that can dynamically adjust home power consumption, under the control of either the power company or the homeowner. A number of power companies and a few states—California and Texas among them—are mandating the use of ZigBee-powered control devices in new building starts. The demand for such “green technology” could finally see ZigBee take off in a big way.

Analog Devices demonstrated mobile TV carried over Mobile Terrestrial DMB on a variety of devices. These are clearly aimed at the European market, where that standard is prevalent, and not the U.S., which is still assessing the MediaFlo vs. DVB-H fallout. They also had a fun demo of their audio chips, enabling a pickup-equipped acoustic guitar to sound like it was unplugged.

Qualcomm showed off its mirasol displays, based on a reflective MEMS technology. Combining high resolution with extremely low power consumption, the devices rely on optically resonant cavities instead of LCD pixels; they require no backlighting and can work equally well indoors or in direct sunlight. Qualcomm is right in considering this a “disruptive technology,” but we’d like to see full-color displays in production before drawing final conclusions.

All told, CES was a harrowing, fun experience, like skiing moguls or riding a roller coaster.

If there was any lingering question that portable consumer devices are driving the electronics industry, CES put it to rest.

MicroTouch is Going Mobile

Expanding

the Possibilities

3M Touch Systems

MicroTouch Flex Capacitive Touch Sensors for Mobile Applications TM

• Nearly Invisible ITO

Proprietary index matching technology to minimize ITO visibility

• Ultrathin Substrate

0.05 mm PET substrate enables compact design

• Creative Form Factors

Allows designers the freedom to explore a myriad of shapes

• High Volume Production

Roll process is capable of producing millions of units per month

Learn more about MicroTouch Going Mobile by calling 888-659-1080 or visit www.FlexCapTouch.com for details.

3M © 2007 MicroTouch is a trademark of the 3M Company.

news ON Semiconductor to Acquire AMIS Holdings, Inc.

ON Semiconductor Corporation and AMIS Holdings, Inc., parent company of AMI Semiconductor, have announced the signing of a definitive merger agreement providing for the acquisition of AMIS by ON Semiconductor in an all-stock transaction with an equity value of approximately $915 million.

“The acquisition of AMIS furthers the transformation of ON Semiconductor into an analog and power solutions leader with enhanced scale, higher value and higher margin products, deep customer relationships and an expanded addressable market,” said Keith Jackson, ON Semiconductor president and CEO. “Combining ON Semiconductor’s leading standard products and advanced manu-

74 percent and 26 percent, respectively, of the combined company.

ON Semiconductor president and CEO Keith Jackson will serve as president and CEO of the combined company. Corporate headquarters will remain in Phoenix, Arizona, with a significant presence maintained in Pocatello, Idaho, Belgium and various other locations worldwide. ON Semiconductor non-executive Chairman J. Daniel McCranie will continue as non-executive chairman of the Board of Directors of the combined company, which will be expanded to eight members with the addition of Christine King, CEO of AMIS. ON Semiconductor, Phoenix, AZ. (602) 244 6600. [www.onsemi.com].

AMI Semiconductor, Pocatello, ID. (208) 233-4690. [www.amis.com].

TSMC Unveils New 65 Nanometer Mixed-Signal and RF Tool Qualification Program

nd

er exploration ether your goal speak directly ical page, the ght resource. technology, es and products

ed

facturing infrastructure with AMIS’s growing standard products business and substantial custom product portfolio will enable the comcompanies providing solutions now bined company more comprehensively adexploration into products, technologies and companies. Whether your goal is to research the latest datasheetto from a company, mp to a company's technical page, the goal of Get Connected is to put you in touchdress with the right resource. Whichever level of our customers’ needs.” gy, Get Connected will help you connect with the companies and products you are searching for.

Under the terms of the agreement, which onnected has been approved by both boards of directors, AMIS shareholders will receive 1.150 shares of ON Semiconductor common stock for each share of AMIS common stock they own. Based on the closing stock price of ON Semiconductor on December 12, 2007, this represents a value to AMIS shareholders of approximately $10.14 per share. Upon completion of the transaction, ON Semiconductor will issue approximately 104 million shares of common stock on a fully diluted basis to comGet Connected with companies mentioned in this article. plete the transaction. ON Semiconductor and www.portabledesign.com/getconnected AMIS stockholders will own approximately

End of Article

PORTABLE DESIGN

Get Connected with companies mentioned in this article.

Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) has unveiled a comprehensive Electromagnetic (EM) Tool Qualification Program that drives its Design Service Ecosystem partners to ensure greater accuracy of EM simulators and extractors used in applications such as high-speed digital clock circuits and high-frequency mixed-signal RF designs.

Targeting TSMC’s 90 and 65 nanometer (nm) process technologies, the program improves device model accuracy, supports a wider selection of qualified EM tools, significantly reduces customer EM tool evaluation efforts, lowers the risk and eases adoption of TSMC advanced process technologies.

Typically, high-frequency circuit designers select a set of devices, such as inductors, to be included in their design, and evaluate different EM simulators from different tool vendors, trying to match EM simulator data to silicon measurements provided by foundry. Most of the time the results are different due to the variability of the process data and the wide variety of different test devices. Through the EM Tool Qualification Program, TSMC provides EM tool vendors a standardized set of devices and silicon measurements, and a unified technology file for extraction and modeling, thus eliminat-

ing the data inconsistency, reducing tool evaluation time and improving design accuracy. This is especially significant in nanometer RF designs where obtaining accurate device models at high frequency has created the bottleneck for first pass design success.

As part of the EM Tool Qualification Program, TSMC developed, and silicon-verified, a set of commonly used spiral inductors and provides the devices and the process data to EM tool vendors to verify the tool accuracy and ability to match silicon data. Once qualified, a tool qualification report is generated and posted on TSMC-Online, TSMC’s customer portal for designers to download and review. Multiple EDA partners participate and are being qualified in the program including Agilent, Ansoft, Cadence, Helic, Integrand, Lorentz, OEA, Silvaco and Zeland.

TSMC North America, San Jose, CA. (408) 382-8000. [www.tsmc.com].

Interoperable SystemVerilog Methodology Ready for Download

Cadence Design Systems, Inc. and Mentor Graphics Corp. have announced immediate availability of the Open Verification Methodology (OVM). Distributed under the standard open-source Apache 2.0 license, the OVM source code, documentation and use examples may be downloaded free of charge from www. ovmworld.org.

The OVM, based on IEEE Std. 1800-2005 SystemVerilog standard, is the first open, language-interoperable SystemVerilog verification methodology in the industry. The OVM provides a methodology and accompanying library that allow users to create modular, reusable verification environments in which components communicate with each other via

standard transaction-level modeling interfaces.

It also enables intra- and inter-company reuse through a common methodology and classes for virtual sequences and block-to-system reuse, and full integration with other languages commonly used in production flows. As a joint development initiative between Mentor Graphics and Cadence Design Systems, the OVM is supported on multiple verification platforms ideally suited to both novice and expert verification engineers.

The OVM includes the foundation-level utilities necessary for building advanced object-oriented, coverage-driven verification environments and reusable verification IP (VIP) in SystemVerilog. The OVM reduces the complexity of adopting SystemVerilog by embed-

ding verification practices into its methodology and library, and significantly shortens the time to create verification environments. It easily integrates plug-and-play VIP and ensures code portability and reuse.

A production version of OVM is available immediately with additional functionality planned for release later in 2008. Cadence and Mentor have collaborated to ensure that the OVM runs on their simulators and enables backward compatibility with their existing environments, Advanced Verification Methodology from Mentor Graphics and Incisive Planto-Closure Methodology (Universal Reuse Methodology module) from Cadence.

Cadence Design Systems Inc, San Jose, CA. (408) 943-1234. [www.cadence.com].

Mentor Graphics Corporation, Wilsonville, OR. (503) 685-7000. [www.mentor.com].

Xilinx Names New President & CEO

Xilinx, Inc. has announced that Moshe Gavrielov, 53, has been appointed president and chief executive officer (CEO), succeeding Wil-

lem P. Roelandts, 63, who remains chairman of the board. Gavrielov becomes only the third Xilinx CEO in its 24-year history, and brings nearly 30 years of executive management and engineering experience with semiconductor and software companies to Xilinx. Gavrielov’s appointment is effective immediately.

Most recently, Gavrielov served as executive vice president and general manager of the fastgrowing verification division at Cadence De-

sign Systems, Inc. Before that, Gavrielov spent seven years as CEO of Verisity Ltd., where he grew the company from a $4M start-up, taking it through its initial public offering (IPO) in 2001 to a $70M publicly traded company, and ultimately to its acquisition by electronic design automation leader Cadence in 2005.

Prior to joining Verisity, then Cadence, Gavrielov spent nearly ten years at LSI Logic Corp., where he served in a variety of executive management positions, including executive vice president for the $1.3B products group, senior vice president of international markets, general manager for Europe, and general manager of the application-specific integrated circuit (ASIC) division. Gavrielov began his career in engineering and engineering management at National Semiconductor and Digital Equipment. Gavrielov earned a bachelor’s degree in electrical engineering and a master’s degree in computer science from the Israel Institute of Technology (Technion) in Haifa, Israel. He possesses five patents.

In his new role, Gavrielov succeeds one of the most highly respected CEOs in the industry.

Roelandts was named president and CEO of Xilinx in 1996 after a 30-year management career at Hewlett-Packard Co. Just before joining Xilinx, he served as senior vice president responsible for all aspects of HP’s then $6 billion worldwide computer systems business, including research and development, manufacturing, marketing, professional services and sales.

JANUARY 2008

news Over more than a decade, Roelandts has led Xilinx through an intense period of change within the semiconductor industry, growing the company’s sales from $560 million to over $1.8 billion in fiscal year 2007. During his tenure, Roelandts significantly expanded the company’s global business and initiated its successful market diversification strategy to better address high-growth end markets, including consumer, automotive, industrial and defense.

These markets have grown from 12 percent of total revenues in fiscal year 2002 to 45 percent of total revenues today.

Xilinx, San Jose, CA. (408) 559-7778. [www.xilinx.com].

Hydrogen Fuel Cells for Portable Devices

At CES, Canadian start-up Angstrom Power Inc. announced the completion of a six-month test of fully integrated hydrogen fuel-cell-pownd ered mobile devices. Offering twice the runtime of batteries and with recharge times on er exploration ether your goal the order of 10 minutes, Angstrom’s EverOn speak directly capability proposes to supplant the lithium-ion ical page, the ght resource. batteries commonly used in today’s portable technology, electronic devices. es and products Angstrom’s power platform was successed fully integrated into MOTOSLVR L7 handsets for the trial, with no modification to the outside dimensions of the devices. The trial devices did not rely on the use of any battery—instead, they drew power from Angstrom’s Micro Hydrogen platform, which is comprised of a novel fuel companies providing solutions now cell innovative exploration into products, technologies and companies. Whether your goal is to research thearchitecture, latest datasheet from a company,micro-fluidics and mp to a company's technical page, the goal of Get Connected is to put you in toucha with the right resource.

Whichever level tank. of refillable hydrogen storage Angstrom gy, Get Connected will help you connect with the companies and products you arehas searching for. demonstrated research results showing onnected twice the talk-time of the equivalent batterypowered devices in side-by-side testing.

Angstrom’s fuel storage is designed for tight integration with the fuel cell and features metal hydrides. Metal hydrides bond hydrogen molecules directly to the surface of the material; hydrogen desorbs from metal hydrides in a self-regulating fashion at low pressures and ambient conditions.

The company is currently collaborating with world-leading battery manufacturers, Get Connected with companies mentioned in this article. portable electronic device makers—includwww.portabledesign.com/getconnected ing Motorola—and mobile service providers

End of Article

10

PORTABLE DESIGN

Get Connected with companies mentioned in this article.

toward the commercialization of its Micro Hydrogen technology.

The commercialization of Angstrom’s technology reached another milestone on November 16th, 2007, when the International Civil Aviation Organization (ICAO) created new regulations that will permit Angstrom’s devices to be transported globally in the passenger cabin of commercial aircraft. Final approval is expected before the regulations take effect in January 2009. With approval from Transport Canada, which preceded the ICAO regulations, Angstrom products have already made more than 60 commercial flights to date.

Angstrom Power Incorporated, North Vancouver, BC. (604) 980-9936. [www.angstrompower.com].

Neonode to Launch N2 Mobile Phone in U.S.

Swedish mobile technology company Neonode will launch their latest mobile phone Neonode N2 in the United States in 2008. The cutting-edge phone utilizes Neonode’s patented neno user interface and zForce optical touch screen technology, offering users an intuitive and easy to navigate experience.

The most recent development in mobile phone technology is the emerging popularity of the touch screen. Neonode N2 uses the most advanced touch screen technology, the zForce optical touch screen. It doesn’t need any hard pressure or stylus but works quickly and accurately by reacting to sweeping and tapping signals on the screen. The intuitively organized user interface, neno, delivers quick and easy access to applications and content.

Neonode N2 was launched in Europe (third quarter 2007) to critical acclaim. Neonode N2’s United States phone carrier and retail availability will be announced the second quarter 2008.

Neonode demonstrated its Neonode N2 mobile phone as well as their technologies at this month’s Consumer Electronics Show.

Neonode also announced that it has joined with U.S. sales channel development and supply chain company, Distribution Management Consolidators Worldwide LLC (DMC), to form Neonode USA. The new entity will market existing and new innovative products within North America, Latin America and China, and will commercially market the Neonode technology globally.

Neonode USA, New York, NY. (917) 312-0694. [www.neonode.com].

Breakthrough in Glass Substrates for OLEDs

Saint-Gobain and Novaled have demonstrated the feasibility of large area OLEDS, based on a new high-performance metallic anode, with Saint-Gobain Recherche technology and Novaled OLED proprietary developments.

Researchers at Saint-Gobain Recherche (SGR) have created a highly conductive transparent electrode “Silverduct,” bringing up to 10 times better surface conductivity than traditional ITO (Indium Tin Oxide). Thanks to the Novaled PIN OLED technology for highefficiency OLEDs, samples were successfully manufactured on large area surfaces. SGR and Novaled now see the possibility to produce OLED devices up to 100 cm², which will ease the manufacturing of large OLED lighting products.

Traditional ITO coated glass impedes the race to large area OLED, due to its limited abil-

ity to carry current over distances longer than a couple of centimeters. Therefore, for large area OLEDs, the ITO layer must be topped with a thick metallic grid to prevent gradient of light emission caused by the sheet resistance of ITO alone (typically 30 ohm/sq). The new anode Silverduct has a sheet resistance of less than 4 ohm/sq, thus enabling large area OLEDs without additional metal grids. This is an important step especially for transparent and bottom emission OLEDs in which the metal grid is visible. Additionally, by eliminating the metal grid Silverduct offers significant potential for reducing manufacturing costs.

OLEDs are semiconductors made of thin organic material layers of only a few nanometers thickness. They emit light in a diffuse way to form an area light source. In a fast growing display market OLEDs are key part of a revolution: the dream of paper-thin, highly efficient displays with brilliant colors and great flexibility in design is becoming reality. OLEDs represent the future of a vast array of completely new lighting applications and at the same time offer the potential to become even more efficient than energy-saving bulbs.

Novaled AG, Dresden, Germany. +49 351 796 5819. [www.novaled.com].

SDR Forum Report Makes Technology Recommendations for the 700 MHz Spectrum

The Software Defined Radio (SDR) Forum, a nonprofit international industry association supporting the advancement of reconfigurable wireless technology, has issued a report identifying how SDR and cognitive radio technology can facilitate implementing a nationwide interoperable broadband network in the 700 MHz spectrum that conforms to Federal Communications Commission (FCC) regulations.

Initiated by the Forum’s Public Safety Special Interest Group (SIG) and prepared by an ad hoc committee, the 21-page report (“Technology Considerations and Recommendations for Software Defined Radio Technologies for the 700 MHz Public/Private Partnership”) cites the upcoming auction and licensing of the 700 MHz spectrum as a unique opportunity to fulfill the growing demand for spectrum resources for commercial and public safety broadband applications.

The report notes that the FCC has adopted the strictest ever build-out rules for wireless services and established rules to govern the partnership between commercial carriers and the public safety community in sharing spectrum and network resources. Though it acknowledges that improving public safety communications

through sharing resources with a commercial system is an innovative concept for using the new 700 MHz spectrum, the report recognizes the challenges that implementing the proposed network presents. Derived from the FCC requirements, the challenges include meeting the divergent needs of commercial and public safety users; coverage; shared operational control; robustness; adaptability; and spectrum use in the absence of network build-out.

The Forum report offers specific examples of how these technologies can be used to address critical implementation challenges of systems that meet the FCC’s defined service rules.

One such approach incorporates SDR, cognitive radio and dynamic spectrum access technologies—in both the system infrastructure and subscriber units—to provide a highly flexible network solution that can meet diverse requirements and develop in concert with technology and operational evolution.

SDR Forum, Denver, CO. (303) 628-5461. [www.sdrforum.org].

JANUARY 2008

11

analysts’ pages iSuppli Trims 2008 Semiconductor Forecast

Citing global economic woes, iSuppli Corp. has reduced its forecast for global semiconductor revenue growth in 2008, but still foresees a positive year for the market—particularly in the second half. iSuppli now predicts

figure 1 Worldwide Semiconductor Revenue Forecast (Revenue in Millions of U.S. Dollars) 380,000 361,379

Millions of U.S. Dollars

360,000 334,061

340,000 320,000

303,492

300,000

291,360

280,000 260,000

260,222

270,930

240,000 220,000 200,000

2006

2007

2008

2009

2011

2010

figure 2 iSuppli Global Electronic Equipment Revenue Forecast (Revenue in Millions of U.S. Dollars) 2000000

Millions of U.S. Dollars

1865261.988 1776266.815

1800000

1683117.977 1598466.449

1600000

1499163.574 1400000

1395579.454

1200000

1000000

12

2006

PORTABLE DESIGN

2007

2008

2009

2010

2011

global semiconductor revenue will rise to $291.4 billion in 2008, up 7.5 percent from an estimated $270.9 billion in 2007. This represents a 1.8-percentage-point reduction from iSuppli’s previous prediction in September of a 9.3 percent increase for the year. Figure 1 presents iSuppli’s forecast for global annual semiconductor revenue.

Global semiconductor sales in 2008 will be negatively impacted by rising energy costs.

Furthermore, the sub-prime mortgage crisis is dimming the economic outlook for the United States next year. This will have global repercussions, impacting demand in other nations.

These factors will contribute to underinvestment and nervous customers in 2008, restraining growth as they cut orders.

First-Half Struggles Semiconductor market conditions will be extremely weak in the first half of 2008. Global chip revenue during the first six months of the year will decline to $135.9 billion, down 4.5 percent from $142.3 billion in the second half of 2007.

Memory market conditions will be very poor during the first half of 2008, with prices falling due to oversupplied conditions for DRAM and NAND-type flash memory early in the year.

The DRAM market is expected to undergo a pricing recovery in the second quarter of 2008, but NAND will not begin to rebound until the third quarter. Because of this staggered recovery, the impact of memory’s resurgence will not be felt by the overall semiconductor market until the third quarter of 2008.

With memory devices expected to account for 21.6 percent of global semiconductor revenue in 2008, developments in this market will have a major impact on the overall chip industry. The normal, seasonal up tick in semiconductor sales will drive the recovery in memory in the second half. However, iSuppli cautions that the potential arrival of a much-feared recession in 2008 could put a damper on this expected growth and may scuttle the anticipated second-half recovery.

Equipment Outlook Reduced Along with the reduction in the semiconductor outlook, iSuppli has reduced its 2008 growth

forecast for all types of electronic equipment.

Global electronic equipment revenue is expected to rise to $1.6 trillion in 2008, up 6.6 percent from $1.5 trillion in 2007. This is down 0.4 of a percentage point from iSuppli’s previous forecast of 7 percent growth. Figure 2 presents iSuppli’s forecast for global annual electronic equipment revenue.

Notebook PCs and 3G mobile handsets attained strong growth in shipments in 2007.

However, growth in these products is not expected to reach the same levels in 2008.

Equipment revenue in 2008 also will be impacted by economic concerns and reductions in capital spending.

RF Power Semiconductor Market Will Near $1 Billion in 2012

A new report by ABI Research predicts that the market for RF power semiconductors—those with outputs of 5W or more—will approach $1 billion by 2012, with markets outside of wireless infrastructure starting to take up the slack.

But according to research director Lance Wilson, “The shape of the industry five years hence will depend on three critical questions.

At the manufacturing level, will the introduction of gallium nitride and silicon carbide RF power devices mean the demise of Si LDMOS? With mobile/3G infrastructure markets in decline, will they continue to drive

iSuppli Corporation, El Segundo, CA. (310) 524-4000. [www.isuppli.com].

Ultrawideband Beginning to Take Off

The market for Ultrawideband (UWB) finally started to take off in 2007, reports InStat. Though regulatory hurdles over UWB still persist worldwide, the first UWB-enabled notebook PCs have shipped last year from Dell, Lenovo and Toshiba, the high-tech market research firm says.

“The primary question for UWB now is: Will other product segments follow where PCs lead?” says Brian O’Rourke, In-Stat analyst.

“UWB is a very flexible technology in that it supports multiple standards, including WUSB, Bluetooth 3.0, IP over UWB and Video over UWB. This should enable the technology to gain design wins in a wide range of product segments, including PC peripherals, Consumer Electronics (CE) and mobile phones.”

Recent research by In-Stat found the following: • UWB-enabled notebook PCs hit the market in mid-2007. PC peripherals will follow in 2008.

• CE and communications applications with UWB won’t hit the market in volume until 2010.

• In 2011, over 400 million UWB-enabled devices will ship.

In-Stat, Scottsdale, AZ (480) 483-4440. [www.in-stat.com].

the RF power semiconductor industry as they have in the past? Will the market segments outside of wireless infrastructure shore up this market space?”

To answer these and other questions, ABI Research undertook a market sizing study for all RF power semiconductors with power outputs above 5W, operating at frequencies of 3.8 GHz and below. (A later study will target those operating at higher frequencies.) The study sizes the RF power semiconductor market into six usage-based segments and 24 subsegments, providing a highly detailed, marketdriven analysis.

The six major segments are: wireless infrastructure, military, ISM (Industrial/Scientific/Medical), broadcast, commercial avionics and non-cellular communications. Each of these is subdivided into between two and six specialty segments.

The need for such a study arose, according to Wilson, because “This market has been overshadowed for many years by the wireless infrastructure sector. Now that new 3G/cellular wireless infrastructure deployments are declining, there is a paucity of information about how the rest of the industry is faring. This

study puts wireless infrastructure—which is well understood—into the context of the rest of these markets.”

ABI Research. Oyster Bay, NY. (516) 624-2500. [www.abiresearch.com].

WiMAX Will Be Successful, Study Says

Forward Concepts has announced the publication of its newest in-depth study of the global WiMAX market. The new 300-page study, “WiMAX ‘08: The 3G+ Broadband Alternative,” is an in-depth analysis of operators, equipment, chips and broadband alternatives, both wired and wireless.

According to the principal author, Carter L. Horney, “3G cellular (HSPA and EV-DO) and mobile WiMAX are the technologies that will serve the majority of the 2012 mobile wireless broadband market, but HSOPA (High Speed OFDM Packet Access), LTE (Long Term Evolution) and/or Ultra Mobile Broadband (UMB) will also be available then.” Key study findings include: • WIMAX, variously as fixed or mobile services, will bring broadband access services to rural and undeveloped regions of the world.

• WIMAX growth in India will be strong and will precede 3G rollouts.

• WIMAX will become large in China, but on the heels of 3G TD-SCDMA. • If mobile WiMAX can supplement existing cellular networks as an overlay, it will become a mainstream technology.

Will Strauss, Forward Concepts’ president and editor/contributor of the report said “High profile cellular operators that have put their weight behind Mobile WiMAX include Sprint Nextel in the U.S., Rogers in Canada, KDDI and Softbank in Japan, and Telefonica in both Spain and Latin America.” The study also notes that the supporting ecosystem is growing, for example: • Over 200 Operators are deploying WiMAX, worldwide • Over 30 companies are supplying WiMAX infrastructure equipment JANUARY 2008

13

analysts’ pages • Over 16 companies are providing WiMAX client equipment • Over 19 companies offer 802.16e MAC/ PHY baseband chip sets • Over 15 companies are now offer WiMAX radio transceiver chips Forward Concepts, Tempe, AZ. (480) 968-3759. [www.fwdconcepts.com].

Despite Progress, Uncertainty Remains for WiMAX

WiMAX continues to make gains, with network trials becoming commercial deployments, and well-known vendors adding the technology to their product portfolios, reports In-Stat. Despite many positive events over the last 12 months, however, WiMAX still faces much uncertainty, the high-tech market research firm says.

“Investor pressure could force Sprint to pull back on its announced deployment,” says Daryl Schoolar, In-Stat analyst. “As the largest planned deployment, Sprint’s actions could impact what other carriers do with WiMAX, and negatively impact the entire WiMAX community.”

Recent research by In-Stat found the following: • Shipments of 802.16e-compliant infrastructure overtook 802.16d in 2007.

• North America service revenues will account for 41% of all service revenues in 2012.

• Vendors remain uncertain over the form and business case for WiMAX femtocells.

In-Stat, Scottsdale, AZ. (480) 483-4440. [www.in-stat.com].

Teardown Reveals Apple’s iPod touch is More Than an iPhone Without a Phone

On the outside, Apple Inc.’s iPod touch looks a lot like its iPhone. On the inside, there’s a strong resemblance too—but a dissection conducted by iSuppli Corp.’s Teardown Analysis service reveals the touch sports a distinct design and unique advancements compared to the iPhone.

14

PORTABLE DESIGN

An iPhone Minus the Phone?

Functionally, the Apple iPod touch is an iPhone minus several features, including cellphone capability, Bluetooth and certain software elements. Otherwise, the core features of the iPhone user experience are all present in the iPod touch, including orientation sensing, Web surfing via Wi-Fi and the product’s signature feature: a 3.5-inch diagonal touch screen with multi-touch sensing. These advanced features place the iPod touch right at the top of Apple’s iPod line.

“The iPod touch likely represents the future of the high end of the iPod line,” said Andrew Rassweiler, teardown services manager and principal analyst for iSuppli. “Click Wheelinterface and Hard-Disk Drive (HDD)-based versions of the iPod are expected to wane in favor of touch-screen and flash-memoryequipped models like the iPod touch. But despite its functional and physical outward resemblance to the iPhone, and the fact that its internals borrow heavily from the iPhone, the iPod touch is no iPhone clone, and has its own unique design.”

Family Resemblance Rassweiler estimated the iPod touch and iPhone designs have a 90 percent commonality in terms of components.

For example, the key Integrated Circuit (IC) at the core of both the iPod touch and iPhone is Samsung Electronics Co. Ltd.’s video/applications processor, a chip based on an ARM microprocessor core and employing stacked on-package memory. Costing $13.19 based on iSuppli’s October estimate, the Samsung processor accounts for 8.5 percent of the iPod touch’s total cost.

Another common part between the two products is a power-management IC from NXP Semiconductors Netherlands B.V., costing $2.61 and accounting for 1.7 percent of the iPod touch’s cost in October.

Design Departure However, the iPod touch’s design differs from the iPhone in that it is uniquely optimized to meet its form-factor and cost requirements.

To cut space usage, the iPod touch makes use of some advanced packaging for its components not seen in the iPhone, including 0201 diodes and passive components in 01005 enclosures on the touch’s WLAN module.

“This is the first time iSuppli has seen these components in a product we’ve torn down,” Rassweiler said. “Apple products always seem to push the envelope in terms of space savings, and therefore we often first see the newest, most-compact components in Apple products.”

The iPod touch design also pushes the envelope in terms of memory density. The highend version of the product includes 16 Gbytes of NAND flash memory, more than any product in the Apple iPod line. In contrast, the high-end iPhone offers only 8 Gbytes of NAND flash.

Another notable difference is in the Printed Circuit Board (PCB) design. The iPod touch employs a single PCB as opposed to the iPhone’s modular two-PCB design.

Other differences between the touch and the iPhone include a new set of components to support the iPod touch’s Wireless LAN (WLAN) functions and the location of the touch-screen circuitry on the main PCB—rather than on the touch-screen module.

The arrival of the flash-memory-based touch will have major implications for the rest of Apple’s iPod line, iSuppli believes.

“The touch, along with the nano, may drive Apple’s HDD-based iPods close to extinction in the near future,” said Chris Crotty, senior analyst, consumer electronics, for iSuppli.

“While not a dollar-for-byte match for HDDs, flash now offers sufficient capacity that many consumers are willing to trade off storage for advanced displays and features.” iSuppli Corporation, El Segundo, CA. (310) 524-4000. [www.isuppli.com].

Keep your most precious stuff safe and secure

Don’t put important applications in the hands of commodity compact flash card suppliers. White Electronic Designs’ CompactFlash® is made for critical industrial or medical applications with the same reliability and attention to detail that our military products receive. Commodity flash cards may have hidden component changes that affect performance. We offer complete traceability and provide customer notification for any part changes.

New Medical Series 1 CompactFlash cards from White Electronic Designs offer unmatched reliability and stability even in power-down interruptions.

To learn more, visit www.whiteedc.com/compactflash

Other Key Features: • Firmware control • World class wear-leveling to extend product life • Data loss protection • Densities from 128MB to 8GB • High Endurance — 4 x 106 Cycles • Obsolescence Management and Revision Control • Environmentally Resistant Conformal Coating Option • Dedicated 32-bit RISC Flash Controller • RoHS Compliant • Error Correction Control (ECC) • Brown Out Protection

www.whiteedc.com

Tel: 602.437.1520 • Fax: 602.437.9120 Microelectronics • Display Systems • Interface Electronics • Electromechanical Products * Not authorized for use as critical components in life support devices or systems.

CompactFlash® is a registered trademark of SanDisk Corporation.

cover feature flash memory

Dealing with the Limitations of Flash Memory Low-power non-volatile memory is critical for a wide range of portable devices. In many of them, flash is not an option.

by X erxes Wania, President and CEO, and Steven Cliadakis, VP of Worldwide Sales and Marketing, Sidense

E

Embedded non-volatile memory (NVM) is a critical component in a wide range of applications that require a cost-effective, secure and low-power means of storing critical data and code. Two diverse portable device examples— RFID tags and implantable medical devices— demonstrate the need for this type of memory.

RFID tags, which include both a silicon chip and an antenna, provide a simple and inexpensive way to deliver accurate data on tagged items (Figure 1). Applications for these tags include tracking consumer retail goods, verifying the authenticity of pharmaceuticals, tracking automobiles through tollbooths and tracing lost pets. Embedded NVM for these tags must be cost-effective, adding negligible cost to these very low priced components—some tags cost less than 10 cents in large quantities. This requires NVM that adds no cost to the chip processing and has a small footprint. The memory must also dissipate very little power to maxi-

16

PORTABLE DESIGN

mize the read range of these tags. The tags must also be field-configurable, which eliminates masked ROM as a storage medium.

Implantable Medical devices are not what most people think of when they hear the term “portable devices.” However they are, indeed, part of this general category with some very unique requirements. With each generation, devices such as pacemakers/defibrillators and cochlear implants become more complex, with ever increasing data storage requirements. As an example of these “ultimate body computers,” ICDs (Implantable Cardioverter Defibrillators) have to not only hold large amounts of history data, they also need to store operational information such as threshold voltages and trigger heart rates, along with the processor code that tells the device what to do (Figure 2).

The latter two needs require an extremely reliable non-volatile memory, with retention rates greater than 10 years. Device failure is not an

with standards. with Wind River.

Mike Deliman Here’s a guy who appreciates the view from above. When he’s not trekking the high plains and mountain passes of Tibet, Mike Deliman is working on aerospace and defense projects for Wind River. He’s fond of Mars rovers, solar panels, and astronauts; and his real-life heroes are Albert Einstein and the Dalai Lama. He’s aiming high.

Regional Developer Conference, Aerospace and Defense Edition Register now to join Wind River and our partners at one of three , full-day conferences dedicated to Wind River’s aerospace and defense solutions including: Wind River's new VxWorks 653 Platform 2.2, Wind River Real-Time Core for Linux (with FSMLabs technology), Wind River's VxWorks AMP/SMP multicore support, ARINC 653 and Integrated Modular Avionics (IMA) , and DO-178B safety certification http://www.windriver.com/announces/ad_conference/index.html

March 12, 2008

March 27, 2008

April 2, 2008

Hilton Santa Clara 4949 Great America Parkway Santa Clara, CA 95054 Tel.: 408-330-0001

Turf Valley Resort 2700 Turf Valley Road Ellicott City, MD 21042

Four Seasons Resort & Club Dallas at Las Colinas 4150 North MacArthur Boulevard Irving, TX 75038 Tel.: 972-717-0700

Tel.: 410-423-0833

® 2008 Wind River Systems, Inc. The Wind RIver logo is a trademark, and Wind River is a registered trademark of Wind River Systems, Inc. Others marks are the property of their respective owners.

cover feature

Flash Memory – It isn’t for Everything Flash memory technology has made tremendous gains over the past few years. Driven primarily by the consumer market, flash has found its way into a wide range of consumer devices that need to store large amounts (Gigabytes) of digital audio, graphics and video content; it is being used to store boot-up and other code for processor cores; and is currently being touted as a more reliable, lower-power alternative for hard disk drives in low-end PCs. While a very useful non-volatile memory (NVM) technology for devices that do not require high levels of stored data security and minimal cost, flash technology does have some inherent shortcomings that preclude its use in certain applications—mostly embedded—that require low cost, small memory footprint, a high level of security, and scalability to leading-edge process nodes and beyond (Table 1).

Standard Logic CMOS

Scalable <90nm

Scalable <3.3V

High Density

Field Prog.

Low Cost

Read Access <10ns

Secure

NVM (antifuse based)

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Flash (floating gate)

No

No

No

Yes

Yes

No

No

No erasable, readable

Table 1 Flash memory has some weaknesses that eliminate it as a choice for certain embedded applications where other NVMs that are not based on floating-gate technology make more sense.

Scalability is one area where flash memory has severe limitations. The technology works by storing charge on a floating insulated gate. Unlike DRAM, which is refreshed periodically, flash’s stored charge must remain intact for long periods of time and should have a retention period of 10 years or more. As process nodes shrink to 90 nm and below, oxide thicknesses decrease, resulting in increasing levels of charge leakage and a decrease in flash data retention rates. As a result, flash technology runs one to two generations behind the leading-edge logic CMOS processes in which SoCs are fabricated to keep costs low and feature sets rich.

NVM technologies that are not based on a floating gate, such as those that depend on gate oxide breakdown to program a memory bit, do not suffer from this charge leakage issue.

To embed flash in a standard logic CMOS process requires additional masks and process steps. These extra steps add significant cost to the chip, around 30%-50%. For many consumer-driven applications, where profit margins are razor thin, embedded flash is just not a viable alternative.

For applications that require only one-time or few-time programmable memory in large quantity, such as processor boot-code storage, embedded flash on the same chip as the processor(s) makes the chip too large and adds additional silicon cost to the end product. For embedded applications that are few-time programmable, such as boot code that may be updated infrequently, a small footprint OTP memory with an unallocated memory sector that can be programmed and swapped with a previously programmed sector is a smaller and less expensive alternative to flash.

Finally, many applications require a very high degree of security to protect hardware and software chip resources, as well as user information and digital content. These uses range from low-bit-count security keys and IDs to multi-megabit code storage. This has become increasingly important over the past few years with the proliferation of mobile consumer devices that download and store huge amounts of copyrighted digital content, requiring a high level of protection against piracy through the use of encryption keys and other techniques. A chip developer who fails to protect third-party IP may be at serious legal and financial risk. Flash is just not a very secure storage medium. Since flash memory is programmed through a charge-storage mechanism, it can be read (and pirated) using voltage contrast microscopy or altered (maliciously or accidentally) using SEM or FIB (focused ion beam) equipment. Charge on a floating gate in flash memory can be removed through exposure to high temperature, light or electron and ion beams. Since NVM solutions based on oxide breakdown technology do not store charge on a floating gate, they don’t have this charge removal problem and cannot have their contents read through voltage contrast techniques.

So while flash has its uses, primarily for storing large amounts of frequently updated data, it doesn’t have the security, cost and process scalability advantages of an embedded, dense OTP memory. Designers should consider using embedded OTP IP as an enabling storage technology in many of their designs.

18

PORTABLE DESIGN

cover feature figure 1

Both RFID and implantable medical chips demonstrate the need for embedded NVM with the attributes of small size and cost, high reliability, long retention rate, very low power dissipation and field configurability.

An RFID tag for tracking live or inanimate objects requires very low cost and small memory for storing IDs.

option—even if device failure is not life threatening, it requires replacement and an invasive surgical procedure, with the accompanying risk factors associated with any surgery.

Electronic devices that are implanted within the human body need to withstand severe external conditions. The body constitutes a corrosive environment, which means that devices, in which their power sources are hermetically sealed, need to be replaced when their battery levels fall below certain threshold voltages—a period of several years. This means that the electronics package, including the non-volatile memory, must be ultra low power. Long battery life also translates to a smaller battery size for a given medical application, resulting in the smallest possible device size for implantation.

While widely diverse in function and usage, both RFID and implantable medical chips demonstrate the need for embedded NVM with the attributes of small size and cost, high reliability, long retention rate, very low power dissipation and field configurability. Flash memory technology does not provide all of these capabilities and designers must look elsewhere for embedded NVM IP for many of their chips (see sidebar “Flash Memory – It isn’t for Everything”).

(courtesy SanDisk)

figure 2

An ICD not only has to monitor and control irregular heart rhythms, it has to do so reliably storing code and operational parameters in non-volatile memory for several years. (courtesy www.defibrillator-help.com)

Sidense Corp., Ottawa, Ontario Canada.

(613) 287-0292. [www.sidense.com].

JANUARY 2008

19

wireless communications mobile WiMax

Mobile WiMax: How to Make Mobile WiMax Consumer Devices a Reality Mobile WiMAX promises a true broadband Internet experience.

But making it mobile isn’t easy.

by Frank Ferro, Director of Business Development, Sonics, Inc.

W

With the completion of the IEEE 802.16e specification, mobile broadband service is now beginning around the world to bring fixed broadband services to homes and businesses. There are now over 75 commercial networks in operation worldwide supporting 1.3M subscribers.

The bulk of these subscribers are using fixed WiMax service. To continue subscriber growth, network service providers have realized that giving consumers the ability to “take the Internet wherever you go” has huge potential. To do this effectively, mobile devices are needed that will mimic the Internet experience at home regardless of location.

Original equipment manufactures (OEMs) have provided the first generation of mobile WiMax products including PCs, smart phones, gaming devices and ultra-mobile PCs (UMPC). Unfortunately, these devices are expensive and do not meet the battery life requirements consumers have come to expect.

20

PORTABLE DESIGN

Given this, OEMs are challenging semiconductor manufacturers to significantly reduce price and power consumption since the underling silicon makes up a large percent of the overall system power.

Road to Low Power

Since WiMax is based on complex Orthogonal Frequency Division Multiplexing MultiAccess (OFDMA) technology, vendors have been focused on functionality, interoperability and time-to-market. This evolution is similar to cellular, wireless LAN (WLAN) and Bluetooth. All of these wireless technologies were initially expensive and power hungry, and the resulting devices were large with limited features. As standards and the market stabilized, chip companies began to focus on cost and power reductions.

The methodology employed to achieve these reductions varied depending on the company.

The Newest

Wireless Solutions

ZigBee

New Products from:

®

RFID Bluetooth

Connect® ME & Connect® Wi-EM www.mouser.com/digi/a

™

GPS WLAN

GPS Receiver Module www.mouser.com/tyco/a

Cellular ISM

ZigBee RF Transceivers www.mouser.com/ aerocomm/a

The ONLY New Catalog Every 90 Days

Experience Mouser’s time-to-market advantage with no minimums and same-day shipping of the newest products from more than 335 leading suppliers.

RF Monolithics Short Range Radios and RFICs mouser.com/rfmonolithics/a

The Newest Products For Your Newest Designs

www.mouser.com Over 900,000 Products Online

(800) 346-6873

wireless communications

figure 1 CPU

DSP

CPU

(MAC)

(PHY)

(MAC2)

BUS

Many would rely on the next generation semiconductor technology node along with better power management design techniques. Some would also look for processors and peripherals that were more power-efficient. These techniques have clearly achieved good results, since many of today’s mobile devices have acceptable operating times.

Even so, the demand for more complex wireless systems continues to push forward.

For example, while common cell phones may have acceptable battery life, smart phone batteries, under heavy use, are likely to last only one day. Or an MP3 player battery life may be fine, but add video and WLAN to it and battery life becomes a problem again. Now consider the effects of adding WiMax to these devices for a true mobile broadband experience. This new capability will continue to push all aspects of the system to reduce power.

SoC Design Methodology

nd

Technology decisions for mobile WiMax chip designs often center on choosing a I/O CTL processor with the performance to meet the speed requirements while also supporting low-power features. Other component decisions include a digital signal processor (DSP) to support real-time algorithm processing, Typical WiMax SoC with additional Wireless Protocol. ed input and output (I/O) devices and the size and types of on-chip memory. Along with choosing system components, architecture decisions need to be made about which functions will be implemented in software vs. hardware. These choices significantly influcompanies providing solutions now ence the power, exploration into products, technologies and companies. Whether your goal is to research the latest datasheet performance from a company, and overall cost mp to a company's technical page, the goal of Get Connected is to put you in touchofwith right resource.

Whichever level of and applicathethesystem.

From a business gy, Get Connected will help you connect with the companies and products you aretion searching for. point of view, decisions need to be made onnected to determine if the SoC will support other wireless protocols that could include WLAN, GSM, CDMA, Bluetooth and/or GPS. Any combination of these wireless technologies is possible, but adds significant complexity to the overall system design.

A typical embedded WiMax SoC block diagram is shown in Figure 1 (Note: the diagram has been simplified, focusing only on the issues concerning power). In this configuration, the system memory is shared between the Get Connected with companies mentioned in this article. processing elements [although many systems www.portabledesign.com/getconnected use tightly coupled memory (TCM)] and each

er exploration Memory ether your goal speak directly ical page, the ght resource. technology, es and products

End of Article

22

PORTABLE DESIGN

Get Connected with companies mentioned in this article.

MAC has control of the system resources and peripherals. Much care is typically taken in selecting individual blocks to be power-efficient.

However, the final chip performance may not meet the intended power consumption targets due to the interaction between the processor blocks and the memory.

In current SoC designs the CPU(s) controls the data flow and the interaction with memory and peripherals. Since the design is “CPU-centric” the processor is frequently in an active state, which utilizes the most power. In addition to the control issue, the system has multiple processing elements that are competing for resources including access to memory and peripherals. With traditional bus architectures, bandwidth is limited with the potential for long latency. Given this, the processor(s) will often waste cycles due to bus conflicts and waiting for data that will again leave the processor in an active state longer than necessary.

Maximize Processor Efficiency

Building on many of the existing systemlevel power-saving techniques, an alternative “interconnect-centric” SoC architecture enables a significant reduction in overall power.

This methodology starts from the view of the interconnect and builds out. Using a “micronetwork” (Figure 2) allows the SoC designers to model the interaction between all processing elements in order to optimize data flow and processing efficiency while also applying power-saving techniques across the entire SoC. In addition to other advantages, the creation of a micro-network offers many system advantages from the perspective of power consumption.

Advanced Interconnect Architecture

A micronetwork provides an advanced interconnect fabric along with data flow services. Efficiency is improved by adding new flow control services to the SoC. For example, the micro-network can support functions that include quality of service (QoS) to set data priorities, firewalls to protect regions in memory, error handling, data width conversions and power management. These new data flow services allow the CPU(s) to be-

System Considerations

The gain in processor bandwidth can have other positive impacts on the system. It is certainly possible to reduce the clock speed of the processor thus lowering the active power consumption. As mentioned previously, it is typically better to process the data as quickly as possible and return to low-power mode.

This is a trade-off that needs to be evaluated

wireless communications

come a facilitator thus improving its overall efficiency, which will have the effect of allowing it to remain in a low-power state for longer periods of time.

Many micro-networks support a non-blocking architecture along with multi-threading capability. A non-blocking transaction model offers the advantage of servicing requests from multiple processors at the same time with minimal latency in the response (versus a blocking transaction model that services one processor at a time). Multi-threading offers the advantage of splitting processes into logic threads in order to improve the overall processing efficiency (e.g., real-time functions in one thread and channel information in another).

WiMax SoCs can take full advantage of this architecture given that there are multiple processors, often with high bursts of data traffic.

This is especially true for SoCs that have multiple wireless protocol MACs on a single chip.

In this situation, non-blocking capability simplifies the data flow since each processor will have predicable bandwidth that will minimize the number of cycles wasted waiting for system resources. As in any wireless system the goal is to process the data quickly and return to low-power mode. This improvement in duty cycle will contribute to the reduction in average power consumption of the SoC. These processor efficiency improvements become even more significant as the amount of data to be processed increases. For typical CPU and cache configurations, reductions in instructions cycles of fifteen percent have been shown in simulations for processing large amounts of data (i.e., time waiting for data after a cache miss with non-blocking versus blocking). Having a non-blocking architecture will be a key performance advantage for mobile WiMax devices that have video processing capability.

based on the specific application requirements. The gain of processing power in the MAC can allow the system software designer the flexibility of adding new functions to the MAC. These functions may have previously been done by the applications processor or other hardware. Integrating as many functions as possible into the MAC has the advantage of a â&#x20AC;&#x153;zero loadâ&#x20AC;? architecture for the applications processor. This will save overall system power since the applications processor will be able to remain in low-power mode during data processing and not have to share the work load with the MAC.

Power Control

Designing with an interconnect-centric architecture also can allow for decoupling of each processor and peripheral from the system. With decoupling, the interconnect acts as a buffer between the system components, thus enabling independent clock control and voltage levels to each section of the chip.

Clocks and power can be removed from sections of the SoC for maximum power saving when that portion of the chip is not in use. The interconnect works in conjunction with an external power unit to enable features such as auto-wakeup, rapid power-on and power-off. Fast wakeup and power-down times would be difficult to achieve if implemented by the CPU due to long instruction cycle delays.

figure 2 CPU (MAC)

Memory

CPU (MAC2)

{

Data Flow Services Advanced Fabric Data flow Services

Sonics Micronetwork DSP (PHY)

Peripherals

WiMax SoC with a Micro network.

Conclusion

The need for mobile broadband services is pushing mobile devices to the limit in terms of processing power and battery life. Innovative techniques and architectures that drive reduction in power consumption for mobile WiMax devices are now required as the market has reached a maturity level that warrants these efficiency gains. A design methodology that centers on the interconnect allows SoC designers to look at the overall system from a data flow perspective in order to maximize processor efficiency, minimize latency and improve overall system power control.

Sonics, Inc., Mountain View, CA. (650) 938-2500. [www.sonicsinc.com].

JANUARY 2008

23

consumer electronics mixed-signal design

Applying an Integrated Approach to Mixed-Signal SoC Verification As mixed-signal design complexity is expanding, verification complexity is exploding. Implementing an integrated verification flow can save a lot of headaches.

by K aren Chow, Technical Marketing Engineer, Design to Silicon Division, Mentor Graphics Corp.

M

Mixed-signal systems-on-chip (SoCs) increasingly involve more and more digital processing functions isolated into multiple power domains, hundreds or thousands of analog-digital interconnections and operating frequencies always closer to pure RF. Clearly, genuine fullchip verification of such complex chips calls for careful planning and organization, as well as flexible simulation technologies. Whether you are verifying a power-management circuit, a single-chip multi-standard radio transceiver, or a mobile communications processor, different strategies are required. Technologies that allow transparent and efficient combinations of analog/RF descriptions, analog/mixed signal (AMS) behavioral models and pure digital descriptionsâ&#x20AC;&#x201D;all interoperating under a common verification platformâ&#x20AC;&#x201D;can help maximize fullchip, mixed-signal verification.

Mixed-signal design starts are on the rise.

An AMS SoC designer applies various design

24

PORTABLE DESIGN

formats for the different blocks, with different levels of abstraction. The different formats are typically classified into either digital or analog design. For purely digital designs, many production-proven tools are available for standard cell creation, behavioral language simulation, synthesis and place and route. For analog designs, traditional tools are used for schematic entry, accurate devicelevel simulation, handcrafted layout and interactive wiring.

So how do you integrate the design blocks at the chip level and complete the testing and verification? Do the blocks really fit together at the top level? Will the design function as planned? To ensure a working design, an AMS SoC chip-level design needs to be verified in its entirety. For this purpose, digital/analog (D/A) integration is mandatory. Shrinking manufacturing processes require inclusion of parasitics for analysis, and the integration of parasitic

LatticeECP2M FPGAs More of the Best

ϑ 4 to 16 SERDES (3.125Gbps) Only 100mW per channel

ϑ Up to 5.3Mb of Block and Distributed RAM

Supports PCI Express, Ethernet

ϑ Up to 95K LUTs

& other packet protocols

ϑ DSP Blocks

With multiply and accumulate

ϑ PLLs and DLLs

For optimized frequency synthesis & clock alignment

ϑ Flexible I/O Up to 601 I/O

ϑ Pre-Engineered Source Synchronous I/O Up to 840Mbps LVDS I/O

ϑ Superior Configuration Options

• Encrypted bitstream support • TransFR™ technology for easy field updates • Dual boot support

LatticeECP2M: The First Low-Cost FPGA with 3Gbps SERDES LatticeECP2M FPGAs give you “More of the Best” for less.

Visit our website at www.latticesemi.com. You’ll find information about Lattice’s complete line of FPGAs, including LatticeECP2M, LatticeECP2™, LatticeSCTM Extreme Performance System Chip FPGAs, LatticeXPTM non-volatile FPGAs and many more. If you haven’t looked at Lattice FPGAs lately, look again – things have changed.

Get more for less with Lattice’s new LatticeECP2M™ family. No other low-cost FPGA offers up to 16 SERDES channels with full-duplex serial data transfers at rates up to 3.125Gbps. Best of all, each SERDES channel operates on a cool 100mW at maximum speed.

The LatticeECP2M family offers even more, including up to 5.3Mb of RAM, high-speed DSP blocks, 533Mbps DDR2 memory interface and SPI4.2 support. Plus, 128-bit AES Encrypted Bitstream support and Transparent Field Reconfiguration (TransFRTM) allow you to keep your designs secure and easily upgradeable even after your product has shipped.

For design software and a FREE FPGA handbook go to latticesemi.com/ecp2m

©2008 Lattice Semiconductor Corporation. All rights reserved. Lattice Semiconductor Corporation, L (& design), Lattice (& design), LatticeECP2M, LatticeECP2, LatticeSC, LatticeXP, TransFR, and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries, in the United States and/or other countries. Other marks are used for identification purposes only, and may be trademarks of other parties.

consumer electronics

data adds yet another level of complexity to this problem. However, a post-layout simulation netlist can be created that includes parasitics and handles various data formats and that will effectively re-simulate the design while accounting for layout parasitic effects to ensure signal integrity.

Yield problems and multiple spins are caused by missed deep submicron effects. Mixed-signal SoC designs require full-chip timing analysis as well as full-chip signal integrity analysis.

Unfortunately, flat full-chip parasitic netlists are huge and impossible to simulate with traditional flat SPICE-type simulators.

Addressing Integration Issues

As a designer, you require increased capacity in analysis tools, but the tools may not be able to meet this requirement, so selected net extraction is used to reduce the netlist size. nd Unfortunately, selected net analysis misses important full-chip effects, especially interer exploration ether your goal actions between critical nets and non-critical speak directly nets. D/A partitions require different extracical page, the ght resource. tion modes and netlist formats, but having technology, separate D/A extraction results in incorrect es and products interface net delays. As a result, post-layout ed simulation and debugging can be very challenging. Extra resources and scripting are needed to make the analysis flow work. The netlist reassembly process is manual and error-prone. Often, the extracted netlist is not compatible with the analysis tool, and the companies providing solutions now block pindatasheet order from requires manual netlist edexploration into products, technologies and companies. Whether your goal is to research the latest a company, mp to a company's technical page, the goal of Get Connected is to put you in touchits. withTo the avoid right resource. of theseWhichever pitfalls,leveldesigners need a gy, Get Connected will help you connect with the companies and products you aretool searching for. flow that integrates the extraction tool onnected with the mixed-signal simulator, successfully working out these issues and enabling designers to complete full-chip post-layout analysis.

How does this flow work?

End of Article Get Connected

with companies mentioned in this article. www.portabledesign.com/getconnected

26

Mixed-Signal Verification Flow

A standard RF SoC design includes the RF front-end, analog baseband and digital signal processing (DSP) blocks. On the full-custom design side (analog and RF), the first step is to capture the design using a schematic capture tool (Figure 1). Using a simulation tool, it is possible to determine the characteristics

PORTABLE DESIGN

Get Connected with companies mentioned in this article.

of the circuit and to decide whether it meets the specifications or if revisions need to be made to the architecture. Once the design has been finalized, full-custom layout is completed. The layout is then verified by completing design rule checking (DRC), layout versus schematic (LVS) and parasitic extraction. In doing post-layout simulation with the parasitic resistance, capacitance and inductance in place, you can see if the design will still meet the specifications.

A typical digital design starts with a hardware description language such as Verilog or VHDL to describe the functionality of the design. This is referred to as register transfer level (RTL) design. This RTL design is then simulated to test functionality. Synthesis converts the RTL design into a gate-level netlist containing standard cells and the connections between them. Static timing analysis then predicts the expected timing of the circuit. Other types of analysis include power analysis and signal integrity analysis. From here, the placeand-route tool creates the layout, and extraction is run to verify the timing. Circuit debugging can force a new place-and-route run, synthesis job, or even change the HDL source code. Analog/RF flows require manual schematic capture and layout, unlike digital designs, which tend to have a highly automated data-creation flow.

When designing mixed-signal chips, full custom and digital components are combined together on the same chip, and verifying timing, functionality and power are critical for success.

Each block can have their I/O and performance specified such that individual designers can independently design each block. For interface purposes, a small functional model of the interface can be used; and as the design approaches completion, a mixed-mode simulator can be used to verify this interface. Mixed-mode simulators allow you to run digital logic cells with a digital simulator, while still using a SPICElevel simulator for analog and RF blocks. To do this, mixed-signal verification needs to occur at several different parts of the flow.

First, during the design phase, once the fullcustom analog and RF schematic capture and

interconnect delays overwhelm gate delays at smaller technology nodes. Physical effects are now the leading factor in the failure to achieve acceptable yield. AMS SoC designers need a parasitic extraction tool that delivers accurate parasitic data for comprehensive and accurate mixed-signal post-layout analysis and simulation. An extraction tool that is able to extract interconnect parasitics hierarchically, such as Mentor’s Calibre xRC, can address these

figure 1 Digital Design RTL

The Extraction-to-Simulation Flow

Let’s examine the chip-level extraction to post-layout simulation flow in more detail.

The interaction between RF blocks, analog baseband subsets and digital baseband subsets of modern RF systems is becoming tighter.

Often, the verification of these interactions is impossible, putting first silicon at risk of failure. ADVance MS RF is an effective simulation solution for verification of such circuits.

The technology provides 100x or 1000x speedup ratios over regular time-domain simulation and enables complete simulation of RF SoCs. It can simulate communication systems containing tightly linked RF and baseband functions with complex digital signal processing (DSP) in VHDL or Verilog. For example, direct conversion receivers or amplifiers with high-speed digital automatic gain control can be simulated.

Verifying such systems requires simultaneous, transistor-level simulation of the RF part with the baseband part in acceptable CPU times, including all of their analog-digital connections.

The designer needs a language-neutral environment including SPICE, VHDL, Verilog and standard analog behavioral languages such as VHDL-AMS and Verilog-AMS. Post-layout analysis has become increasingly important in sub-micron designs because

consumer electronics

simulation has been completed, and the RTL simulation has been completed, a top-level test bench can be put together that will test the functionality of the full chip, including all of the analog-to-digital interface interactions.

To enable full-chip simulation, some analog blocks may be modeled using VHDL-AMS or Verilog-AMS. Once full-chip mixed-signal simulation has been completed, chip-level assembly is done to tie all of the different analog, RF and digital layout blocks together. DRC and LVS are run at the full-chip level. Then parasitic extraction is run, with different types of extraction happening depending on the design style. Finally, mixed-signal post-layout simulation tests whether the design still meets the specifications. If it does, then it’s time to tape-out. If not, then some re-design will need to occur.

No

Analog Design

Chip-Level

RTL Simulation

Schematic Capture

Top-Level Testbench

Synthesis

Simulation

Mixed-Signal Simulation

Static Timing Analysis

Custom Layout

Chip-Level Assembly

Place and Route

DRC/LVS

DRC/LVS

Extraction

Extraction

Extraction

Static Timing Analysis

Post-Layout Simulation

Post-Layout Simulation

Design Meets Specs?

Yes

Yes

Design Meets Specs?

No

Yes

Design Meets Specs?

No

Tapeout!

Mixed-Signal Process Flow.

issues. The tool delivers compact, hierarchical, transistor-level parasitic data, which can be back-annotated and simulated with fullchip mixed-signal simulation tools. In using parasitic extraction, the effects of parasitic capacitance, resistance and inductance on neighboring lines (crosstalk) can be measured and corrected. Static leakage in portable devices can account for a significant percentage of total power consumption, and being able to measure and compensate for it can increase battery life.

JANUARY 2008

27

consumer electronics

Importance of Extraction for Portable Designs

Doing extraction can enable more robust portable designs. In addition to coupling capacitance, a large spectrum of new capacitance and resistance interactions become relevant in low-power designs implemented in advanced processes. For example, vias are now significant contributors to net parasitic

figure 2 Time-It Command PrimeTime Command File

Schematic Hierarchy Analog

Digital

Analog

Analog

nd

Delay Calculation

Calibre LVS

Digital DSPF/ SPEF

PrimeTime Time-It

SDF

Calibre Interactive PEX

Analog

Calibre xRC

er exploration ether your goal speak directly ical page, the ght resource. technology, es and products

Analog DSPF

Layout GDSII

ADMS .INCLUDE Index

Layout Hierarchy Analog

Digital

ed

.BIND File

Analog

Analog

Verilog Gate-Level

Analog

Extraction Input

Extraction

Netlist Assembly & Simulation

An Example of an Integrated Mixed-Signal Extraction-to-Simulation Flow.

companies providing solutions now

exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, mp to a company's technical page, the goal of Get Connected is to put you in touchcapacitance. with the right resource. level of coupling is Also,Whichever poly-contact gy, Get Connected will help you connect with the companies and products you arebecoming searching for.increasingly important. The higher

onnected

End of Article Get Connected

with companies mentioned in this article. www.portabledesign.com/getconnected

28

operating frequencies enabled by the smaller geometries now make interconnect inductance relevant.

The copper interconnects being used to reduce parasitic resistance are harder to control dimensionally and cause interconnect resistance and capacitance variations across a die.

They also require greater metal uniformity to control these variations, which means metal-fill simulation must be included because planarity variations also affect circuit performance. Nanometer device isolation techniques, like shallow trench isolation, cause

PORTABLE DESIGN

Get Connected with companies mentioned in this article.

device performance to change depending on the distance from the gate to the edge of the diffusion. Finally, designers need to be able to check that the optimizations made by the layout engineer during device construction have not degraded circuit performance. For these reasons, performing mixed-signal parasitic extraction is important.

When using a verification interface, such as Calibre Interactive, you can set up extraction for each individual block and have it target either the analog, RF, or digital engine in the simulator. There are several inputs that are supplied to the interface: the layout gds file, the source netlist, the LVS and extraction rule files, and a command file for the delay calculator (Figure 2). The schematic hierarchy is read into the GUI and provides a hierarchy tree that determines the extraction hierarchy and modes. LVS and extraction are then run, and the output netlist for the various domains are produced. For the digital blocks, delay calculation is run using either PrimeTime or Time-It, and an SDF file is produced. For the analog and RF blocks, a DSPF file is produced. The digital and analog/RF blocks are automatically stitched together for simulation. When using this extraction-to-simulation flow, there is a minimum of changes required to the pre-layout test bench to set up the post-layout simulation.

In summary, using extraction-to-simulation integration enables full-chip post-layout analysis for mixed-signal designs, speeding up design closure. It detects critical effects caused by layout parasitics and allows for effective cost reduction by minimizing risk and rework. This kind of verification strategy enables designers to meet schedules and minimize time to working silicon, requiring fewer resources to set up and maintain flows.

Mentor Graphics Corporation, Wilsonville, OR. (503) 685-7000. [www.mentor.com].

(IGH 0ERFORMANCE 0ORTABLE !UDIO #ODEC WITH #LASS $ 3PEAKER $RIVER

#3 , (IGHLY )NTEGRATED #ODEC $RIVES /NE 7ATT PER #HANNEL TO %XTERNAL 3PEAKERS &EATURES 3TEREO #ODEC s (IGH 0ERFORMANCE 3TEREO !$# $!# #APABLE OF 3AMPLING 5P TO K(Z D" $YNAMIC 2ANGE ! WTD n D" 4($ . s &LEXIBLE 3TEREO !NALOG )NPUT !RCHITECTURE !NALOG )NPUT -58 0'! AND !,# s $UAL -)# )NPUTS WITH -)# 0RE !MPS s $IGITAL 3IGNAL 0ROCESSING %NGINE s -ASTER 6OLUME #ONTROL s /N "OARD "EEP 'ENERATOR

#3 ,

#LASS $ 3TEREO -ONO 3PEAKER !MPLIFIER

3YSTEM &EATURES s .ATIVE 3UPPORT FOR 3TANDARD !UDIO

AND -(Z -ASTER #LOCK 2ATES s 3TEREO 0LAYBACK M7 s 6ARIABLE 0OWER 3UPPLIES 6 TO 6 $IGITAL AND !NALOG #ORE 3UPPLY

6 TO 6 #LASS $ !MPLIFIER 6 TO 6 (EADPHONE !MPLIFIER 6 TO 6 )NTERFACE ,OGIC

s #HIP "LOCK 3ELECT 0OWER $OWN -ANAGEMENT s &LEXIBLE $IGITAL AND !NALOG 2OUTING -IXERS s ) # ¤ #ONTROL 0ORT /PERATION s (EADPHONE 3PEAKER $ETECTION )NPUT s 0OP AND #LICK 3UPPRESSION s !VAILABLE IN A PIN 1&. PACKAGE

s &ILTERLESS 07- X 7 INTO G 6 X M7 INTO G 6

3TEREO (EADPHONE !MPLIFIER s 'ROUND #ENTERED /UTPUTS s (IGH 0OWER /UTPUT AT n D" 4($ . s #APABLE OF $RIVING X M7 INTO G 6

!PPLICATIONS 0ART

$EMO "OARDS

{Ó xÓ

$YNAMIC 3AMPLE 4($ .

2ANGE 2ATE

nÊ`

qnnÊ` ÈÊ â

0OWER 3UPPLY

!NALOG ) /

6 É6 ÊrÊ£°ÈxÊ6ÊÌ ÊÓ°ÈÎÊ6Æ iÊ iÛi Ê 6*ÊrÊÓ°ÎÇÊ6ÊÌ Êx°ÓxÊ6Æ É"]Ê *Ê> `Ê 6 ÊrÊ£°ÈxÊ6ÊÌ Êΰ{ÇÊ6 -* Ê"ÕÌ«ÕÌÃ

$IGITAL ) /

-* Ê > `Ê Ó-Ê i>`iÀ

#ONTROL

3OFTWARE &EATURES

-ASTER #LOCK 3UPPORT

£Ó°äÊ> `Ê Ó Ê i>`iÀÊ iÝ 1 Ê -Ì> `>À`Ê Õ` Ê > `Ê1- Ê ÌÀ

à «ÕÌ

/ iÊ , {Ó xÓÊ«À Û `iÃÊi>ÃÞÊiÛ> Õ>Ì Ê vÊÌ iÊ -{Ó xÓÊv ÀÊÌ iÊÃÞÃÌi Ê iÛi Ê>ÀV ÌiVÌ°Ê VViÃÃÊÌ ÊÌ iÊ , {Ó xÓÊL >À`Ê 2EFERENCE ÃÊ«À Û `i`ÊÛ >Ê i>`iÀÊ« Ã]Ê ÀÊ ÀiÊV ÌÀ ÊV> ÊLiÊ LÌ> i`ÊLÞÊ>ÌÌ>V }ÊÌ iÊ , {Ó xÓÊL >À`ÊÌ ÊÌ iÊ

{Ó £Ê $ESIGN , {Ó xÓ `À ÛiÀÊL >À`°Ê ÀÀÕÃÊ> à ʫÀ Û `iÃÊÌ iÊ >Þ ÕÌÊwÊ iÃÊv ÀÊÌ ÃÊÀiviÀi ViÊ`ià } ÊÌ Ê i «Êà « vÞÊÞ ÕÀÊL >À`Ê`ià } ° "OARDS 2EFERENCE $ESIGN

{Ó £ $RIVER "OARD

s 0ORTABLE -EDIA 0LAYERS s 'AME $EVICES s -0 0LAYER !CCESSORIES s 0ORTABLE '03 s )# 2ECORDERS s $IGITAL #AMERAS s #AMCORDERS

/ iÊVÀi` ÌÊV>À` Ã âi`Ê

{Ó £Ê À ÛiÀÊ >À`Ê >ÃÊ>ÊÀi Û>L iÊ , {Ó xÓÊÀiviÀi ViÊ`ià } ÊL >À`Ê> `ÊiÃÃi Ì > ÞÊ vÕ VÌ ÃÊ>ÃÊ>Ê`i ÊL >À`Êvi>ÌÕÀ }Ê> > }Ê> `Ê` } Ì> Ê>Õ` Ê É"]Ê>Ê1- Ê «ÕÌ]Ê iÝ 1 ÊV ÌÀ ]Ê> `Ê ÊL>ÌÌiÀÞ « ÜiÀi`Ê «iÀ>Ì °

0 / 2 4! " , % ! 5 $ ) / # / . 6 % 2 4 % 2 3

00

¥ #IRRUS ,OGIC )NC !LL RIGHTS RESERVED #IRRUS ,OGIC #IRRUS AND THE #IRRUS ,OGIC LOGO DESIGNS ARE TRADEMARKS OF #IRRUS ,OGIC )NC !LL OTHER BRANDS AND PRODUCT NAMES IN THIS DOCUMENT MAY BE TRADEMARKS OR SERVICE MARKS OF THEIR RESPECTIVE OWNERS

WWW CIRRUS COM .ORTH !MERICA ʳ£Ênää ÈÓx {än{ !SIA 0ACIFIC ʳnxÓÊÓÎÇÈ änä£ *APAN ʳn£Ê­Î®ÊxÓÓÈ ÇÇxÇ %UROPE 5+ ʳ{{Ê­ä®Ê£ÈÓn n £ Îää

portable power designing for low power

Extend Battery Life Using Programmable Clock Technology Few things will do more to improve the power profile of your next portable design than getting better control of the clock.

by Greg Richmond, VP of Engineering and CTO, SpectraLinear, Inc.

S

System designers are continually looking for ways to minimize power consumption in both line-powered systems and especially in battery-powered systems. Line-powered systems benefit from lower power by reducing supply components, cooling costs and becoming more “green,” while the benefits for portable systems include these as well as extended battery life.

This article reviews the methods for reducing system power consumption through optimized clocking of system components and highlights the benefits of programmable clock technology in achieving this goal.

Time Is Power

In digital systems, the classic equation for power dissipation, P=I*V, is transformed to include the clock frequency, F, by noting that the current is equal to the rate at which digital nodes with average switching capacitance C are charged to voltage V and then discharged to ground. The power dissipation equation then becomes P=V*(C*V*F), or P=C*V2*F. 30

PORTABLE DESIGN

This equation clearly indicates that minimizing the equivalent system switching capacitance and voltage by using components manufactured in more advanced, smaller geometry processes will reduce system power. The tradeoff here is the higher cost of advanced components and the additional cost of generating multiple voltages and signaling levels, such as input clocks, since these components often introduce different supply voltages. Notice also that controlling the system clock frequency(s) can have a dramatic effect on power consumption. Let’s look first at controlling the system clock frequency as a primary method for power reduction, and follow that with an analysis of minimizing the power consumed by clock signal distribution and then minimizing the power consumed by the clock generator itself.

Controlling the System Clock

System clock signals are traditionally supplied by discrete oscillators or by crystals that are connected to ASICs having integrated

portable power where one or more components have an internal clock multiplying PLL, abrupt frequency transitions (like starting and stopping a clock) can create system timing violations because the “downstream” multiplying PLL is not able to stop immediately or can become unstable when the frequency ramps below its safe operating range. If it is not possible to put the system into an idle or no-op mode when the frequency moves outside of the safe range, then it may still be possible to use “frequency slewing” instead. As shown in Figure 1, frequency slewing is the ability of a clock generator to switch smoothly between one or more frequencies in real time while the system is operating.

For systems that operate directly at the supplied clock frequency, there is no limit to the minimum frequency or frequency slew rate, dF/dt. However, in systems where one or more components have downstream frequency multiplying PLLs, care must be taken to ensure that the frequency slew rate can be “tracked.”

The limit for safe tracking is set by the clock generator frequency slew rate, dF/dt, the downstream PLL bandwidth and the amount of PLL phase error allocated in the component and system timing budgets. While these limits are calculated theoretically, it is also recommended

figure 1 High processing demand

System Inactive

Clock Freq

crystal oscillators. Multiple oscillators and/or crystals in a system are not cost-effective when compared to a single crystal and a silicon clock generator, which uses Phase-Lock-Loop, or PLL, technology to replace them. In addition the silicon clock generator is much more reliable than the mechanical crystal resonators it replaces, and it can be designed to include advanced EMI and power reduction capabilities.

As mentioned previously, the primary advantage of a silicon clock generator in reducing system power is its ability to minimize the average system frequency. This is traditionally done by monitoring the system processing and I/O demand and then either stopping or slowing the clock through direct pin or I2C control of the clock generator. The processing demand monitor can be as simple as a wired OR keypad activity detector or as complex as a firmware algorithm to monitor CPU activity. Care must be taken in the design of the clock generator to ensure that clocks stop and start “glitch” free. This means that the generated clock signal should always have a pulse width high and low time that does not fall below the minimum specification.

Stopping the clock instantaneously may not always be an option, however. In many systems

Low processing demand

Fmax dF dt

Time

Dynamically adjusting clock rate to match demand.

figure 2 Oscilloscope Capture

Oscilloscope Capture

Voltage

3.5 3 2.5 2 1.5 1 0.5 0 -0.5

10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90

1

2

3

4 time (s)

5

6

108

Frequency (Hz)

109

1

2

3

1010

4

5

6

time (s)

FFT (Oscilloscope Capture Buffer #1)

107

0

7 x10 -8

Magnitude (DB)

Magnitude (DB)

Voltage

4 3.5 3 2.5 2 1.5 1 0.5 0 -0.5 -1 0

10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90

7 x10 -8

FFT (Oscilloscope Capture Buffer #2)

107

108

Frequency (Hz)

109

1010

40% power savings and -20db EMI reduction from Programmable Clock Waveform Tuning.

JANUARY 2008

31

portable power

that the safe limits be empirically verified by increasing the frequency range and slew rate to the point of system failure and then limiting them by an acceptable safety margin. Because these variables are different for every system and component, the ideal clock generator

not having the ability to optimize the signal would result in a 40% increase in power consumption (= (5V-3.5V)/3.5V).

Reducing Clock Generator Power

The final knob to be tweaked in our quest to

figure 3 300K

XIN/ 3 CLKIN

PLL with Modulation Control PCin

XOUT 2 PCout

To I/O VDD 1

nd

VSS 5

er exploration ether your goal speak directly ical page, the ght resource. technology, es and products

V-Reg

To Core

Programmable Configuration Register

6 SSCLK1/REFCLK1 Output Buffers, Dividers and Switch Matrix

7 SSCLK2/REFCLK2 8

SSCLK3/REFCLK3 SSON#/FS

4 SSCLK4/REFCLK4 PD#/OE

SpectraLinearâ&#x20AC;&#x2122;s SL15101 Programmable Clock.

should have programmable upper and lower frequency limits, programmable slew rates and permit access directly to the PLL dividers that set the output clock frequency.

ed

Optimizing Clock Distribution

companies providing solutions now

A secondary consideration for reducing sys-

tem consumption is optimized distribuexploration into products, technologies and companies. Whether your goal is to research the power latest datasheet from a company, mp to a company's technical page, the goal of Get Connected is to put you in touchtion withof thesystem right resource.

Whichever level ofthe impedance clocks.

Matching gy, Get Connected will help you connect with the companies and products you areof searching for. the board trace and end load will ensure that

onnected

End of Article Get Connected

with companies mentioned in this article. www.portabledesign.com/getconnected

32

the signal is free from ringing, which minimizes the peak-to-peak voltage of the clock signal and hence the power consumption as well as the radiated Electro-Magnetic Interference or EMI. Ideally the clock generator would have programmable impedance to ensure a good match to various line impedances, lengths and loads, and also a programmable rise/fall time to slow the edges, which reduces high frequency harmonic content and minimizes EMI. An example of a poorly matched and well matched clock signal and the resulting spectral content is shown in Figure 2. Note that in this example,

PORTABLE DESIGN

Get Connected with companies mentioned in this article.

minimize system power is to reduce the power consumption of the clock generator itself. This is especially important if the clock generator remains active to supply the system heartbeat while the rest of the system is idle. As before, it is important that the clock generator be manufactured in an advanced technology to minimize internal switching currents. In many cases the operating voltage of advanced processes does not support the higher voltage that may be the single system supply or that is needed for the external clock signals. In this case the clock generator should have internal regulators, which not only allow low power operation at higher supply voltages, but also provide improved immunity to system noise and maintain a stable clock.

But there are other trade-offs as well with regard to lowering the internal operating voltage.

As the operating voltage goes lower, the maximum operating frequency of the internal PLL is reduced. This in turn limits the output frequency and increases the long-term jitter of the

portable power output clock. Long-term jitter is the measure of edge uncertainty for edges spaced “n” clock periods apart. A typical value for “n” is 1000, and a typical failure mode for excessive longterm jitter is closure of serial communication eye diagrams (increased bit error rates) and jittery pixels in high-resolution graphics displays.

Ideally then, the clock generator would have programmable internal voltage levels so that the voltage can be reduced to just that required for the maximum frequency and long-term jitter performance required by the system.

And just as various portions of a system are powered down when not required, the clock generator should be capable of powering down its unused sections independently. In fact, in the lowest power operating mode, when just the crystal oscillator is running, it would be advantageous to control the amplitude of the crystal oscillation waveform. Whenever crystal oscillator waveform amplitude control is provided, it is important that the clock generator still provide maximum gain during power-up to ensure reliable crystal startup. Most crystal manufacturers recommend a “negative resistance” at startup of at least 5x the crystal’s maximum rated Equivalent Series Resistance, or ESR.

tile memory or configured in real time through the 2-pin I2C port.

A block diagram of the SL15101 is shown in Figure 3. Using the methods described in this article, the product can be programmed to provide optimum system performance with minimum power dissipation.

In summary, this article has focused on the advantages of a programmable clock generator for reducing system power by a variety of methods. To control system power, use clock start/stop in direct clock systems and frequency skewing in clock multiplying systems. To control clock distribution power, use voltage matching to minimize signal swing and impedance matching to minimize line ringing. To control clock generator power, you can trade off PLL frequency vs. jitter and power; independently minimize core operating voltages; and control the amplitude of crystal oscillator waveforms. All of these are made substantially easier—or even possible—through the use of programmable clock generators.

Spectra Linear, Inc. Santa Clara, CA (408) 855-0555. [www.spectralinear.com]

Programmable Clock Generators

Programmable clock generators are available from a variety of suppliers such as Texas Instruments, Cypress Semiconductor and SpectraLinear. One example of a programmable clock generator that provides programmable optimization in all of the areas discussed so far is the EPro clock family from SpectraLinear.

The company offers various Electrically Programmable, or EPro, clock products incorporating from 1 to 4 low-power PLLs with up to 2048 nonvolatile control bits. The PLLs can be programmed to consume less than 2 mA each.

This product provides programmable min/max frequency, frequency slew rate, output impedance, rise/fall times, output drive levels, oscillation amplitude and internal voltage regulators as well as power-down of various sub-blocks.

The program can be stored in internal nonvolaJANUARY 2008

33

portable power designing for low power

Lower Supply Voltages Enable Low-Power Portable Electronic Devices Few power management methods will help your energy budget more than dropping the supply voltage. But doing so while maintaining clock frequency and signal integrity is no easy trick.

by Aditya Rao, Product Marketing Engineer, Memory Products Division, Microchip Technology Inc.

T

The tremendous growth in the semiconductor industry over the last two decades has largely been a result of the scaling of CMOS devices which, over the years, has yielded lower costs with more die per wafer, smaller feature sizes and increased performance. However, device scaling has reached a point of threshold today, wherein its benefits are realized only if a device’s power consumption can be reduced by a few orders of magnitude. Power minimization is of paramount importance for designers today, especially in the portable electronic device market, where devices have become increasingly feature rich and power hungry.

Low supply voltages play a significant role in determining the power consumption in portable electronic device circuits.

This article will examine the benefits of low voltage within portable electronic designs, showing how the advantages of low power can be achieved.

34

PORTABLE DESIGN

An electronic device’s overall power consumption can be represented by: PTOT=αCTOTVDD2f +VDDIOFF; where IOFF=Ioe(-qVTH/nkT) Equation 1: An Electronic Device’s Overall Power Consumption

The first term in Equation 1 represents dynamic or “switching” power, while the second term represents static power—primarily due to leakage currents. (The short-circuit power, which forms less than 5% of the total power, is not included.) As a result of scaling over the years, the dynamic power has remained almost constant (Figure 1), so increases in switching frequency (α), clock frequency (f) and total capacitance (CTOT) have been largely offset by the supply voltage (VDD).

The paradox faced by designers is that a

G e t o n t h e F a s t Tr a c k Donâ&#x20AC;&#x2122;t let custom requirements slow you down.

Our existing products and custom design expertise help our clients to quickly meet complex design requirements.

VadaTech is a leader in AdvancedTCA, AMC, cPCIe, VXS, XMC and custom board-level technology.

Dedicated to leading-edge technology for the most demanding applications; we pride ourselves on our extraordinary capability to quickly create designs in response to our customer requirements.

Our service to the aerospace and telecommunications markets has resulted in a quickly growing line of AdvancedTCA, AMC, cPCIe, VXS, XMC and custom boards for processing, communication, storage, and platform interoperability.

ATC800

Sprint past the competition with VadaTech as your teammate!

W W W . V A D A T E C H . C O M T E L 1 . 7 0 2 . 8 9 6 . 3 3 3 7

NEW BIGGER VENUE

5-6 March 2008 | Amsterdam

6th

Sponsors

EDITION

Five reasons to REGISTER NOW TEST

LEARN

Speaking organisations range from:

See website for the full programme of over 50 speakers

…the latest technology

SOURCE

…new suppliers/partners at the world’s largest avionics expo

…from the main conference, workshops, masterclasses and FREE exhibitor presentations

NETWORK

…with the press, speakers and attendees on the industry cruise, direct from the dock of the show

For conference programme and exhibitors list go to

ENJOY

…some R&R (with clients of course!)

Part of

portable power

gating (Figure 2a), which uses high thresholdvoltage transistors or sleep transistors in circuit blocks that switch infrequently. This results in zero standby currents during the inactive state.

Dynamic supply-voltage scaling is another method employed that is often used in lowpower designs to efficiently tackle the power/ performance trade-off. The underlying principle is to scale the supply voltage down along non-critical timing paths, thereby lowering the overall dynamic power consumption. However, along timing-critical paths, the supply voltage is kept at its nominal value to ensure timing closure. It must also be noted that the additional voltage levels and their integration into the design increase the overall cost of the design.

Modifications involve adaptive supply-voltage scaling, based upon the sub-circuit workload.

Next, dynamic threshold-voltage scaling can be used, where the threshold voltage of cells is increased by controlling the substrate biasing. A larger threshold voltage implies reduced passive leakage, thus shrinking the static power consumption. Therefore, choosing supply-voltage or threshold-voltage scaling depends upon whether dynamic or static power dominates the power equation.

Architectural optimizations implemented during the RTL and synthesis phases of the

figure 1 Dynamic and Static Power Consumption with Technology Scaling 100

1990 1995

2000

2005

2010

2015 2020

Dynamic Power

1 Normalized Power

reduction in supply voltage helps to reduce power but, on the flipside, it limits the clock frequency. Additionally, a reduction in supply voltage reduces the saturation current through the MOSFET, thereby cutting speed and performance. Hence, the supply voltage plays an important role in the speed vs. power tradeoff.

To counter this reduction in saturation current, threshold voltage (VTH) has also scaled down. This has led to a tremendous surge in sub-threshold leakage current (IOFF) and static power, especially in the deep submicron process technologies (Figure 1). Minimizing this is expected to be a significant challenge for future low-power designs. Table 1 shows the effect of scaling on various parameters.

Todayâ&#x20AC;&#x2122;s consumer-electronics market is driven by battery-operated, wireless applications and portable devices that are becoming increasingly sophisticated. All of this has created a huge demand for longer battery life. As a result, design practices today are increasingly focusing on the demands and requirements of the end application and target markets, rather than just overall system optimization, for better performance. In fact, to achieve this, foundries nowadays offer multiple options on threshold voltage, supply voltage and oxide thickness for the same process, providing designers with the flexibility to choose the best device for helping them overcome some of the limitations of power-performance trade-offs, enabling them to tailor designs to the needs of the end application. For example, portable applications that place a higher premium on power consumption are often designed using higher VTH transistors, trading off performance for lower power. On the other hand, fast switching circuits will use low VTH cells.

There are many methods that designers can employ to reduce power consumption in portable electronic devices. One is known as clock gating (Figure 2b). Clock power is an important component of overall dynamic power. One way to reduce clock power is to use clock gating, which dynamically disables the clock in unused parts of the circuit. This avoids the unnecessary power dissipation caused by charging and discharging the clock signal at these unused gates. Gating is generally achieved by ANDing the clock signal with a clock-gate signal, which rises whenever the part of the circuit that needs to be gated is active and remains low otherwise. Many synthesis tools offer clockgating insertions at the RTL level.

Another commonly used technique is power

0.01

0.0001

Static Power

0.0000001

500 350 250 180 130 90 65

45

22

Gate Length (nm)

Dynamic and Static Power Consumption with Technology Scaling.

figure 2 CLK Latches

Sleep Virtual VDD

Input L1 L1

High VTH

Pull-Up Network (PUN) Low VTH Input

Modifying Circuit to Enable Clock Gating CLK

Pull-Down Network (PDN) Low VTH

Virtual GND Sleep

High VTH

L2 Output L2

EN Output

Logic Circuit

Logic Circuit

EN Gating Clock

Clock Gating by ANDing CLK Signal (Enable) and Enable Signals Input L1 L1

Logic Circuit

L2 Output L2

Sleep = 0 => Normal Operation, Logic ON Sleep = 1 => Power Gated, Logic Turned OFF (a) Power-Gating Circuit Reduces Static Power

(b) Clock Gating Reduces Dynamic Power

(a) Power Gating using Sleep Transistors and (b) Clock Gating.

JANUARY 2008

37

portable power

design flow are critical as key design tradeoffs are made in this phase. Mapping and sizing techniques are often used on the netlist to find the high switching inputs. These are then mapped to low-capacitance inputs. If possible, pipelining techniques should be implemented to further save power.

Scaling to the deep sub-micron level has opened the door to a number of second-order

table 1 Parameter

Relation

Full Scaling

General Scaling

W, L, tOX

-

1/S

1/S

VDD, VTH

-

1/S

1/U

Area

WL

1/S

1/S2

COX

1/tOX

S

S

CL

COXWL

1/S

1/S

IDSAT

COX(W/L)V2

1/S

S/U2

Intrinsic Delay (tP)

CLV2/IDSAT

1/S

U/S2

Avg. Power (PAV)

CLV /tP

1/S

S/U3

Power Delay Product

CLV2

1/S3

1/SU2

2

2

2

Full Scaling = Dimension and voltage scales by a factor “S” (S>0) General Scaling = Dimension and voltage scales with different factors.

The Impact of Scaling on Device Parameters.

effects, such as tunneling, channel-length modulation, punch through, drain-induced barrier lowering and velocity saturation. All of these effects further impact both power consumption and performance, making designs increasingly complicated and causing a growing need for newer, more innovative materials and processes. For example, the use of High-K dielectrics helps mitigate the effects of tunneling with thicker gate oxides. Strained-Si helps improve mobility, which mitigates the effects of velocity satu-

table 2 Device Material From í To

Effect

AI í CU

Reduces Interconnect Delay Time

SiO2 í Low-K

Reduces Interconnect Delay Time

Si í Silicon On Insulator (SOI)

Lower Capacitance, no latch up

Si í Strained Si

Higher Mobility

Poly-Si í Metal Gate

Higher Effective Oxide Capacitance

SiO2 í High-K

Reduced Oxide Leakage Currents New device materials and their advantages.

38

PORTABLE DESIGN

ration and allows for higher threshold voltages for the same “on” current. This reduces static power. Table 2 shows the list of proposed new materials and their respective advantages.

Signal Integrity (SI) has become a major concern today, especially in deep sub-micron processes. Lower noise margins with supplyvoltage scaling have meant more stringent restrictions on the signal output and quality. This is particularly demanding with faster rise times and increased slew. SI issues creep in not only when data that is latched is incorrect, but also when data that needs to be latched doesn’t arrive at the right time. Substrate coupling, crosstalk and circuit interconnects are the primary culprits for SI problems.

Some tips and tricks for overcoming these SI problems include: • Use differential signals at high fanout nodes.

• Use ECL signals for clocking.

• Use parasitic extraction tools that model 3D parasitics and inductance, especially in high-frequency designs. This increases the accuracy of the slew-rate prediction.

• Model capacitors as nodal capacitors, as opposed to capacitors to ground.

• Match impedance at the package boundary.

• Use decoupling capacitors between the supply voltage and ground at the external pins.

• Limiting di/dt helps reduce crosstalk and ground bounce.

• Optimize layout for fewer metal layers and minimum wire length.

• Give greater margins during design to allow for costly post-silicon SI defects.

Non-Volatile Memory Technologies

The non-volatile memory market, consisting primarily of flash and serial EEPROM, is one of the fastest growing in the semiconductor industry. EEPROM devices are particularly useful in portable and consumer-electronic applications, providing system programmability and data storage. They also find applications in power-down storage, error diagnostics, secure data storage, maintenance logs and configuration storage, and often as look-up tables and analog controls in consumer-electronic applications. What makes serial EEPROM attractive is its high endurance, low cost, byte-level programmability and low power. These attributes make it ideal for portable consumer-electronic applications, such as MP3 players, camcorders and wireless Bluetooth applications (Table 3).

Serial EEPROM devices are becoming increasingly power savvy. Leading providers of

Floating-Gate Design Challenges

Portable applications, with their scaling of other onboard chip components, have forced serial EEPROM devices to operate over a wide voltage range, typically 1.8V to 5.5V. The real challenge is to ensure fast access and erase times, along with reduced write times at low supply voltages, while reducing power consumption at higher supply voltages. An additional critical design consideration is to ensure that standby current is as low as possible, especially in battery-operated devices.

One great advantage of non-volatile memory is that a flash or serial EEPROM device’s power supply can be shut down to ensure zero memory leakage when not in use. When operating at lower supply voltages, write times in these devices increase dramatically. Hence, chargepump designs are critical in obtaining writetime optimizations. The big challenge here is to obtain the highest internally generated write voltage at the lowest possible supply voltage, to ensure faster write times.

Another significant challenge associated with technology scaling in floating-gate designs has to do with thinner oxides, resulting in poor write quality. This causes lower endurance and severely affects data retention. Also, writes are generally performed at high voltages (greater than ± 10V) making the thinner gate oxides more vulnerable to permanent oxide damage and charge loss. This severely affects reliability.

Using materials with high dielectric constants for the oxide is one way to reduce the impact of dielectric scaling. To optimize the time taken to read from floating-gate non-volatile memories, the address decoding times must be optimized. The real challenge here is that at low supply voltages, the on currents are ex-

tremely low, making current sensing challenging and slow. Boosting the voltage on the word line to obtain higher on currents is one way to work around this problem.

On the other side of the spectrum, scaling has helped reduce the cost per bit, with reduced die sizes and cost. It has also helped reduce power consumption, and has made these devices significantly faster with every generation of scaling. Today, low supply-voltage operation is inevitable. The conundrum facing designers with serial EEPROMs is that having low power is useful in applications such as smart cards and DRAM modules. However, higher performance and faster access times are required when used with embedded applications and microcontrollers. Going forward, supply-voltage limitations with smaller gate lengths are expected to lead to smaller EEPROM supplyvoltage ranges.

Using lower supply voltages to help reduce dynamic power is inevitable with scaling. However, the resulting increased static power is expected to pose the biggest challenge for lowpower portable designs in the future. To offset the slowdown in scaling, newer, more innovative materials like Silicon-on-Insulator (SOI) are being used to make devices more robust.

Additionally, advanced packing technology is quickly integrating into designs, with flip-chip technology becoming increasingly popular.

More sophisticated testing methodologies and EDA tools are helping designers to model systems better, thereby reducing turnaround times and costs.

Thus, while scaling may not keep the same pace going forward, better systems, improved tools, increased use of software and architectural optimizations, newer materials and improved processes can bring the benefits of lower cost, increased performance and lower power.

portable power

EEPROM devices today specify EEPROM devices with typical standby currents of around 0.01 micro Amperes (μA). In fact, newer serial EEPROM parts effectively tackle the speedpower trade-offs as well. For example, the 1 Mbit 25AA1024 or 25LC1024 (25XX1024) serial EEPROM devices from Microchip Technology are not only the fastest (20 MHz) 1 Mbit SPI serial EEPROMs available, but they also have a deep power-down mode feature that helps to reduce power consumption. These additional low-power features make these devices well suited for low-power designs up to around the 1 Mbit density level. (Serial flash memory devices typically have standby currents around 15 μA at this high-end density.)

table 3 1 Mbits 512 Kbits 256 Kbits

Printers, Scanners, Smart Cards, GPS, Remote Control, Energy Meters, Hearing Aid, Wireless, VoIP

128 Kbits 64 Kbits 32 Kbits 16 Kbits

Cell Phones, Cordless Phones, Digital TV, HDCP, Facsimile, Set Top Box, Digital Camera, PDAs, Bluetooth Headsets

8 Kbits 4 Kbits 2 Kbits 1 Kbits

DVD, MP3, VCR, CD, Home Appliances, Car Alarm Systems, DDR DIMM Modules, LCD Monitors

Application Software, Data Memory, Program Storage, Configuration Storage, Maintenance Logs

Last Number Call, Data Setting, Log Data, Secure Data Storage, Error Diagnostics, System Settings

User Setting, Initial Channel Setting, Fine-tuning, Usage Record, Initial Data Settings, Configuration Settings

Application and usage of Serial EEPROM devices, by density.

Microchip Technology, Inc. Chandler, AZ. (480) 792-7200. [www.microcip.com

JANUARY 2008

39

product feature Altera Zeros Out Power, Zeros in on Portable Designs MAX IIZ CPLD combines 29 μA static power, instant-on performance in a 5x5 mm package.

by John Donovan – Editor-in-Chief

figure 1

The money play in consumer electronics is cell phones, and few chip vendors can make a stronger pitch for sockets than the programmable logic camp—quick time-to-market, lower BOM cost, the ultimate in flexibility to accommodate evolving protocols, different regional standards and even over-the-air software updates of hardware. What’s not to like?

The problem, of course, is that traditionally FPGAs—SRAM-based FPGAs in particular—have been too power hungry for handsets, and the low density of CPLDs has limited them to glue logic chores. As CPLD densities have risen, some of these chores have gotten quite sophisticated, with CPLDs handling system-level power management as well as communication between the main processor and peripherals.

Altera designed its new MAX IIZ family specifically to address the power, package and price constraints of the portable applications market.

They made some major modifications to the MAX II’s look-up table (LUT) architecture with an eye to low-power embedded applications, combining low power and instant-on capability in a 5mm x 5mm micro-BGA (MBGA) package.

The MAX IIZ initially comes in two densities:

figure 2

the EPM240Z has 240 logic elements, 192 macrocells, 80 I/O pins and 8K of user flash memory; the EPM570Z has 570 logic elements, 440 macrocells, 160 I/O pins and the same 8K of flash. Both include an internal oscillator.

The real story here is power consumption and density. The devices utilize a 0.18-micron process, 1.8V core voltage and 6-metal-layer flash to provide both high functionality and zero

40

PORTABLE DESIGN

power consumption in a single device. The term “zero power” originated with Phillips back when static power was in the mA range; zero power came to mean anything in the μA region. Altera claims the MAX IIZ is zero powe’ based on the EPM240Z’s 29 μA static power while running at 50 MHz; dynamic power in that case is 8.9 mA. With a density about half way between the CoolRunner-II XC2C128 (128 macrocells) and XC2C256, at 50 MHz the IIZ’s dynamic current (Icc) is about half (8.9 vs. 18 mA), while the static current (0 MHz, 25°C) is somewhat higher (29 vs. 20 μA). The flash-based FPGA camp will protest that this isn’t zero power, but it’s a close enough approximation for all but the most demanding medical applications. As for which chip makes the most sense in a given application, all things being equal it will vary with the usage model, but in this comparison the MAX IIZ would most often have the edge.

In terms of density, Denny Steele, Altera’s senior marketing manager for Low Cost Products, claims that the MAX IIZ offers 6x the density and 3x the I/Os in the same package size as traditional macrocell-based CPLDs. This derives from the use of MBGA packaging instead of the micro-leadframe QFN favored by Xilinx and Lattice. In a 5x5 QFN you can expect to get 20-21 I/Os and 32 macrocells, whereas the EPM240Z provides 80 I/Os and 192 macrocells in the same size package. More horsepower and more functionality while using less power in the same piece of board real estate is a pretty compelling argument.

MAX IIZ devices are supported by free Quartus II Web Edition software version 7.2, SP1, which integrates with all leading third-party synthesis and simulation tools.

Production-qualified MAX IIZ EPM240Z M68 devices will begin shipping in the first quarter of 2008 at $1.25 in high volumes. All MAX IIZ devices will be shipping in production by the second quarter of 2008. Additionally, over 20 MAX IIZ design examples, enabling designers to quickly and cost-effectively create and customize their designs, are available at www.altera. com/max2example. The MAX IIZ demo board will be available by the second quarter of 2008.

Xilinx’ highly successful CoolRunner line has long been the obvious choice for handling communication between cell phone processors and their peripherals. Actel, Lattice and QuickLogic have all designed products to capture those sockets, but so far with limited success. With the advent of the MAX IIZ, Altera has picked up—or perhaps thrown down—the gauntlet.

The MAX IIZ is a worthy competitor and well deserving of being Portable Design’s product of the month.

Altera Corporation, San Jose, CA. (408) 544-7000. [www.altera.com].

08

20

...Your Vehicle to Success in the

Fast Paced

Telecom Market

www.mountainviewalliance.org

The Mountain View Alliance puts you in the drivers’ seat! Now you can become part of this fast-paced 2-day conference designed to accelerate the adoption of open-specication based components and platforms. Take your place in the design and evolution of commercial off-the-shelf implementations in the telecommunication and wireless infrastructure. Set your plans to include a diverse and effective conference that brings company’s and individuals together from the entire COTS ecosystem.

Mountain View Alliance Communications Ecosystem Conference March 11 and 12, 2008 South San Francisco Conference Center

www.mvacec.com

design idea Flexible Over/Undervoltage Detector Monitors Negative and Positive Voltage

figure 3

by Franco Contadini and Bich Pham, Maxim Integrated Products Inc. Multi-voltage supply supervisors (such as the MAX6887) provide several voltage-detector inputs for positive voltages, each with factory-set thresholds for undervoltage and overvoltage. The /RESET output asserts when any input drops below its undervoltage threshold, or when you assert the manual reset (MR). The /OV output asserts when any input exceeds its overvoltage threshold. These capabilities are useful, but telecom applications often require that you monitor a negative supply voltage for the RF circuitry as well.

figure 1

figure 2

-6V

By combining the circuits of Figures 1 and 2, one pair of terminals warns of under or overvoltage for multiple positive voltages and one negative voltage.

REF

R1 IN_

MAXIM MAX6764

R1

R2

UVH

REF

+

+

*VREFUV

R2

VCC

Internal Reference 0.5V

UV1H OV1H

+

OVH +

figure 4

UV

- UV MONITOR GND

CH1-0V

-

OV MONITOR

*VREFOV

CH1=VM

OV

REF1=UVIN

R3

REF1/CH2-0V

CH2=UV

VH *VREFOV and VREFUV are referenced to 0.6V according to the device’s tolerance.

CH3=OVIN

MAX6887 adjustable input option.

This IC (in SOT23 package) is a CH3/CH4 - 0V simple window comparator that monitors a supply voltage with separate under/overvoltage outputs.

To monitor negative voltage you can make use of the MAX6887 adjustable-input option (Figure 1), in which a level-shifting circuit connects one side of the resistive divider to a positive level and the other side to the negative voltage. This approach, however, produces inverted output logic.

If, for example, you monitor -6V with thresholds at -6.5V and -5.5V, the circuit asserts /UV when VIN = -6.5V and /OV when VIN = -5.5V. The circuit of Figure 2 overcomes this limitation by adding a simple window-detector IC (Figure 3) to monitor the negative supply. The detector’s /UV output connects to the multi-voltage supervisor’s /OV output, and the detector’s /OV output connects to the supervisor’s /RESET output.

Thus, the /RESET output goes low when the negative voltage decreases to -5.5V, and the /OV output asserts low when the negative voltage increases to -6.5V. Three resistors (R1-R3) set the under- and over-voltage thresholds UV and OV. R1 connects to a positive reference voltage, and R3 connects to the monitored negative voltage.

If your system doesn’t include a positive reference voltage, you can use the supervisor’s 2.55V BP output. To maximize DC accuracy, the sum of R1+R2+R3 should draw only a few microamps from the BP output. Using the principle of superposition, you can then calculate the voltages at UVIN and OVIN for any given set of resistor values as follows: VUVIN = VBP × VOVIN = VBP ×

( (

R 2 + R3 R1 + R 2 + R3 R3 R1 + R 2 + R3

) )

− VM × − VM ×

( (

R1 R1 + R 2 + R3 R1 + R 2 R1 + R 2 + R3

where VM is the monitored negative supply voltage.

42

PORTABLE DESIGN

) )

, ,

CH4=OV

These waveforms illustrate operation of the Figure 3 circuit.

Operation of the Figure 3 circuit is illustrated in the scope shot of Figure 4, in which the yellow trace (CH1) represents the monitored negative voltage VM as it ranges from 0V to -7V. Other traces are: R1 (black) = UVIN CH2 (blue) = MAX6764 /UV CH3 (green) = OVIN CH4 (pink) = MAX6764 /OV. The nominal value for the monitored negative voltage is -6V. Both /OV and /UV outputs have a 10 kΩ pullup to 5V, and the VCC terminals of both ICs connect to a 5V supply. The MAX6764 Output /UV (MAX6887 /OV Output) goes low at VM = -6.55V (and goes high at VM = -6.52V).

The MAX6764 output /OV (MAX6887 /RESET Output) goes low at VM = -5.53V (and goes high at VM = -5.55V).

INTO TECHNOLOGY COMING TO A CITY NEAR YOU rtecc.com

products for designers Direct Digital Synthesis IC for Low-Power, Portable Designs Analog Devices, Inc. is expanding the applicability of its industry-leading direct digital synthesis technology into battery-powered industrial, communications and defense electronics applications with the introduction of a complete low-power, low-cost Direct Digital Synthesizer (DDS) specifically designed for wireless, handheld equipment.

Unlike competing approaches used to synthesize a digitally controlled frequency, the AD9913 is the first DDS device to deliver a 250 MHz clock rate while consuming as little as 50 mW of power. At less than $5 in volume quantities and available in a compact chip-scale package, the new IC is ideally suited for portable barcode scanners, radar detectors, remote radio controls and other products that require a cost-effective combination of performance and low-power operation.

Unlike phase-locked loop (PLL) devices, which suffer from settling times measured in microseconds and fine-tuning limitations, the AD9913 settles in nanoseconds with granularity well below 10 mHz. Other approaches, including field-programmable gate arrays (FPGAs) with embedded DDS functions, have difficulty matching the AD9913’s greater than 80 dB spurious-free dynamic range (SFDR) performance on a 100 MHz output signal while requiring higher operating power and the addition of a discrete digital-to-analog converter (DAC) to synthesize the sine wave. The AD9913 includes an on-chip 10-bit high-speed DAC with no price premium compared to a stand-alone DAC. The fine-tuning granularity and higher SFDR of the AD9913 allow it to more quickly and accurately generate a stable signal in the band of interest. In a remote radio-controlled application, for example, such as an unmanned aircraft, this means the operator is less likely to lose contact with the airplane due to frequency interference that can result in a dropped signal.

The AD9913 is available in full production quantities. The AD9913 costs $4.65 per unit in 100,000-unit quantities and is available in a 32-lead LFCSP (lead-frame chip-scale package).

Analog Devices, Norwood, MA. (781) 329-4700. [www.analog.com].

Li-Ion/Li-Polymer Chargers with Auto USB or AC Power-Source Selection Microchip Technology Inc. has announced sampling of the MCP73837 and MCP73838 (MCP73837/8) dual-input, high-current Li-Ion/Polymer charge-management controllers with automatic USB or AC adapter power-source selection. The single-cell, fully integrated chargers enable charge currents of up to 1A from an AC power source, plus charging currents of up to 100 mA or 500 mA from a USB port. They have several on-chip safety features, and are available in 10-pin MSOP and 3 mm x 3 mm DFN packages, to enable smaller, faster and safer battery-charger designs.

Auto power-source selection from either a USB port or AC adapter means that MCP73837/8-based charger designs can automatically charge from a PC’s USB port when no AC power is available. When powered from a USB port, the devices ensure compliance with USB power specifications and adjust outputs accordingly. The result is that one charger design can support multiple power sources. Additionally, with high charge currents up to 1A from an AC power source, the MCP73837/8 devices enable faster charging cycles and less recharging down time.

On-chip safety features, such as thermal regulation, cell-temperature monitoring and charge-timers minimize charger-related system damage, resulting in safer and more efficient charger designs.

Microchip also announced the MCP73837/8 evaluation board, (Part # MCP7383XEV-DIBC), to help designers evaluate the MCP73837/8 chargers in their designs. The board can be ordered now at www.microchipdirect.com, and is expected to ship in late December. It is priced at $40 each.

Samples of the MCP73837/8 chargers are immediately available in 10-pin MSOP and 3 mm x 3 mm DFN packages, for $0.89 each in 10,000-unit quantities.

Microchip Technology Inc., Chandler, AZ. (480) 792-7200. [www.microchip.com].

Ultra-Low-Power Microcontroller Texas Instruments has announced the availability of five new families of MSP430F2xx high-performance microcontrollers, the industry’s lowestpower 16-bit general-purpose microcontrollers (MCUs). The new microcontrollers provide a direct upgrade path for corresponding devices in TI’s popular MSP430F1xx generation of ultra-low-power MCUs, easing development and offering complete software and pin compatibility while delivering twice the performance, twice the battery life and increased memory. MSP430F2xx MCUs enable developers of meters, sensors, industrial control systems, handheld instruments and a host of other embedded systems to extend the performance and lifetime of their products with minimal redesign (see www. ti.com/msp430f2xx-pr for more information).

With a high level of analog integration, TI’s MSP430F2xx MCU architecture is designed for the requirements of a new generation of control systems.

The devices integrate on-chip memories of up to 120 Kbytes, and a 20-bit address word increases total addressable memory to 1 Mbyte without paging, supporting the development of more complex programs. A wide range of analog and digital peripheral options enable enhanced features in end products while reducing system costs and power consumption. For example, almost no battery drain occurs with standby power consumption as low as 0.5 µA, and fast wake up from standby mode further reduces battery load.

The MCUs have a wide operating voltage range of 1.8 to 3.6 volts and a flexible clocking architecture that allows the designer to implement their select processing speed versus operating voltage. Battery life and system cost are further optimized by achieving the full processor speed of 16 MHz, at 3.3V, giving margin for the power supply design requirements.

With up to 120 Kbytes of flash and 8 Kbytes of RAM, the MSP430F241x and MSP430F261x are targeted for systems needing extensive processing capability, while the MSP430F24x and MSP430F23x are more general-purpose devices. Among the devices, the MSP430F2418 and MSP430F2618 are optimized for operation in low-power ZigBee networks, while the MSP430F2410 targets applications such as IEEE 802.15.4 wireless networks and automatic meter reading.

All five families are available now in volume quantities. Evaluation tools are also available now for all devices.

Texas Instruments Inc., Dallas, TX. (800) 336-5236. [www.ti.com].

44

PORTABLE DESIGN

Connect One has developed SecureGAP, a costeffective, firewallon-a-chip solution that allows M2M devices to be safely connected directly to the public Internet. SecureGAP safeguards vital proprietary information for application owners through security and data segregation, which serves as a gatekeeper and natural firewall between the host processor and the Internet as well as significantly cutting connectivity costs and simplifying deployment. This technology has been introduced in the CO2128, Connect One’s newest and lowest cost IP controller that provides Internet connectivity, encryption and superior security for a host processor or device. The CO2128 powers Connect One’s entire range of modules and device servers.

The CO2128 works as a coprocessor, offloading all security and communication aspects from the main processor. As a firewall between the host processor and the Internet, SecureGAP prevents intruders from tapping directly into the host processor’s data. By maintaining a physical barrier between the public Internet and the application as well as encrypting data using SSL3, the CO2128 makes it completely safe to transfer data to and from any host processor over the Internet via 802.11b/g WiFi, 10/100 BasedT LAN, GPRS, or dial-up connection. Architecturally designed into the CO2128 as an offload engine, SecureGAP serves as the most trustworthy and reliable option for secure and efficient connectivity, and is technically superior to software firewalls installed on the host CPU. CO2128 supports LAN, Wi-Fi and all types of dial-up/wireless modems (AMPS, CDMA, CDMA2000, CDPD, GPRS, GSM, IDEN and TDMA cellular protocols). It includes a full secure TCP/IP stack, plus upper layer protocols like SMTP, POP3, MIME, HTTP, WAP, FTP ,TELNET and SerialNet mode for serial-to-IP bridging. It also includes a Web server with two websites: one for the application and one for configuring iChipSec CO2128.

The CO2128 operates at an industrial temperature range of -40° to 85°C (-40° to 185°F) and is RoHS compliant.

Connect One Semiconductors, San Jose, CA. (408) 572-5675. [www.connectone.com].

High-Performance Clock Generators ON Semiconductor has announced the expansion of its PureEdge high-performance clock generation portfolio with the introduction of two best-in-class devices, the NB3N3002 and NB3N5573.

The NB3N3002 and NB3N5573 are 3.3 volt clock generators that create selectable Host Clock Signal Levels (HCSL) and sub-picosecond (ps) jitter quality clocks at 25 MHz, 100 MHz, 125 MHz and 200 MHz. These devices are ideal for PCI Express, Gigabit Ethernet and FBDIMM applications. The PureEdge architecture provides increased design flexibility and reduces system cost compared to standard crystal oscillators and competitive silicon-based clock generation devices.

The NB3N3002 generates one differential HCSL output clock, while the NB3N5573 delivers dual output. Employing advanced 0.25 micron (um) CMOS technology, the devices significantly outperform competitive devices with phase noise comparable to expensive Surface Acoustic Wave (SAW) crystal oscillators. These devices generate high-quality clocks from a low-cost 25 MHz crystal with four selectable output frequencies and integrated 1:2 fanout buffer (NB3N5573). The device provides phase noise of -130 decibels relative to the carrier per hertz (dBc/Hz) at 100 KHz offset from the carrier frequency.

Like all of ON Semiconductor’s PureEdge devices, these new clock generators free up more of the system designer’s precious timing budget and offer true design flexibility. Silicon-based clock generation ICs, such as the NB3N3002 and NB3N5573, are inherently simpler to manufacture than expensive crystal oscillators. This results in lower overall system costs and vastly shorter lead times. The NB3N5573 is a pin-compatible drop in replacement for the competitive function device ICS557-3. The NB3N5573 provides much better jitter performance and was implemented without the Spread Spectrum feature making it a better value where SSM is not required.

Offered in a 5.0 mm x 4.4 mm lead-free (Pb-free) TSSOP-16 package, the NB3N3002 and NB3N5573 are budgetary priced at $1.80 per unit in 2,500 unit quantities.

ON Semiconductor, Phoenix, AZ. (602) 244 6600. [www.onsemi.com].

Peripheral Controller with MLC NAND Flash Support Cypress Semiconductor Corp. has introduced a new West Bridge peripheral controller with Multi-Level Cell (MLC) NAND Flash support that enables designers to use lowest-cost, highest-density flash storage.

The West Bridge Astoria controller supports up to 16 MLC NAND Flash devices, which cost approximately three times less than Single-Level Cell (SLC) NAND Flash devices for the same storage density.

By fully offloading management of USB and storage from an embedded processor, the West Bridge Astoria peripheral controller saves critical processor resources and maximizes data-transfer performance.

The controller marks the debut of Cypress’s fast-interleaving N-Xpress MLC NAND Flash control technology, with static wear-leveling, bad block management and 4-bit ECC (Error Correction Coding) to support up to 16 SLC/MLC NAND devices. The storage port can be configured so designers can select up to two SDIO devices such as Bluetooth, Wi-Fi, GPS and SD cards, making Astoria ideal for applications such as data cards and dongles. Astoria also supports other types of storage from a list that includes Secure Digital High Capacity (SDHC) v. 2.0, MultiMedia Card+ (MMC+) v. 4.2 cards, CE-ATA for HDD, as well as various types of controlled NAND. The flexible processor interface enables connection to most embedded processors adding a selection of Asynchronous SRAM, ADMUX (Address Data Multiplexing), SPI (Serial Peripheral Interface) and NAND interfaces to the Pseudo-CRAM interface of Antioch.

The West Bridge Astoria controller features up to 27 programmable GPIOs and 16 USB endpoints. It comes in a small 100-ball VFBGA (Very Fine Ball Grid Array) package that measures only 6 mm x 6 mm and 0.5-mm pitch. Additionally, Astoria supports standard handset frequencies such as 19.2 MHz and 26 MHz for clock input, removing the need for an additional crystal.

Cypress Semiconductor, San Jose, CA. (408) 943-2600. [www.cypress.com].

JANUARY 2008

45

products for designers

Firewall Technology for M2M Applications

products for designers

Eval Board Demonstrates Extended Battery Life for Portable Designs Actel Corporation has announced the new Icicle Kit evaluation board for the company’s 5 µW IGLOO FPGA. The kit showcases the ultra-low-power attributes, flexible implementation options and battery-saving advantages of IGLOO for portable applications. The $99 kit allows designers to easily and rapidly program, evaluate and modify their low-power IGLOO-based portable designs. Powered by a rechargeable lithium-ion battery, the 1.4” x 3.6” Icicle evaluation board consumes less than one-seventh the power of competitive FPGA development solutions in a design the size of a small cell phone.

The Icicle board is an environmentally friendly, RoHS-compliant solution that integrates a nonvolatile, 125,000-gate AGL125 IGLOO FPGA. The board includes the built-in, rechargeable lithium-ion battery, USB-to-UART interfaces and power management circuits.

In addition to the Icicle evaluation board, the kit includes a sophisticated programming stick for extended programming functionality. Also offered is a free, unlimited-use license for the Actel Libero Integrated Design Environment (IDE) Gold edition. This enables designers using the Icicle Kit to take advantage of the advanced power analysis tools recently introduced with Actel’s Libero IDE v8.1 to identify key sources of power in their designs. Other kit elements include user’s guide and tutorial, printed circuit board (PCB) schematics, layout and sample design.

The Icicle Kit is available immediately from Actel for $99.

Actel Corporation, Mountain View, CA. (650) 318-4200. [www.actel.com].

MicroPower Hall-Effect Switch with Complementary Push-Pull Outputs Allegro Microsystems has introduced a new ultra-sensitive, Hall-effect switch with latched digital outputs and either unipolar or omnipolar actuation. It features operation at low supply currents and voltages, making it ideal for battery-operated electronics. Key features such as: lower minimum Vcc, a small, low-profile package and push-pull complementary outputs, all serve to satisfy present and future trends in battery-operated consumer products. This new device is targeted at the consumer and industrial markets.

The low operating supply voltage, 1.65V to 3.5V, and unique clocking algorithm assist in reducing the average operating power consumption. For example, the power requirements are less than 15 µW with a 2.75V supply. Unlike some traditional Hall-effect switches, Allegro’s A1171 allows the user to configure how the device is magnetically actuated. Under default conditions the device will activate output switching with either a north or south polarity magnetic field of sufficient strength.

In the EW, 6-pin, microleaded package, the polarity specific actuation can be set by the user via an external selection pin to operate in a unipolar mode, switching only on a north or south polarity field. Lastly, the A1171 has two push-pull output structures, which source and sink current to eliminate the need for external pull-up resistors. This polarity-independence, as well as the minimal power requirements, allows the A1171 to easily replace reed switches, providing superior reliability and ease of manufacturing while eliminating the requirement for signal conditioning.

Allegro’s A1171 is currently available in the EW (2 mm x 1.5 mm x 0.4 mm DFN) package. The A1171 is priced at $0.38 in quantities of 1,000 and has a 10-12 week typical lead time to market.

Allegro MicroSystems, Inc., Worcester, MA. (508) 853-5000. [www.allegromicro.com].

46

PORTABLE DESIGN

Ultra-Small Solid-State Drive for Handheld Devices Intel Corporation announced its latest entry into the solid-state drive market with the Intel Z-P140 PATA Solid-State Drive (SSD), one of the tiniest in the industry aimed at handheld mobile devices. Smaller than a penny and weighing less than a drop of water, these 2 Gbyte and 4 Gbyte ultra-small devices are fast, low power and rugged, with the right size, capacity and performance for mobile Internet devices, digital entertainment and embedded products.

SSDs use flash memory to store operating systems and computing data, emulating hard drives. The Intel Z-P140 PATA SSD has an industry standard parallel ATA (PATA) interface and is optimized to enhance Intelbased computers, and will be an optional part of Intel’s Menlow platform for mobile Internet devices debuting in 2008.

The Intel Z-P140 is the smallest SSD in its class, making it attractive to designers and manufacturers of mobile and ultra-mobile devices. Comparatively, the Intel Z-P140 is 400 times smaller in volume than a 1.8-inch hard disk drive (HDD), and at .6 grams is 75 times lighter. It is also a much more durable alternative to HDDs. The 2 Gbyte and 4 Gbyte capacities are large enough to store mobile operating systems, applications and data such as music or photos. It is extendable to 16 Gbytes for added storage capacity.

The Intel Z-P140 PATA SSD offers read speeds of 40 Mbytes/s and write speeds of 30 Mbytes/s. Critical to mobile applications, its active power usage is 300 mW and only 1.1 mW in sleep mode, which helps to extend a device’s battery life.

With a 2.5 million hour mean time between failures (MTBF) rate, this PATA-based chip scale package delivers reliable solid-state performance in an extremely tiny footprint. The Intel Z-P140 is currently sampling with mass production scheduled in the first quarter of 2008. The 4 Gbyte version will follow the 2 Gbyte product.

Intel Corporation, Santa Clara, CA. (408) 765-8080. [www.intel.com].

Tensilica has added an optional full-speed, non-intrusive instruction trace capability to all of its Diamond Standard and Xtensa configurable processor cores. Tensilica’s TRAX-PC processor trace capture macrocell is Nexus 5001 compatible and ideal for debugging complex, challenging real-time applications such as engine and motor control.

Software control and use of the on-chip TRAX hardware is fully integrated into Tensilica’s Xplorer integrated design environment (IDE) so software engineers can easily develop and debug programs while using the TRAXPC trace macrocell.

Tensilica’s TRAX-PC processor trace capture block is an optional item for use with all Tensilica Diamond Standard and Xtensa processors. It provides tracing information through an SoC’s JTAG debug port without requiring added device pins. It helps designers trace all changes in program flow (“PC” means “program counter”) including exceptions and interrupts. The trace block uses a circular on-chip trace buffer with userdefined sizing to capture the trace stream and accepts PC-based triggers and external trigger inputs.

Tensilica’s associated software tools convert the compressed trace into an annotated program disassembly for easy debugging. These tools are fully integrated into Tensilica’s world-class Eclipse-based, Xtensa Xplorer integrated design environment (IDE). The Xplorer IDE provides a powerful visualization and debugging environment to both develop and debug programs using the TRAX-PC trace macrocell.

The TRAX-PC processor trade capture macrocell is available now for use with all current Tensilica processor products.

Smallest Color SVGA Display Kopin Corporation has announced the smallest color SVGA display (800 x 600 resolution) in the LCD industry. The CyberDisplay SVGA LVS microdisplay has the same size (0.44” diagonal) as Kopin’s current CyberDisplay VGA display (640 x 480 resolution), allowing it to utilize the same optics and housing developed for the VGA display.

This new display is the culmination of Kopin’s development program to shrink the full-color pixel size to 11.25 µm square. The CyberDisplay SVGA LVS display exhibits remarkably sharp color images.

Kopin combined smaller pixel transistors and the planar multi-metal layer process offered by 8-inch Si IC processing with an enhanced nanotechnology process for its liquid crystal alignment and a precision cell-gap liquid crystal assembly process.

Kopin’s CyberDisplays are transmissive LCD displays with the same architecture as LCD flat-panel TVs, but with ultra-high pixel densities. The new 0.44” CyberDisplay SVGA LVS display is targeted for PC and HDrelated video eyewear applications. CyberDisplay SVGA LVS samples are available to select customers for evaluation and design-in.

Kopin Corporation, Taunton, MA. (508) 824-6696. [www.kopin.com].

Tensilica Inc., Santa Clara, .CA (408) 986-8000. [www.tensilica.com].

Ultra-Low-Noise, High-PSRR, LDO Linear Regulators Maxim Integrated Products has introduced the MAX8902A/MAX8902B, the industry’s smallest 500 mA, low-noise, low-dropout (LDO) linear regulators. Packaged in a tiny, 2 mm x 2 mm TDFN, these devices provide up to 92 dB PSRR (at 5 kHz), 16 microVrms output noise, and a low, 100 mV (max) dropout voltage at full load (500 mA). The MAX8902A/MAX8902B are ideal for noise-sensitive and space-constrained applications, such as smartphones, PDAs, PMP/MP3 players, GPS devices and ultra-mobile/notebook PCs. The MAX8902A/MAX8902B offer ±1.5% output-voltage accuracy and a wide, 1.7V to 5.5V input-voltage range. The MAX8902A features preset pin-selectable output voltages between 1.5V and 4.7V, and the MAX8902B allows users to adjust the output voltage between 0.6V and 5.3V using two external resistors.

To maximize battery life, these devices consume a low, 80 microamp operating current and less than 1 microamp shutdown current. Other features include a programmable soft-start circuit to prevent high inrush currents, short-circuit protection, reverse-current protection and thermal shutdown.

Available in a thermally enhanced, 2 mm x 2 mm, 8-pin TDFN package, the MAX8902A/MAX8902B are fully specified over the -40° to +125°C automotive temperature range. Prices start at $1.25 (1000-up, FOB USA).

Maxim Integrated Products, Inc., Sunnyvale, CA. (408) 737-7600. [www.maxim-ic.com].

JANUARY 2008

47

products for designers

Integrated Real-Time Trace Support for Xtensa and Diamond Cores

ceo interview analog CMOS. So Maxim has worked more on the portable side, since CMOS tends to favor lowpower operation. At Micrel we have both CMOS and bipolar, so we cover the gamut.

A lot of the power management products we’ve developed are aimed at the handset market. We got involved early on with Qualcomm, and as a result we started developing cell phone products.

Samsung and LG turned out to be good customers for us because they were also CDMA. We wound up becoming the king of LDOs (low drop-out regulators); at the time they wouldn’t even allow a switcher in a cell phone because they made too much noise. We still produce more varieties and types of LDOs than anyone in the world.

Now we’re getting more into switchers because we have to increase efficiency. Last year we introduced a family of “SuperLNRs” (Low Noise Regulators) that feature the advantages and ease of use of LDOs with low noise, high PSRR (power supply rejection ratio) and ultra-fast transient performance. They have the efficiency of a switcher but the simplicity and ease of use of an LDO. We’re also trying to produce an LDO with the world’s lowest output voltage; we’re currently at around 1.3V, trying to get down to 1V. Then we came out with another product called Hyper Light Load, which is a portable product. The problem you have with normal sleep mode is the time required to wake the product up. With Hyper Light Load we can wake a switcher up quickly from sleep mode and still have good transient response.

Without technology that can operate below 0.7V—and as low as 0.2V—we can’t be in 65 nm designs. The challenge we face in portable power management is to be able to work efficiently from high input voltages and still deliver very low output voltages. As you lower the output voltage the accuracy becomes critical; at 0.7V, 5% accuracy is only a few millivolts. Also, switchers become rather noisy at 0.7V; a typical switcher running at minimal capacity can easily generate over 10 mV of ripple.

Now you’ve already used up a third of your noise margin for the entire system. This is the advantage of having our own fab—we can look ahead to see where we need to go and develop the processes to get there.

Ray Zinn Micrel january 2008

With over 5000 catalog products, Micrel offers a broad range of high-performance analog, mixed signal and digital ICs that address high-growth markets including cellular telephones, portable electronics, set-top boxes, desktop and notebook computers, networking and communications. The majority of the company’s revenue is derived from power management standard products that largely target portable designs.

Ray Zinn is a cofounder of Micrel and has been its President, Chief Executive Officer and Chairman of its Board of Directors since the company’s inception in 1978. Like many of Silicon Valley’s founders, Ray began his career at Fairchild Semiconductor. In those days you couldn’t just call up Applied Materials if you needed tools, you had to make them yourself. Ray invented the wafer stepper in 1974, a basic technology that has been in use ever since. That process orientation and drive to invent new technologies has been a constant at Micrel ever since.

Portable Design: Micrel produces a wide range of power management ICs. This is a hot market with a number of large players. How do you position your products vs. those of your competitors?

Zinn: Micrel is differentiating itself in parametric performance and process technology. Our products offer small solution sizes, high efficiency, low noise and excellent transient performance.

In terms of technologies, we’re kind of a marriage between LTC and Maxim. LTC uses a low-cost process and then puts a lot of effort into design and application support. A lot of what LTC does is still bipolar analog, which tends to be higher power and higher voltage. Maxim, on the other hand, was an offshoot of Intersil. What Intersil did well was

48

PORTABLE DESIGN

Portable Design: Micrel is spending money on wafer fabrication facilities in San Jose at a time when a lot of companies are going “fab lite” or even fabless, relying on Asian foundries for their silicon. What is your thinking behind this investment?

Zinn: We feel that having our own fab gives us a competitive advantage in terms of process technology differentiation, design and manufacturing cycle time, and even cost. We have always thought it was important to have a fab to control our own destiny, to be able to differentiate our products. There are now fabs in China that will allow customers to go

in and create their own processes, and that’s a new twist that’s happened in the last 10 years.

I started the company in 1978, and three years later we had our own fab. We were the first true foundry. My brother actually started it in 1971; it was called Advanced LSI, and they were strictly a foundry. I ended up buying it in 1981 from Siemens. But it wasn’t until 1985 that we started to create our own products.

We got into analog then because I didn’t think that in the digital world I could get the margins that I needed. Since Maxim and LTC were doing quite well, we decided to build design teams along the same lines.

Today we own our own fabs, the building and equipment, we have an excellent cost structure and we’re virtually debt-free. We still do some foundry work—for example, we make solar cells for our largest customer. But mostly we make our own chips.

Portable Design: Micrel derives a substantial portion of its net revenues from standard products. But in handsets in particular, more and more support chips—or at least their functions—are getting pulled into SoCs. What is Micrel doing in response to this trend?

Zinn: It’s true that more support functions are becoming standardized and then getting integrated. However, handset OEMs constantly try to differentiate mid- to high-end handsets by going beyond what’s considered “standard,” and that creates continuous opportunity for “add-on functions” that big analog baseband chips can’t integrate or anticipate early enough to integrate. Recent examples are the expanding use of application processors for high-end graphics and multimedia; GPS chipsets in non-CDMA handsets; larger LCD screens; and >3M pixel cameras requiring zoom, autofocus and high-current flash drivers.

Portable Design: In portable electronics, batteries are improving orders of magnitude more slowly than the products that rely on them. To what extent can smart power management address this issue beyond what’s already being done?

portable device use state. Some examples are dynamic voltage scaling for applications processors; Hyper Light Load Mode for state retention and light load conditions; and high-efficiency RF subsystem power management. Smart power management has enabled dramatic improvements in battery life, and there’s every reason to believe this will continue to be true going forward.

Portable Design: How do you see the portable market— consumer electronics in particular—evolving over the next 3-5 years?

Zinn: Service providers and cell phone makers are going to continue to try to differentiate themselves in terms of design, features and form-factors. I expect to see them add digital TV; GPS with extensive map and up-to-the-minute local point-of-interest information; improved PDA/computing functions; more multi media and gaming features; and of course more video content and capabilities.

The basic phone will improve a lot, too. Video phones will appear, along with improved digital picture quality due to larger, high-resolution screens. This will require higher data rate transfers. Pentaband phones will be common, with Wi-fi, WiBro and WiMAX support. Flash memory will be able to handle huge files.

Portable Design: How do you see Micrel changing over the same timeframe?

Zinn: Micrel will continue to offer the building blocks enabling innovation in cell phones. We’ll continue to focus on ease of use for customers. We’ll continue to push into smaller packages. We’ll continue to develop high-PSRR LDOs in higher frequency ranges, including more internal-inductor ICs; moving to higher integration PMICs (power management ICs); more focus on partnering for reference designs; and possibly digital power management if and when the value/price point in the market is reached.

Micrel, Inc., San Jose, CA (408) 944-8088. [www.micrel.com].

Zinn: Just a few years ago, cell phones were primarily voice-centric devices. However with the increased competition, service providers and cell phone makers are aiming to differentiate themselves in terms of design, features and form-factors. Some of these new features include multi-mega pixel cameras with high-power flashes, GPS navigation systems, high-efficiency multi-band power amplifiers, digital TV functionality, and much more. The cell phone battery chemistry has remained the same during this period of time, with battery capacities trending up only slowly. Battery technology will continue to improve incrementally, with the advent of 2.3V Li+ batteries and eventually fuel cells.

The surest way to get added functionality is by improving the efficiency of the overall power management. Smart power management will continue to increase battery life through advanced state management, where the most efficient power delivery mode is selected for any given

JANUARY 2008

49

The RTC Group is a media services company specializing in bringing companies and their products to a focused group of electronic and computer manufacturers. RTC is proud of its track record of blazing new trails in search of marketing value for our clients. Portable Design magazine is the newest addition to RTC Groupâ&#x20AC;&#x2122;s collection of publications.

advertiser index 3M Touch Systems

7

www.3m.com/touch

event calendar

Altera Corporation

2

www.altera.com

02/05-07/08

AVIONICS EXPO

36

www.avionics05.com

Cirrus Logic

29

www.cirrus.com

Delkin Devices

51

www.delkin.com

AFCEA West 2008 San Diego, CA www.afcea.org 02/08-10/08

So. California Linux Expo Los Angeles, CA www.socallinuxexpo.org

EmbeddedCommunity.com Lattice Semiconductor Corporation

4 25

www.embeddedcommunity.com www.latticesemi.com

02/12/08

Real-Time & Embedded Computing Conference

Linx Technologies, Inc

Atlanta, GA www.rtecc.com/atlanta2008

Mouser Electronic

21

www.mouser.com

02/19/08

MVACEC

41

www.mvacec.com

Real-Time & Embedded Computing Conference

www.mountainviewalliance.org

Huntsville, AL www.rtecc.com/huntsville2008

National Semiconductor

52

www.national.com

02/21/08

Real-Time & Embedded

43

www.rtecc.com

4

www.linxtechnologies.com

Real-Time & Embedded Computing Conference

Computing Conference

Melbourne, FL www.rtecc.com/melbourne2008

VadaTech

35

www.vadatech.com

03/03-07/08

White Electronic Designs

15

www.wedc.com

Wind River Systems, Inc.

17

www.windriver.com

SD West 2008-01-14 Santa Clara, CA www.sdexpo.com 03/11-12/08

Mountain View Alliance Communications Ecosystem Conference San Francisco, CA www.mvacec.com 03/17-18/08

VoiceCon Orlando 2008 Orlando, FL www.voicecon.com If you wish to have your industry event listed, contact Sally Bixby with The RTC Group at sallyb@rtcgroup.com

PowerWise® LED and OLED Drivers for Energy-Efficient Handheld Lighting Designs national.com/LED LM4510 Synchronous Step-Up DC-DC Converter Enables OLED Displays LM45 LM4510: DC-DC converter with wide adjustable outpu output voltage

LM27 Charge pump LED controller with programmable LM2755: patte pattern generators that facilitate multi-zone backlighting by in independently controlling RGB indicator LEDs

LM2757: Smallest inductorless LM2 boo regulator for keypad lighting boost and peripheral features including USB On-The-Go (OTG)

LM27 White LED driver with digital LM2756: brigh brightness control and flexible LED configurations for multiple display or keyp lighting systems keypad

Applications Handheld and portable lighting including handset, GPS navigation, and portable medical devices

To learn more about LED drivers visit: national.com/LED

© National Semiconductor Corporation, 2007. National Semiconductor,

, and PowerWise are registered trademarks of National Semiconductor Corporation. All rights reserved.