featured product: by RTC Media

featured product:

iMAT Antenna Technology

PORTABLE SOFTWARE

wireless communications: Isolated Mode Antenna Technology consumer electronics: Verification Management portable power: Adaptive Voltage Scaling

March 2008

www.portabledesign.com

An RTC Group Publication

CEO Interview: Carl Schlachte, ARC International

contents

departments

editorial letter dave’s two cents industry news analysts’ pages product feature products for designers second opinion

cover feature Fred Frantz, L-3 Communications

Next-Generation Design Issues 20 in Communications

Isolated Mode Antenna Technology 26 Frank M. Caimi Ph.D, Mark Montgomery, and Paul Tornatta, SkyCross

Verification Management: 34 The Path of Evolution

Rahul V. Shah, Sibridge Technologies Darron May, Mentor Graphics

portable power

Processor Energy Savings Through 38 Adaptive Voltage Scaling

Mark Hartman, National Semiconductor

technology focus

FPGA Prototyping 42 Speeds Development of Consumer Electronics

Andy Haines, Synplicity

ceo interview

Carl Schlachte 52

ARC International

Rad SW Compo

H/W, S/W Portability

IEEE P1900 Portable

Load Balancing

SDR Forum

Software Radio Handover

Quality of Service USB Connector

Policy C Antenna volume: 19mm Conformance Effec

n Ve ol To

consumer electronics

IEEE 802.21

wireless communications

Regulat

rs Use End

Netw ork Op er at or

Bruce Fette Ph.D, General Dynamics C4 Systems Mieczyslaw M. Kokar, Northeastern Univ. Mark Cummings, enVia

12 Analysts’ Pages

rs do en V l

Putting Intelligence in “Bricks” 16

do r

New Languages

wide, 10mm long, 2.5mm

Compon e n t P rovid ers

5 6 8 12 44 45 50

Com ponent

Providers

Board Length Dedicated to Antenna: 10mm

29 Wireless Communications

44 Featured Product

MONTH 2008

team editorial team

Editorial Director Editor-in-Chief Managing Editor Copy Editor

Creative Director Art Director Graphic Designer Director of Web Development

Web Developer

Associate Publisher Product Marketing Manager (acting) Western Advertising Manager Western Advertising Manager Eastern Advertising Manager

Warren Andrews, warrena@rtcgroup.com John Donovan, johnd@rtcgroup.com Marina Tringali, marinat@rtcgroup.com Rochelle Cohn

art and media team Jason Van Dorn, jasonv@rtcgroup.com Kirsten T. Wyatt, kirstenw@rtcgroup.com Christopher Saucier, chriss@rtcgroup.com Marke Hallowell, markeh@rtcgroup.com Brian Hubbell, brianh@rtcgroup.com

management team

Untitled-2 1

3/7/08 4:34:12 PM

Circulation

Marina Tringali, marinat@rtcgroup.com Aaron Foellmi, aaronf@rtcgroup.com Stacy Gandre, stacyg@rtcgroup.com Lauren Trudeau, laurent@rtcgroup.com Nancy Vanderslice, nancyv@rtcgroup.com Shannon McNichols, shannonm@rtcgroup.com

executive management

HOW WELL DO YOU KNOW THE INDUSTRY?

Chief Executive Officer Vice President Vice President of Finance Director of Corporate Marketing Director of Art and Media

John Reardon, johnr@rtcgroup.com Cindy Hickson, cindyh@rtcgroup.com Cindy Muir, cindym@rtcgroup.com Aaron Foellmi, aaronf@rtcgroup.com Jason Van Dorn, jasonv@rtcgroup.com

portable design advisory council Ravi Ambatipudi, National Semiconductor Doug Grant, Analog Devices, Inc. Dave Heacock, Texas Instruments Kazuyoshi Yamada, NEC America

corporate office WWW.EMBEDDEDCOMMUNITY.COM

The RTC Group 905 Calle Amanecer, Suite 250 San Clemente, CA 92673 Phone 949.226.2000 Fax 949.226.2050 www.rtcgroup.com

For reprints contact: Marina Tringali, marinat@rtcgroup.com. Published by the RTC Group. Copyright 2007, the RTC Group. Printed in the United States. All rights reserved. All related graphics are trademarks of the RTC Group. All other brand and product names are the property of their holders. Periodicals postage at San Clemente, CA 92673 and at additional mailing offices. Postmaster: send changes of address to: Portable Design, 905 Calle Amanecer, Suite 250, San Clemente, CA 92673. Portable Design(ISSN 1086-1300) is published monthly by RTC Group 905 Calle Amanecer, Suite 250, San Clemente, CA 92673. Telephone 949-226-2000; 949-226-2050; Web Address www.rtcgroup.com.

embeddedcommad_14v.indd 1 PORTABLE DESIGN

11/13/06 5:55:59 PM

The 2008 Portable Design Editor’s Choice Awards

Every year Portable Design singles out for recognition those new products that we consider to be the most innovate, choosing from among the thousands of product releases that cross our desks. This year has seen an outburst of highly creative, and some potentially disruptive, products—so much so that in some categories we’ve been forced to select multiple winners, not being willing to overlook some clearly outstanding products.

editorial letter

In the 27 years I’ve been working in and around the electronics industry, I’ve never seen such an explosion of innovation as we’ve witnessed in the last few years in portable consumer electronics. Since computers decisively lost the convergence battle to cell phones, we’ve now got handsets that take pictures, make movies and deliver music, video, TV and CD-quality audio in addition to making phone calls. I like the fact that my phone can guide me to my destination when I’m traveling and then find the nearest Chinese restaurant. Wireless has turned out to be the long-sought “killer app” that would keep the semiconductor industry on the fast track. The number of wireless interfaces in portable devices is constantly expanding. So you want a new phone: Single, tri- or quad-band? EDGE, EV-DO, HSDPA/HSUPA, TD-CDMA, TD-SCDMA, or LTE? Do you want that with Wi-Fi, Bluetooth, WiMAX or NFC? If the choices aren’t endless, the permutations seem to be. Wireless technologies are evolving rapidly and will continue to do so for many years to come. The challenge of fitting all this technology into a tightly constrained space—and then powering it from a tiny battery—has forced engineers to be highly innovative. Power management has gotten extremely sophisticated, and “low power” is a tune that everyone is singing. Low-power devices—with an order of magnitude better performance-per-milliwatt than their predecessors—are coming out regularly. On the RF side, MIMO antennas—until recently a lab experiment—are appearing on cell phones to handle multipath problems. The lab-to-fab cycle is getting shorter every month.

Innovation in Portable Design john donovan, editor-in-chief

The winners of the 2008 Portable Design Editor’s Choice Awards are: Category Analog/Mixed Signal ICs Audio Development Kit EDA Logic/Interface Memory Processor ICs Processor Cores

Company National Semiconductor Wolfson Cadence CoWare Mentor Graphics QuickLogic SST TI Microchip Freescale ARM Tensilica

Multimedia

ARC

Power Management

Maxim

Programmable Logic

Actel Altera Xilinx

RF/Microwave

Analog Devices

Sequoia Communications

Linear Technology

Software

National Instruments

Test & Measurement

Tektronix

Keithley

Innovation of the Year

SkyCross

Product Continuous-Time Sigma-Delta ADC (ADC12EU050) Audio and PMIC (WM8350) Low-Power Methodology Kit ESL 2.0 Technology Release inFact intelligent testbench ArcticLink All-in-OneMemory (SST88VP1107) MSP430F2x family PIC32 family MC9S08QE8 (QE8) MCUs Coretex-A9 Diamond Standard 106Micro Vraptor-based multimedia subsystems (AV 417V) Ultra-Low-Noise, High-PSRR, LDO (MAX8902A/MAX8902B) ProASIC3L Max IIZ Spartan-3A Mobile WiMAX transceivers (AD9354/55) Single-Chip, 7-Band, Polar HEDGE RF Transceiver (SEQ7400) Direct-Conversion I/Q Demodulator (LT5575) LabView 8.5 Real-Time Spectrum Analyzers (RSA3000B) 4x4 MIMO RF test system (2820/2895/2920) iMAT Isolated-Mode Antenna

Portable Design salutes the designers behind these outstanding products and hopes that this well deserved pat on the back will encourage them to deliver even more innovative products next year and beyond.

MONTH 2008

dave’s two cents

Homes in Dallas rarely have a basement, so much of the plumbing resides in the attic. The best time to address nagging water supply issues is winter, when the attic is a bearable temperature. This winter, I had two plumbing problems: two leaky shower valves, and the water in one shower took too long to get warm. A leaky shower didn’t seem important to me until my wife measured about two gallons of water per day per shower. My daughter claimed that the slow warming shower was what made her nearly always late. So, in the interest of family harmony, something had to be done. The leaky valves are fancy, constant-temperature mixing valves with lifetime warranties. The user’s guide provided very detailed mechanical drawings. I did not realize, however—until it was too late—that the drawings were meant to intimidate anyone trying to dis-

dave’s two cents on...

Attic Adventures and Digital Design assemble and repair the valves. So I ended up with non-functioning and even leakier valves. The builder must have thought that lifetime warranties meant just that and soldered in the connections, making it impractical (if not impossible) to remove. After all, why would you use fittings if they were supposed to last a lifetime? My wife called the valve supplier and they sent two new valves free of charge. I used the internal valve body to replace the old units and success was mine! Now, on to the slow warming shower… Turns out this shower is the most distant from the hot water supply. While we selected lowflow shower heads to save water, this doesn’t necessarily translate into time saved. I’m intrigued by the “heat-on-demand” system and some day may install one. But for now, instead, I installed a higher flow-rate shower head. While hanging out in the attic, I began to think about plumbing. Once I had referred to digital circuit designers as device plumbers. They spent most of their time virtually connecting one device to another, and there were PORTABLE DESIGN

plenty of simulation tools to ensure success. However, digital designs today have changed. In the last year, the effective processor clock rates for multimedia phones have doubled. Memory sizes also have increased dramatically, pushing designers to ever smaller geometries. Therein lies the challenge. Without any form of active power management, circuit solutions can provide the functionality, but not adequate run-time with today’s battery capacity. If 3G functionality depended solely upon battery capacity improvements to meet run-time goals, 3G would not be available for some time—given that it takes about 10 years to double battery capacity. Designers must find new ways to manage digital circuits to do more with less. To extend run-time in the deep submicron digital circuit, both active and static losses must be reduced. A common technique is adaptive voltage scaling (AVS). This method finds the minimum voltage required to support the needed propagation delay. This falls under the category of not using any more energy than needed. Other methods deploy forward and backward biasing circuits. Using 45 nm as an example, forward body bias (FBB) can improve performance by 15 percent, thus doing more with less. Another bias technique uses reverse body bias (RBB) to reduce leakage current. This technique can reduce leakage by 40 percent. Other techniques include using power and voltage domains, technology scaling and addressing SRAM leakage. Processor and DSP companies continue to develop various techniques to reduce energy loss while improving performance—giving portable products more functionality with less energy. Designing for the portable equipment space, digital designers need to consider power management as a key strategy. Like I had to fix the leaky valves, digital designers must reduce static losses and do more with less. For my two cents, whether saving water or energy, it takes an active solution to get the job done! Otherwise, you will have to do less in order to use less. Our industry must continue to develop solutions that minimize trade-offs between functionality and run-time. If I can delay attic chores another month I can claim that it’s just too hot to work up there. Take my advice, if the mechanical drawing shows more than 10 interconnecting items, call a professional or digital designer!

news Cadence Acquires Chip Estimate

Cadence Design Systems, Inc. has announced that it has acquired Chip Estimate Corporation, a leader in delivering IC planning and enterprise-level IP reuse management solutions. Founded in 2003, Chip Estimate products enable electronics design teams to predict the die size, yield, power consumption, performance and cost of chips based on almost any design architecture, IP and silicon process node options. In addition to its chip planning technology, Chip Estimate has developed the industry recognized portal, ChipEstimate.com, which hosts a collaborative partnership of over 175 IP suppliers and foundries featuring over 6,000 IP components. The unique combination

er exploration ether your goal speak directly ical page, the ght resource. technology, es and products

of Chip Estimate’s IC prediction technology and chip planning portal enables customers to perform technical and cost-benefit what-if analysis to drive cost-optimized IC design and ed reduced project risk in a more efficient and reliable manner. “We are excited to be combining our capabilities with an industry leader,” said Adam Traidman, president and CEO of Chip Estimate. “Chip Estimate customers companies providing solutions now will significantly from the synergies exploration into products, technologies and companies. Whether your goal is to research the benefit latest datasheet from a company, mp to a company's technical page, the goal of Get Connected is to put you in touchand with opportunities the right resource. Whichever createdlevel byof the combinagy, Get Connected will help you connect with the companies and products you aretion searching for. of the companies, and together we can onnected deliver even greater value to the electronics design community.” “The Chip Estimate technology and Web portal are great complements to the Cadence solutions portfolio and fit perfectly with our strategy to partner with the design IP industry instead of compete with them,” said Craig Johnson, corporate vice president, Marketing and Strategy at Cadence. “In addition to providing reliable ROI analysis to our customers, we will enable Get Connected with companies mentioned in this article. IC companies to improve their internal IP www.portabledesign.com/getconnected reuse productivity.”

End of Article

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The acquisition was completed March 7. Terms of the agreement were not disclosed. Cadence Design Systems Inc, San Jose, CA. (408) 943-1234. [www.cadence.com].

IEEE Begins Standard to Optimize Radio and Spectrum Resources Usage in Wireless Networks

The IEEE P1900.4 Working Group, which will create a standard to optimize radio usage and improve the overall capacity and quality of service of wireless systems in a multiple radio access technologies environment, held its first meeting February 6-8 in Madrid, Spain. The group approved the content of a baseline document for IEEE P1900.4 at the meeting. P1900.4 is being developed within the IEEE Standards Association Corporate Standards Program, which offers a streamlined, corporate-focused approach to standards development. The standard is scheduled for completion in February 2009. IEEE P1900.4, “Architectural Building Blocks Enabling Network-Device Distrib-

uted Decision Making for Optimized Radio Resource Usage in Heterogeneous Wireless Access Networks”, will address the functional architecture of the overall system, information exchange and seamless handover between a network and the devices using it. Three primary use cases were identified at the Madrid meeting—dynamic spectrum allocation, dynamic spectrum access and distributed radio resource usage optimization. These scenarios are intended to improve overall wireless system capacity and quality of service in a multiple radio access environment. The system architecture and protocols selected will help

optimize radio resource usage by exploiting information exchanged between a network and mobile terminals. This capability for radio resource optimization extends to the support of multiple, simultaneous links and dynamic spectrum access. For more information about these projects and how to get involved, visit http://www. ieeep1900.org/. IEEE, New York, NY. (212) 419-7900. [www.ieee.org].

New IP-XACT Specification to Aid Design and Advanced Verification

The SPIRIT Consortium has added two key features to its IP-XACT specification: support for IP using transactional modeling styles and a new tight generator Interface (TGI). The IP-XACT specification, an XML databook that documents many different aspects of IP modules, enables designers using IPXACT tools to automatically create many different expressions of a design in a consistent and correlated way. Design and verification engineers will benefit from using this available specification through the automation of IP processing. IP-XACT specifications document hardware and software views of a design. They document the interface on an IP, including identification of ad-hoc connections, interfaces to standard buses and custom buses. This allows system design and verification tools processing the IP to automatically recognize the integration requirements. They also document the views of the design, as well as register and memory-map information. Building on the IP-XACT 1.2 specification, IP-XACT 1.4 extends the IP-XACT data model to enable IP with transactional interfaces to be fully documented. IP with transactional interfaces are widely used for architectural exploration, performance modeling and verification methodologies. In keeping with the IP-XACT goals of being language- and design-style neutral, the XML schema supports a wide range of transaction-level modeling (TLM) styles expressible in a range of HDLs, including

SystemVerilog and SystemC. IP-XACT 1.4 allows designers to freely mix and process IP with both transactional and traditional RTL wire interfaces in the same designs. Existing IP-XACT users are assured forward compatibility to the 1.4 release, with some simple processing scripts that will automatically migrate existing IP-XACT data into the new data model. IP-XACT 1.4 also introduces the Tight Generator Interface (TGI) as a key mechanism for maximizing generator portability across all IP-XACT Design Environments. Generators are a key part of the IP-XACT specification used to process the XML data into a wide variety of usable design data. They encapsulate specialist designer knowledge in a way that can be deployed in any IP-XACT design. TGI enables generators to be written using a programming language-neutral API, ensuring compatibility with all IP-XACT Design Environments. This increases the choice of generators available to IP-XACT designers and reduces the cost of developing and maintaining generators across the range of IP-XACT Design Environments. SPIRIT Consortium, Napa, CA. (707) 265-8193. [www.spiritconsortium.org].

IMEC Reports Methodology to Analyze Process Variability Compatible with DFM Tools

At DATE IMEC reported a variabilityaware modeling (VAM) flow that analyzes process variability of sub-45 nm technologies, which enables designers to optimize their system design for timing, energy and yield versus expected application load. The flow assesses the impact of process varia-

tions and degradation effects of sub-45 nm technologies on the system performance by giving valuable information to the designer. IMEC’s VAM flow can hook into commercial design for manufacturing (DFM) tools and has been validated on industrial process technology data and IP cores. Leveraging on IMEC’s leading expertise in advanced sub-45 nm process technology and system design technology, IMEC developed the VAM flow for percolating information

on process variability of sub-45 nm technology from the transistor up to the system level. VAM enables IP block and system designers to make predictive assessment of architecture design options and to identify design bottlenecks before manufacturing. In this way, functional problems and parametric uncertainty of their designs caused by process and material variability of deep sub-micron technologies can be overcome. IMEC validated the VAM flow by propagating commercial TSMC 45 nm variability data to estimate performance and energy for an ARM926 processor. The VAM output was used to optimize the processor before manufacturing using a commercial tool flow. Qualcomm and Samsung are currently the two first top-tier industrial partners in IMEC’s Technology-Aware Design program. IMEC has recently also signed a cooperation agreement with SI2 to pursue alignment with industry standardization effort for SSTA. IMEC, Leuven, Belgium. +32 16 28 12 11. [www.imec.be].

MARCH 2008

news TriQuint to Acquire WJ Communications

TriQuint Semiconductor and WJ Communications, Inc. have announced a definitive agreement for TriQuint to acquire WJ. Through this acquisition, TriQuint expects to expand its presence in the wireless infrastructure market comprised of cellular base stations and wireless and cable broadband infrastructure. The acquisition also provides TriQuint with a Silicon Valley-based design center and accelerates the evolution to multi-function modules for infrastructure applications.

TriQuint has focused on bringing the technical innovation and cost savings it provides in the handset market to the evolver exploration ether your goal ing requirements of the communications inspeak directly frastructure market. WJ shares TriQuint’s ical page, the ght resource. vision of combining RF power, switching technology, and filtering in cost-effective module solues and products tions for base station and other infrastruced ture applications. Under the terms of the agreement, TriQuint will acquire by merger all outstanding shares of WJ for $1.00 per share, implying a purchase price of approximately $72 million. Excluding one-time charges, TriQuint companies providing solutions now expects dealfrom toa company, be neutral to earnings exploration into products, technologies and companies. Whether your goal is to research the latest the datasheet mp to a company's technical page, the goal of Get Connected is to put you in touchduring with the right resource. level of fiscal 2008Whichever and accretive thereafter. gy, Get Connected will help you connect with the companies and products you areThe searching for. transaction has been approved by the onnected Board of Directors of both companies and is expected to close within 90 days, subject to an affirmative vote by WJ shareholders and other customary conditions.

End of Article Get Connected

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TriQuint Semiconductor, Hillsboro, Oregon. (503) 615-9000. [www.triquint.com].

TI, Maple Design, Virtutech Join OSCI

The Open SystemC Initiative (OSCI), an independent non-profit organization dedicated

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to supporting and advancing SystemC as an industry-standard language for electronic system-level (ESL) design, today announced it has added three new members—Texas Instruments Incorporated (TI), Maple Design Automation and Virtutech, Inc.—to its growing ecosystem of system-on-chip (SoC) companies, tool vendors, intellectual property suppliers and embedded software developers. Virtutech enters the organization as the tenth Corporate Member, joining ARM Ltd.; Cadence Design Systems, Inc.; CoWare, Inc.; Forte Design Systems; Intel Corporation; Mentor Graphics Corporation; NXP Semiconductors; STMicroelectronics; and Synopsys, Inc. With the addition of TI and Maple Design Automation, OSCI’s Associate Corporate Members number more than 25 companies. OSCI offers a range of membership options for companies and not-for-profit organizations. The organization consists of six volunteerbased technical working groups (WG) overseen by a board of directors that helps shape direction and strategy. Open SystemC Initiative (OSCI), San Jose, CA. (408) 266-9753. [www.systemc.org].

Open Virtual Platforms for Virtual Prototyping, Embedded Software Development

Imperas Ltd. has launched Open Virtual Platforms (OVP) to establish a common, open standard solution for developers to quickly and inexpensively simulate embedded software on system-on-chip (SoC) designs. The donation, representing approximately $4 million worth of technology investment, includes modeling technology, Imperas’ existing library of models, and OVPsim, a proven reference simulator. Imperas will support and manage the OVP Web site, and will contribute

much of its innovation to keep this infrastructure evolving. OVP addresses problems embedded software developers have when modeling the SoC that hosts their software. These range from modeling environment complexity, lack of open resources for building platforms, to insufficient simulation speed for software verification. The OVP Web site is found at www.OVPworld.org. It will serve as the portal for OVP, with details about the technology, a discussion forum for the OVP community, and links to download all OVP components. Available for download, free of charge are: APIs for building platform verification infrastructure, and developing behavioral and processor models; existing model libraries of processors, behavioral components, peripherals and platform templates; and OVPsim, a free reference simulator shipped as an executable. The Web site offers presentations, datasheets, videos, demonstrations, discussion forums, press information, resources and the OVP technology for download including models of ARM, MIPS and OpenRISC OR1K processors. Imperas, Ltd., Thame, Oxfordshire, U.K. +44 1844 217114. [www.imperas.com].

TSMC Announces Reorganization

TSMC announced that it has approved the request of Dr. Kenneth Kin, Senior Vice President of Worldwide Sales and Service, to retire at the end of this year. Prior to his retirement, Dr. Kin will serve as Senior Vice President of Special Projects responsible for ongoing new business initiatives and developing new strategic businesses, effective March 1. Dr Kin will continue to report directly to Chief Executive Officer Dr. Rick Tsai until his retirement. TSMC announced that beginning March 1, its Operations I and Operations II organizations will merge with technology and service marketing units under the Corporate Development Organization to form the new Advanced Technology Business Organization and Mainstream Technology Business Organization.

These two new organizations will respectively take responsibility for formulation, development and execution of advanced technology and mainstream technology business objectives, and will assume full accountability for financial performance. In addition, the Worldwide Sales and Service Organization will merge with the market analysis and research units under the Corporate Development Organization to form the Worldwide Sales and Marketing Organization, which will integrate the company’s sales and marketing functions. The worldwide account management teams will serve both the Advanced Technology Business and the Mainstream Technology Business organizations, and retain their role as the customer contact for both entities. The newly established Advanced Technology Business, Mainstream Technology Business, and Worldwide Sales and Marketing Organizations will respectively come under the leadership of Senior Vice President Dr. Mark Liu, Senior Vice President Dr. C.C. Wei and Vice President Jason Chen, and all will report directly to CEO Dr. Rick Tsai. In addition, other organizations in the company will also readjust to support this reorganization soon. TSMC North America, San Jose, CA. (408) 382-8000. [www.tsmc.com].

LSI Buys Infineon’s HDD Business

Infineon Technologies AG has entered into a definitive agreement, under which LSI Corporation will acquire Infineon’s hard disk drive (HDD) business. Under the terms of the agreement, LSI will purchase the Infineon HDD business, which

designs, manufactures and markets semiconductors for HDD devices. Infineon will transfer its complete HDD activities, including customer relations as well as know-how and will grant an IP license. Also included in the transaction is a design service agreement. The transaction does not comprise significant assets and transfer of employees. Financial details were not disclosed. “The sale of our HDD business is yet another step toward our overall commitment to streamlining our business activities to focus on our core markets,” explained Sandro Cerato, Vice President and General Manager of the ASIC Design and Security Business Unit at In-

fineon Technologies. “In LSI, we have found an excellent company with a mutual interest in supporting our customer base. Infineon is fully committed to work with LSI to provide a seamless transition.” “Through the addition of the Infineon HDD business, LSI has taken another significant step toward becoming the leading worldwide provider of silicon solutions for hard disk drive makers,” said Ruediger Stroh, Executive Vice President and General Manager, Storage Peripherals Group, LSI. “We expect the acquisition to immediately accelerate revenue with a top-tier customer, Hitachi Global Storage Technologies, while enhancing our competitive position in the desktop and enterprise space.” The acquisition is expected to close in the second calendar quarter of 2008 following the satisfaction of regulatory requirements and other customary closing conditions. Infineon Technologies North America Corp., Milpitas, CA. (866) 951-9519. [www.infineon.com].

MARCH 2008

analysts’ pages Micron/Nanya MOU – Qimonda’s Bane or Boon?

On Monday March 3 Micron and Nanya announced the signing of an MOU that had already been anticipated for a couple of weeks. Under their agreement the companies will explore potential technology sharing, and a joint technology program for DRAM development and design to focus on sub-50nm technologies. Many in the investment community nervously anticipate that this move works against the Inotera joint venture between Nanya and Qimonda. At Objective Analyses we believe that the opposite is more likely—that Nanya’s agreement with Micron may prove to bolster the Qimonda JV. One week earlier Qimonda took the unusual step of announcing their DRAM road map for

perfect sense for the company to team up with a stacked-capacitor expert. If the company can marry Micron’s stacked capacitor technology with Qimonda’s trench capability, they may be able to ramp the 4f² technology more rapidly, cutting costs and gaining a competitive edge. It is less clear why Micron would be interested in such a deal. We also cannot tell what this means to Qimonda, who may have to fend for themselves to develop stacked-capacitor expertise. During Qimonda’s road map conference call company officers explained that Qimonda understands stacked capacitors, having manufactured them in their SOC products for the last 15 years. As for the MOU indicating the end of the Qimonda/Nanya Inotera JV, we do not embrace this viewpoint, and anticipate further cooperation in the future. Objective Analysis, Los Gatos, CA. (408) 356-2549. [www.objective-analysis.com].

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Can the Semiconductor Market Regain its Momentum in 2008?

companies providing solutions now

thethenext process generations. The comexploration into products, technologies and companies. Whether your goal is to research latest three datasheet from a company, mp to a company's technical page, the goal of Get Connected is to put you in touchpany with the right resource. level of cell architecshowed off aWhichever new DRAM gy, Get Connected will help you connect with the companies and products you areture searching for. that allows the company to achieve the

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ultimate goal for any memory technology—a 4f² cell. This new approach marries Qimonda’s unique trench know-how with the stacked capacitors used by most other DRAM makers. The trenches will be used to construct bit lines rather than capacitors, allowing the circuitry to run under the DRAM cell, cutting chip area by about 30% compared to the industry-standard 8f² cell or 15% compared to the 6f² DRAMs made by Micron and Samsung. Nanya understands how to make trench technology, but we suspect that their stackedcapacitor expertise is lacking—thus it makes

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According to iSuppli Corp., the semiconductor growth cycle is entering a period when traditionally an acceleration in revenue growth would be expected. However, with the current cycle delivering such weak growth and with economic worries mounting, concerns are rising over whether the semiconductor industry can regain its momentum and manage to expand this year. iSuppli’s current forecast calls for the global semiconductor industry to achieve revenue growth of 7.5 percent in 2008, up from 4.1 percent in 2007. But amid signs of weakening pricing and reduced demand for NAND flash, as evidenced by Apple Inc.’s recent slashing of its expected 2008 order levels for the memory and Intel Corp.’s financial warning, iSuppli expects to modestly trim its 2008 semiconductor growth forecast later this month. With the current growth cycle having hit bottom in February 2006, the semiconductor market normally would be expected to undergo a robust rebound in early 2008, following the industry’s normal cyclical pattern. However, the current cycle is generating so little growth

that a strong market expansion is not expected this year. Despite this, factors including tighter inventory controls and a limited economic downturn are expected to keep semiconductor growth positive for the year, noted Dale Ford, senior vice president, market intelligence at iSuppli. Inventory on the Wane Ford noted that semiconductor cycles tend to lose momentum due to supply/demand balance factors within the electronics value chain, rather than because of overall end-demand issues. An imbalance in supply/demand is most easily seen through an analysis of excess inventory levels. “In the early stage of the expansion, we see the sales momentum return, we see the growth come back and we see companies eager to capture market share,” Ford said. “Thus, we have over production and over capacity. Then, later on, the market must bring things back into balance, which leads to a correction.” However, Ford noted that the inventory situation shows that the industry is currently in a reasonably healthy balance at this point in the semiconductor growth cycle. “The last major downturn (in 2001) had a perfect storm of over-build of capacity, a collapse in demand and out-of-control inventory levels,” Ford said. “The industry has gone through a learning period on how to manage capacity more tightly. We’re now getting an earlier warning signal for excess inventories. Once there was a signal that inventories were out of balance, the industry responded quickly to get them back into balance. Once the inventories stabilize, we will see a return to balance between production and demand.” Ford noted that excess semiconductor inventories in the electronics value chain are expected to fall to the $3.3 billion range in the first quarter. This will be down dramatically from its peak of $6.1 billion in the first quarter of 2006. Meanwhile, semiconductor makers plan to manage overall factory utilization in 2008 at levels comparable to 2007, helping to restrain supply growth and to keep pricing from falling too much for many semiconductor part types. Furthermore, Ford said that most economists predict the U.S. economy will show

“This is where the fate of the year lies,” Ford said. “Whether the year turns out well or not, the second quarter is the best indication of what will happen this year.” iSuppli Corporation, El Segundo, CA. (310) 524-4000. [www.isuppli.com].

either low growth or experience a mild recession in 2008 but will avoid a major recession this year. With global electronics manufacturing growth projected to drop modestly in 2008 compared to 2007, this will limit the negative economic impact on the semiconductor industry. A Shrinking Cycle The lack of a major increase in semiconductor revenue growth momentum reflects a longterm trend in the chip industry toward more restrained expansion. “It’s interesting to go back 20 years and see the shifts in long-term growth rates,” Ford said. “Years ago, the global semiconductor market maintained a 27 percent Compound Annual Growth Rate (CAGR), then it slowed to 17 percent, and now we are in a period of approximately 7 percent long-term CAGR. These are maturing dynamics. This is a larger and more mature industry—and it’s acting like a larger and more mature industry.” Second Quarter Showdown Whether the semiconductor market can shake off its woes and achieve growth in 2008 will hinge largely upon the industry’s performance in the second quarter, Ford predicted. The first quarter will be seasonally slow, with revenue declining by 7.5 percent compared to the fourth quarter of 2007. However, revenue growth will rebound in the second quarter, rising by 4.6 percent sequentially. With flat growth of 0.1 percent in the fourth quarter and an 11.8 percent increase in the seasonally strong third quarter, the second quarter performance will be a key indicator of market momentum for the second half of 2008.

2007 was Momentous for UMD Market

2007 was a year of significant events in the enigmatic Ultra Mobile Devices (UMD) market, reports In-Stat (http://www.in-stat. com). Major moves were seen on multiple fronts including connectivity, new ultra mobile devices and new processors, the hightech market research firm says. In addition, the industry is now beginning to accept that there can only be one Internet. Multiple versions with limited/cut content and performance depending on whether the user’s device identifies itself to the network as a phone or a PC are not an acceptable solution for consumers. “Major moves by processor manufacturers will continue to enable new UMD designs (primarily UMPCs and MIDs),” says Ian Lao, In-Stat analyst. “New processor platforms such as Silverthorne from Intel and Isaiah from VIA will continue to target not only performance but also power dissipation.” Recent research by In-Stat found the following: • Long-range wireless broadband, such as WiMAX, and new wireless technologies like Gobi, a new platform from Qualcomm, are poised to bring anywhere connectivity to reality. • The market accepts the mobile Internet usage concept as seen by the success of products such as the Q1/Q1Ultra, iPhone and N810 from Samsung, Apple and Nokia respectively. • The fragmented nature of consumer usages makes it all but impossible to meet the significantly different usage needs with one do-all device. In-Stat, Scottsdale, AZ. (480) 483-4440. [www.in-stat.com].

MARCH 2008

analysts’ pages Intel Strategy Draws New Competitors

Intel is now battling with new competitors in addition to known adversaries—AMD and IBM—making the next few years competitive for the silicon giant, reports In-Stat. Due to anticipated slower growth and lower pricing in the PC market, Intel’s key base since the 1980s, Intel is looking to new markets for growth opportunities, the high-tech market research firm says. “Intel’s CEO, Paul Otellini, identified ultramobile PCs (UMPCs)/Mobile Internet Devices (MIDs), emerging markets PCs as key targets (allegedly worth US $10 billion each) and consumer electronics, giving the competition ample warning to prepare for Intel’s onslaught,” says Jim McGregor, In-Stat Principal Analyst. “Intel’s expansion into emerging form-factors, such as MIDs, with low-power products expands its list of competitors, particularly those in the ARM processor camp.”

er exploration ether your goal speak directly ical page, the ght resource. technology, es and products

Samsung Top Mobile WiMAX Equipment Vendor

Samsung has been ranked at the top of the latest Vendor Matrix for WiMAX equipment vendors released by ABI Research. Motorola and Cisco Systems claimed the second and third spots in the company’s new evaluation of worldwide mobile WiMAX equipment vendors. The Vendor Matrix is an analytical tool developed by ABI Research to provide a clear understanding of vendors’ positions in specific markets. Principal analyst Philip Solis commented, “The top companies in this ABI Research Vendor Matrix are all strong in providing various wireless and wired parts of telecommunica-

tions solutions, which will be critical in constructing a comprehensive offering. Most of these companies have also done early work in critical smart antenna solutions and OFDMA, holding strong intellectual property portfolios ed in these areas.” Recent research by In-Stat found the following: Vendors are assessed by ABI Research on • AMD will shadow Intel’s move into emerg- the important parameters of “innovation” and ing form-factors with accelerated process- “implementation” across several criteria unique ing units (APU). to each vendor matrix, such as customer wins, • IBM will continue pushing the POWER contract awards, global reach, market share, companies providing solutions now processor architecture servers and from con-a company, patents, R&D spending, time-to-market and exploration into products, technologies and companies. Whether your goal is to researchfor the latest datasheet mp to a company's technical page, the goal of Get Connected to put you in touch the rightbelieves resource. Whichever levelmovers, of sumer iselectronics, butwith In-Stat it first among others. gy, Get Connected will help you connect with the companies and products you are searching for. may exit the semiconductor business withonnected in a decade due to high fab costs, competi- ABI Research, Oyster Bay, NY. (516) 624-2500. [www.abiresearch.com]. tion and changing business models. • ARM suppliers and VIA will compete with Intel for MID/UMPC, what In-Stat refers to as Ultra Mobile Devices (UMDs), design wins. • Intel will maintain its leadership position in computing, but faces competition and difficulty overcoming other barriers in consumer electronics.

End of Article Get Connected

with companies mentioned in thisScottsdale, article. In-Stat, AZ. (480) 483-4440. www.portabledesign.com/getconnected [www.in-stat.com].

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cover feature portable software radios

Putting Intelligence in “Bricks” Cognitive radio technology can provide more robust, effective public safety communications capabilities and tools.

by Fred Frantz, Director, Law Enforcement Programs, Advanced Research Division, Global Security & Engineering Solutions, a division of L-3 Services Incorporated

The size and weight of early public safety portable radios led them to often be referred to as “bricks.” While that reference had more to do with the physical characteristics of the radio, it also implied that the radios were not all that sophisticated. Today’s public safety radios, however, incorporate a significant amount of software that processes RF signals. In fact, most high-end portables fit typical engineering definitions of software defined radios. (The SDR Forum’s most recent definition for software defined radio is a radio in which the physical layer’s operating functions are implemented using software.) For example, typical public safety portable radios today can support multiple protocols, can be reprogrammed for different protocols, channel assignments, talk groups (for trunked radio systems), and so on. While software defined radios have added significant flexibility to public safety portable radios, the next step in the progression of capabilities is to add cognitive capabilities to public safety portables. A radio is considered cognitive if it is aware of its environment and internal state and can make decisions about its radio

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operating behavior based on that information and predefined objectives. Much of the initial research into cognitive radio occurred through military research that was focused on dynamic spectrum access. The concept of dynamic spectrum access is to identify available spectrum that is not utilized and use it as needed to avoid interference, maintain connectivity, expand capacity, and so on. A successful demonstration conducted under the DAPRA xG program proved the viability of the overall concept. However, dynamic spectrum access is often associated with accessing unlicensed spectrum or spectrum outside that licensed to the user, neither of which is likely to provide immediate value to public safety users. The key for public safety is to develop cognitive radio technology beyond the concepts of dynamic spectrum access.

Interoperability

Interoperability has been a long-standing challenge in public safety communications; numerous examples have been cited over the past several years in which responders with

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incompatible radios have been unable to communicate. While there have been significant improvements in deploying shared systems, shared channels and gateways, the problem still exists that responders to an incident can have incompatible radios. The ultimate interoperability solution (from a technical standpoint) would be for a responder’s radio to configure itself to meet the requirements and the capabilities of the communications established for an incident. The Software Defined Radio (SDR) Forum identified the potential for SDR technology to support interoperability in a 2006 report on SDR Technology for Public Safety1: “This capability improves interoperability by further enabling radios to be reconfigured to meet the requirements of the incident to which the subscriber is responding. This seamless interoperability with minimal user intervention is a model that could be achieved as multi-band, multi-service SDRs become well established in the public safety community.” Researchers are developing prototype capabilities to recognize waveforms to allow radios to reconfigure to the communications capabilities in place (for incident or disaster response). For example, researchers at Virginia Tech and Cognitive Radio Technologies are developing a Public Safety Cognitive Radio design to provide interoperability by first sensing the environment to identify frequency and waveforms in use, then provide the user with the option of reconfiguring the radio accordingly2.

er exploration ether your goal speak directly ical page, the ght resource. technology, es and products

The London Bombing Scenario

While researchers are developing prototype capabilities to address the interoperability challenge, thedatasheet SDR Forum is looking at other appliexploration into products, technologies and companies. Whether your goal is to research the latest from a company, mp to a company's technical page, the goal of Get Connected is to put you in touchcations with the of rightcognitive resource. Whichever level of radio technology for pubgy, Get Connected will help you connect with the companies and products you arelic searching for. safety to encourage further research. The onnected Forum’s Public Safety Special Interest Group is conducting a series of analyses to identify use cases for cognitive capabilities for public safety. The first of these analyses reviewed the events, the response to and the communications challenges of the terrorist bombings in London on July 7, 20053. The analysis approach looked at a real scenario as inspiration for ideas on how cognitive radio could enhance public safety communications. One such concept involves the ability to Get Connected with companies mentioned in this article. extend network coverage beyond the coverwww.portabledesign.com/getconnected age envelope of network infrastructure using

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multiple hops from radios outside the coverage envelope to a radio configured as a repeater. In the London scenario, responders at the scene of explosions inside the subway tunnels were unable to communicate to their aboveground networks. Cognitive radio capabilities could be used to automatically reconfigure radios to include a repeater capability to extend network coverage to areas where radios are otherwise cut off from their infrastructure, particularly during initial response to an incident before additional communications resources can be deployed. As explained in the SDR Forum report, this network extension would allow transmissions to be passed back and forth from the incident site along a network of individual responder radios operating in peer-to-peer mode to a radio that can communicate with the main radio system/network. A radio would be positioned where it could maintain connectivity with the aboveground infrastructure (such as at an opening to the tunnel) and function as a repeater to bridge between the otherwise disconnected radios and the infrastructure. Depending on distribution of radios in the tunnels, additional radios could also be automatically reconfigured to act as repeaters among the disconnected radios. While this particular example was derived from the London scenarios, there is more general applicability. For example, in a scenario in which there is significant infrastructure loss (such as a major hurricane), the proposed capability could provide the ability to maintain connectivity where there are coverage holes, or where temporary and mobile network capabilities create dynamic coverage footprints. This particular use case is the basis of a research challenge sponsored by the SDR Forum. It was defined as one of the problem areas of the Forum’s Smart Radio Challenge, in which university student teams compete to demonstrate technical solutions to research problems.

Dynamic Prioritization

Another concept identified in the SDR Forum’s report involves dynamic prioritization. Land mobile radio trunking systems today have prioritization capabilities that allow certain talk groups to be granted access to the network more readily than others. However, such prioritizations are statically defined. One of the observations about the London scenarios

700 MHz Approaches

Another application of cognitive radio technology in subscriber performance is outlined in a recent SDR Forum report on the application of technologies to the newly auctioned 700 MHz spectrum. “Transmit power control, which is employed today in many commercial cellular systems, can improve the efficiency of the system. Currently implemented techniques are focused primarily on maximizing battery life by controlling transmit power as a function of distance from the cell site. This is generally performed by an individual handset as a function of its location. A more sophisticated cognitive radio approach could be implemented that incorporates

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(although not in the context of a trunked radio system) is that the dynamic nature of an incident response changes the priority that should be given to communications from an individual responder. The report thus introduces the concept of dynamically assigning priorities based on evolving aspects of an incident. Such aspects can include, but are not limited to, the role that a particular responder is performing in the incident, the type of data being communicated, or the physical location of the responder. The role of cognitive capabilities here is in the ability to adjust in real time those priorities based on the unfolding events of the incident, communications resources demands and availability, and the changing roles of individual responders over the course of an event. Implementation of this cognitive capability will likely require functionality at both the subscriber unit and within the network infrastructure. The subscriber unit provides input based on responder role, type of data being communicated and location information, while the network cognitive capabilities include load balancing and resource management. Cognitive capabilities with a portable radio can also improve radio performance in terms of parameters such as transmission quality and battery life. For example, cognitive radio algorithms could be implemented to adjust waveform bandwidths and frequency selections based on the geolocation and relative positions of the users. Waveform parameter adjustments allow the radio to trade off parameters such as data rates, coverage and interference based on the dynamic RF environment, location of devices, and so on.

the locations and activities of multiple users to improve performance of multiple users and multiple links. For example, frequency selection for one link could be selected to minimize adjacent channel interference to another user, allowing that user to maintain a lower transmit power, which in turn maximizes battery life. Cognitive capabilities in such scenarios are likely to be distributed among subscribers and the network; subscriber devices may provide information about the RF environment while decision logic relating to multiple links and subscribers would likely be performed at the network.”4

Next Steps

While the technology is promising, and there are demonstrable capabilities from both the research community and the military, there are still some steps that must occur before such devices will be available for public safety use. In addition to the ongoing research and development, there are some regulatory considerations that must be addressed. While none of the capabilities proposed above require public safety radios to operate outside licensed frequencies, the capabilities may require some adjustments to the type acceptance processes currently required for public safety radios. The other major area that will need to be addressed is the development of policies and procedures, and subsequent training of users, to best exploit new capabilities. While much of the cognitive radio capability would be transparent to a public safety officer, understanding of additional capabilities will be important to maximize their impact and value. A new generation of radios for public safety is rapidly approaching the marketplace, capable of far more than simply receiving and transmitting on a specific frequency defined by the user or programmed into the radio. By reconfiguring to meet the needs and circumstances of each incident, such portable radios can provide significant tools and capabilities to support public safety end users, network managers and communications unit leaders. They will be the most sophisticated “bricks” around. L-3 Communications Corporation Chantilly, VA. (703) 708-1400. [www.l-3com.com/qses].

[1] SDR Forum, Software Defined Radio Technology for Public Safety,” SDR Forum Report No. SDRF-06-P-0001-V1.0.0, April 2006, available at www.sdrforum.org. [2] B. Le, F. Rodriguez, Q. Chen, B. Li, F. Ge, M. ElNainay, T. Rondeau, and C. Bostian. “A Public Safety Cognitive Radio Node,” SDR ’07, Denver, CO, November 2007. [3] SDR Forum, Use Cases for Cognitive Applications in Public Safety Communications Systems, Volume 1: Review of the 7 July Bombing of the London Underground, SDR Forum Report No. SDRF-07-P-0019-V1.0.0, November 2007, available at www.sdrforum.org. [4] SDR Forum, Considerations and Recommendations for Software Defined Radio Technologies for the 700 MHz Public/Private Partnership, SDR Forum Report No. SDRF-07R-0019-V1.0.0, December 2007, available at www.sdrforum.org. MARCH 2008

cover feature portable software radios

Next-Generation Design Issues in Communications If wireless devices are to communicate and interoperate autonomously, they first need to speak a common language.

by B ruce Fette PhD, Chief Scientist, General Dynamics C4 Systems; Mieczyslaw M. Kokar, PhD, Northeastern University; Mark Cummings PhD, Managing Partner enVia

Next-generation communication systems are presented with many design challenges. We are moving into an age where the rules for spectrum access may change faster than new equipment can be fielded and faster than new software for the equipment can be developed. At the same time, heterogeneity is increasing. The rate of development of new technologies and new air interface standards (AISs) is continuing to grow. Research is now exploring many new modes for finding spectrum, for negotiating for use of spectrum, for adapting the modulation to fit into available spaces, and for protocols by which radios can exchange their capabilities in this new field of Cognitive Radio and Dynamic Spectrum. Several organizations are hard at work to lay down the necessary groundwork to support these new concepts. The Software Defined Radio Forum has established the Cognitive Radio Work Group (CRWG) and the Meta Language for Mobility1 Work Group (MLMWG), while

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IEEE has set up the SCC41 committee to address related technology questions. Furthermore, there are calls for improved interoperability in public safety radios. This opens the question of how one radio might tell another radio about the communication protocols they have in common, and thus how to interoperate. [1] In order for Cognitive Radio applications to be built upon reasonably standardized software components, and validated stable communication signaling protocols, we need to begin to identify what messages must be exchanged between radios, and between the radios and their base station support infrastructure. We must specify standardized etiquettes and protocols that assure stable network behavior. And we must define the method by which revisions of not only software, but revisions of system control behaviors are updated to radios in the field. We need to define the protocols by which a subscriber to multiple services can interact with one or more and even

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languages that the actors could possibly use. SDR Forum is working on a formal language with computer process-able semantics that could be used as a common language for all this communication.

perform handover amongst these services. The analysis of these requirements revealed that in order to satisfy the dynamic nature of possible companies providing solutions now types of messages that the radios will have to exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, mp to a company's technical page, the goal of Get Connected is to put you in touchexchange with the right resource. Whichever level and “understand,” it isof not possible to gy, Get Connected will help you connect with the companies and products you areprovide searchingan for. exhaustive list of messages and proonnected tocols. Instead, we need to define the language standards that will provide the capabilities of expressing a wide variety of possible exchanges, including those that have not been anticipated at the design time of the radio equipment or software development. To achieve such a goal, the languages must have not only formally defined syntax, but also formal, computer-processable semantics. The formal syntax and semantics will enable radios to interpret any message that is expressible in the language. Get Connected with companies mentioned in this article. The MLMWG has defined a number of use www.portabledesign.com/getconnected cases of Cognitive Radios, and from these use

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cases we will begin to define how policy, capability, etiquette and protocol are communicated amongst radio members of a network. Our early exploratory work in this topic has considered examples of both formal languages and non-formal description languages for specific applications. The formal languages used for the use cases included such languages as Web Ontology Language (OWL) and rule languages, like Semantic Web Rule Language (SWRL). The examples of non-formal description languages include: 1) Vita Radio Transport for Analysis of RF Spectrum (VITA 49), 2) E2R Functional Description Language, and 3) various publications on use of XML as a generic means to describe capability to both human and machine. We are also closely tracking the work of IEEE SCC41 / P1900 and 802.21 activities, which are performing related work. The goal of the MLMWG is to symbiotically integrate the advantages of the descriptive languages with the formal languages so that radios not only can use the terms that are already known to domain experts, but also understand the messages formulated in the new standard languages. Two of the first use cases developed within the SDR Forum2 are the “London Bombing Scenario” and the “Chemical Plant Fire”3. This is being further evolved as a technical specification of what a CR might be expected to be able to do, and how it might be done by the CRWG and MLMWG of the SDR Forum. The use cases encompass a wide range of radios (non flexible, flexible, partially SDR, fully SDR), types of users, types of data, types of security requirements, etc. Through these use cases we quickly find the true value of a software defined radio and its flexibility to easily and rapidly respond to changes of waveform and protocol. Specifically we expect the description languages to address: 1) Hardware capabilities of the radios (Frequency bands, modulations, MAC protocols, access authorizations, etiquettes, etc.) 2) Networks available to a user (parameters, restrictions, costs) 3) Security/privacy (constraints, policies) 4) Information types (QoS, Priorities) 5) Local spectrum (spectrum activity, propagation properties)

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IEEE 802.21 has proposed a new standard [2] to facilitate optimization of handover between dissimilar AISs. Originally focused on Wi-Fi to WiMax, IEEE802.21 is currently working to extend it to a more general solution. This standard proposes to use some of the Semantic Web technologies—RDF for data representation and SPARQS for querying—to achieve flexibility of the possible designs. The E2R research in the European Union has developed a Functional Description Language (FDL). FDL is an XML-like language that can be used to describe the capabilities of a radio. By parsing the XML description of the radio, the radio prepares a corresponding set of software objects, and can then schedule the execution of these objects onto corresponding processors. Since this is a non-formal language at this time, the processing of its descriptions needs to be hard coded in a procedural language that the radio would then execute. IEEE P1900.5, now part of SCC 414, is completing a chartering process to work on the development of policy languages. Policy languages are commonly used to manage wired computer network resources such as routers, and thereby manage changes in network topology and performance and to suppress spam traffic and Malware. In much the same way, policy can be distributed in a wireless network to convey the most recent version of regulatory policies regarding frequency bands, power levels, modulations, and spectrum access exchanges required to access the network. This ability is important to the concept of cognitive radio, and the radio’s ability to understand what it is allowed to do to find available spectrum or connectivity, and what it is not allowed to do. For example, a radio is allowed to look for unused spectrum in the 2.4 GHz ISM band, but only up to a specified EIRP within the United States. Different rules and specifics of the frequency band edges apply in other countries. Another interesting example is the FCC 3150 MHz de-

cision to allow communication in a band otherwise reserved for radar, when no radar user is present. So in order to be effective, a radio must not only know the local policy, but must also know which policy is the local policy. It must switch to a new local policy if the radio is moved to a new location. In other words, a radio must be able to interpret a new set of policies once they are made accessible to the radio. MLMWG is working closely with the IEEE to bring forward this important capability. Vita Radio Transport (VRT) is another example of specifying how radio components can communicate in standardized languages within the radio. In this particular case, consider that a radio base station may be remotely located from the antenna, and that the radio waveforms are communicated to both transmit and receive over a fiber-optic cable. At a remote location, the signal is demodulated, converted to speech and the speech is transmitted over another fiber optic to a VoIP network. The communication between

6) Network to subscriber control (policies) 7) Manufacturer (Hardware and software policy) 8) Types of users (Authority, Priority, etc.) 9) Types of data (Async., Isoc., narrow band, broad band, etc.)

Providers

The SDR Forum is working with multiple industry members to identify the requirements of next generation radio systems, to coordinate existing and planned standards, languages and functions that will be needed for next generation radio networks, systems and software components.

MARCH 2008

cover feature [1] M. Cummings, D. Bourse, T. Cooklev, S. Das, M. Kokar, B. Lyles, R. Normoyle, J. Strassner, P. Subrahmanyam, “IEEE 802.21: The Leading edge of a larger Challenge,” submitted to IEEE Communications Magazine, Jan 2008. [2] IEEE P802.21/D9.0 February 2008, Draft Standard for Local and Metropolitan Area Networks: Media Independent Handover Services,” currently under ballot in IEEE standards activities.

the RF front end and the modem back end can be performed using the VITA 49 VRT protocol. The protocol is able to describe sample rate, time stamps, beam-forming, gain, stream identifiers, and any of several sampling formats. While this specification assumes considerable distance between the RF front end and the modem at the base station, it is a proof of principle that standardized languages can be defined for communication between internal radio components, and that by doing so, we can utilize standardized software and standardized interfaces (APIs). The goal of MLMWG is to extend this capability by allowing radios to replace the standardized software with generic software that will be able to interpret and implement any communication streams expressed in a formal language. The overall objective of the MLMWG is to work with all appropriate segments of the communications community to develop languages that meet the broadest cross section of needs

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possible, that are widely adopted, and can evolve to match the evolution of technologies, AISs, regulatory policies and industry needs. In conclusion, important new capabilities are being explored in the application of SDR radios, and the groundwork is now being laid upon which exciting new capabilities that are now in planning will be built. General Dynamics C4 Systems Scottsdale, AZ. (480) 441-3033. [www.gdc4s.com]. Northeastern University Boston, MA. (617) 373-2000. [www.northeastern.edu]. enVia Partners Silicon Valley, CA. (650) 854-4406. [www.envia.com].

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wireless communications antenna technology

Isolated Mode Antenna Technology Need multiple radiation patterns and improved link performance gain in a tiny space? A single antenna with multiple feeds may be the answer. by Frank M. Caimi, Ph.D, Mark Montgomery and Paul Tornatta, SkyCross

iMAT is a new antenna technology that improves antenna gain and receiver sensitivity, significantly enhancing device performance and network capacity in MIMO or related communications systems using multiple antennas. Although it is counterintuitive to think that a single antenna can offer the performance benefits of multiple antennas, the iMAT solution enables a single antenna structure to behave like multiple antennas through the use of multiple feed points. Each feed provides high isolation, low correlation and high per-feed radiation efficiency without the need to design and place multiple antennas in a small space. To obtain the benefits of MIMO or diversity communications systems, antennas typically must be properly configured to take advantage of the independent signal paths that can exist in the communications channel environment. [1] With proper design, one

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antennaâ&#x20AC;&#x2122;s radiation is prevented from traveling into the neighboring antenna and being absorbed by the opposite load circuitry. Typically, a combination of antenna separation and polarization is used to achieve the required signal isolation and independence. However, when the area inside devices is extremely limited, this approach often is not effective in meeting industrial design and performance criteria. As a result, the industry has settled for single antenna solutions or diversity configurations with poorly performing ancillary antennas. So how did SkyCross achieve the seemingly impossible task of designing a single antenna with multiple feeds? SkyCross realized that different modal excitation of a single radiating structure is possible while maintaining isolation between multiple feeds located on the same structure. Therefore, isolation between the feeds is possible. Also, the

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wireless communications

antenna pattern produced by each feed can be sufficiently different so signals transmitted or received between the different feed points are essentially independentâ&#x20AC;&#x201D;a requirement for higher gain diversity systems and highthroughput MIMO communications.

MIMO Metrics and Correlation Coefficient

For a MIMO communications system to fully exploit independence of signal channels, the transmitter and receiver must utilize multiple antennas with prescribed metrics. Metrics for MIMO communications systems have been developed, and many sources exist in the scientific literature. One metric commonly used to measure the potential for an antenna system to produce independent received signals is the antenna pattern correlation coefficient, which is defined by the following equation 1. This equation is specific to a two-antenna system and produces a coefficient whose magnitude is normalized to unity based on electric field components measured in a 3D antenna range. If the antennas produce completely orthogonal patterns, the coefficient magnitude is zero. Conversely, two antennas with the same field component pattern produce a coefficient magnitude equal to one, as shown in Figure

equation 1

figure 1

Correlation = 1 Exactly the same radiation pattern

Ant 1&2

Ant 1

Ant 2

Low Isolation High coupling

Correlation = 0 Completely different radiation patterns

Ideal

Ant 1 Ant 2

High Isolation Low Coupling

1b Ideal

Antennas on the left have coupled near-radiation fields and highly correlated inputs, coupling energy from one into the other. The ideal situation is shown for the antennas at right where little radiation is coupled between antennas, and the correlation coefficient is zero.

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1a. Because MIMO communications systems rely on separate spatio-temporal channels to achieve greater information transfer capacity, it is desirable to establish separate spatial directional response for each antenna to obtain the necessary channel independence. This creates a preference for sufficient pattern independence to produce a correlation coefficient magnitude below a certain threshold. The communications channel itself is also involved in achieving separate or independent spatio-temporal paths, and modifications to Equation 1 for those effects can be included for completeness. [3, 4]

Antenna Coupling or Isolation

The importance of isolation or reduced coupling between multiple feed antennas canâ&#x20AC;&#x2122;t be over emphasized, since energy transmitted from one antenna can be absorbed by neighboring antenna(s). The situation is as shown in Figure 1b. Since iMAT provides sufficiently large isolation between feedpoints, the effect of unwanted coupling between antennas becomes negligible. This advantage can improve the radiation efficiency and therefore Total Radiated Power (TRP) by several dB (a factor of 1.5 or more) compared to similar non-iMAT solutions. Coupling and its effect on antenna efficiency, and ultimately on TRP is illustrated pictorially in Figure 2. Currently, iMAT supports legacy networks and is essential for next-generation protocols that require diversity or MIMO such as HSxPA, WiMAX, 802.11x and LTE. iMAT creates a new way to think about creating a diversity or MIMO system. Ultimately, by using the advantages derived from better performing MIMO systems, end users will be able to realize the full potential of their wireless services and demand faster connections at an increasing rate.

iMAT WiMAX/Wi-Fi Technology Example

To illustrate the above effects and the benefit of the iMAT approach, refer to Figure 3 showing an example of a USB antenna application

Three-Antenna Example for 802.11n

The 802.11n standard specifies a threeantenna solution to provide MIMO capability. Generally, three antennas require sufficient spacing to reduce coupling between elements. The iMAT solution is a single antenna solution shown in Figure 5. The antenna consists of a single radiating structure with separate feed cables.

Efficiency %

antenna-pattern-derived, envelope correlation coefficients, as shown in Figure 4d. Although radiation efficiency is improved, an added benefit is the reduced correlation coefficient achievable with iMAT versus close proximity mulfigure 2 tiple antenna solutions. Correlation coSkyCross iMAT Antenna Technology efficients of less than 0.5-0.7 are desirable Single SkyCross Antenna Conventional Two with iMAT Antenna Approach for MIMO and diversity communications systems. Although d achieving these corre2 1 2 1 lation coefficient valEFF ues is possible with 0 60 Coupling 0 60 multiple antennas -10 50 -10 50 on a given platform, -20 40 Coupling the iMAT solution is -20 40 EFF -30 30 ready-made, requir-30 30 Frequency ing little additional Frequency engineering design. • Low correlation coefficient • High channel correlation (typically <0.2) In addition, for those coefficient (>0.5) • High efficiency • Low Radiation Efficiency antenna systems not • High isolation • Poor isolation able to achieve low correlation values, the benefits of iMAT Illustration of the advantages of the iMAT single antenna over multiple include improved individual antennas showing enhanced efficiency and reduced inter-element coupling. system capacity and data rates. dB

for the 2.4-2.5 GHz band. Shown is a typical USB device consisting of a printed circuit board (PCB) assembly, enclosed in a plastic housing, with USB connector at one end. The space available for the antennas is assumed to be at the opposite end of the PCB. The width of the device is 20 mm and the length and height available for the antennas are 10 mm and 2.5 mm, respectively. The majority of the PCB, between the antennas and the USB connector, is a continuous RF ground. Three different antenna solutions are shown for comparison. The first consists of two meanderline monopoles in the same form-factor as illustrated in Figure 3. The distance from the ground available for the radiator is 10 mm, or λ/12 in free-space; however, the monopoles are made an effective λ/4 length through the use of a meanderline, slow-wave structure. The second case also uses the same meanderline monopoles, but with an added metal shielding strip extending from the PCB ground and between the two monopoles. The third case considers the iMAT solution that includes a similar meanderline loading method for space efficiency, but one that maintains a half-wave equivalent electrical length as a single resonator. The iMAT solution in this case uses a half-wave mode of a specially shaped element where the location of each feed port is carefully configured to provide the desired isolation. A comparison of measured performance for the three solutions is shown in Figure 4. All three approaches yield good impedance match with a VSWR of 2 or better over the band. (Figure 4a). However, the coupling, (S21) for the monopoles is poor—about -4 dB as shown in Figure 4b. The addition of the ground extension between the antennas provides marginal improvement of S21 to about -6 dB. The iMAT solution has considerably better isolation, with S21 values between -10 and -15 dB in the designated band. The S21 value has a direct impact on efficiency due to signal loss to the neighboring antenna and its associated load. Not surprisingly, the iMAT solution shows better efficiency than the other solutions as shown in Figure 4c. Similarly, the iMAT solution produces more diverse antenna patterns as indicated by the graph of

figure 3 USB Connector Antenna volume: 19mm wide, 10mm long, 2.5mm tall

Board Length Dedicated to Antenna: 10mm Example WiMAX USB antenna illustrating small antenna volume of 19 mm wide by 10 mm high, extending away from PCB distal end by 10 mm, and measured correlation coefficient less than 0.4 and efficiency of 68 percent for the same antenna.

MARCH 2008

figure 4

-2

-4

3.5

-6

-8

S21 (dB)

VSWR

Two Monopoles Two Monpoles with Ground Between iMAT Solution

4.5

2.5 2

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(b)

70 60 50 40 30 20 10

Two Monopoles Two Monpoles with Ground Between iMAT Solution

0.9 Envelope Correlation Coefficient

Two Monopoles Two Monpoles with Ground Between iMAT Solution

(a)

Two Monopoles Two Monpoles with Ground Between iMAT Solution

Efficiency (%)

-10

0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1

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2.6 (d)

Comparison of (a) VSWR, (b) S21, (c) Radiation Efficiency and (d) Envelope Correlation Coefficient for three cases: two monopoles, two monopoles with ground plane isolation tab and iMAT antenna showing advantages from the isolated mode methodology.

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wireless communications

cardioid pattern that is essentially different from the pattern produced by the adjacent feed. The net result is a low computed correlation coefficient using Equation 1. Values less than 0.2 are achievable as shown in Figure 7b over the operating band where computations were performed on both the twoand three-dimensional far-field patterns

figure 6 0

S11=S22=S33 S12=S23=S31

-5

S(dB)

The antenna VSWR and isolation characteristics are shown in Figure 6a. VSWR for each feed is below 2:1 (RL<-10 dB), and the isolation between each feed is also nominally -10 dB over the 2.4 to 2.5 GHz band. Unlike most closely spaced antennas, the isolation improves as the frequency is swept through the resonance where the VSWR or return loss is optimized. This is a distinguishing characteristic of the iMAT antenna versus using separate, closely spaced radiators. Shown in Figure 6b is the radiation efficiency for excitation at only one of the feeds, since each is identical due to the symmetric design of the antenna element. With proper tuning the efficiency exceeds 60 percent across the entire ISM band, as shown. Normally, in this frequency regime with 10 mm spacing, the isolation would be much less and the efficiency would be substantially reduced from 60 percent. Another necessary feature of an antenna designed for a MIMO application is a low correlation coefficient. To see how this is achieved, in Figure 7a we show the far-field patterns produced by two of the three elements. Each feed of the antenna produces a

-10

-15

-20

(a) 2.3

2.35

2.4

2.45

2.5

2.55

2.6

Frequency (GHz) 100

figure 5

90 80

â&#x20AC;˘ Uses a combined monopolar structure with three isolated ports.

70 Efficiency (%)

56mm long 10mm diameter

â&#x20AC;˘ Equivalent of three antennas in a single whip-type assembly with three cables.

60 50 40 30 20 10 (b)

0 2.3

2.35

2.4

2.45

2.5

2.55

2.6

Frequency (GHz) Example 802.11n antenna in a single structure and three separate feed connections using iMAT.

a) Return loss and isolation (dB) and b) radiation efficiency versus frequency for the single element iMAT 802.11n antenna.

MARCH 2008

figure 7 Gain 2450 MHz 0

Isotropic Azimuth Only

5 60

300

0 -5 90

270

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330 0.8

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er exploration ether your goalPattern independence and low correlation coefficient needed for MIMO and Diversity applications are benefits of the 802.11n iMAT implementation. a) Azimuthal far-field pattern for different feeds showing independence and b) Envelope correlation coefficient take for either 3D pattern (blue) or azimuthal speak directly pattern (green). ical page, the ght resource. technology, es and products

produced by the antenna. In both cases these are more than sufficient for any diversity or MIMO application. In summary, these examples show that iMAT makes diversity or MIMO systems possible, even in instances where the industry long ago decided such implementation was impossible. companies providing solutions now SkyCross has discovered a way to reap all the exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, mp to a company's technical page, the goal of Get Connected is to put you in touchbenefits with the right resource. Whichever level antennas—mulof of optimized multiple gy, Get Connected will help you connect with the companies and products you aretiple searching for. radiation patterns and improved link onnected performance gain leading to faster data rates, increased network capacity and better reliability—in one small antenna. End users want trendy devices with lots of features that perform well, and they want their devices to hold a charge for weeks. iMAT optimizes antennas to deliver a satisfying user experience. Higher gain and efficiency provide users with better signal strength, even when the nearest tower or base unit is far away. This capability reduces dropped calls, increases range Get Connected with companies mentioned in this article. and enables faster data transfer for high-definiwww.portabledesign.com/getconnected tion video, music, etc.

End of Article

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SkyCross USA Viera, FL. (321) 308-6600. [www.skycross.com].

[1] Parson, S.D., “The Mobile Radio Propagation Channel,” 2nd edition, Wiley, 2000 [2] S. Blanch, J. Romeu, and I. Corbella, “Exact representation of antenna system diversity performance from input parameter description,” Electronics, Letters, 1 May 2003, Volume 39, Issue 9, pp. 705-707. [3] Breit, G. and E. Ozaki, “Phone Level Radiated Test Methodologies for Multi-Mode, MultiBand Systems,” IWPC Transactions “Handset Antenna Technologies for MultiMode, MultiBand, Durham, NC, Jan 2007. [4] Kalliola, et al., “Angular Power Distribution and Mean Effective Gain of Mobile Antennas in Different Propagation Environments,” IEEE Trans, Vehic. Tech. v. 51, no. 5, Sept. 2002.

The Microchip name and logo, and the Microchip logo are registered trademarks of Microchip Technology Incorporated in the USA and in other countries. PICtail is a trademark of Microchip Technology Incorporated in the USA and in other countries. All other trademarks mentioned herein are property of their respective companies. ©2007, Microchip Technology Inc.

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consumer electronics verification management

Verification Management: The Path of Evolution You have gigabytes of verification data—what does it all mean? Verification management is both the next hurdle and the next path in verification evolution. by R ahul V. Shah, Director, ASIC Engineering Division, Sibridge Technologies and Darron May, Product Marketing Manager, Mentor Graphics

It is a universal truth that evolution is a neverending progression. Whether biological or technological, evolution is all about overcoming the hurdles in the path of development. We evolve and cross one hurdle and soon face another, then evolve again. For example, new modes of transportation were invented to resolve the traveltime issue, and now there is too much traffic. Whether it is in the air or on the freeway, this is one of many hurdles we must cross in transportation. The verification industry is no different. “Verification effort increases exponentially with design complexity.” True as this statement is, there is another truth lying behind it. “Design complexity itself grows exponentially with each technological advance.” Exploding verification complexity and HVL-based random environments churn out so much verification data that it is impossible to track. Thus, verification management is both the next hurdle and the

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next path in verification evolution. Soon it will become one of the key factors in achieving first spin silicon success. In simpler times, when verification was predictable, 70 90% of a typical ASIC was developed in-house with the remainder consisting of third-party IP blocks. Verification was accomplished with either purely directed test cases or a semi-random environment using Perl or some other scripting language. The complete verification team sat under one roof, encouraging a much higher flow of information between team members and their manager. Compared to what we face today, the complexity of these designs was much lower. Linking and tracking everything was fairly simple. Simple scripts instilled confidence that regression runs were clean, and wellreviewed, directed test plans and code coverage were good enough to sign off on verification. Technological growth has meant more work

consumer electronics for engineers, but the market is not ready to begrudge more time to tape out. Verification teams must meet the same expectations within the same amount of time on much more complex designs. To generate more data and try more scenarios in less time, new languages and concepts, such as constraint-driven randomization, have been introduced. Similarly, reusability has become an important component in both design and verification development code. However, all these fuel an engine that generates more and more base code, which we want to reuse again and again, and every project gives birth to more reusable code. Additionally, as there is no scarcity of storage or processing power, it is possible to develop complex libraries that keep growing from the daily contributions of reusable base code. This is a good thing, as it leads toward the collection of reusable data, yet it also feeds a system that, if not managed properly, can turn all this data into a giant black box, misleading designers to reuse code that, while presumed to work correctly, can carry bugs into a design without their knowledge. In sum, the issues confronting the verification industry today have less to do with technology and more to do with management (Figure 1). This reflects the character of the current design and verification environment, which features more third-party code, dispersed verification teams, vast volumes of data and the need for automated verification management solutions. Fortunately, there are early indications that the EDA industry has already foreseen this and has started taking steps to help the verification industry evolve through verification management.

Higher Content of Third-Party Code

The current generation of highly complex chips has a much higher number of third-party components compared to earlier generations. This can be design IP (DIP) as well as verifica-

tion IP (VIP). The IP supplier can be from another company or from a different department within a corporation. Although the IP supplier provides documentation, sample test cases and a test environment with their IP, they probably know nothing about your environment. If you know the history of a particular DIP, you can define how much verification will be necessary for that particular design, and verifying silicon-proven DIP at the module level might not be a good utilization of verification time; yet ignoring the integration issues when you combine silicon-proven DIP at the chip level can be a disaster. For example, there may be critical signal requirements for the DIP that need to be

figure 1 Verification Management Third Party Design IP External Reusable Code

Power and Performance Analysis

Offshore Verification Team Mixed Environment With Different Methodologies

Functional Coverage with Random Testcases Third Party Verification IP

Verification Done?

Directed Test Cases for coverage clouser.

Assertions Time Lines Regression Results Bug Tracking

The variety and volume of chip verification components that must be managed to reach verification closure continues to grow beyond the limits of manual methods.

MARCH 2008

consumer electronics

met for it to work properly; such as a specific reset duration or the routing and handling of interrupt lines. These issues might not show up in module-level verification, as the complete environment is stand-alone, but once the DIP is integrated, there will be common logic for the clock, reset and interrupt for the entire chip. Thus, the specific DIP requirements need to be included.

Outsourcing is a cost-cutting measure, especially for verification. Yet, nothing is free. The most common outsourcing concerns are visibility and communication.

er exploration ether your goal speak directly ical page, the ght resource. technology, es and products

Integrating various VIP blocks from the same or different third-party vendors at the chip level can also deliver unwelcome surprises, especially if you do not know the integration issues. Given this complexity, you need to track each of your third-party components to make sure that you are moving in the right direction. The fact that silicon IP is proven just does not cut it any more.

companies providing solutions now

Verification Are Global exploration into products, technologies and companies. Whether your goal is to research the latest datasheetTeams from a company, mp to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. level ofmeasure, espeOutsourcing is aWhichever cost-cutting gy, Get Connected will help you connect with the companies and products you arecially searching for. for verification. Yet, nothing is free. The

onnected

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with companies mentioned in this article. www.portabledesign.com/getconnected

reduced cost of outsourcing verification tasks is offset by the risks of having an outsourcing team thousands of miles away. You expect your outsourcing partner to understand your technology, know your pain and communicate properly. My experience in the ASIC design and verification services industry during the last couple of years has taught me that the most common outsourcing concerns are visibility and communication. If you are a verification manager, you have good reason to be anxious. What if the outsourced verification team wastes your critical schedule time and money making something

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Get Connected with companies mentioned in this article.

you did not ask for, or presents a rosy picture on top of a lot of messy code, which youâ&#x20AC;&#x2122;ll have to manage? Many verification managers get burned by incompetent outsourcing partners. Even if the outsourcing arm does a good job on their block, it is very important that they understand the chip-level integration issues. They must also have clear ideas about the various dependencies and priorities and their impact at the chip level. Most of the time, it is up to the verification manager to manage this task remotely, purely at the mercy of the data shown by the external outsourcing arm.

Verification Data

The invention of Hardware Verification Languages (HVL) is one of the major events in the field of verification. With new randomization approaches, it is practical to run thousands of scenarios with simple base code. This is great, but again not free of cost. The amount of data generated needs to be analyzed before you can make anything meaningful out of it. Instead of writing directed test cases, verification engineers are now moving toward functional coverage and coverage-driven verification. Top-level scenarios or various features of the functional specification can be encapsulated into a well-written coverage plan. Engineers can track the functional coverage report and map the functional coverage plan to gain confidence about the generated stimulus. Creating a functional coverage plan and iterating random test cases will not result in a high degree of confidence, unless the results are properly checked. For example, functional coverage directs the randomizer to generate more and more random scenarios, but it might not check if the outcome of the generated stimulus is a desired response or not. A functional coverage plan that is not properly tied to verification results, including the coverage data and the results of the verification run (in terms of pass or fail), can give false confidenceâ&#x20AC;&#x201D;a serious pitfall for any verification manager. On top of stimulus data, features and requirements must

consumer electronics be tracked with respect to their level of priority or importance; as opposed to finding bugs randomly and, consequently, missing critical bugs due to resource and schedule constraints. Managing the complete verification schedule, tying all the milestones together, keeping track of the progress reports from all the teams and looking at the bigger picture is a huge task. Many companies have a dedicated position, along with a verification manager, solely for tracking their Microsoft project plan.

Verification management is all about collecting and analyzing the right data at the right time.

The Big Picture

It is not that we do not track all of the data; it is just that we track the data in isolation. There are many bug tracking systems, but few automatically relate a particular bug to the delay in a timeline or a hole in the functional coverage plan. Teams still rely on an experienced verification engineer or manager to identify these things and make a manual link. There are timelines, but they do not get linked automatically with regression reports or unexpected releases. Again, someone has to do it manually, and the scope of this task is not only increasing but also becoming more and more complex. Verification management is all about collecting and analyzing the right data at the right time. The EDA industry is beginning to understand these issues, incorporating things

like functional coverage planning that can be automatically linked with the actual coverage results, so you do not have to make the link between the plan and the results manually. A new feature in Questa from Mentor Graphics allows metadata to track verification information, such as the actual engineer working on a particular feature or the verification engine being used. This will definitely help managers track their resources automatically. It also helps evaluate resources in terms of their performance. Steps are being taken to make a standardized database format, for example the Mentor Graphics Unified Coverage Database (UCDB), to store all simulation data. This in itself is a good indication that the EDA vendors did realize the growing data issues early on and, as a result, started taking steps in the right direction. At times I wonder whether verification is following the evolutionary footsteps of the software world. For example, verification engineers adopted object oriented programming much later than their software counterparts, and now we are moving toward standard databases. Maybe now is the time when ASIC verification is becoming complex enough to follow the lead of software development cycles. In the future, there may be some kind of single portal for verification managers that helps them see all the complex relations between timelines, distributed team impacts, bug reports, regression reports, functional coverage data, and so on. Until that becomes a reality, we run the risk of chip failures if we do not focus on verification management as the next, beneficial evolutionary mutation. Sibridge Technologies Fremont, CA. (510) 279-3755. [www.sibridgetech.com]. Mentor Graphics Corporation Wilsonville, OR. (503) 685-7000. [www.mentor.com].

MARCH 2008

portable power adaptive voltage scaling

Processor Energy Savings Through Adaptive Voltage Scaling AVS utilizes closed-loop control and configurable gains to achieve maximum system energy efficiency. by M ark Hartman, Applications Engineering Manager, National Semiconductorâ&#x20AC;&#x2122;s Advanced Power Group

Frequency and voltage scaling are commonplace in portable electronic processors. These devices are providing more and more functionality and demand the highest data processing efficiency. Adaptive Voltage Scaling (AVS) provides the lowest operation voltage for a given processing frequency by utilizing a closedloop approach. The AVS loop regulates processor performance by automatically adjusting the output voltage of the power supply to compensate for process and temperature variation in the processor. In addition, the AVS loop trims out power supply tolerance. When compared to open-loop voltage scaling solutions like Dynamic Voltage Scaling (DVS), AVS uses up to 45% less energy (Figure 1). AVS is a system-level scheme that has components in both the processor and power supply. The Advanced Power Controller (APC) provides the AVS loop control and resides on the processor. The Slave Power Controller

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(SPC) resides on the power supply and interprets commands from the APC. The IP provided in the APC and SPC automatically handle the handshaking involved in frequency and voltage scaling, simplifying system integration in the application. AVS uses a novel closed-loop approach to voltage scaling. The AVS loop is closed around the performance of the processor, eliminating any excess voltage margin. This is in contrast to table-based DVS systems, which must include extra voltage margin. The AVS loop also provides the ultimate kelvin sense connection for the voltage regulator feedback by actually sensing the voltage in the load. This eliminates voltage error due to the ground difference between the power supply and the processor. The power supply tolerance is also trimmed out automatically by the AVS loop, further reducing the margin voltage. All these reductions in the supply voltage yield a dramatic energy savings

The Processing Engine

The key blocks in the system are illustrated in Figure 2. The Advanced Power Controller (APC), licensed by National Semiconductor, provides the AVS loop control and all voltage/ frequency scaling handshaking. The PowerWise Interface (PWI) is an open standard interface. This two-wire, serial interface provides the necessary bandwidth and protocols for AVS. Finally, the Energy Management Unit (EMU) provides the voltage scaling and regulation. The APC handles all aspects of voltage control, and has the ability to actively minimize the power consumption of the host processor. It is realized in synthesizable RTL and has the following functional components: • Hardware Performance Monitor (HPM), • Digital loop filter and • PowerWise Interface (PWI) master module. These elements work together to allow simple and accurate voltage control from the external power supply. The hardware performance monitor (HPM) and digital loop filter are used in AVS to measure the performance of the digital circuit for a given operating performance requirement. The measurement data from the HPM is processed in the digital loop filter and sent to the PWI master to output a voltage request to the power supply. In the closed-loop AVS system, there exists both continuous time (power supply) and discrete time (HPM, discrete compensation) elements. Therefore, sampled-data theory can be used to analyze the system. The HPM outputs a digital word and has as its input both desired performance (clock frequency) and analog voltage. This digital word is a relative measurement of the silicon performance. The sampled-data control loop attempts to regulate this measured output to the reference input, which is also a digital word. The loop stability will be determined by the discrete-time compensation, which can be implemented any number of ways. Power savings is further optimized by partitioning the SoC design into several independent

portable power

voltage domains. For example, the processor may have a core and a hardware accelerator that operate on different scaling voltage domains. The APC 2.0 enables control of multiple AVS domains, commonly needed in state-of-the-art SoC design. The APC 2.0 can accommodate up to 16 slaves over the PWI 2.0.

figure 1 Power and Energy Savings Comparing RUN/IDLE fixed voltage with DVS and AVS Power Fixed Vdd Power DVS Power AVS

100 90 80

Relative Power

in the processor because the dynamic energy usage is proportional to the voltage squared.

F MHz

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Time Comparison of fixed voltage, DVS and AVS energy savings in a processor.

The PWI is an open standard interface where the serial data is transferred through the SCLK and SDAT pins. Data transfer rate up to 15 MHz fulfills the bandwidth needs of closedloop AVS. This bandwidth is necessary and must be guaranteed by the interface so that the loop can operate without too much lag. The last component to the AVS loop is the Energy Management Unit (EMU). The EMU provides stable voltage scaling and regulation to the processor core(s), as well as supporting voltages such as the PLL and logic supplies. To operate in the AVS loop, the EMU must contain the Slave Power Controller (SPC), which interprets the PWI commands. The EMU specifications will affect the AVS loop performance. Just as it is essential for the PWI to provide bandwidth, the EMU must also satisfy bandwidth requirements. AVS not only provides great energy savings, but also simplifies system integration. The AVS loop operates autonomous to the processor and requires no software intervention, except for a few one-time configuration settings. In addiMARCH 2008

portable power

tion, the APC has a voltage monitor that senses when the voltage is settled to the appropriate level for a given target operating frequency, simplifying the handshaking that occurs between voltage and frequency scaling.

figure 2 VIO, VFIXED, etc.

VCPU

Processing Engine CPU

VDSP

HPM APC2

HPM

DSP

PWI 2.0

Energy Management Unit (EMU)

SPC2

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Embedded Memory

Closing the Loop CMU

Memory Controller

The Adaptive Voltage Scaling (AVS) loop and its components.

Frequency and Voltage Scaling

A review of frequency and voltage scaling will aid in understanding the key benefits of AVS. The basic idea is to scale the frequency to the workload demanded of the processor, and in turn scale the voltage to the minimum required to operate at the current frequency. The benefit of doing this is that the dynamic (switching) energy used for a given process (measured in processor clock cycles) is proportional to the square of the supply voltage. For example, 100 clock cycles at 1.2V uses more energy than 100 clock cycles at 0.9V, regardless of the operating frequency. In any frequency/voltage scaling system, there are two transitions that can occur: a rising and falling frequency/voltage scaling event. A rising frequency/voltage scaling event begins with a request for a higher operation frequency by some workload monitor. To support this higher operating frequency, the system must first increase the supply voltage via some 40

PORTABLE DESIGN

method (AVS and DVS are two examples). After the voltage has settled to its new, higher value, the system engages the requested higher frequency operating clock. Likewise, a falling frequency/voltage scaling event begins with a request for a lower operation frequency. However, in this case the supply voltage is already high enough to support the lower frequency, and the operating clock is immediately reduced. Now the system reduces the supply voltage in order to match what the new, lower operating frequency needs. One important difference in a falling frequency/voltage scaling event is that any undershoot in the supply voltage transient must be accounted for as extra margin in the system (Figure 3). Therefore it is desirable to eliminate undershoot. The AVS system achieves accurate and controlled voltage scaling by using a configurable feedback loop with the power supply. By changing the reference, one can change the amount of voltage margin at a particular operating frequency. By changing the loop gain, one can change the slew rate of the voltage scaling events. The AVS loop even distinguishes between rising and falling voltage scaling events so that different gains and thus different slew rates are applied. This allows one to minimize undershoot on a falling transition while minimizing rise time on a rising transition. Recall that minimizing undershoot directly translates to reduced supply voltages and energy usage. This and other means of flexibility are built in to the APC. The AVS loop is a true closed-loop system, and only requires a few parameters to be configured. Just like any feedback system, the loop must be compensated to provide a stable response. The APC has registers that set the gain of the loop. The gain must be set high enough to provide adequate rise and fall times, but low enough to guarantee an overdamped response (no over or undershoots). This is a straightforward exercise since we are only affecting the gain of the loop, and can be done on a bench or through the equations provided in the APC IP documentation. Besides setting the gain of the loop, the reference must also be set. The reference to the AVS

portable power

loop is a digital word that corresponds to the desired processor performance, as measured by the HPM. Essentially, this is like regulating the delay margin in a setup time spec. Since the loop is directly regulating the processor performance, any amount of desired margin can be programmed. This gives flexibility to go from an aggressive, optimal efficiency design to a conservative, less efficient design. By setting the AVS loop gain and reference, the loop will automatically handle voltage scaling.

The voltage monitor enables the system to scale voltage at a faster rate since the exact time the voltage has settled is known. This in turn allows the system to scale between frequencies at a higher rate and increase system efficiency by spending less time at higher voltages. The AVS system offers optimal voltage scaling for a given processor. By virtue of closed-loop performance regulation, the lowest voltage for a given operation condition is always selected. The gain of the loop can be

figure 3 1.2 Overdamped Underdamped

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Undershoots increase voltage margin.

Monitoring Voltage

An important but not often mentioned feature of the APC is the voltage monitor. The voltage monitor greatly simplifies voltage and frequency scaling by providing a â&#x20AC;&#x153;power goodâ&#x20AC;? flag for every voltage scaling event that occurs. This is particularly important when scaling to a higher voltage/frequency. The new, higher frequency cannot be engaged until the voltage rises to support the shorter delay times. The voltage monitor allows the processor to switch to the new, higher clock frequency as soon as the voltage has settled to its new, higher value. This not only allows the system to run faster, but also eliminates the need to characterize the power supply rise and fall times, which vary with component tolerances.

configured for both rising and falling voltage scaling events, further reducing margin needed for undershoots. The voltage monitor contained in the APC further reduces system integration complexity by providing an indicator that the voltage has settled to its new value. This provides an automatic handshaking between voltage scaling and frequency scaling. Through closed-loop control and configurable gains, the maximum system energy efficiency is achieved. National Semiconductor Corporation, Santa Clara, CA. (408) 721-5000. [www.nsc.com].

MARCH 2008

technology focus FPGA prototyping

FPGA Prototyping Speeds Development of Consumer Electronics Only FPGA-based prototypes run fast enough to exercise very complex software applications and operating systems.

by Andy Haines, Senior VP of Marketing, Synplicity

New consumer devices entering the market are powered by sophisticated SoCs containing many embedded processors with hundreds of thousands or even millions of lines of code. A good example is the Apple iPhone, which reportedly contains at least three ARM processors. The increased use of software in these devices provides an effective means for product differentiation because increased software content equates to more features. But, software development for todayâ&#x20AC;&#x2122;s ASICs and SoCs can take up to 18 months, so companies need to start development well in advance of a chip roll-out date. Waiting until after the first silicon is available is no longer an option if a company wants to hit the tight time-to-market windows associated with the consumer electronics industry. So, how can all of this software be thoroughly verified in the SoC when time-to-market is such a critical component in the delivery of the latest consumer electronic products? Increasingly, SoC development teams are turning to FPGA-based prototypes as a solution to verifying and delivering these types of products

PORTABLE DESIGN

in a timely manner. The advantage of using an FPGA prototype is a bug-free ASIC design that is ready in time for the tape-out. Another important benefit of prototyping is that the software embedded into the ASIC or SoC can be integrated with at-speed hardware much earlier in the project so design teams can expedite software development. These key benefits have propelled FPGA-based prototyping to the forefront as the verification methodology best suited for the timely delivery of highly reliable consumer electronic products. FPGA-based prototypes are an ideal verification platform because they can run software at least 10X faster than alternative verification methodologies such as emulation and simulation. While RTL simulation offers a high level of visibility into the design, the low performance associated with running software simulation makes booting a phone chipset, for example, a lengthy process that can take up to 30 days. As a result, this time constraint limits the level and amount of verification that can be performed. Other hardware/software

technology focus

ologies available today. The benefit of FPGA prototyping is multiplied if copies of the FPGA prototype are spread among software labs, or even for customer acceptance trials. The software can be distributed to large numbers of potential users to find many ways to lock up the OS, crash an application or generally do things that the software engineer never imagined. Offthe-shelf, high-performance FPGA boards like the HAPS (High-speed ASIC Prototyping System) from Synplicity, facilitate this proliferation by offering an economic and time-saving prototyping solution. In the end, using more boards helps find more bugs. FPGA-based prototyping equips designers

figure 1 Example

Mobile Phone Boot

1000000

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co-simulation approaches, using higher-level models, can reduce the operating system boot to 10 days—still not very useful. Moreover, these approaches require the development of a complex test bench, which by its very nature is always incomplete. A “C” model simulation offers shorter runtimes, perhaps as quick as 24 hours, but can’t deliver the level of detail ASIC designers typically require. While each of these verification alternatives has a place in the verification flow, only FPGA-based prototypes run fast enough to exercise very complex software applications and operating systems. In addition, optimal system integration and software testing requires simulation speeds above 10 MHz—50 to 100 MHz is optimal. FPGA-based prototypes are the only solution capable of achieving these speeds. This becomes important as many unforeseen software bugs are related to the complexity of integrating operating system, applications and hardware. An FPGA prototype provides a unique environment that allows many extra months of rigorous software testing at this crucial integration stage. For example, an FPGA-based prototype can run millions of test vectors per second, making it a million times faster than traditional software simulation. So, a chip-set designed for a mobile phone application, which previously could take up to a month in a software simulator, takes only 30 seconds to simulate using an FPGA prototype (Figure 1). So, what is the best time to introduce prototyping into the development cycle? Verification of this type is most valuable when performed before the SoC design is signed off. FPGA prototypes are primarily used when the project requires high speed and capacity during the integrations stages. Consider the case where the ideal fix for a software integration problem lies in hardware modification. For example, this might involve the extraction of a cycle-hungry DSP algorithm into a coprocessor or tailored device logic. If the point of discovery of such a requirement occurs after the SoC is already well into tape-out, or maybe even finished and sampled, then it is unlikely that the required change to the device will be considered; whatever the benefit to the end product. Indeed, early FPGA prototyping positively encourages timely design changes, and one growing use of FPGA prototypes is to trial these hardware/software partitioning trade-offs at the very early stages of a project. Hardware-assisted verification is an important addition to the other verification method-

HW/SW Coverification “C” Model Simulation

10000 1000 100 10

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In-System Test

to better handle the emerging challenges associated with increased device and software complexity. However, there is room for improvement to integrate the prototyping hardware and EDA tools more fully. Additionally, much still can be done to make prototypes faster to bring up and easier to change. The ultimate goal is to create an environment where designers can get to work quickly, debug rapidly and make changes without delay. The ability to run “atspeed” will be an indispensable part of SoC verification. Synplicity, Inc., Sunnyvale, CA. (408) 215-6000. [www.synplicity.com].

MARCH 2008

product feature Multiple Signals, Single Antenna iMAT uses a combined monopolar structure with isolated ports to enable MIMO—or a combination of air interfaces—on a single antenna.

by John Donovan, Editor-in-Chief Many next-generation protocols—HSxPA, WiMAX, 802.11x and LTE, among others—require multiple antennas for diversity or MIMO (multiple-in, multiple-out). Using multiple antennas in an RF system yields higher link gain, which in turn yields faster data rates, increased network capacity and better reliability. But on a tiny cell phone PC board, where do you put all these separate antennas in order to minimize antenna coupling, stray radiation and PC real estate? SkyCross has introduced its Isolated Mode Antenna Technology (iMAT), which enables a single device antenna to perform like multiple antennas through the use of multiple feed points. Each feed accesses the antenna as if it consisted of multiple antennas, each with high isolation, low correlation and high perfeed antenna efficiency. The multiple radiation patterns produced by an iMAT antenna have low correlation so they cover different spatial regions to achieve pattern diversity and signal independence. This makes the way the device is “pointed” with respect to towers and base units less crucial. MIMO is tricky to implement in a small space. The 802.11n standard, for example, specifies a three-antenna solution to provide MIMO capability. Generally three antennas require sufficient spacing to reduce coupling between elements. The iMAT antenna uses a combined monopolar structure with three isolated ports, providing the equivalent of three antennas in a single whip-type assembly with three cables. VSWR for each feed is below 2:1 (RL<-10 dB), and the isolation between each

SkyCross iMAT Antenna Technology Single SkyCross Antenna with iMAT

Conventional Two Antenna Approach

-10

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• High channel correlation coefficient (>0.5) • Low Radiation Efficiency • Poor isolation

PORTABLE DESIGN

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• Low correlation coefficient (typically <0.2) • High efficiency • High isolation

feed is also nominally -10 dB over the 2.4 to 2.5 GHz band. With proper tuning the efficiency exceeds 60% across the entire ISM band. Normally, in this frequency range with 10 mm spacing, the isolation would be much less and the efficiency would be substantially reduced below 60%. iMAT enables designers of handsets, PC cards, USB dongles, personal navigation and other wireless electronics to offer MIMO communications, even in applications where such implementation has been considered impossible due to space constraints inside mobile devices. Traditionally, MIMO leverages multiple antennas at both the radio transmitter and receiver to improve communication performance. The single-antenna solution from SkyCross eliminates the need to configure multiple antennas and reduces the number of parts required to build a device. A greater number of efficient, iMAT-equipped devices on a network can improve the capacity and bandwidth of the entire system. iMAT enables operators to optimize network performance without any additional investment in infrastructure. iMAT supports legacy networks and is essential for next-generation protocols such as HSxPA, WiMAX, 802.11x and LTE—all of which require diversity or MIMO. iMAT helps deliver better signal strength to end users, even when the nearest tower or base unit is far away. This reduces dropped calls and enables faster data transfer for high-definition video, music and more. iMAT antennas also exhibit minimal power loss, extending battery life. Portable Design spent some time reviewing antenna and transmission line theory trying to figure out how SkyCross could possibly achieve the performance it claims from a single antenna. SkyCross’ explanation is, “Through the use of induced and coupled signals associated with higher order modes on the antenna structure, the proprietary technology method nulls the coupling between feed points. Each feed produces independent radiation patterns with correspondingly low correlation coefficient.” OK, by studying the current and voltage distribution on a monopole antenna, you can theoretically choose feed points that enable you to feed different signals to the antenna. But maintaining a low VSWR over the entire band would be a neat trick unless you were willing to try to match a non-resonant antenna, which wouldn’t be very efficient. But beam forming from a monopole?! Guess I’ll have to read their patent application. SkyCross USA, Viera, FL. (321) 308-6600. [www.skycross.com].

products for designers TI Takes OMAP in a New Direction

ARM Brings 3D Graphics to Cell Phones

On the opening day of its annual Developer Conference in Dallas, TI announced the availability of four new OMAP processors, based on ARM Cortex-A8 core, providing a combination of laptop-like performance at handheld power levels in a single chip. With more than four times the processing power of today’s 300 MHz ARM9 devices, the superscalar Cortex-A8 core runs up to 600 MHz and is integrated into four new OMAP35x applications processors for a wide range of possible applications, including portable navigation devices, Internet appliances and portable patient monitoring devices. TI has long been one of the largest ARM licensees, but to date it has always used DSPs as coprocessors. According to Gerard Andrews, TI OMAP Marketing Manager, TI is extending its popular OMAP line—highly customized for handset applications—to a broader range of markets, including automotive, consumer, embedded and medical. The integrated, single-chip devices combine photo-realistic graphics and TI’s video DSP technology, providing a combination of integrated multicore processing capabilities in a single-chip. TI’s OMAP35x generation of devices consists of four distinct singlechip processors: the superscalar OMAP3503 running at 1200 DMIPS; the OMAP3515, with an integrated OpenGL ES 2.0 graphics engine for gaming applications; the OMAP3525, which targets embedded applications; and the OMAP3530 for multimedia smart devices. These processors offer a variety of combinations of the Cortex-A8 core, multimedia-rich peripherals, OpenGL ES 2.0-compatible graphics engine, video accelerators and TMS320C64x+ DSP core. TI’s DaVinci software technology for videocentric customers will be available for the highest-performance video in the OMAP35x devices, including the OMAP3525 and OMAP3530. The device architecture leverages a multicore design, so that each core is fully optimized for the tasks it is responsible for to maximize efficiencies. The chips are manufactured using a 65 nanometer lowpower process technology incorporating TI’s SmartReflex technology. The OMAP3503 ($25.95 each in 100u) is available in two packages. The OMAP3503 in 0.4 mm pitch is sampling now. The 0.65 mm pitch version of the OMAP3503 will be available in 2Q08. The other three devices (OMAP3515, OMAP3525 and OMAP3530) will be available with complete development tools in the second half of 2008.

If you’re bored with the simple 2D games on your cell phone, ARM is on your wavelength. ARM has announced the ARM MaliJSR297 software for 3D graphics, the first product to enable developers of Java applications to take advantage of the latest hardware graphics features found in OpenGL ES 2.0 graphics processing units (GPUs), such as the ARM Mali200 GPU. With the established Mali-JSR184 software (formerly Swerve Client), ARM is one of the leading suppliers of middleware that enables 3D graphics to be used in Java games. Ericsson Mobile Platforms are the lead Partner for the Mali-JSR297 software, complementing the Mali200 GPU and ARM graphics middleware in the HSPA-enabled mobile platform, U500, bringing console-class gaming to 2009 feature phones. With the ARM Mali-JSR297 software, game developers now have complete control over the visual appearance of their games, enabling the creation of graphics displays on mobile phones that are similar to those seen on high-end gaming consoles and PCs. The Mali-JSR297 software demonstrates a leap in graphics quality that meets consumer demands for advanced-content entertainment on mobile phones. In order for Java applications to make use of the graphics hardware, handset manufacturers require an efficient software engine that minimizes the number of calculations that Java games need to perform in order to display the graphics. The Mali-JSR297 software builds on ARM’s legacy in graphics solutions and eliminates the risk of integration issues. Furthermore, the new features in the Mali-JSR297 software reside beneath the gaming applications that users download to their phones and open up the full power of OpenGL ES 2.0, the API used in leading games consoles such as the Sony PlayStation 3 and which is supported by the Mali200 GPU. The ARM Mali-JSR297 software empowers developers with the artistic freedom to produce games with more personality, despite limited display size, which previously had not been possible for mobile Java applications. The ARM Mali-JSR297 software will be released immediately following ratification of the JSR297 standard, with pre-release versions available from ARM in Q3 2008. ARM Inc., Sunnyvale, CA. (408) 734 5600. [www.arm.com].

Texas Instruments Inc., Dallas, TX. (800) 336-5236. [www.ti.com].

Low-Power, I/O-Optimized FPGA Family Actel Corporation has introduced IGLOO PLUS, a new family of low-power field-programmable gate arrays (FPGAs) claiming the industry’s best power-, area-, logic- and feature-per-I/O ratios in a programmable device. The new 5 microwatt (5µW) I/O-optimized IGLOO PLUS family also offers up to 64 percent more I/Os than the company’s IGLOO family, and supports independent Schmitt Trigger inputs, hot swapping and Flash*Freeze bus hold. An IGLOO PLUS device delivers 6x better static power consumption, a 50% reduction in dynamic power consumption, a 2x improvement in I/O density and as much as 2.7x the logic density compared with SRAM-based programmable logic devices in a similar package. Ranging from 30,000 to 125,000 gates, the IGLOO Plus family features three 1.2V devices that have been optimized to better meet the needs of I/O-intensive portable applications. In addition to the increase in I/Os per device, the new devices also feature four I/O banks for independent level shifting. Enabling the device to better support varying voltage levels, this is key for bridging between application processors and application-specific standard products (ASSPs), where differing I/O standards and voltages may be utilized. IGLOO PLUS devices support cost- and area-effective level shifting between 1.2-, 1.5-, 1.8-, 2.5- and 3.3V I/O standards and interface translation. Samples of the IGLOO PLUS devices will be available in May with qualified devices available in Q3 2008. Volume pricing starts at $1.95 for the 120I/O AGLP030 device in a CS201 package. Actel Corporation, Mountain View, CA. (650) 318-4200. [www.actel.com].

MARCH 2008

products for designers

Programmable Receiver With “Jam Avoidance” Micrel Inc. has announced that it is launching the world’s first programmable receiver featuring jam avoidance. The MICRF218, which is part of Micrel’s QwikRadio family, is initially targeted at garage door openers and tire pressure monitoring systems. It is the world’s first integrated ASK/OOK receiver with selectable IF bandwidth for 300 to 450 MHz operation. The MICRF218 can “escape” from a jamming source and migrate to an alternate frequency. This is a crucial feature due to recent homeland security measures deploying a new mobile radio system. This new radio system presents the possibility of jamming at 390 MHz, a frequency also commonly used by garage door remote controls. The MICRF218 receiver system can avoid jamming by switching to a quieter frequency. The MICRF218 can accommodate two reference crystals with the use of an external switch. It features a fully integrated IF section with built-in image rejection. The IF section has dual IF bandwidths that are externally selectable. In addition, a wide IF bandwidth can be chosen for backward compatibility with older transmitters that are LC-based. Wide IF bandwidth allows the receiver to capture a signal that slightly deviates from the intended communication frequency, or one can select a narrow IF bandwidth that operates with a crystal-based transmitter to improve selectivity to increase communication distance. There is no sacrifice of performance with either option. For tire pressure monitoring system applications, a -40° to +125°C operating temperature range can cause significant frequency deviation in the transmitter. The MICRF218AYQS in wide IF bandwidth mode can accommodate transmitter signal drift due to temperature changes in the operating environment. The IC is currently available in volume with pricing starting at $1.71 for 10K quantities. Micrel, Inc., San Jose, CA. (408) 944-0800. [www.micrel.com].

Custom Platform Combines Full-Chip, Mixed-Signal, Analysis and Verification for IC Design Magma Design Automation Inc. has announced immediate availability of Titan, the first full-chip mixed-signal design, analysis and verification platform. Unlike other custom design solutions, Titan tightly integrates custom/analog implementation with digital implementation, circuit simulation, transistor-level extraction and verification—providing a quantum leap in efficiency and productivity for analog designers. Because Titan is based on Magma’s unified data model, it works seamlessly with Magma’s Talus digital IC implementation, FineSim Pro circuit simulation, Quartz RC transistor-level extraction and Quartz DRC and Quartz LVS physical verification products. As a result, analog and digital design teams are no longer isolated and can have clear visibility into their counterparts’ design space. In traditional flows, chip finishing—the point at which the digital and analog blocks of a design are placed and routed together—is a time-consuming and manual task. Titan Chip Finishing, the first product to be released on this platform, provides complete and automated chip finishing capabilities. This fast, high-capacity system integrates custom layout with the Talus place-and-route capabilities. It can manipulate the largest designs with ease, automates analog and special net routing through an efficient constraints-based approach and makes all custom layout changes immediately available for physical and timing verification sign-off analysis through a live interface with Talus, Quartz DRC and Quartz LVS. Titan Chip Finishing can implement late engineering change orders (ECOs) that affect both analog and standard-cell components without significantly delaying the schedule. Titan offers an integrated simulation environment using Magma’s circuit simulator, FineSim, along with QuickCap for parasitic extraction. The FineSim interface also allows for full-chip circuit simulation, offering SPICE-level accuracy for the analog portions of the design and fast SPICElevel accuracy for the digital portions of the design. This ensures that the analog/digital interfaces are well simulated and verified before committing the chip to silicon. Magma Design Automation, Inc., Santa Clara, CA. (408) 565-7500. [www.magma-da.com].

HDMI 65 nm IP Solution for Portable Designs MIPS Technologies, Inc. has announced the industry’s first 65 nm IP offerings for HDMI (High-Definition Multimedia Interface). MIPS Technologies’ solution is optimized for HDMI connectivity in low-power, portable transmit applications—including digital still cameras, camcorders, portable media players, game consoles and cell phones, as well as digital home receive applications such as high-definition DTVs and display units, A/V receivers and set-top boxes. HDMI has emerged as the dominant digital interface for a wide array of consumer electronics, representing today’s de facto standard for creating high-bandwidth, streamlined connections between digital devices. MIPS Technologies’ rare expertise in both high-performance analog IP and connectivity IP solutions—such as USB—uniquely positions the company to offer the most comprehensive HDMI IP solution at the most advanced geometries—including a PHY and digital controller for both transmit and receive applications. Through integration onto the SoC, the company’s IP reduces the overall system cost of implementing HDMI in consumer devices and consumes significantly less power than existing stand-alone HDMI interface chips commonly used today. The HDMI transmit IP is optimized for today’s low-power requirements crucial for portable and cell phone applications—supporting data rates of 1.65 Gbits/s per TDMS channel (approximately 5 Gbits/s in total) and video resolutions up to 1080p at 60 Hz. The HDMI transmit IP is also available in a version capable of up to 10.2 Gbits/s for applications demanding higher data rates. The HDMI receive IP integrates configurability options to support data rates up to 10.2 Gbits/s and video resolutions to 1080p at 120 Hz, 1440p and beyond. The HDCP (High-Bandwidth Digital Content Protection) encryption/decryption feature is available as an option. Additionally, the integrated DMA will eliminate the need for a separate audio and/or video interface, allowing autonomous access from the HDMI controller to the audio and video information stored in the SoC system memory. “MIPS Technologies is plugging into a compelling market trend with a HDMI solution that helps address some of today’s real-world digital consumer challenges,” said Rich Wawrzyniak, senior market analyst, ASIC & SoC, Semico Research. “HDMI is poised to proliferate rapidly and the demand to transfer HD video content from portable devices, coupled with the need for longer battery life, mean that small area and low power consumption are not only critical but will drive the integration of HDMI onto the SoC.” MIPS Technologies, Inc., Mountain View, CA. (650) 567-5000. [www.mips.com].

PORTABLE DESIGN

H.264 Scalable Video Codec Stretch Inc. has announced support of the Scalable Video CODEC (SVC) extension to the popular H.264 video compression standard. Commonly referred to as H.264 SVC, this emerging standard enables access to video footage irrespective of network bandwidth or decoding capability of the client device and allows active management of video storage, dramatically reducing system costs. Stretch is initially targeting the video surveillance market, though VP of Marketing Bob Beachler says their scalable codec technology is also suited to portable designs. The dramatic rise in usage of video surveillance coupled with adoption of network-based surveillance solutions has created the demand for the ability to view surveillance footage “anywhere, anytime.” Yet the varying bandwidth of connections, and the differing viewing capabilities, from security centers to cell phones, has required a complex mix of different video encoding standards, resolutions, frame rates and quality levels. H.264 SVC solves this complexity by creating a single encoded video stream that can be “scaled” to support varying levels of resolutions, frame rates and quality levels. This allows the video to adapt to differing bandwidth and viewing capabilities throughout a networked system without resorting to expensive transcoding solutions.

H.264 SVC’s unique “layered” approach to video scaling allows recorded video to be reduced in size and quality over time, but preserving a baseline of video information. In this way, storage requirements can be reduced for older video, and more recent video footage can be maintained at a higher level of quality—important for evidentiary records of recent events. In this way, overall storage costs can be reduced. The Stretch H.264 SVC implementation is applicable to both IP Cameras and Digital Video Recorders (DVRs), and will be integrated as part of its Intelligent Encoder suite of video and audio codecs, which currently supports MJPEG, MPEG4 and H.264. Stretch, Inc., Sunnyvale, CA. (408) 543-2700. [www.stretchinc.com].

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MARCH 3/18/08 2008 3:00:03 47 PM

products for designers

ENERGY STAR-Compliant Power-SPM Module

Visual Enhancement Engine for Mobile Multimedia

Fairchild Semiconductor has introduced a Power-SPM module that increases efficiency in power supplies to meet stringent ENERGY STAR requirements. The Power-SPM FPP06R001 is a highly integrated synchronous rectification module that increases power efficiency, system ruggedness and space efficiency in power supply designs. Incorporating two PowerTrench MOSFETs and a high current gate driver in a compact transfer-molded package, the Power-SPM simplifies board design, eliminates up to 10 discrete components and reduces board space by 20 percent. It provides 10 percent lower on-resistance and 16 percent lower stray inductance compared to discrete solutions, which results in lower thermal dissipation and reduced voltage stress. Its high efficiency is instrumental in helping power supply designs meet next-generation ENERGY STAR requirements. These requirements specify that power supplies must achieve 85 percent or greater efficiency at normal output load conditions. Key advantages of the FPP06R001 include integration of two PowerTrench MOSFETs and a high current gate driver replaces up to 10 discrete components; very compact EPM15 package addresses the low-profile requirements of high-end, ultra-slim SMPS designs; 10 percent lower on-resistance versus comparable discrete solutions; 16 percent lower stray inductance reduces unwanted high voltage spikes, which increases design margin and lowers EMI; and excellent high current driving capability with its built-in buffer IC. The Power-SPM module is part of a comprehensive portfolio of Fairchild’s energy-efficient products. From 1W to 1200W, Fairchild’s solutions meet regulations that are of paramount concern to today’s designers such as ENERGY STAR, PFC requirements, the <1 Watt Initiative and other green regulations. Fairchild recognizes that today’s applications require increased efficiency even as their product features multiply and the product itself shrinks in size. Fairchild continues to develop cutting-edge solutions that integrate functionality and advance packaging technologies to improve efficiency and thermal characteristics while saving board space and reducing component count. The FPP06R001 utilizes lead-free (Pb-free) terminals and has been characterized for moisture sensitivity in accordance with the Pb-free reflow requirements of the joint IPC/JEDEC standard J-STD-020. Samples are available now at $5.00 each.

QuickLogic Corporation has announced the Visual Enhancement Engine (VEE) to enable next-generation multimedia products. The proprietary VEE technology provides high-quality contrast optimization for a wide range of mobile consumer and prosumer devices. It specifically addresses the mobile industry’s need to provide consumers with a TV-quality viewing experience while extending battery life at the same time. In order to deliver a power-efficient, yet flexible solution for the multitude of use cases, application and baseband processors and LCD displays, QuickLogic and Apical Limited partnered to architect and develop the optimal blend of Apical algorithms with QuickLogic’s video enhancement algorithms and patented ViaLink programmable fabric for mobile and portable multimedia products. The core of the VEE technology is based on the proven iridix algorithm licensed from Apical Limited, developed by scientists from the ground up to model the methods that the human eye uses to adapt viewed scenes and images to changing ambient light conditions. By intelligently re-mapping display data to enhance sub-regional variations, VEE improves the viewability of images and video without affecting on-screen graphics, an important use case when consumers have a splitscreen between Web browsing and Mobile TV or YouTube functionality. VEE also allows a mobile device to provide a superior user experience in outdoor and bright ambient light environments without increasing the LCD backlight, thus preserving precious battery life. In indoor or low ambient light conditions, VEE allows the mobile device to operate with a lower LCD backlight while maintaining the visual experience, a common use case when watching movies on a mobile device during an airplane flight. One of the true benefits of the VEE architecture is that its settings can be updated in real time, adapting the algorithm as the ambient lighting conditions change. The Visual Enhancement Engine is available now as a PSB for QuickLogic’s PolarPro family of programmable solution platforms. It is also being integrated as a hard logic implementation in the next generation of the company’s ArcticLink solution platform line, with sampling expected in Q3 2008. QuickLogic Corporation, Sunnyvale, CA. (408) 990-4000. [www.quicklogic.com].

Fairchild Semiconductor Corporation, South Portland, ME. (207) 775-8100. [www.fairchildsemi.com].

SoC Hardware Verification Platform EVE has introduced ZeBu-Personal for system-on-chip (SoC) hardware verification and software development, demonstrating it at DATE. ZeBu-Personal shortens time to tapeout, improves product quality and eliminates costly respins, while accelerating software development ahead of silicon. It leverages the same hardware, models and engineering across the entire design cycle, making it cost-effective for every design team. ZeBu-Personal, based on Virtex5-LX330 field programmable gate arrays (FPGAs) from Xilinx, features a PCI Express card system and offers fully automated front-end compilation and run-time software. It includes comprehensive verification modes for fast testing of hardware, hardware/software integration and embedded software validation. It has interactive hardware debugging capabilities for thorough debugging, and is competitively priced to meet budget constraints. Able to handle design capacity up to five million application-specific integrated circuit (ASIC) logic gates, ZeBu-Personal’s memory capacity extends to two gigabits of DDR2 DRAM and 512 Mbits of SSRAM of memory. A maximum performance of 250 MHz is made possible through a 1 Gbit/s Lowvoltage differential signaling (LVDS) interconnection scheme between FPGAs. ZeBu-Personal incorporates EVE’s patented reconfigurable testbench (RTB) to achieve unmatched performance in co-emulation with any kind of software testbench. In co-emulation at the transaction level, it can reach 60 megahertz (MHz). It is supported by an expanding catalog of synthesizable memory models that includes SDRAM, DDR, DDR2, DDR3, GDDR and Nand/Nor Flash and transactors such as PCIe, USB, Ethernet, LCD developed by EVE for previous ZeBu generations. ZeBu-Personal accommodates the same in-circuit-emulation (ICE) interface and the same speed-bridges supported by ZeBu-UF for protocols such as PCI, PCI-X, video, audio and ICE connectors, including Mictor, ERNI and Samtech. ZeBu-Personal is shipping now, and is priced from $24,000. EVE, San Jose, CA. (408) 881-0440. [www.eve-team.com].

PORTABLE DESIGN

XtremeDSP Development Platform for Low-Cost Video Development Xilinx, Inc. has announced the immediate availability of the XtremeDSP Video Starter Kit – Spartan-3A DSP FPGA Edition, a complete development platform for video applications that require low-cost and highperformance video processing. This new kit gives designers of video applications everything they need to accelerate their development including robust video specific intellectual property (IP), reference designs, XtremeDSP and Xilinx Embedded Processing development tools, and a Spartan-3A DSP FPGA development board with video daughter card. Video processing performance requirements in markets such as surveillance are increasing beyond the capabilities of a traditional DSP processor. FPGAs can be used in these applications as coprocessors to offload performance critical processing operations or as stand-alone video processing engines. The parallel computing nature of the FPGA fabric supports much higher sampling rates and more data throughput than a standard digital signal processor, delivering 3 to 4x the performance along with better computational power efficiency. The fabric of the Spartan-3A DSP family is optimized for DSP and delivers industry-leading cost/performance of 20 billion multiply-accumulates per second (GMACS) for under $30.

The XtremeDSP Video Starter Kit – Spartan-3A DSP FPGA Edition includes video-specific IP including a new Video Frame Buffer Controller (VFBC), three reference designs to help accelerate development, software drivers and hardware interface support for the various I/O interfaces. This IP coupled with Spartan-3A DSP 3400A FPGA development board, cables, VGA camera and FMC-video I/O module supports DVI input, single channel in and out composite, S-video in and out and dual camera interfaces. The kit also comes complete with System Generator for DSP and the Xilinx Embedded Development Kit (EDK). System Generator for DSP enables the use of The Mathworks Simulink and MATLAB modeling environment for FPGA design. The XtremeDSP Video Starter Kit – Spartan3A DSP FPGA Edition is available now for $1,595. Xilinx, San Jose, CA. (408) 559-7778. [www.xilinx.com].

MARCH 2008

second opinion Putting the Touch on Portable Functions Projected-capacitive touch is the only approach that’s capable of supporting the next generation of intuitive human interfaces for portable gear. by John Feland, Technical Marketing Manager, Synaptics Incorporated

t’s no secret that designers of portable electronic products are packing more and more functionality into their gear. Today’s portable phone is seldom just your phone, for example, but may also be your jukebox, your video game player, your Web browsing device and more. The challenge of the new generation of portable products is to make all that functionality accessible in an easy and intuitive way. The foundation for solving that challenge is projected-capacitive touch input technology. Projected-capacitive touch technology is appearing in a range of input configurations on various kinds of handheld products. Besides conventional square-shaped pads, it is also being implemented in small buttons, sliders, bars, strips and circular wheels. In a growing number of laptop computers, especially the consumer-oriented machines, companies such as Gateway and HP are replacing mechanical buttons with capacitive multimedia buttons to play music, fast forward and rewind, control volume, start up a movie, etc. These buttons (as well as other touch input configurations) can be backlit so they’re easier to see, they’re thinner than their mechanical counterparts and they are more conducive to sleek, modern industrial design. These strengths are also being put to good use in other types of projected-capacitive touch input devices for mobile phones and other small devices today, letting OEMs provide a more facile human interface and differentiate products through usability. Exactly what gestures a touch screen responds to and how it responds are, of course, entirely at the discretion of the OEM. In its new Yepp-P2 media player, for example, Samsung opted to support a circular motion for fast scrolling and a flick gesture for moving through a group of photos, one by one. Creative Zen, in turn, provides a very intuitive way to scroll up or down through the screen contents of its Vision MP3 Player by incorporating a vertical scroll bar on which the user moves a finger up or down. And doughnut-shaped input wheels, adopted by several portable device makers, are effective for any knob-like function, such as volume control and zooming in and out. Leveraging the consumer’s experience with jog dials and volume controls, a wheel-shaped touch sensor is extremely effective in scrolling through long lists very quickly. Projected capacitive is just one of a number of touch input technologies available on the market today, but it’s the only approach that’s capable of supporting the next generation of intuitive human interfaces for portable gear. The reason is that—unlike resistive and surface-capacitive 50

PORTABLE DESIGN

technologies, for example—projected capacitive is capable of sensing multiple fingers at the same time, expanding the toolset available to human interface designers. Multiple-finger input gives designers a new degree of freedom in crafting a human interface by linking their applications to novel input modes. Apple Computer’s iPhone is noteworthy for putting dual-finger operation to good use. In its mapping application, for instance, the iPhone operator uses a one-finger touchdown to zoom in, a two-finger touchdown to zoom out. While not a familiar mode of zooming in and out for most of us, this one-two punch is extremely easy to learn and remember. Likewise the pinch gesture of the iPhone’s picture viewer, which makes photos smaller as the gap between the forefinger and thumb grow smaller; unpinch, in turn, makes photos bigger as the thumb/finger gap also grows. With touch sensors, OEMs can tap into a variety of natural or easily learnable gestures to make access to their products’ functionality easier, more sophisticated or more fun. By enabling multi-finger input, projectedcapacitive touch sensors multiply the possibilities. On the downside, of course, the more simultaneous touchdowns that occur, the more processing that’s required to identify them. And imprudently designed multi-finger input modes can confuse the user. And there is a limit to the number of fingers you can actually fit on the screen of a portable device. Portable products sell in two waves. The first wave consists of people who buy the ID of the product, how it looks. The second wave buys the usability of the product, as reports come in from the first-wave buyers. Projected-capacitive touch sensors impact both waves. The surface of a classic candy bar phone looks like a cobblestone street, with mechanical buttons sitting in holes molded into the front of the phone. Touch input sensors, in contrast, integrate into the surface of the gear, enabling sleeker, edgier designs that can even support special lighting effects. As for usability, a well-designed touch interface encourages users to make full use of a product’s functionality (which makes the phone companies happy because it drives their revenue per user). We have yet to even scratch the surface of what’s possible with multi-finger input. Synaptics Inc., Santa Clara, CA. (408) 454-5100. [www.synaptics.com].

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ceo interview Carl Schlachte

ARC International

many transistors you can put down on a piece of silicon, the tools that you’re using, the architecture of processor, etc., etc. – those are all important, but they’re not ultimately what the user cares about. They have to serve an end purpose, which is what really matters.

Portable Design: You’ve chosen to focus on multimedia subsystems, which seems a bit afield from your core expertise. How have you gone about acquiring that expertise?

Consumer electronics have been both a boon and a bane for the semiconductor industry. The boon is the profits to be made if you can grab a socket in a device that ships in the hundreds of millions of units. The bane is the low margins, short timelines and fluctuating feature sets that require a lot of flexibility on the part of designers—if not an outright crystal ball. A large part of the solution is using configurable processors in the SoCs that take up much of a cell phone’s real estate. Designers can roll their own processors optimized for the needs of a particular application instead of designing around the limitations of standard IP products. ARC International pioneered configurable processors, which today are at the core of their multimedia subsystem products. Portable Design talked recently with ARC’s President and CEO Carl Schlachte about his take on the technology, the company and the industry in general.

Portable Design: You’ve said that developers need to focus on portability. Why is that important?

The constraints for developing a battery-powered device are inherently challenging, and by addressing them you wind up with a better design. The choices and trade-offs that you make in favoring lowpower are ultimately the kinds of things that will make you successful in the consumer electronics market, even if you are not making a battery-powered device. It’s all about die size, it’s all about power dissipation, can you put it in a cheaper package, and so on. You just end up with a better design.

Portable Design: You claim that the semiconductor industry hasn’t caught up with what’s happening in the market. What do you mean by that?

Semiconductor companies tend to get fixated on their own technology and not on what the user experience actually is. So an insistence on how

PORTABLE DESIGN

There are a couple of really good reasons for being in multimedia in the first place. Our whole multimedia strategy is built around the dynamics in the marketplace, where there’s been volume production of devices; and we have a royalty-based model which requires that we focus on volume. We started off with a very good configurable processor design. The issue became: If you want to get into the multimedia space, what facilities do you have to have on board to take that to the next level? We have design tools that are specifically suited for developing a configurable microprocessor and programming it, and that really lead to multimedia. We looked around the market to see what other technology was available, and we made some very good acquisitions on that basis.

Portable Design: With your move into subsystems, you’re moving from being a semiconductor company to being a systems company. What are you doing to meet that challenge?

Becoming more of a systems company is not an easy thing to do. Part of the answer is that we are staffing up in those areas to make us more system aware, through hiring, acquisitions and investments. Our relative R&D investment is currently higher than our peers for those reasons.

Portable Design: Are you looking more toward developing IP in-house, or rather relying on an ecosystem like ARM’s?

We already have an ecosystem in place; we work with partners, and we’ll continue to do that. Our belief is that there are certain key areas of technology that we need to control on behalf of our customer in order to maintain the user experience – and those are the areas in which we’ve been making acquisitions.

Portable Design: ARC was certainly a pioneer in configurable processors, though you’re hardly without competition now. Just how do you position ARC vs. your competitors in that space—in particular ARM, who is dominant in the portable designs you seem to be targeting?

To be fair, I don’t think we’re actually targeting ARM. If an SoC designer has chosen an ARM host, there’s nothing that says he can’t use one of our multimedia accelerators next to it in order to accomplish the job. We’re pioneers in configurability – we are the ones who initially developed the technology, then other companies moved into the space. Our attitude has been, “Configurability is great, but what is its end purpose?” It’s really about personalization. It’s about the ability of our end customer to have the design that they want. That’s why moving into multimedia and becoming more of a systems company was really important.

Portable Design: While a proponent of configurability, you claim that configurability at the box level doesn’t matter. Why is that?

Configurability – the ability to change things via software – is important; but the ability to change the underlying design – the physical portion of the semiconductor – I don’t think that’s as important to the manufacturers, by virtue of the fact that it’s a specialized process. Generally when you want to change something, the piece of silicon is already committed to a board in a box, so the entire process is difficult and doesn’t actually help your return on investment. Also, including the facilities in the semiconductor in order to make it reconfigurable tends to be prohibitively expensive, and that takes you out of the market.

Portable Design: A lot of the arguments that you’ve made for configurability can be extended slightly to include programmability. Once you’ve configured a processor and it’s burned in the silicon, you can no longer configure it. Do you see applications that might require programmability in addition to configurability?

Portable Design: Back to the system level, what can you tell us about “Energy PRO”?

Portability is where the industry is going, so you’ve really got to offer support for that in the architecture. To do that we’ve created a technology called Energy PRO, which allows you to control energy consumption from both the hardware and software sides. Software can take a look at things in a system and adjust the hardware for the appropriate energy level. We’re doing low-power design techniques to make sure we wind up with the best power profile. We also work with partners like Cadence to work on the entire low-power design flow holistically.

Portable Design: How can we expect to see ARC change over the next few years?

Probably along the same path that we’re on right now. We’ll continue to concentrate on area and power efficiency and how it pertains to what we are doing in system-level design. What are we doing and multimedia as it relates to audio and video? How are we providing technologies that allow our customers to differentiate on that basis? A couple of years from now you’ll see ARC as more of a consumer systems company in terms of the semiconductor and intellectual property we are providing and less of a microprocessor company, although that’s at the heart of everything we do. ARC International San Jose, CA (408) 437-3400 [www.arc.com]

We pay pretty close attention to what customers are asking for, and we haven’t gotten a lot of demand for it. Everyone seems to like the idea, but the practical implementation tends to be a bit difficult. When our customers look at the area and size penalties in volume production, they tend to not want to pay those penalties to get the extra flexibility.

Portable Design: Looking at the block diagrams for your cores, you use quite a number of hardware accelerators, which are surely finely tuned. Doesn’t this argue against the concept of programming in software?

It does. In essence you have to balance the two competing needs. If we look at an algorithm and decide that it’s better to have an entropy encode/decode engine and assist that, we would add that in. The thing that we’ve erred on in each of these cases is the degree of programmability associated with that, so we’ve retained configurability the entire way through. You can add or delete multiples, those sorts of things, to get the performance and area that you need.

MARCH 2008

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