Portable Design - November 2008

SPECIAL EDITION

LOW-POWER

Design Techniques wireless communications: A Deeper Look At The "+" of HSPA+ Maximizing Range in Mobile Handsets product feature: Synopsys Custom Designer AMS

NEW Section product focus: Power Management ICs

October-November 2008

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An RTC Group Publication

CEO Interview: Warren East, ARM

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contents

departments

PRODUCT FOCUS

editorial letter 5 industry news 6

NEW SECTION analyize this 10 analyze this 10 analysts’ pages 12

NEW SECTION product focus 32 product focus 46 products for designers 50 product feature 54

46 >92% peak efficiency in industry’s smallest package

SPECIAL EDITION Cover Features

Low-Power Design Techniques Consumer Technology and Low-Power 16 Design: Inseparable Forces Open UPF/IEEEp1801 20 Standard Roadmap

47 lighting management IC for Smart Phones and PMPs

Reducing Power in Video-Intensive 26 Portable Applications Optimize Power Consumption in Portable 30 Electronics Using Integrated Load Switches Non-Volatile Memory Options in 34 Portable Designs

wireless communications

48 PMICs for OMAP35x processor-based designs

aximize Range in Mobile Handsets 38 M with CMOS-on-Sapphire RF Switches

Dylan J. Kelly, Peregrine Semiconductor Corporation

Not Just a Mathematical Symbol: A 42 Deeper Look at the “+” of HSPA+

Ziad Asghar, Texas Instruments

ceo interview

Warren East 56

49 Step-Down Regulators target portable designs

ARM November 2008

3

team editorial team

Editorial Director Editor-in-Chief Managing Editor Copy Editor

Creative Director Art Director Graphic Designer Director of Web Development Web Developer

Warren Andrews, warrena@rtcgroup.com John Donovan, johnd@rtcgroup.com Marina Tringali, marinat@rtcgroup.com Rochelle Cohn

art and media team Jason Van Dorn, jasonv@rtcgroup.com Kirsten T. Wyatt, kirstenw@rtcgroup.com Christopher Saucier, chriss@rtcgroup.com Marke Hallowell, markeh@rtcgroup.com James Wagner, jamesw@rtcgroup.com

management team

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Circulation

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executive management John Reardon, johnr@rtcgroup.com Cindy Hickson, cindyh@rtcgroup.com Cindy Muir, cindym@rtcgroup.com Aaron Foellmi, aaronf@rtcgroup.com Jason Van Dorn, jasonv@rtcgroup.com

portable design advisory council Ravi Ambatipudi, National Semiconductor Dave Heacock, Texas Instruments Kazuyoshi Yamada, NEC America

corporate office The RTC Group 905 Calle Amanecer, Suite 250 San Clemente, CA 92673 Phone 949.226.2000 Fax 949.226.2050 www.rtcgroup.com

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4

PORTABLE DESIGN

I Hear You

The decision was hard fought, with Sergey Brin, Larry Page and Bill Gates personally lobbying the commissioners on the importance of opening up these channels, which they claimed would spur both competition and innovation.

AT&T and Verizon—who paid heavily for C Block spectrum in the FCC’s recent auction— were against the idea, though their obvious economic self-interest didn’t contribute to their credibility.

The strongest opposition came from the entertainment industry, who feared that unlicensed devices on these frequencies would interfere with wireless microphones. Even Dolly Parton weighed in, asking the commissioners to delay the hearing so she could comment further. Dolly Parton appearing before the buttoned-down FCC would certainly have caused enough of a media circus to break into the evening news— and derail the proceedings. In the end, Chairman Martin ruled that the public interest was best served by opening up the white spaces for unlicensed portable devices.

editorial letter

A

Almost lost in all the election media frenzy was the FCC’s approval on November 4 of a plan to open the white spaces between broadcast TV channels to cell phones, laptops and a wide range of portable consumer electronics devices. These frequencies between 54-698 MHz are highly prized, as they can easily penetrate buildings and other obstructions; they also enable far faster communication than you can get over Wi-Fi, which operates at 2.4 and 5 GHz. “White spaces are the blank pages on which we write our broadband future,” said Democratic Commissioner Jonathan Adelstein during the meeting. “Let’s hope this is not just Wi-Fi on steroids but Wi-Fi on amphetamines as well because it will be that fast.”

How fast is that? Cable modems—the fastest it gets right now—can theoretically deliver 20 Mbit/s downloads, though mine typically tops out at 5 Mbits/s when no one else is online and the wind is right. While I haven’t seen any test results, some sources are predicting multichannel MIMO white-space modems in a few years delivering 40 Mbits/s—an 8x improvement over the best you can hope for currently. I don’t know about amphetamines, but that’s definitely north of espresso.

Trust and Verify

Low-power, unlicensed wireless devices are covered by Part 15 of Title 47 of the Code of Federal Regulations. Under Part 15, compliance is a self-approval process where the

Wi-Fi on Amphetamines john donovan, editor-in-chief

manufacturer performs the necessary tests and determines that the device complies with the rules. The FCC makes the rules and trusts the manufacturer to verify compliance. Every lowpower wireless device you own has a Part 15 compliance stamp on it somewhere.

In this case the FCC went one step further, conducting extensive device tests to verify that in fact unlicensed devices could co-exist in the white spaces without causing interference to legacy users. “Normally, the Commission adopts prospective rules about interference and then certifies devices to ensure they are in compliance,” Martin said in a statement. “Here, we took the extraordinary step of first conducting this extensive interference testing in order to prove the concept that white space devices could be safely deployed.”

Hang in There

While the FCC ruling has immediate effect, the white spaces won’t open up until next February, when all U.S. analog TV signals go off the air. It will then take some time for consumer electronics manufacturers to get their new wireless devices certified and into production, and it will take longer to get the wireless infrastructure in place.

So “Wi-Fi on amphetamines” isn’t right around the corner, but it is coming soon. It will be worth the wait.

November 2008

5

news Long Time Coming

exploration er your goal eak directly page, the resource. hnology, and products

Freescale Exits Handset Business, Banks on Basestations

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Faced with increasing competition and flagging sales, Freescale Semiconductor is exiting the mobile handset chip business.

Freescale CEO Rich Beyer announced that mpanies providing solutions now the company is negotiating with interested oration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, expectsWhichever to reach to a company's technical page, the goal of Get Connected is to put you in touchparties with the and right resource. levela ofdecision in the Get Connected will help you connect with the companies and products you arenext searching for. 90 days.

60 to nected Following the announcement, Freescale took a $3.4 billion non-cash charge against its thirdquarter earnings, in response to its impending exit from the cell phone chip market and a weakening global economy. The company then announced that it intends to cut its worldwide work force by at least 10% over the next year, including about 2,400 jobs worldwide. The job cuts don’t include hundreds of engineers involved in designing cell phone products. Freescale said it expects to spend about $175 million Get Connected on restructuring over the next year and cut anwith companies mentioned in this article. www.portabledesign.com/getconnected nual costs by $400 million.

End of Article

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PORTABLE DESIGN

When Freescale was spun off from Motorola four years ago, job number one was to find another large customer for its cell phone chips, which it has been unable to do. All of the big five cell phone makers— Nokia, Samsung, Motorola, LG and Sony Ericsson—have existing relationships with chipset makers, and Motorola’s rivals were reluctant to partner with a company so closely tied to it.

In addition, although Motorola gave Freescale the right to sell chips it developed for its phones to other manufacturers, it didn’t allow the company to sell the software needed to make them work efficiently.

Earlier this year, Motorola finally allowed Freescale to sell such software, but by then it didn’t matter.

The final straw was Motorola’s recent announcement that it intends to source its next-generation handset chips from multiple suppliers. Freescale was able to wangle a golden handshake at the end of their exclusive contract, but the handwriting was clearly on the wall.

The lack of a strong partnership in the cell phone market is lethal, considering the amount of R&D investment needed to stay in a very fast-moving game. Recently STMicroelectronics and NXP Semiconductor—both quite strong companies—formed a wireless handset IC joint venture in order to pool R&D and manufacturing resources.

Even they are being forced to retrench in the face of difficult macroeconomic conditions.

The cell phone market is one where you have to either scale up or get out. Freescale made the prudent decision to do the latter.

The squeeze will now be on. The cellular business currently accounts for about 20% of Freescale’s revenue. While the company is reworking is cost structure through layoffs and selling its six-inch Scottish fab, it still needs to find a replacement for the cellular cash flow.

with Nokia. “We’ve got a well run custom business anchored with a great, solid relationship,” Templeton said. “We are going to continue to operate that and operate it well.”

Meanwhile, TI is pushing forward in the portable arena, recently introducing the C6745 DSP, C6747 DSP and OMAP-L137 low-power, floating-point applications processors. Focusing on high-performance, low-power processing, TI is doubling down on OMAP’s strength in the handset market.

They’re basically putting their money where your mouth is.

John Donovan, Editor-in-Chief

Basestations to the Rescue

Beyer says he intends to increase investment in other core areas including multicore platforms, media application processors and automotive chipsets. The latter has been a big moneymaker for Freescale, though that market is currently down and liable to stay that way for a while.

Freescale recently announced the MSC8156, a wireless basestation DSP boasting 6 GHz of performance. The new chip features six StarCore SC3850 cores running at 1 GHz each, giving the chip 48 GMACs DSP performance. The MSC8156 can handle numerous next-generation standards including WiMAX, LTE and TD-SCDMA. According to reports, the new Freescale chip outperforms Texas Instruments’ widely used TCI6487 at the same price point. Since TI recently announced that it is selling its merchant baseband semiconductor business unit, this is a good time for Freescale to up the ante in the baseband market. According to Semico research, revenue for baseband DSPs is up 21.5% this year compared to 6.5% for the overall DSP market. Freescale will find it difficult to displace TI, the market leader in baseband chipsets, but in a market where performance is everything, they have a good shot at it.

John Donovan, Editor-in-Chief Freescale Semiconductor, Austin, TX. (800) 521-6274. [www.freescale.com].

TI Exits Merchant Baseband Business, Banks on Handsets

Texas Instruments has announced that it is selling its merchant baseband semiconductor business, but will continue to support its custom baseband customers. The company will begin reducing cellular baseband operations immediately and take a restructuring charge of approximately $110 million across the next three quarters. It intends to cut expenses in the wireless business by one third more about $200 million per year, especially

Texas Instruments Inc., Dallas, TX. (800) 336-5236. [www.ti.com].

Microchip, ON Semiconductor Bid for Atmel in its cellular baseband operation. TI CEO Rich Templeton said the company will focus its remaining wireless investments on OMAP applications processors for smart phones.

TI is currently the second largest supplier of the merchant baseband chips behind Qualcomm, according to Will Strauss of Forward Concepts Inc.; about three quarters of its wireless revenue comes from baseband chips. According to Strauss, TI is hanging on to its higher-margin 3G chips and unloading lower-margin ones that go into 2G and 2.5G phones.

TI’s major customer for its custom baseband chipsets is Nokia, which has indicated that it will also start buying such chips from STMicroelectronics, though this move probably won’t impact TI’s cash flow in the near future. TI’s situation here is not unlike that faced by Freescale, who saw its sole customer—Motorola—also decide to start buying from STMicroelectronics. TI, however, is in a much less tenuous position, having a broader product line and wider customer base. It also feels secure in its relationship

Following the demise of Cadence’s bid for Mentor Graphics, you might think that daytime drama was dead in Tech World. You’d be wrong, of course.

On October 2 Microchip and ON Semiconductor—having been turned down privately— launched a public and hostile $2.3 billion takeover bid for Atmel semiconductor. At five dollars cash per share, the offer represents a 54% premium over Atmel’s share price on the date of the offer.

Under the proposed deal, Microchip would acquire Atmel’s microcontroller architecture business, adding its 8- and 32-bit products to its own product line. Microchip would also take over Atmel’s ASIC division, which it hopes to sell prior to the acquisition using the proceeds from that sale to help fund the takeover. Microchip CEO Steve Sunday indicated in interviews that he already has an interested buyer.

For its part, ON Semiconductor would acquire Atmel’s nonvolatile memory division along with its RF and automotive units. ON Semiconductor plans to use $410 million in cash and a credit facility to finance the takeover. Microchip’s Sanghi claims his company currently has $1.5 billion in cash and so won’t November 2008

7

news

exploration er your goal eak directly page, the resource. hnology, and products

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mpanies providing solutions now

need any access to the credit markets. Atmel, for its part, is cash poor, posted a $4.7 million loss in the last quarter, and its stock price is down 46% year on year. It’s been struggling for years to break out in the competitive microcontroller market, but it’s still struggling. All of that makes it a prime takeover target.

Considering that its suitors intend to dismember Atmel, it’s not surprising that its initial response was “buzz off.” But considering the trajectory of its stock and the fact that we’re at the beginning of what may be a historic global recession, just saying no to $2.3 billion in cash might not be such a bright idea.

Stay tuned for more exciting developments.

John Donovan, Editor-in-Chief

oration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, Technology Inc., Chandler, AZ. to a company's technical page, the goal of Get Connected is to put you in touchMicrochip with the right resource. Whichever level of 792-7200.

Get Connected will help you connect with the companies and products you are(480) searching for.

[www.microchip.com].

nected

ON Semiconductor, Phoenix, AZ. (602) 244 6600. [www.onsemi.com].

End of Article Get Connected

with companies mentioned in this article. www.portabledesign.com/getconnected

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PORTABLE DESIGN

Atmel Corporation, San Jose, CA. (408) 441-0311. [www.atmel.com].

Intersil Acquires Kenet

Intersil Corporation has signed a definitive agreement to acquire Kenet, Incorporated, a privately held, fabless semiconductor company with leading technology in the design and man-

ufacture of high-speed, extremely low-power data converters.

Kenet’s innovative FemtoCharge CMOS technology yields high performance and ultralow-power analog-to-digital converters in an extremely small die area. The size and power advantages of Kenet’s data converters enable increased functionality in a variety of industrial and communications products such as portable digital oscilloscopes and software defined radios.

The boards of directors of both companies have unanimously approved the merger. The acquisition adds an additional two million dollars of operating expenses per quarter, and is expected to become accretive in 2010. Intersil may record a one-time charge to operating income for purchased in-process research and de-

velopment expenses when the closing occurs.

The amount of that charge, if any, has not yet been determined. Closing of the merger is expected to be completed within days. Signal Hill acted as advisors for Kenet on the transaction.

Intersil Corporation, Milpitas, CA. (408) 432-8888. [www.intersil.com].

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©2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners.

analyze this

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Cellular handsets play the roles of MP3 player, TV, radio, navigator, camera, Web browser, PDA and, yes, telephone. Feature creep provides opportunities for the system designer, but semiconductor integration takes them away at the same time.

The hottest new feature in handsets is GPS to enable navigation features and location-based services. Implementation options for GPS vary.

One option is to add a GPS receiver to an existing design. Receivers such as the uN3010 from Atheros and PMP2525 Hammerhead II from Infineon integrate easily into mobile designs.

Coming in BGA or CSP packages and integrat-

Calling All Designers: Time to Get Creative with Cellular Functionality joseph byrne, the linley group

ing digital and RF functions, the receivers connect to a host pro­cessor using a serial port and to an antenna via an external SAW filter.

But the stand-alone GPS chip is going away, as suppliers of Bluetooth chips integrate the GPS function in their offerings. The NavLink 6.0 from Texas Instruments is one example of a Bluetooth-GPS combination chip, and others will follow. Alternatively, the GPS function can be integrated with the cellular baseband pro­ cessor. The SH-Mobile G series of baseband chips for the Japanese market integrates the GPS baseband. Qualcomm has long integrated GPS into its cellular chip set as well, handling the digital functions in the baseband pro­cessor and integrating the RF transceiver with the cellular transceiver. System designers should focus on Bluetooth-GPS combination chips for their projects because they are economical and deliver good performance.

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PORTABLE DESIGN

FM radio is another function proving popular in certain markets. Oddly, FM receivers are better received where low-cost phones are comparatively popular, while FM transmitters are better received where high-end phones sell comparatively well. FM transmitters enable stored music to be played back from the handset over a nearby radio, such as in a car.

Again, the options are to use a stand-alone chip, a combo chip, or a baseband pro­cessor that integrates the function. None of the latter ship yet, but a few such products will ship in 2009. Infineon has built an FM receiver into its X-Gold 113 and 213 cellular chips, which target low-cost GSM and EDGE handsets. For 3G phones, Broadcom integrates an FM transceiver into its BCM21551 all-in-one cellular chip, and FM is increasingly available in combination with Bluetooth transceivers.

Designers targeting low-cost phones will find Infineon’s baseband pro­cessors among the best offerings in the market, and their integrated FM a unique differentiator. Designers of feature phones and smartphones will find several options for Bluetooth chips integrating FM from the leading Bluetooth vendors, such as Texas Instruments, Broadcom and CSR. Core cellular technology is changing as well.

Low-cost GSM and EDGE chip sets now commonly integrate the baseband pro­cessor and RF transceiver in a single chip. Some also integrate the power-management unit. The result is that hardware designers have little work to do to complete a handset design. Major additional components required include memories and power amplifiers. Companies with such “single-chip” designs include Broadcom, Infineon, ST (via its acquisition of NXP, which had acquired the design from Silicon Laboratories) and TI. MediaTek, the third largest supplier of cellular chip sets, is also readying a single-chip design.

Designs of 3G phones are more complex.

Figure 1 shows how the block diagram for a 3G smartphone is far more complex than that of a low-cost 2G phone. The latest feature for 3G phones is diversity reception. In what is known as a Type III advanced receiver, two receivers operate simultaneously. The baseband pro­cessor performs maximal-ratio combining

analyze this (MRC) to blend the two signals to create a stronger whole. A key implication of diversity reception is that it requires a second receive chain. Some early designs use a second receiver chip, but transceiver suppliers now offer RF transceivers that integrate the second receive path.

Diversity reception is mostly used to enable 3G downstream rates of 7.2 Mbits/s and faster.

It is a key step toward MIMO (multiple-input, multiple-output) receivers. Best known as a key technology in 802.11n wireless LAN, MIMO is also specified in the HSPA+ 3G standard and 4G standards, such as LTE and WiMax. In MIMO, the transmitter simultaneously outputs two or more separate data streams on the same channel, and the receiver pieces them together.

A mobile device is likely to only support MIMO on the receive path, because upstream data rates tend to be lower than downstream rates, and to conserve power. From a systemdesign perspective, little additional hardware is required compared to the diversity receiver because the baseband processor handles the key decoding function. The receive path, however, must be “clean,” minimizing noise and maximizing linearity, for the MIMO signal processing to work.

The base station, where MIMO transmission is implemented, nearly doubles in complexity, however. Not only must there be more signal processing, but a separate transmission path— including expensive power amplifiers and bulky antennas—is required for each stream. This additional complexity is one inhibitor to the roll out of HSPA+ and 4G technologies.

By offering integrated products, cellular-chip suppliers are absorbing much of what had been in a system designer’s purview. The cellularchip suppliers, however, have an important disadvantage: time. It may take one or two years for them to complete design of a super chip. Their OEM customer and the cellular operator may take another year or more to qualify the design for mass production.

The opportunity for the system designer is to take a design already in production and enhance it with new functions, exploiting the window of time between when operators and end customers first find value in the function and when the

cellular-chip supplier can absorb it into his own design. The window is closing on GPS, but it may soon open on near-field communications (NFC), a type of link that enables electronicwallet and other functions dependent on proximity for security. Already gaining popularity in Japan, NFC could gain traction worldwide if supported by retailers.

Creative designers, alternatively, can try to turn the tables. Instead of focusing on what functions can be added to the handset, think instead of how cellular connectivity can enhance other systems. One example is remote meter reading, which uses the cellular network to transmit the meters’ output. The Amazon Kindle exemplifies another example: turn around a failed product concept (e.g., an e-book reader) by tying it to wireless technology to enable a new usage model. Chip designers can envisage such applications, but until the market is proven, they cannot afford to develop chips specifically to support the application. System designers, however, have more flexibility, provided they apply their imagination and creativity.

Joseph Byrne is a senior analyst at The Linley Group. With more than 15 years of industry experience, he is one of the industry’s leading analysts covering the semiconductor market. He has published numerous reports analyzing various segments of the industry and is the coauthor of A Guide to Wireless Handset Processors and A Guide to High-Speed Embedded Processors. Before joining The Linley Group, Joe served as a principal analyst for semiconductors at Gartner Research and held consulting positions with Gartner, Deloitte Consulting and smaller firms in the U.S. and Europe. Joe began his career as a microprocessor designer for SMOS Systems, where he honed his technical skills as a principal engineer. He holds a bachelor of science degree in electrical engineering and computer science from Duke University and an MBA from the University of Michigan.

Generic 3G Feature Phone

LCD SLOT

LCD Touchscreen

SDRAM 1 4 7 #

2 5 8

Baseband Processor

3

Flash

6 9

BT/GPS/ FM/WLAN

0

I2C, I2S, USB

DigRF RF Transceiver

Companion Chip

Battery

USB

PA

Parallel

Sensor

FEM

Generic 3G Feature Phone

Generic ULC Phone LCD 1 4 7 #

2 5 8

3 6

Baseband Processor

SDRAM

9

Flash

0

PMU

RF Xcvr

PA

Battery

FEM

Generic ULC Phone

The Linley Group, Mountain View, CA. (408) 281-1947. [www.linleygroup.com].

November 2008

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analysts’ pages With UMB Left Behind, LTE and WiMAX Battle for 4G Supremacy

In 2008, the road to wireless 4G cleared a bit, with ultra-mobile broadband (UMB) left publicly by the roadside, narrowing the path to two technologies: LTE and WiMAX, reports In-Stat. Both 4G technologies, meaning those technologies that are expected to meet the requirements of IMT-Advanced, are far from being commercially deployed, the

• Mobile WiMAX and LTE will represent only a miniscule portion of total 2G/3G/4G cellular subscriptions in 2013, with GSM/ EDGE/GPRS expected to account for more than 55 percent of the total 4.8 billion subscriptions.

• HSPA may turn into 802.16e WiMAX’s true competitor, and also may delay LTE roll-outs.

In-Stat, Scottsdale, AZ. (480) 483-4440. [www.in-stat.com].

UMD Silicon Could Outsell PC Semiconductors

Ultra-mobile computing could far outsell desktop and notebook PCs in the long run, and is now garnering much attention from semiconductor firms, reports In-Stat. Intel is gearing up to do battle with ARM—the RISC-based, incumbent, intellectual property (IP) company that has dominated the embedded mobile semiconductor market for consumer electronics devices for much of this decade, the high-tech market research firm says.

“Mobile devices are now performing many

exploration er your goal eak directly page, the resource. hnology, and products

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high-tech market research firm says. Both LTE Advanced and 802.16m WiMAX are being specially crafted to offer 100 Mbit/s mobile throughput and 1 Gbit/s stationary mpanies providing solutions now throughput; these extremely high throughput oration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, are expected to a company's technical page, the goal of Get Connected is to put you in touchcapabilities with the right resource.

Whichever to levelbeof a critical part Get Connected will help you connect with the companies and products you areof searching for. IMT-Advanced requirements. the ITU’s nected “Mobile WiMAX effectively came on the scene in 2006 with South Korea’s WiBro; the earliest commercial LTE deployment will be in 2009,” says Gemma Tedesco, In-Stat analyst. “Overall, In-Stat expects that mobile WiMAX will ultimately outpace LTE over the next few years due to timing of network roll-outs.”

Recent research by In-Stat found the following: • The success of the Sprint/Clearwire mobile WiMAX roll-out is expected to have a huge Get Connected effect on whether or not large worldwide opwith companies mentioned in this article. www.portabledesign.com/getconnected erators will roll out mobile WiMAX.

End of Article

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PORTABLE DESIGN

more computing-related tasks than in the past, thus placing additional performance and power demands on processors,” says Jim McGregor, In-Stat analyst. “But battery technology cannot currently keep pace with these ever-increasing demands and, at the same time, consumers want compact mobile devices that they can

easily slip into a pocket, thus, precluding the use of a larger battery. Processing solutions that offer high performance, while limiting power consumption, are needed.”

Recent research by In-Stat found the following: • Intel’s expansion into emerging form factors, such as UMDs and MIDs, with lowpower products expands the list of competitors.

• Applications will dictate solutions in the short run; other factors, such as economies of scale and relationships, will decide solutions in the long run.

• There will be no clear semiconductor maker “winner” in the short run.

In-Stat, Scottsdale, AZ. (480) 483-4440. [www.in-stat.com].

Intel Maintains Microprocessor Momentum in Q3

Intel Corp. gained market share in the worldwide microprocessor business in the third quarter of 2008, on both a sequential and a yearover-year basis, padding its lead in the industry, according to iSuppli Corp.

In the third quarter of 2008, Intel accounted for 80.4 percent of global microprocessor revenue, up 0.3 percentage points from 80.1 percent in the second quarter of 2008. The company extended this gain on the year-over-year comparison, growing its share by 1.7 percentage points from the 78.7 percent it held in the third quarter of 2007.

The picture was slightly different at rival Advanced Micro Devices Inc. (AMD), with the company losing share on a year-over-year basis. In the third quarter of 2008, AMD accounted for 12.1 percent of worldwide micro-

processor revenue, a decrease of 1.8 percentage points from the 13.9 percent it held in the third quarter of 2007.

However, on a sequential basis, AMD’s short-term position improved, with the company’s share rising 0.1 of a percentage point from the 12 percent it held in the second quarter.

The table below represents iSuppli’s preliminary estimates for global quarterly microprocessor market share. Please note that the figure and this release present revenue for the entire global microprocessor market, including x86, RISC and other types of general-purpose microprocessors. This ranking is not limited to the x86 PC microprocessor market.

“Intel’s growth is largely due to the strength of its product portfolio in the notebook segment,” observed Matthew Wilkins, principal analyst, compute platforms, for iSuppli. “In the third quarter, Intel achieved a double-positive, producing share growth on both a sequential and year-over basis, while main rival AMD grew in the short term only.”

Due to the sequential decrease in share of the “others” category, Intel and AMD’s share growth in the third quarter came largely at the expense of smaller suppliers. iSuppli believes the increasingly competitive environment resulting from the global financial crisis is the key reason for this.

Q3 not as bad as feared

While there were some signs that PC demand weakened in the third quarter, iSuppli’s early estimates indicate that PC shipments actually reported healthy growth over the third quarter of 2007, up in the region of 12 to 14 percent.

The notebook segment retained its strength and momentum, and continued to be a key

growth driver for the PC industry in the third quarter. iSuppli’s current PC forecast calls for unit growth of 12.5 percent in 2008. iSuppli Corporation, El Segundo, CA. (310) 524-4000. [www.isuppli.com].

NAND Flash Market Faces Historic Downturn in 2008 and 2009

Once one of the fastest-growing segments of the global semiconductor industry, the NANDtype flash memory market has been stricken by weakening consumer spending, causing revenue to decline in both 2008 and 2009, according to iSuppli Corp. iSuppli’s revised forecast predicts that worldwide NAND flash memory revenue will fall by 14 percent to the $12 billion level in 2008, down from $13.9 billion in 2007. In 2009, global NAND flash memory revenue will decline by another 15 percent. iSuppli’s previous forecast, issued in the third quarter, called for a 3 percent decline in 2008 and 12 percent growth in 2009.

The year 2008 will mark the first time that worldwide NAND flash revenue has declined on an annual basis.

This represents a major reversal of fortune for a product whose revenue routinely expanded by triple-digit percentages in the late 1990s and early 2000s, and that as recently as 2005 generated 62.2 percent annual growth.

The NAND market is being impacted by several factors.

The biggest challenge is the nature of the applications that drive sales of NAND flash memory.

Preliminary Q3 2008 World Wide Microprocessor Revenue Market Share* (Percentage Share of Global Revenue) Supplier Q3 2008 Market Share Q2 2008 Market Share Q3 2007 Market Share Q3 2008 Sequential Change Q3 2008 Year-Over-Year Change Intel 80.40% 80.10% 78.70% 0.30% 1.70% AMD 12.10% 12.00% 13.90% 0.10% -1.80% Others 7.50% 7.90% 7.40% -0.40% 0.10% Total 100% 100% 100% Source: iSuppli Corp. October 2008 *This table presents revenue for the entire global microprocessor market, including x86, RISC and other types of general-purpose microprocessors.

This Ranking is not limited to the x86 PC microprocessor market.

November 2008

13

analysts’ pages

Applications including Personal Media Players (PMPs), flash memory storage cards and USB flash drives account for almost 80 percent of total NAND chip demand.

These products mostly are sold in retail stores, which have significant bargaining exploration power on pricing, especially during a downer your goal eak directly turn in the market. With the challenging sales page, the situation and the inventory overhang among resource. hnology, OEM customers, the NAND chip suppliers and products have no choice but to cut chip prices to increase their sales. d “Unlike other memories, which depend more on non-consumer/non-retail products, NAND flash is bearing the brunt of the challenging retail conditions,” said Nam Hyung Kim, chief analyst at iSuppli. “Combined with mpanies providing solutions now uncertain global economic conditions and a oration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, of right killer applications, the to a company's technical page, the goal of Get Connected is to put you in touchlack with the resource.

Whichever level of NAND flash Get Connected will help you connect with the companies and products you arememory searching for. business is facing a triple whammy. nected “Beyond the macroeconomic and structural challenges, the NAND flash industry also is experiencing the fundamental challenge of declining demand elasticity. With sufficient capacity in their existing flash storage cards and USB flash drives, consumers don’t need to upgrade their products and are not as sensitive to price declines as they used to be,” Kim added.

Unit shipments of 1 Gbyte equivalent-density NAND chips are expected to rise by 126 Get Connected percent in 2008. While this is down from 179 with companies mentioned in this article. www.portabledesign.com/getconnected percent in 2007, it still represents explosive

End of Article

14

PORTABLE DESIGN

unit growth, which is resulting in oversupply.

In 2009, unit growth will decline to 71 percent.

Over the past five years, the market has averaged a 192 percent increase annually.

This represents a significant decline in the growth rate next year. However, it is not sufficient to offset the challenging demand situation and generate a rise in pricing and supplier revenue.

For this year, the Average Selling Price (ASP) of 1 Gbyte equivalent of NAND is expected to drop by 62 percent, followed by a 50 percent decline in 2009.

Decreasing unit growth in the NAND flash market potentially will impact the semiconductor capital equipment industry. The NAND flash suppliers have been increasing their capital spending to increase their capacities.

However, industry spending will be reduced significantly by 38 percent in 2009.

All in all, the only winners in this market are and will be consumers who have access to fire-sale prices for these flash storage devices due to those issues.

At this time, iSuppli is reiterating its “negative” rating for near-term market conditions for suppliers. iSuppli Corporation, El Segundo, CA. (310) 524-4000. [www.isuppli.com].

3Q-2008 Mobile Handset Shipments Manage to Maintain Forward Momentum Despite Credit Crunch Tsunami

“Given the traumatic news ricocheting around the financial markets, one would almost expect mobile handset markets to have nosedived,” says ABI Research Asia-Pacific vice-president Jake Saunders. “However 3Q-2008 still delivered 8.2% year-on-year growth.”

While mobile phones can be viewed in part as fashion accessories, they also impart other value propositions that are highly valued by end-users. Substantial improvements in key functional areas (e.g. memory, battery life, data speed, processor speed) are being noticed by end-users. Still, many are opting to remain

ucts from Nokia, Sony Ericsson, Palm and Samsung and the iconic iPhone expected to LG Samsung become important drivers for LBS uptake due 7.4% 16.6% to their large screens and text input facilities.

Motorola “Despite its appeal, the handset form fac8.1% tor poses a series of new challenges to GPS Sony / chipset vendors,” says ABI Research director Dominique Bonte. “While minimal power Ericson consumption, price and small footprint are 8.2% even more important in handsets than in Apple PNDs, the bigger issue is related to indoor 2.2% coverage, as handset-based LBS services will be frequently used in urban canyons and inRIM door environments such as shopping malls 2.0% where GPS reception is impaired.”

Nokia Others The very important trend of “combo” chip37.0% 18.5% sets—integrating different radio technologies such as FM, Bluetooth, Wi-Fi and GPS on a Mobile Device Vendor Market Share 3Q2008 single chip—promises to provide a solution to power, footprint and price challenges, while also allowing integration of alternative posiNokia may well claw back some of its lost on open contracts rather than upgrade their handsets and lock themselves into down pay- market share as it now has stronger products tioning technologies such as Wi-Fi to provide Get Connected withNokia technology andhave better indoor coverage and a seamless posicategory. would ments for new phones and potentially expen- in the smartphone companies providing solutions now fared worse were it not for its strong line up tioning experience to the end user. This is evisive monthly commitments.

Get Connected is a new resource for further exploration and low-tier handset segments, The positive news is that handset vendors in theintomid-tier products, technologies and companies. Whether your goaldenced by the recent announcement of Broadis to research the latest from a company, speak directlycom’s partnership with Skyhook Wireless. is where LG datasheet and Motorola felt the imare reporting input costs for handsets are on a which with an Application Engineer, or jump to a company's technical page, the Despite some barraging in the media, downward curve. Vendors have also refreshedgoal pact. of Get Connected is to put you in touch with the right resource. level of servicemanaged you require for type of technology, SonyEricsson to whatever keep market share their handset portfolios and have strengthenedWhichever Connected will help you connect with the companies and products at 8.2%. their mid-tier and low-tier handset line-ups toGet constant you are searching for. appeal to end-users on tighter budgets. www.portabledesign.com/getconnected 4Q-2008 will be a vital quarter for handset ABI Research, Oyster Bay, NY. vendors and mobile operators. Expect to see (516) 624-2500. aggressive marketing and promotional activi- [www.abiresearch.com] ties from operators and vendors alike as they The expected availability of combo chipstrive to lure end-users to upgrade their hand- Availability of Combo Chipsets Get Connected with technology and companies providing solutions now sets in 2009 from major GPS chipset vendors sets before the year’s end.

Will Drive Mass Market Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research the such as Broadcom, NXP and ABI Research has revised its expecta- Integration GPS in GSM speak directly withof an Application Engineer, or jump to a company's technical page, the goalAtheros, of Get Connected is toTexas put you in touch with service you require for whatever type of technology, Get Connected will help you connect with the companies and products Instruments will play an important role in ac- you are searc tions for 4Q-2008 down to 7.5% growth from Handsets from 2009 www.portabledesign.com/getconnected 10.4%. Year-on-year annual growth is thereAccording to ABI Research, GPS semicon- celerating the adoption of GPS in mass marfore likely to be between 10.5% and 11%, to ductor vendors are increasingly focusing on ket handsets, ultimately making it a standard close out the year at around 1.27 billion.

GSM handsets as their next target market for handset feature.

“There are winners and losers in 3Q- GPS chipsets. While until now CDMA hand2008,” notes research director Kevin Burden. sets and navigation devices have been the ABI Research, Oyster Bay, NY. “Nokia stumbled slightly to see its market- main GPS product categories, GSM mobile (516) 624-2500. [www.abiresearch.com]. share shrink to 37.7%. Motorola and LG were phones are expected to increasingly feature also net losers (total market-share: 8.1% and GPS chipsets as handset-based navigation 7.4%) respectively. Winners include Sam- and a wide range of location-based services sung (16.6%), Apple (2.2%) and RIM (2.0%). (LBS) such as local search and social netSmartphones are truly capturing the imaginaworking becomeand popular.

Get Connected with companies Get Connected products featured inGPS this section. tion of the buying public, which is benefitting already has become a standard feature with companies mentioned in this article. www.portabledesign.com/getconnected www.portabledesign.com/getconnected vendors with highly desirable smartphones.” on smartphones, with recently launched prod-

Ad Index

Products

End of Article

November 2008

15

cover feature low-power design techniques

Consumer Technology and Low-Power Design: Inseparable Forces Cadence launched its Power Forward Initiative (PFI) in 2006, soon afterward rolling out the Common Power Format (CPF) specification language. This article draws on inputs at a recent PFI Low-Power Design Summit to explain how CPF addresses low-power design challenges.

by S usan Runowicz-Smith, Business Enablement Group Director and Power Forward Initiative Coordinator, Cadence Design Systems

T

The challenge to “Go Green” is now officially in full swing, and that’s a good thing. Whether what’s on the drawing board is a new MP3 player, phone or state-of-the-art data center, customers are demanding that solutions be more power efficient than ever. The problem is especially compounded in consumer electronics, as demands for increased functionality expand almost in direct proportion to new sets of demands to reduce power consumption. At the same time, higher processing demands and higher power dissipation at advanced process nodes are compounding to make this task even more difficult.

Consumer demand for more power-efficient electronics is converging with a design industry that continually drives toward smaller process geometries. These two forces are moving the existing design infrastructure to a new level, a complete upgrade that includes holistic, automated power-lowering design techniques. Most power control methods in use today are manual

16

PORTABLE DESIGN

and implemented on an ad hoc basis, leading to increased risk and cost. Across the design and manufacturing chain, an urgent need has emerged for an automated, power-aware design infrastructure. Seeing the need to facilitate and support a new era of low-power design innovation, almost three years ago Cadence formed the Power Forward Initiative.

Drawing from the collective expertise of leading technology companies, and now boasting 36 industry members, the Power Forward Initiative has created a more systematic and integrated approach to low-power design, providing a platform for higher-level exploration and IP reuse. Power Forward Initiative members have already extensively validated the Common Power Format (CPF), an open specification language that captures all power-specific design, constraint and functionality requirements, such as multi-supply voltage and power shutoff, in a single file.

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By linking design, verification and implementation domains, the Common Power Format enables automation of power-reduction techniques and increases predictability. No longer constrained by the risk of low yield or costly re-spins, design teams can focus their time and resources on what matters most—innovation.

Achieving both functional and structural verification before incurring manufacturing costs, and with greater time-to-market opportunities, companies across the design and manufacturing chain are adopting new process geometries and using low-power design techniques, profitably, in hundreds of design projects and end products worldwide.

figure 1

structure that removes power barriers, spurs innovation and delights mutual customers.

Recently, some 250 engineers in Silicon Valley attended the PFI Low-Power Design Summit, held at Cadence’s San Jose headquarters.

They came away with first-hand, practical advice on low-power design techniques using the widely adopted Common Power Format (CPF).

“Since the PFI was launched, membership has grown from 10 to 36 companies,” said Pankaj Mayor, business development group director. “PFI focus has shifted from developing and validating CPF to practical use of lowpower solutions for design and sharing this information with the industry. This resonated well with the attendees of this summit—85 percent of whom are already engaged in low-power design or will be within the next six months.”

Mayor opened the day-long conference by announcing that LSI Technology, Chartered Semiconductor and SIS in Taiwan had joined the Power Forward Initiative. Throughout the day, PFI member companies AMD, TSMC, ARM, Faraday, Freescale, Chartered Semiconductor, UMC and Alchip presented in sessions on low-power design in action.

NVIDIA Saves Power

exploration er your goal eak directly page, the resource. hnology, and products

d

mpanies providing solutions now

oration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of Get Connected will help you connect with the companies and products you are searching for.

Chris Malachowsky of NVIDIA describes power-saving design efforts.

nected

End of Article Get Connected

with companies mentioned in this article. www.portabledesign.com/getconnected

18

PORTABLE DESIGN

As the sponsor of the Power Forward Initiative, Cadence has taken a leadership role in comprehensively addressing the power design gap facing the greater electronics ecosystem.

Advisory members to PFI have already executed dozens of proof-point projects to validate the Power Forward approach, promote adoption of the Common Power Format, and launch the CPF standardization process. With the support of member companies, the Power Forward Initiative has established a new design infra-

The morning keynote by Chris Malachowsky (Figure 1), an NVIDIA founder, set the stage for further discussions on low power. “When you begin your design you have to ask yourself what is the lowest power you can operate at for the job you’re trying to do? You have to take a holistic view of your design.”

Malachowsky said NVIDIA has three ways of looking at low-power designs: One is when building something for the absolute lowest power in portable devices, two is performance that is dictated in a PC chassis, and three is designing at the highest end to get the highest performance in a power budget.

He said that they got their best results when they designed from the ground up a GPU for the lowest power footprint possible for an applications processor in a mobile device. “It uses only 200 mw of power at full usage. By comparison, a desktop machine probably leaks 15-20 watts at idle.”

Many power-saving methods have also been applied to their flagship video processors, Malachowsky said. “We have aggressive clock gating, aggressive enabling and disabling, like active termination, clock frequency, power VDV levels, etc. We have seen a 2-3x improvement in our performance per watt.”

The broad support by IP companies in the ecosystem for CPF-based flows was illustrated in presentations by ARM, ARC, Virage and Sonics.

The hot topic of architectural low-power trade-off techniques hosted a standing-room-only crowd with presentations from Cadence featuring chip planning and C-to-Silicon Compiler, Calypto and Sequence.

figure 2

Low-Power Design Challenges

After listening to the overview on low-power design challenges given by panelists representing LSI, Freescale, NXP and Virage Logic (Photo 2), attendees came away with some observations repeated throughout the discussion: • Most low-power opportunities are at the system level, where trade-offs can be more easily made. Herve Menager, NXP, said that the industry “lacks tools for systemlevel analysis of low-power design tradeoffs. We use spreadsheets and it is a broad estimate. We can capture our power intent now, but we must understand what the applications can do with it.”

• Low-power solutions are essential to compete. “CPF is a maturing enabler,” said Anis Jarrar, of Freescale.” You can’t live without it for doing low power intent.”

• Know your standard cell libraries. “You must know what is updatable and what is not,” said Jarrar. “Demand CPF information from your standard cell and IP providers.”

• Accurate leakage modeling is needed. “We would like to see more robust dynamic power estimation and analysis at the architectural level,” said Ameesh Desai, LSI. “Leveraging thermal gradients is still in its infancy.”

• A complete EDA flow is needed. Our leading customers are taping out at 65-55nm, and as technologies shrink, we need to work together on a low-power methodology with input from foundries, designers, EDA vendors and IP providers,” said Brani Buric, Virage Logic.

“Low-power design complicates design flows, but the payoff is big,” concluded Jarrar.

During the day attendees broke out into in-depth discussions on low-power design, with topics ranging from ARM CPU methodologies, to sequential optimizations for low power, to CPF flow for highly configurable interconnect IP, to name several.

Going Green

Wrapping up the day, a panel led by Ron Wilson, EDN Executive Editor, extended the practical side of the low-power design equation to in-

A panel on the challenges of deploying low-power design included from left: Herve Menager, NXP; Susan Runowicz-Smith of Cadence moderating, Anis Jarrar, Freescale; Ameesh Desai, LSI; and Brani Buric, Virage Logic.

clude techniques people are using to save power at home. Carl Guardino, CEO of the Silicon Valley Leadership Group, gave many down-toearth—and often-times humorous—examples of what he and his family do to save power.

In his opening remarks, Guardino said that “going green” is not just to save the planet, but is in the best interest of companies in Silicon Valley, which can become the epicenter for burgeoning green industries.

He noted that data centers, power-hungry network hubs of the Internet, will continue to consume more power unless the semiconductor industry comes together to find solutions. “By 2011, at current growth rates, data centers will consume enough power to require 10 new power plants in the U.S. alone.”

“The meeting exceeded expectations—in terms of presentations and attendance,” concluded Mayor. “It was an innovative way of marketing Cadence’s leadership in low power.

It validated that our customers are listening to us on this topic. Energy efficiency is an important global initiative, and Cadence is playing an important role in enabling green electronics.”

Cadence Design Systems Inc, San Jose, CA. (408) 943-1234. [www.cadence.com].

NOVEMBER 2008

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cover feature low-power design techniques

Open UPF/IEEEp1801 Standard Roadmap The Unified Power Format (UPF) is a power-intent specification format championed by Synopsys, Mentor Graphics and Magma; it is the main contender to the Common Power Format (CPF) backed by Cadence.

by J ohn Biggs, ARM Ltd; Gary Delp, LSI; Steve Bailey, Mentor Graphics; Kevin Kranen, Synopsys; Rolf Lagerquist, Texas Instruments; Minh Chau, Texas Instruments

T

The global energy and climate crises that have gained significant awareness over the past six to eight years have “fueled” the emergence of so-called “green” technology initiatives in several key markets, most notably the information technology sector. Semiconductor component power consumption represents problematic challenges that include: mega-server farms consuming hundreds of megawatts, handheld consumer devices, and physical device scaling below 45nm semiconductor process nodes. The result has been a newfound awareness that “offby-default” may become the mantra for nextgeneration semiconductor design practice.

In the realm of semiconductor design, offby-default gives rise to the notion that if a sub-module on a System-on-Chip (SoC) com-

20

PORTABLE DESIGN

ponent is not actively processing data, then the sub-module should be “switched-off” with respect to the SoC’s power grid. For “high end” Power-Managed SoCs (PM-SoCs), the offby-default engineering task translates into the creation of hundreds of power domains and an array of specialized and, heretofore, unknown and unexplored power savings techniques.

The power-savings efforts used by chip designers have a single degree of freedom with respect to the IP core reuse that dominates the architectural design process for SoCs. It is not uncommon to find that 90% of an SoC may be the product of IP reuse. IP cores are integrated across a broad spectrum of components in various application markets characterized by performance, function, and in the context

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cover feature

of this article, power requirements. The increasing power complexity associated with PM-SoCs has served as a wakeup call to the industry and created a desire for standardized power-intent specification formats such as the Unified Power Format (UPF) and the Common Power Format (CPF).

When specifying power intent for a PMSoC, semiconductor design and verification teams recognize the value of a power-intent specification side file that is processed in conjunction with the PM-SoC’s RTL specification.

Power management and power intent acutely affect every phase of the SoC design and manufacturing cycle. There exists no manufacturing proxy for the complexity of semiconductor design and no current or past EDA proxy for the pervasive methodology impact that has been

figure 1

{

upf_a

exploration er your goal eak directly page, the resource. hnology, and products

set_scope /UP create_power_domain TOP -include_scope # Contiguous, Extend of Top = (UP, UP/DMA) set_scope MAC create_power_domain PD_1 -include_scope # Contiguous, Extent of PD_1 = (UP/MAC, UP/MAC/RCV, UP/MAC/BFR)

UP MAC

DMA RCV

XMT

BFR

d

created by power-intent specification. Component manufacturers are keenly aware that their design team’s EDA methodology flows are defined by a few major EDA suppliers. It mpanies providing solutions now is this methodology impact from power-manoration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, that screams so loudly to a company's technical page, the goal of Get Connected is to put you in touchagement’s with the rightpervasiveness resource. Whichever level of Get Connected will help you connect with the companies and products you areto searching for. the industry for a standardized power-intent nected format specification.

The EDA industry’s success along the semiconductor technology trajectory has been defined by innovation and cooperation between EDA suppliers and component manufacturers. Chip companies demand interoperability across key interfaces along the value chain from their EDA suppliers, thereby allowing an amalgam of EDA software customized to their company’s needs.

Current 45, 32, and 22nm EDA methodolGet Connected ogy flows are at the “raw material” stage for with companies mentioned in this article. www.portabledesign.com/getconnected overall SoC R&D costs that now exceed $25M

End of Article

22

PORTABLE DESIGN

per component. Component companies must consider the business risks associated with adopting “proprietary technology standards” that lack broad EDA industry acceptance. Becoming “locked-in” to a single chip design reference flow that relies upon non-open, “controlled” specifications from one EDA company presents an unnecessary business and engineering risk for chip executives and managers.

The semiconductor industry’s leading component manufacturers, in cooperation with Accellera, initiated an open standardization effort for power intent that resulted in the Unified Power Format (UPF) 1.0 standard. Since the Accellera UPF 1.0 standard was approved, the IEEE approved a standards committee to develop the P1801 (UPF 2.0) power-intent standard as an evolution of the Accellera UPF 1.0 standard.

An important aspect of any power-intent format standardization is reflected in the full participation by a broad spectrum of companies within the semiconductor industry. In this sense, the UPF standard has received the support of three of the four major EDA vendors: Synopsys, Mentor Graphics and Magma Design Automation. As important as EDA-vendor endorsement is to an EDA standard, the acceptance of the standard by the engineering design community defines the standard’s validity, quality and longevity. As of the printing of this article and to the best knowledge of the UPF EDA endorsers, approximately 70 percent of the major semiconductor companies have plans to adopt UPF into their component design flows.

From the semiconductor foundry perspective, TSMC, the Common Platform (IBM, Samsung and Chartered) and UMC all have proven UPF 1.0 foundry flows in place today.

The UPF 1.0 standard has provided a strong technical base for power-intent specification using a power-domain-centric syntax for isolation, level-shifting and retention policies.

The power-intent flexibility afforded by UPF’s abstraction and definition for power domain scope and extent provides a concise semantic for design-element partitioning within a complex logical hierarchy.

Figures 1, 2, and 3 illustrate a progression of power-domain element inclusion with respect to a power domain’s scope and extent for the

cover feature associated UPF code segments in the respec- Therefore, in Figure 2, upf_b incrementally tive figures. The concept of contiguous versus adds one set_scope and one create_power_ non-contiguous power domains is presented. domain command to upf_a to create power UPF command files upf_a, upf_b, and upf_c domain PD_2. upf_b elevates the scope one hiare applied in subsequent figures with increas- erarchical level with the third set_scope coming power-domain complexity. The example mand, thereby capturing element UP/DMA for walks through the process a designer may inclusion in PD_2, along with extracting elefollow while imposing a power-aware archi- ment UP/MAC/XMT from PD_1 with the –eletecture upon a legacy SoC subsystem. The ex- ments parameter. ample consists of: an embedded processor figure 2 core (UP), a DMA enset_scope /UP gine (DMA), a MAC # Contiguous, Extent of Top = (UP, UP/DMA) create_power_domain TOP -include_scope set_scope MAC upf_b (MAC) with transmit # Contiguous, Extent of PD_1 = (UP/MAC, UP/MAC/RCV, UP/MAC/XMT, create_power_domain PD_1 -include_scope set_scope /UP (XMT) and receive create_power_domain PD_2 -elements (DMA, MAC/XMT) # Non-Contiguous, Extent of PD_2 = (UP/DMA, UP/MAC/XMT) (RCV) instances, and a receive buffer memUP ory (BFR).

MAC DMA The power-aware RCV XMT BFR design constraints may be coarsely defined to reduce the SoC power by applyDesign element UP remains in the Top powing Power Shut-Off (PSO) to the communication subsystem, MAC. In Figure 1, upf_a sets er domain. The create_supply_net and crethe scope at design element UP for the cre- ate_supply_port commands should be used to ation of the “Top” power domain. The second create explicit supply nets and ports at logical set_scope command drops the scope one level hierarchical level UP. Implicit supply port condown in the logical hierarchy to design element nections will then be created for PD_2 within MAC, allowing the second create_power_do- the logical hierarchy to allow supply net conmain statement to create PD_1. PD_1’s cre- nections between elements DMA and XMT. ate_power_domain statement only requires a PD_2’s non-contiguous property requires that –include_scope option to capture all of the ele- implicit supply port connections will pass through PD_1’s logical hierarchy. After power ments identified in the comments of line 4.

Design elements UP and DMA remain in the analysis, the designer realizes an additional Top power domain. The create_supply_net 10% original power savings.

The final designer refinement recognizes and create_supply_port will be used to create explicit supply nets and ports at logical hierar- that the memory buffer can be powered off chy level UP, while implicit supply ports and whenever the UP is powered down. Then Fignets will be created within the logical hierarchy ure 3 incrementally builds upon upf_b (upf_c) for the elements (MAC, RCV, XMT and BFR) with one final create_power_domain statein PD_1’s extent. At this point the new power ment to create a two element, non-contiguous analysis may have reduced the power by 20%, power domain, PD_3. The application of upf_c extracts element UP/MAC/BFR from but it is not yet optimal.

In the next refinement the designer recog- PD_1 with the –elements parameter, while nizes that the transmit module, XMT, should also encapsulating the top element A in the be “on” under different circumstances than the logical hierarchy with the combined use of the MAC’s receiver. In addition, the DMA’s data –include_scope parameter.

The Top power domain no longer has any transmission closely correlates to the MAC’s XMT function, justifying identical power man- design elements. While explicitly creating supagement for the DMA and XMT instances. ply nets and ports, as with PD_1 and PD_2, an

UP/MAC/BFR)

NOVEMBER 2008

23

cover feature

providing increased accuracy in RTL poweraware simulation behavior.

UPF’s command layering, or refinement semantics, allows IP providers to specify the “what” part of power-intent abstractions without worrying about implementation-specific details. UPF command layering enables a reusable, technology-independent UPF specification for vertical market applications of generalized IP cores. The IP user/implementer can provide additional refinement specifications, e.g. use_interface_cell, describing the “how” of the power-intent specification by targeting specific power-management architectures or technology libraries.

UPF 2.0 extends UPF 1.0’s abstractions and refinement capability by adding the concept of supply sets. The power-intent refinement capability has been enhanced with predefined or placeholder supply set handles. By using supfigure 3 ply sets, supply nets can be aggregated into # Non-Contiguous, Extent of Top = (UP, UP/MAC/BFR) TOP -include_scope -elements (MAC/BFR) predefined primary, -elements (DMA, MAC/XMT) # Non-Contiguous, Extent of PD_1 = (DMA, UP/MAC/XMT) PD_2 supply, default_reten# Contiguous, Extent of PD_2 = (MAC, MAC/RCV) PD_1 -include_scope tion, and default_isolation power rails. An association command, associate_supply_set provides syntactic inBFR direction for supply set references. Additional power-rail references can be made for tion and implementation. By allowing IP cores predefined supply set functions such as power, to carry separate UPF power-intent implemen- ground, pwell, or nwell designations. Customtations, design architects can specify power in- ized supply net functions can also be defined.

The supply set abstractions in UPF 2.0 define tent early in the chip-architecture phase.

While UPF 1.0 provides an adequate set of a base functionality for implicit and automatic power-intent semantics, the IEEE P1801 (UPF connection semantics for complex power-intent 2.0) standard extends the power-intent com- hierarchies.

Consider the following implementation/remand set for simulation modeling through the load_simstate_behavior and the set_sim- finement scenarios: 1. UPF Constraints state_behavior commands. Simulation beIP provider needs to identify what is to be havior for low-Vdd-standby can be effectively isolated without prescribing how: modeled using UPF 2.0’s extended definitions for supply levels as defined by the PARTIAL_ set_isolation my_iso -domain my_pd \ ON, UNDETERMINED, FULL_ON, or OFF

-clamp 0 semantics. New power-state definitions have 2. UPF Configuration been introduced to define simstates for supSystem level simulation needs to conply sets such as: CORRUPT_ON_ACTIVITY, figure the logical power control without CORRUPT_STATE_ON_ACTIVITY and having to specify the power supplies: CORRUPT_STATE_ON_CHANGE, thereby additional set of implicit supply port connections will now be introduced for PD_3 into the logical hierarchy for PD_1. This final power optimization analysis shows an additional 10% original power reduction.

In the final analysis, the designer was able to reduce the original SoC subsystem power by 40% through incremental application of UPF constraints without requiring RTL modifications to the legacy design IP. It should be apparent from the above example that by utilizing a UPF power-intent side file in conjunction with the UP SoC IP RTL, the UP IP may be readily ported to additional SoC target markets that may have differing power requirements.

The current and future importance of IP reuse and SoC integration provided an impetus for the UPF 1.0 creators to pay particular interest in the separation of power-intent specifica-

upf_c

set_scope / create_power_domain create_power_domain set_scope C create_power_domain

UP MAC

DMA RCV

24

PORTABLE DESIGN

XMT

3. UPF Implementation Finally, the details of the power supplies are added during implementation: set_isolation my_iso -domain my_pd \

-isolation_power_net VDDG \

-location parent If there is no need for successive refinement, everything can be specified at once: set_isolation my_iso -domain my_pd \

-clamp 0 \

-isolation_signal CLAMP \

-isolation_sense high \

-isolation_power_net VDDG \

-location parent UPF 2.0 provides for a new command, set_port_attributes, to allow specific powerrelevant information to be assigned to power domain ports. Port attributes, such as clamp levels, allow IP providers to control any aspect of a port’s power intent. Further port powerintent refinement is achieved by adding control attributes for related supply sets. EDA tools may use power-intent port attributes for corruption semantics and buffering choices for special-exception nets. Certain UPF properties can also be annotated directly in HDL source code descriptions using UPF 2.0’s command alternative syntax.

The forthcoming UPF 2.0 standard also introduces forty (40) new query commands that can serve as the basis for extensive and interoperable power-intent analysis. With a refined error-handling definition, the TCL-based syntax for UPF 2.0 completes a well-vetted openstandard power-intent specification.

It’s true that open standards do not come to closure overnight and require painstaking, collaborative efforts between suppliers and end users. However, in the end, open standards provide a superior end product for interoperability that is the result of input, refinement and content from many minds and salient interests.

From this vantage point, we believe that market forces will soon converge upon a single powerintent format, the Unified Power Format.

Twentieth-century feminist, Shulamith Firestone, warned that “...power, however it has evolved, whatever its origins, will not be given up without a struggle.” While Ms. Firestone didn’t have semiconductor design on her mind when she spoke these words, the Unified Power Format has given 21st-century design managers and engineering teams a renewed comfort in the inevitable power struggle with 32 and 22nm process nodes.

The UPF 1.0 and IEEE P1801 (UPF 2.0) standards (Table 1) have been vetted through an open standardization process involving the top EDA and semiconductor suppliers in the industry, thereby laying a foundation to address the challenges of power management in the years to come.

cover feature

set_isolation my_iso -domain my_pd \

-isolation_signal CLAMP \

-isolation_sense high

table 1 UPF 1.0/2.0 Base Command Comparison (excluding UPF 2.0 query commands) ** UPF 2.0 includes all UPF 1.0 commands except (#) ** UPF 1.0

IEEE P1801 (UPF 2.0)

add_domain_elements

add_power_state

add_port_state

associate_supply_set

add_pst_state

connect_logic_net

bind_checker

connect_supply_set

connect_supply_net

create_composite_domain

create_hdl2upf_vct

create_upf2hdl_vct

create_power_domain

create_logic_net

create_power_switch

create_logic_port

create_pst

create_supply_set

create_supply_net

describe_state_transition

create_supply_port

load_simstate_behavior

create_upf2hdl_vct

load_upf_protected

get_supply_net (#)

set_partial_on_translation

load_upf

set_port_attributes

map_isolation_cell

set_retention_elements

map_level_shifter_cell

set_simstate_behavior

map_power_switch

use_interface_cell

map_retention_cell

use_retention_cell

merge_power_domains name_format save_upf set_design_top set_domain_supply_net

ARM Inc., Sunnyvale, CA. (408) 734 5600. [www.arm.com].

set_isolation

LSI Corporation, Milpitas, CA. (800) 372-2447. [www.lsi.com].

set_power_switch

Mentor Graphics Corporation, Wilsonville, OR. (503) 685-7000. [www.mentor.com].

set_scope

set_isolation_control set_level_shifter set_pin_related_supply set_retention set_retention_control upf_version

UPF 1.0/IEEE P1801 (UPF 2.0) Command Comparisons

Synopsys, Inc., Mountain View, CA. (650) 584-5000. [www.synopsys.com].

Texas Instruments Inc., Dallas, TX. (800) 336-5236. [www.ti.com].

NOVEMBER 2008

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Reducing Power in VideoIntensive Portable Applications Sequential clock gating during RTL design selectively disables clocks to eliminate unnecessary switching activity, significantly reducing dynamic power consumption in computationally intensive applications such as image processing.

by Mitch Dale, Director of Product Marketing, Calypto Design Systems

W

With the advent of 3G wireless and increasingly advanced integrated circuit (IC) technology, portable consumer devices today are capable of delivering amazingly rich and varied video content. A growing number of mobile products engage users in compelling visual experiences such as live video, interactive gaming, interactive maps, Web browsing and high-definition photography. And, whether in a basic cell phone or full-featured PDA, these capabilities now play a significant role in a product’s appeal and, thus, success in the marketplace.

The power-hungry image processors that enable these applications, however, also present a challenge for the portable system designer. Image processing demands intensive computation for extended periods of time. For example, a mobile device processing video must decompress, decode, scale and apply graphic filters on each incoming frame. It then repeats these computations at a rate of 30 times per second to stream

26

PORTABLE DESIGN

content to the mobile display. It’s a substantial workload, with a voracious appetite for power.

Despite the consumer’s seemingly insatiable desire for video-rich applications, minimizing power consumption and maximizing battery life remain absolute requirements for portable mobile devices. Navigating these conflicting objectives requires a holistic, comprehensive approach to saving power. Portable designers must deploy power-saving techniques throughout the design flow to achieve both standby and active power requirements.

Components of Power

Power optimization in mobile devices starts with an understanding of both static and dynamic power components. Static power is the main contributor to standby power dissipation and results from transistor leakage current. Increased transistor leakage current is a by-product of shrinking device geometries.

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Fortunately for designers, leakage can be addressed automatically during synthesis by using multi-voltage threshold cells. During synthesis cells are selected based on power and performance trade-offs. Higher voltage threshold cells reduce leakage current, but switch more slowly than lower threshold cells. For non-timing critical paths, slower switching, high-voltage threshold cells are used to decrease static power dissipation. As long as the technology library being utilized offers a selection of cells with different thresholds, static power is optimized automatically by low-power implementation tools, and is largely transparent to the designer.

Active power, also referred to as dynamic power, is the consequence of device activity that can be reduced by eliminating unnecessary switching activity. Register transfer level (RTL) clock gating is the most common technique for reducing dynamic power. Clock gating selectively disables clocks to eliminate unnecessary switching activity, significantly reducing dynamic power consumption in computationally intensive applications such as image processing.

plications. Unlike combinational clock gating, sequential clock gating is not a simple translation. It involves sequential analysis of design behavior. Sequential analysis looks at circuit functionality over multiple design states and cycles to identify unnecessary switching activity such as unused data computations in pipelines. It then determines the enable logic condition that eliminates unnecessary switching.

figure 1

en clk

en clk Combinational Clock Gating

Clock Gating Techniques

There are two types of clock gating, combinational and sequential (Figure 1). Combinational clock gating is a straightforward substitution of conditional statements in the RTL code with clock-gating cells inserted into the clock path of registers. Low-power RTL synthesis tools automatically identify and insert combinational clock gating based on pattern matching. The extent to which low-power synthesis tools can apply clock gating is limited by how the RTL is coded. Low-power synthesis tools identify clock gating opportunities by finding explicit “IF conditions” prior to assignment statements in the RTL code. However, these tools are not capable of analyzing and determining where and when “IF conditions” can be added to the RTL code to reduce power. It is up to the RTL designer to place these “IF conditions” in their code so low-power synthesis can translate them into power saving clock gates.

Sequential clock gating is a more powerful optimization technique with proven ability to reduce power in computationally intensive ap-

Sequential Clock Gating

Sequential Clock Gating Comparing combinational and sequential clock gating.

For example, when a register output is being held in the current cycle, sequential analysis can determine the logic condition to disable the switching in combinational logic and registers that generated the data in the previous cycle.

This sequential relationship can be propagated NOVEMBER 2008

27

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figure 2 RTL Design Manual RTL Modifications

Did not meet power

backward and forward across many cycles. RTL designs contain a multitude of sequential relationships that can be exploited to reduce switching activity and, hence, optimize register, memory, clock and combinational logic power.

The potential power savings from sequential clock gating is significant, particularly in applications such as video processing designs that support multiple video formats and data-dependent algorithms. Depending on the incoming video stream, only part of the decode computation and filtering calculations is needed. This provides ample opportunities for clock gating if the designer understands the sequential relationships in their design.

Deploying Clock Gating

Three key elements of implementing a clock gating methodology are: thoroughly identifying all clock-gating opportunities; accurately Did not pass creating the RTL code that implements those Simulation regressions Regression opportunities; and effectively verifying the clock-gated RTL code to ensure it retains the original functionality.

Optimized exploration RTL Until recently, the common approach to clock er your goal eak directly gating has been for designers to examine their page, the code for clock-gating opportunities and to manuDid not resource.

Synthesis meet timing hnology, ally add IF conditions to their RTL code. A typical Did not and products clock-gating design flow includes manually addmeet power Gate Level ing clock gating optimizations, using RTL power d Netlist estimation to gauge the effectiveness of those optimizations, and then running simulation regressions to verify no functionality has been broken.

A typical manual RTL clock-gating design flow.

Eventually the RTL code is synthesized and gatelevel power estimations are available to determine mpanies providing solutions now if more clock gating is required (Figure 2). oration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, There areresource. manyWhichever inefficiencies in this apto a company's technical page, the goal of Get Connected is to put you in touch with the right level of Get Connected will help you connect with the companies and products you areproach. searching Because for. of the vast number of clocknected gating opportunities and complexity of the enable conditions, designers can spend considerable time investigating and modifying RTL code. Since not all clock-gating optimizations will result in a net power savings, and some may have a negative impact timing and area, a trial and error approach is required to create the lowest power design. This manual effort is labor intensive, extends the development cycle and puts additional demands on RTL simulation. Since clock-gating optimizations Get Connected cannot be verified with traditional combinawith companies mentioned in this article. www.portabledesign.com/getconnected tional equivalency checking tools, simulation Low Accuracy Power Analysis

End of Article

28

PORTABLE DESIGN

testbenches and assertions must be developed to verify that the new clock gating has not disturbed the original functionality.

The natural solution to this dilemma is design automation.

Adding Power Optimization Tools into the RTL Design Flow

When adopting new power optimization tools, design teams are well-advised to keep several key considerations in mind. First, it is important that the power savings from a new tool be complementary and cumulative to existing power optimization tools. Second, to avoid long learning curves and additional script development, new tools should accept standard file formats and fit into existing design flows.

Third, it’s important that new tools provide a comprehensive solution so as not to create additional problems elsewhere in the design flow.

For example, automating the identification of clock-gating opportunities is interesting, but it can have a negative impact on productivity unless the tool generates optimized RTL code and comprehensively verifies that the original functionality has not been changed.

Recently, commercially available power optimization tools automate the identification, insertion and verification of sequential clock gating in RTL designs (Figure 3). Incorporating automated sequential clock gating and verification brings power saving benefits to videointensive portable applications.

Such capabilities are embodied in PowerPro CG (for clock gating) and SLEC CG from Calypto Systems Inc. PowerPro CG is an automated RTL power optimization solution proven to deliver up to 60% power savings with little or no impact on area and performance. SLEC CG is a sequential equivalence checker that comprehensively verifies sequential clock-gating optimizations. These tools complement an existing low-power design flow by analyzing sequential behavior in RTL designs and identifying clock-gating opportunities beyond those already present. They fit into existing design flows by reading in standard, synthesizable Verilog and VHDL RTL code.

Additionally, the generated power-optimized RTL code is identical to the original RTL design with additional clock-gating enable logic.

The power-optimized RTL code is then comprehensively verified using sequential logic equivalence checking to ensure no functional changes are introduced. The power-optimized RTL design flows directly into low-power synthesis to take advantage of downstream power optimization capabilities. By relieving the designer from tedious design analysis, manual RTL recoding and time-consuming simulation, productivity and power savings are improved.

Conclusion

Power optimization is a critical requirement for computation-intensive, low-power integrating power-optimization techniques, such as sequential clock gating into existing design flows, where designers can significantly reduce power while actively processing video. With today’s automated sequential clock-gating solution, designers can save additional power and

improve design productivity over their current manual clock gating methods.

Author Bio:

Mitch Dale is director of product marketing at Calypto Design Systems Inc. of Santa Clara, Calif. Dale has more than 17 years of marketing and engineering experience in functional verification. Prior to joining Calypto, he was director of Verification Solutions, responsible for application development of Emulation and Acceleration products within Mentor Graphics.

Previously, Dale was at IKOS systems during which time he functioned as director of marketing and director of software engineering. He holds a B.S. in Applied Mathematics and Computer Science from U.C. Berkeley.

Calypto Design Systems, Santa Clara, CA. (408) 850-2300. [www.calpyto.com].

figure 3

Original RTL Design

Automated Clock Gating

Comprehensive Formal Verification

Sequential Equivalence Checker

Optimized RTL Design

Automated RTL power optimization.

4th Annual International Conference

Lithium Mobile Power 2008 KNOWLEDGE FOUNDATION TECHNOLOGY COMMERCIALIZATION ALLIANCE

Conveniently timed with

knowledgefoundation.com

Advances in Lithium Battery Technologies for Mobile Applications

December 8-9, 2008 Las Vegas, NV USA

Fuel Cells Durability & Performance 2008 December 11-12, 2008

Untitled-1 1

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cover feature low-power design techniques

Optimize Power Consumption in Portable Electronics Using Integrated Load Switches The surest way to eliminate current leakage from a peripheral is to turn it off. Load switches are a critical component in a distributed power management system.

by Philippe Pichot, Texas Instruments

T

The adoption rate of load switches continues to increase across a broad range of end equipment including portable electronics (mobile phones, portable consumer electronics, notebooks or any portable equipment). Load switches are increasingly used in power management architectures to distribute power from a single regulated source or to switch off any unused peripherals (camera module, WLAN module, SD Card slot, LCD display, etc.) with the goal of limiting current leakages and optimizing the power consumption in a system.

This article summarizes important specifications that need to be considered with switch loads in portable electronics, reviews the traditional solutions and shows how integrated load switches can help designers create an optimized solution.

In many new portable designs, there is a growing need to generate multiple power rails in order to supply power or remove

30

PORTABLE DESIGN

power to a variety of peripherals on the board. By turning off the peripheral, the designer can minimize peripheral leakages and help optimize the system’s power budget.

One possible method for achieving this is to use either point-of-load (POL) devices like DC/DC converters or low drop out voltage (LDO) regulators as shown in Solution #1, Figure 1. Then use the enable pins to shut down the rails when they are not needed.

However, this comes at the expense of an increased component count, which most likely will lead to increased board space and cost.

Another solution to distribute and shut off rails is to use a simple load switch as shown in Solution #2, Figure 1. This method is usually preferred because it enables the user to deliver a solution with performance similar to Solution #1, but with less board space and cost, as switches are usually smaller and more affordable than DC/DC converters.

Load switches generally consist of a p-channel MOSFET or PMOS transistor with its gate controlled by a NMOS transistor (Figure 3).

Ideally, the user would like to have an output of the load switch that is identical to its input; however, in real operation the output signal is altered due to parasitic effects of the switch.

To design a load switch-based solution, here are the most important parameters to consider: • rON – On-state resistance from drain to source of the pass FET • tRISE – Rise time of the switch • VIH/VIL – Control thresholds of the switch • ICC and ISHUTDOWN – Quiescent and shutdown current •Q uick Output Discharge feature One of the critical parameters is the on-resistance of the switch since this will impact the dropout the designer will see across the switch.

This is very important when starting a new design with load switches. Designers must be cautious to understand what the maximum acceptable dropout is with regard to their particular application setup (voltage, current). This can easily be calculated using the formula where V is the dropout, rON is the ON resistance of the pass FET and I is the current through the switch.

In the example below, the maximum allowed drop across the switch is 0.026V. Therefore, the on-resistance of the switch must be lower than

over the full temperature range at an input voltage (VIN) of 1.2V. In a PMOS transistor, the rON depends on the input voltage of the switch. The rON curve is shown in Figure 3. As shown, the switch’s ON resistance increases with a decreasing input voltage. As a result, designers must be careful to correctly select the switch they want to use depending on the voltage/current combination that they desire to switch.

Another critical parameter the designer needs

figure 1 1.8-V DC/DC Converter

Enable

1.8-V DC/DC Converter

Enable

1.2-V DC/DC Converter

Processor

1.8-V DC/DC Converter Processor

CAMERA Processor

CAMERA Processor

CAMERA

Solution #1

Switch

1.2-V DC/DC Converter

CAMERA

Solution #2

Camera Module Power Switching Architecture Solutions

figure 2 to consider is the inrush current generated when the switch is iniPeripheral tially enabled. If the DC/DC 1.2-V ±5% 1.2-V ±2% switch turns on with200mA Switch out being controlled, (Pass FET) a large inrush current 1.15-V Min 1.176-V Min will be created that could result in a supply Allowed Drop = 1.176 - 1.15 = 0.026-V rail drop at the input of the switch. This could Application Example with a 1.2-V power rail ultimately impact the functionality of the entire system.

The inrush current can be calculated using the following formula:

For example, with a and a rise time of 1 µS, the inrush current could be as high as 3A! An easy way to avoid this inrush current is to slow down the switch’s rise time. This will NOVEMBER 2008

31

cover feature

figure 3 Ron vs Vin

0.40 0.35

0.4-Ω @ 0.85-V

0.30 0.25 0.20 0.15

0.075-Ω @ 1.2-V

0.10

0.025Ω @ 3.0-V

0.05 0.00 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6

ON-State Resistance, Ron (Ohm)

0.45

Input Voltage, Vin (V)

ON resistance vs. input voltage of the TPS22922

slowly charge the output capacitor and reduce the current peak.

Pass FET In the example above, (PMOS) a rise time of 200 µS VIN VOUT would result in a 15 mA inrush, which is acceptable.

Pull-Up Additionally, when the switch is turned ON from on to an off state, some users prefer not NMOS to have the rail floatRC to adjust the slew-rate of the pass ing and, therefore, use MOS an additional transistor to quickly discharge the output when the switch turns off.

GND Load switches are used in many applications and are conTypical load switch implementation with discrete components ventionally designed using a combination of discrete semiconductors (PMOS, NMOS, capacitors and resistors). The typical setup is illustrated in Figure 4.

The PMOS is the power switch (pass FET), which has its gate controlled by a regular N-

figure 4

32

PORTABLE DESIGN

Channel MOS (NMOS). Logic high turns on the PMOS by pulling its gate to ground through the NMOS, whereas a logic low turns off the pass switch by turning off the NMOS, allowing the PMOS gate to be pulled up to the source through an external pull up resistor. The size of the PMOS device depends on the desired rON. A large PMOS is needed if the user wants to switch with low dropout, and a small PMOS will be enough if only small currents are switched. In order to control the slew-rate (rise time) of the PMOS transistor, a resistor-capacitor network is used to alter a RC time constant as shown in Figure 4.

It is important that the input voltage of the pass FET stay higher than its output voltage, otherwise the input will be clamped via the body diode of the PMOS, which will cause significant current to flow from the output to the input.

This solution based on discrete components is quite flexible but not optimized from a solution size stand point, especially when switching low voltage power rails that cannot allow large dropout across a switch. Most of the time, a PMOS with low rON will be bigger than 5 mm2 or 1.5 mm2 for the most expensive ones, while a standard NMOS will be about 2.5 mm2. If you add a couple of resistors and a capacitor, the solution size can be above 6.5 mm2 and potentially above 10 mm2, depending on the package selected, and this without considering placement space.

Another solution is to use an LDO, which is an interesting solution since it is offered in a single small package. However, the LDO has a major disadvantage in low-voltage systems.

Affordable LDOs have a dropout in the range of 100 to 200 mV, which is not acceptable in most cases when switching low voltage rails.

In the example shown in Figure 2, the LDO solution does not work since the dropout of the LDO (>100 mV) is greater than the maximum allowed dropout across the switch. To some extent, current consumption of the LDO in the range of 50 µA can be an issue as well.

The third and most likely optimal solution is to use an integrated load switch that combines all the functionalities of the discrete implementation. Integrated load switches like the TPS22901 or the TPS22902 from Texas Instru-

cover feature ments are specifically designed as a solution to the challenges that portable power management designers are facing. They integrate all the main features of a discrete load switch on a single die, providing maximum performance and flexibility to the end user.

Modern integrated load switches typically offer: • Ultra-low rON pass P-channel FET • I nternally controlled slew rate without external components •L ow threshold control inputs •U ltra small packaging •< 1µA quiescent and shutdown current •O utput discharge transistor

stitut Superieur D’Electronique du Nord (ISEN) in Lille, France.

Texas Instruments Inc., Dallas, TX. (800) 336-5236. [www.ti.com].

Since the main factor impacting the die size on such a device is the ON-resistance, designers can select devices with different rON values depending of their application needs, therefore optimizing the cost of their solution.

The main advantage of an integrated load switch clearly is the solution size. As stated previously, a discrete implementation will occupy more than 6.5 mm2 while a similar integrated solution like the new TPS22901 in wafer chip scale package is 0.64 mm2, which is more than 10 times smaller!

Another interesting advantage is their ease of use. In the discrete implementation, the user needs to select five components and route their board accordingly. An integrated solution is an easy, proven and quick solution to implement.

Lastly, for users who do not want to see the power rail floating when the switch is turned off, the integrated solution offers the ability to quickly discharge the output rail at almost no additional cost.

In conclusion, using integrated load switches is an easy way to implement distributed power management architecture and to power down applications when they are not being used.

Integrated load switches continue to solve designers’ challenges by providing flexibility, reduced component counts with increased overall reliability.

About the author

Philippe Pichot manages the strategic marketing and development for analog, USB and load switches product lines.

Philippe received his MSEE from the InUntitled-5 1

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Non-Volatile Memory Options in Portable Designs Choosing the right NVM can dramatically impact both the power profile and the price of your portable design.

by C raig Zajac, Product Marketing Manager, Embedded NVM Group, Virage Logic Corporation

T

The number of functions being demanded by consumers in portable devices is growing every day. Gone are the days when it was acceptable to have separate devices providing voice access, email and Web access, music, video and gaming. As the number of features and functions embedded into portable devices increases, so does the need for embedded non-volatile memory (NVM).

Today NVM is used for code storage, digital rights management (DRM), configuration settings, device/vendor IDs and performance tracking to name a few. This article will address the various options available for system designers to include NVM in their portable designs, and will outline the key advantages and disadvantages of each technology option.

Available Options

There are a growing number of options to include NVM in portable designs. The key to effectively selecting the right NVM solution is to understand the basics about both the application requirements and the NVM capabilities.

The most common NVM options for portable devices are: 34

PORTABLE DESIGN

• External EEPROM: stand-alone EEPROM IC available from a wide range of suppliers • Embedded Flash: multiple-time programmable (MTP) NVM requiring a custom process and provided by the foundry • Logic OTP: one-time programmable (OTP) NVM done in a standard logic CMOS process, either available through the foundry or through third-party IP providers • Logic MTP/FTP: multiple-time programmable (MTP) and few-times programmable (FTP) NVM done in a standard logic CMOS process, typically provided by third-party IP providers Understanding the application requirements (target process node and use model) is critical to narrowing the NVM options. Each option has clear advantages and disadvantages. For example, external EEPROM has the broadest range of bit counts and is completely process agnostic, but carries the burden of requiring an additional chip. Embedded flash has high endurance and is capable of supporting up to 1M bit of NVM, but requires a customized process that is not available in advanced process nodes. Logic MTP and Logic FTP provide

cover feature

true multiple-time programmability across a wide range of process nodes, but the available densities are usually limited to 16 Kbits or less. Logic OTP can cover a wide range of bit counts and process nodes, but has limited flexibility because there is only one programming cycle allowed.

Understanding the Use Model

figure 1

16k64k

<16k

Density (Bits)

>64k

System designers with a clear understanding of the use model can quickly narrow the number of options.

Logic External EEPROM The two key dimenOTP sions of the use model are the total number of bits needed and the total Logic FTP Logic MTP number of write cycles required of the NVM. As shown in Figure 1, 1001k 210 10100 1 >1k each technology option Endurance (Write Cycles) is optimized for a particular region in the use exploration NVM choices vary with density and endurance requirements. model space. Applicaer your goal eak directly tions that fall into one of page, the these areas will have a resource. table 1 hnology, straightforward decision and products regarding which NVM External Embedded Logic MTP to use, assuming that it d Logic OTP EEPROM Flash / FTP also meets the process, Read Power 5.5 mW 2.5 mW 13 mW 0.7 mW power and cost requireWrite Power 16 mW 17 mW 13 mW 1.7 mW ments of the system.

One subtlety that is Standby Power 27 µW 25 µW 15 µW 13 µW often overlooked in the mpanies providing solutions now use model analysis inoration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, volves the total number to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of Get Connected will help you connect with the companies and products you areof searching for. cycles needed. For an application reprogram nected quiring the final data to be written only one time, it is critical to understand where the data needs to be programmed. Programming at wafer sort (typically for simple trim applications) most likely requires one program cycle. If the programming needs to be done post-packaging or in the final system (precision trimming, configuration settings, device/ vendor IDs, etc.) there are additional programming cycles required in order to fully test the NVM. Depending on the outgoing quality level requirements, it may be acceptable to forego any testing Get Connected of the NVM and ship untested arrays to the field. with companies mentioned in this article. www.portabledesign.com/getconnected For applications where the quality requirements

End of Article

36

PORTABLE DESIGN

Embedded Flash

are more stringent, system designers may consider migrating to an FTP-based solution that allows the NVM array to be 100% tested before shipment.

Depending on the flexibility of the end-use model, some applications can benefit from a hybrid solution that includes multiple technologies.

A common example is using a small amount of Logic MTP or FTP in combination with a larger block Logic OTP or ROM to create a high-density solution with the ability for small amounts of infield programmability without the added cost of a custom flash process or an external component.

Power Comparisons

Comparing the power consumption of NVM solutions is critical to understanding the impact on the overall system power budget. In this comparison, each of the technologies was evaluated based on an 8 Kbit NVM array (the largest bit count commonly available across all categories).

Read power, write power and standby power are all summarized in Table 1. In most cases, the standby power is driven by the process leakage and not by the NVM. For the read and program power, the values are driven by the underlying technology and the architectural trade-offs.

For external EEPROM, the high power consumption is based on two factors. First, by being an external IC, the interface power is significantly higher than an embedded solution. Second, commodity EEPROM ICs are typically built on a customized process from older geometries and require higher supply voltages (3.3V or 5V) that increase the overall power consumption of the device.

For embedded flash, the higher current is directly related to the capability to support higher density memory arrays. Many of the target applications for high-density MTP use the NVM for code storage, and one of the key requirements for code storage applications is fast access time. In order to achieve faster read and program access times, embedded flash NVM blocks require additional current.

The Logic OTP solutions also target code storage applications, so they trade off faster access times for higher power consumption, but a number of Logic OTP technologies also rely on a high-current programming operation to create physical changes to the silicon structure. Both traditional poly fuse technology and more recent oxide rupture antifuse technology require a high

cover feature Silicon costs are the easiest to estimate. For external EEPROM, it is simply the component cost. For all of the logic-based solutions it is the added cost due to the extra silicon area. For embedded flash, the silicon costs need to include both the added silicon area as well as the process cost added due to the custom flash process.

Figure 2 illustrates the silicon cost comparison for the MTP solutions (external EEPROM, embedded flash, and Logic MTP). For small bit counts (typically less than 16 Kbits), Logic MTP is the most cost-effective. Between 16 Kbits and 128 Kbits of external EEPROM offers the best silicon cost solution, and over 128 Kbits of embedded flash wins. There are a number of variables that can affect the exact crossover point for the different technologies (die size and wafer cost in particular), but the analysis has yielded similar results across a broad range of ICs and process nodes.

Test costs for external EEPROMs are zero, as the devices should come completely tested from the manufacturer. Logic OTP has limited test costs, primarily due to the limited test capabilities of the architecture. Without the ability to electrically test the memory array, the test capabilities are limited to the support circuitry (digi-

256k

512k

-

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-

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-

16k

-

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-

2k

-

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Embedded Flash External EEPROM Logic MTP

-

Second only to the power considerations in portable systems is the overall cost implication.

There are three basic components to the total cost of ownership: • Silicon costs are the costs associated with the reduced net die per wafer by embedding NVM, the additional process costs, or the cost of acquiring an external component.

• Test costs are the costs based on additional production testing as a result of including NVM. • Qualitative costs are the costs that are subjective and include long-term reliability costs, operational support costs, risk, etc.

Silicon Cost Comparison

Silicon Cost per IC

Cost Comparisons

figure 2

-

current to permanently change the properties of the underlying silicon to program the NVM. For the Logic MTP and FTP solutions, the low power is driven by the fact that the available memory densities typically do not support code storage, so the access time requirement is not as stringent. This allows the Logic MTP and FTP NVM blocks to better optimize for power consumption at the expense of access time.

Memory Density (bits) Silicon cost comparison for multi-time programmable (MTP) NVM solutions.

tal control, charge pumps, etc.). For embedded flash, Logic MTP and Logic FTP, 100% electrical testing is possible. The overall test time is governed by the availability of test modes and capabilities in the specific NVM block.

The qualitative costs are by far the most difficult to analyze and will depend on each company’s application-specific requirements. Examples of qualitative costs that need consideration are the cost of supporting an extra component in the bill of materials for the system, the extra pins and board space required to support an external EEPROM, field failures resulting from an inability to test the NVM array, and lack of supply flexibility by being tied to a foundry-specific solution. In most cases, the qualitative cost analysis is used as a tie-breaker when two technology solutions are approximately equal.

Conclusion

Embedded NVM is widely available from a number of sources for use in portable designs.

For each application need, there is at least one potential option, and choosing the right selection requires not only a thorough understanding of the actual end-use model, but the relative merits of each technology option.

Virage Logic Corporation, Fremont, CA. (510) 360-8000. [www.viragelogic.com].

NOVEMBER 2008

37

wireless communications multi-band RF design

Maximize Range in Mobile Handsets with CMOS-onSapphire RF Switches You canâ&#x20AC;&#x2122;t build a multiband RF front-end switch with PIN diodes.

But think twice before going to GaAs.

by Dylan J. Kelly, Peregrine Semiconductor Corporation

M

Mobile handsets need to include many highselectivity filters in order to accommodate the growing number of frequency bands that must be handled by todayâ&#x20AC;&#x2122;s portable multimedia devices. Each handset generation has supported more frequencies, so the number of filters has grown, forcing designers to add switching elements in order to optimize the link budget.

As with all other components in a mobile handset, the cost, performance and form factor of these switches have been under great scrutiny because they operate in the highest-volume consumer market in the world. In addition, the switch manufacturer needs to have a technology roadmap that will allow it to accommodate new bands and functionalities for next-generation phones and beyond. Rising to this challenge, CMOS-on-sapphire RF switches, already available in single-pole, nine-throw (SP9T) configurations, offer the benefits of high linearity and ease of design in the face of shrinking footprints.

38

PORTABLE DESIGN

Adding Bandwidths, Changing Needs

For numerous regulatory, political and technical reasons, the frequency bands used for cellular communications varies across the Americas, Europe and Asia. As a result, products designed into the handset are required to offer multiband support. For instance, it is not uncommon for a GSM phone to support up to four bands (850/900/1800/1900 MHz). UMTS, generally regarded as a successor to GSM, will also require multiband support to enable global roaming and data transmission. When this multiband requirement is combined with the need for high integration, low power, small size and maximized link budget (high linearity), then the challenge facing systems designers becomes even more intriguing.

As cellular telephone service proliferates around the world (there are nearly 3 billion subscribers worldwide, with service reaching 80%

Ongoing Performance Challenges

In order to fill the technology gap created by the four-band requirement, handset designers began using IC-based solutions manufactured using UltraCMOS or GaAs. These technologies readily solved the numerous implementation problems with PIN diodes for multiband operation, and, thus, essentially replaced PIN diodes for the switching function.

In the early days of 3G wireless, designers added WCDMA to GSM/EDGE handsets.

This introduced a challenging third-order intercept (IP3) requirement of +68 dBm on the front-end switch in order to ensure network robustness. This means that the switch cannot generate a distortion signal larger than three trillionths of the WCDMA transmit signal, or the equivalent of one silicon atom in a half-mile string of atoms. UltraCMOS meets this difficult linearity requirement, and it has emerged as the leading solution for RF front-end switching applications due to the benefits of a low-loss, low-capacitance sapphire substrate combined with the fundamentally exceptional linearity of an intrinsic MOS device.

Recently, the need for more switching has been growing at an impressive speed. For instance, in 2007, the majority of 3G handsets shipped with quad-band GSM/EDGE and

wireless communications

of the worldâ&#x20AC;&#x2122;s population), frequency bands continue to be added. Due to the stringent performance requirements dictated by the range needed for effective network operation, highselectivity filters are used liberally in handset front-ends. It works this way: As the frequency band count increases, handset designers incorporate switching elements to optimize the link budget.

Back when handsets were single band, designers used PIN diodes for switching due to their high performance and low cost. However, once handsets combined GSM/EDGE and WCDMA, PIN diodes no longer met size and performance requirements. Requiring long quarter-wave transmission lines and large forward bias currents to operate, PIN diodes ceased to be effective with the introduction of quad-band GSM.

single-band WCDMA, which requires a SP7T switch. By 2008, the integration of three WCDMA bands was required, increasing the switch complexity to a SP9T (Figure 1). This trend of increasing switch complexity is expected to continue. For instance, at the time of this

figure 1

GSM/Edge 850

Front-end Module

GSM/Edge 950 GSM/Edge 1800 GSM/Edge 1900 GSM/Edge 850/900 GSM/Edge 1800/1900

SP9T

3GPP Band I/II 3GPP Band III/IV 3GPP Band V/VIII

Typical multiband handset system layout including a SP9T switch.

writing, there are now nine WCDMA bands defined worldwide, and that number is expected to climb.

By incorporating an UltraCMOS SP9T switch, designers can expect performance specifications, which often exceed those of GaAs-based SP9Ts, while meeting the demand for a smaller footprint. Unlike GaAs switches, UltraCMOS devices do not require external bypassing or filtering components, and are available as a flip chip IC, which NOVEMBER 2008

39

Selecting a System Design

SP9T switches in UltraCMOS and GaAs differ significantly in die size.

table 1

exploration Architecture er your goal eak directly Insertion Loss page, the TRX 865/1980 resource. hnology, TRX 960/2170 and products

d

requires less attention to control line routing and simplifies the printed circuit board (PCB) layout.

figure 2

True SP9T

SP5T+RX SP4T

Nominal (dB)

Nominal (dB)

0.60/0.80

0.55/0.85

0.60/0.80

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0.60/0.80

0.50/0.75

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0.8/1.0

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Nominal (dB)

Nominal (dBm)

TX 915 2fo/3fo @ +35 dBm

-50/-50

-36/-36

TX 1910 2fo/3fo @ +33 dBm

-50/-50

-36/-36

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-118

-103

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oration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, TRXtechnical 2140 page, IMD3 to a company's the goal of Get Connected is to put you-112 in touch with the right resource. Whichever -88 level of Get Connected will help you connect with the companies and products you are searching for.

DC Interface Nominal Nominal

nected

VDD Range

VIH Decoder

1.4V

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End of Article

Performance Comparison between UltraCMOS and GaAs SP9Ts.

Get Connected

with companies mentioned in this article. www.portabledesign.com/getconnected

40

PORTABLE DESIGN

An RF front-end switch must support WCDMA and GSM/EDGE signals simultaneously, so it must be the most linear element in the handset in order to ensure the expected range. In fact, it is required to be the most linear solid-state device of any high-volume application in the world. Handset systems designers are effectively faced with two choices in switches: UltraCMOS or GaAs. In addition to RF performance characteristics that will maximize range and optimize the link budget, some additional considerations include: voltage handling, die size, system size, ease of design, ESD tolerance.

Voltage Handling In UltraCMOS, the transistors on sapphire are dielectrically isolated from one another, so they can be placed in series (or stacked) to tolerate the very high voltages levels that can be present in an antenna switch. Although CMOS is low-voltage technology, peakto-peak voltage handling of 50V is readily tolerated. Additionally, on-chip bias generation provides for optimized performance and eliminates the need for external DC blocking capacitors.

Die Size Figure 2 compares a WEDGE SP9T implementation in UltraCMOS and GaAs. Note the significant difference in die size: the UltraCMOS die measures 1.43 mm2, which is approximately half the die size of the GaAs SP9T of 2.85 mm2. With the fine design rules of aluminum metallization and the flexibility to place FETs in any orientation, UltraCMOS allows RF switches to be implemented more compactly than GaAs. The complementary devices, analog control capability and MOS capacitors allow for control of both series and shunt RF FETs with a simple four-wire interface and low current drain. Figure 2 also shows the implementation areas for the 4:16 decoder in the two designs.

ESD Protection Because it is a CMOS technology, UltraCMOS offers an advantage of integrated ESD protection devices. As a result, devices manufactured using this process have Class 2 (2000V) HBM tolerance on con-

wireless communications figure 3

RF Performance Table 1 summarizes 43% Module Area Reduction 5.4mm the SP9T performance of the two technologies.

4.5mm Insertion loss performance is approximately equal, while linearity performance of UltraCMOS far exceeds that of GaAs. The wide VDD range of UltraCMOS aligns with existing Wire Bond SP7T Flip Chip SP9T SB WCDMA - QB GSM TB WCDMA - QB GSM handset supply voltages, and bias generators are in development for Moving to standard flip-chip packaging can reduce the module area by 43%, direct operation from even while adding more functionality to the switch (SP7T vs. SP9T). battery voltage or 1.8V supplies.

UltraCMOS RF switches provide tremendous value to handset front-ends, particularly in multiband applications where very high IP3 is required. As 3G handsets continue to increase in complexity, the switches will simultaneously need to scale to higher throw counts. We are likely to also see the integration of multiple switches on a single die.

These developments will fully exploit the advantages of UltraCMOS, and are increasingly difficult for GaAs switches to achieve.

In this market, an achievable, long-term improvement roadmap will likely prove to be a critical factor in a technologyâ&#x20AC;&#x2122;s success.

The good news is that UltraCMOS is positioned to handle the future needs of handset designers.

3.2mm

Ease of Design With flip-chip technology, the switch can be placed as a surface-mount device (SMD).

Since all of the other components in the FEM are typically SMDs, the need for any wirebonding equipment is eliminated. Shipped in tape-and-reel form, these flip-chip switches are inserted in the module using standard placement machines, resulting in the lowest manufacturing cost. Additionally, at less than 250 Îźm mounted height, flip-chips reduce the overall module thickness, which is critical to meeting the height demands for handset slimming.

Including shunting FETs on all ports in the UltraCMOS die also has tremendous impact on ease of module design and performance.

Because all signal paths are shunted to ground by the shunt FET, noise generated throughout the rest of the system has no impact on the active path. By controlling the impedances of the isolated ports at the plane of the switch ports, the module designer does not have to optimize the entire signal chain simultaneously, but can instead focus only on the active path. Shunt FETs also provide very high isolation performance, which relaxes the spurious requirements on transceivers, and ensure protection of receive SAW filters from high RF power and ESD events.

trol pins and 1500V HBM tolerance on RF pins, so UltraCMOS switches are highly robust against ESD damage. This reduces module fallout during manufacturing, and also dramatically reduces the required ESD circuitry at the antenna to meet stringent IEC61000-4-2 requirement, recovering circuit board area and eliminating some insertion loss.

4.7mm

System Size Switches that use standard flip-chip chipscale packaging technology can significantly reduce the footprint of handset front-end modules (FEMs). These FEMs are usually fabricated in costly low temperature cofired ceramic (LTCC), so reductions in module area directly impact the total solution cost. Figure 3 shows how migration from wirebonding to flip-chip reduced the LTCC substrate area consumed by 43% while simultaneously increasing the supported frequency band count from five to seven.

Peregrine Semiconductor, San Diego, CA. (858) 731-9400. [www.psemi.com].

NOVEMBER 2008

41

wireless communications multi-band RF design

Not Just a Mathematical Symbol: A Deeper Look at the “+” of HSPA+ The “+” brings the always-connected experience to par with a desktop Web browsing experience and enables a whole new world of personalized user features.

by Z iad Asghar, Operator and Strategy Manager, Chief Technology Officer, Wireless Business Unit, Texas Instruments

W

We’re entering a new realm of mobile possibilities, driven by advanced semiconductor solutions and innovations across the market. The mobile user experience is reaching exciting heights today, and capabilities will only increase as features and data transfer rates advance. Users are no longer tethered to their desks—the handset brings consumer electronics functionality and data management to the palm of their hands, and inspires connections without boundaries.

Significant changes made recently to the 3rd Generation Partnership Project’s (3GPP) highspeed packet access (HSPA) in the form of the HSPA+ standard, promise to drive HSPA’s capabilities to a new level to support this mobile evolution. Handset updates and air interface enhancements work together to bring the “+” to fruition and greatly improve the user experience.

While the “+” brings many exciting advancements to the table, what exactly does it mean for handset requirements and overall cost? Additional

42

PORTABLE DESIGN

antennas, multiple receive and transmit channels in the digital baseband (DBB), enhanced handset memory and more complex communication algorithms are just some requirements needed to drive HSPA+ to its full potential. Other features of the standard drastically alter handset cost, size and power consumption as well.

Let’s take a look at the salient features of HSPA+ and inspect what the “+” in HSPA+ truly means for handsets and the overarching mobile experience.

Foundational Enhancements: Speedier Data Rates, Greater Spectral Efficiency, More Efficient Power Use

PC-based DSL connections typically provide peak data rate transfers of 6 Mbits/s in the downlink and less than 1 Mbit/s on the uplink, and previous versions of HSPA provide peak rates of 14.4 Mbits/s in the downlink and 5.76

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Mbits/s in the uplink. HSPA+, however, allows data rates of up to 43.2 Mbits/s on the downlink and 11.5 Mbits/s on the uplink. The “+” brings the Web browsing experience to life on handsets through these dramatically increased data rates. It enables speedier multimedia transfers, higher-resolution video streaming and multiuser gaming, among other options.

More efficient power consumption with the “+” also improves talk and standby time, and reduces interference to increase network capacity. Features like continuous packet connectivity (CPC) and enhanced cell forward access channel (FACH) make this possible and help HSPA+ drive longer standby and talk time.

figure 1

Rel-99 WCDMA

DL: 384 Kbps UL: 384 Kbps

Broadband Downloads

Broadband Uploads

Rel-5 (HSDPA)

Rel-6 (HSUPA)

HSPA

Enhanced Voice and Data Capacity Rel-7

Rel-8 HSPA+

LTE and beyond

DL: 14.4 Mbps DL: 14.4 Mbps DL: 28.8 Mbps DL: 43.2 Mbps UL: 384 Kbps UL: 5.76 Mbps UL: 11.5 Mbps UL: 11.5 Mbps

exploration er your goal eak directly HSPA+ technologies enable faster data rates that bring browsing experiences to life on mobile handsets. page, the resource. hnology, and products

CPC reduces the control channel overhead, which is especially important in cases where a d small amount of data is transferred periodically, such as in the case of mobile Web browsing.

CPC employs discontinuous transmission and reception (DTX/DRX), which also reduces the interference that handsets experience in the mpanies providing solutions now downlink and uplink. Though DTX and DRX oration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, in previous versions to a company's technical page, the goal of Get Connected is to put you in touchare withpresent the right resource.

Whichever level of of HSPA, adGet Connected will help you connect with the companies and products you arevancements searching for. in HSPA+ enable handsets to enter nected power-saving modes more quickly and frequently, instead of requiring more time in full awake mode before entering DRX/DTX. Another version of CPC, high-speed shared control channel (HS-SCCH)-less transmission, does not require HS-SCCH transmission for the first hybrid auto request query (HARQ) transmission. HS-SCCH channel carries control information for HSDPA, introduced in Release 5 in the HSPA standards family. This feature, particularly important with smaller, Get Connected average packet sizes, uses blind detection of with companies mentioned in this article. www.portabledesign.com/getconnected the data format to lessen the downlink signal-

End of Article

44

PORTABLE DESIGN

ing requirements. This reduces the amount of control data received and transmitted, increases network capacity and extends battery life. Such enhancements make voice-over-Internet protocol (VoIP)-like applications more feasible, since the handset can switch to a low-power state during the gaps between data packets.

Enhanced CELL_FACH is a feature that enables HSPA capability in the uplink and downlink while the handset is in the CELL_FACH state.

This feature allows users to get packet access without any interruptions, which leads to a significantly improved user experience, faster data session establishment and speedier downloads.

Since the total download time is often dominated by the session setup time, reducing this component leads to a much better user experience.

Multicast/broadcast single frequency network (MBSFN) was also introduced as a part of HSPA+ advancements. MBSFN, a more enhanced version of multimedia broadcast multicast service (MBMS) introduced in previous iterations of HSPA, improves cell edge performance. MBSFN requires multiple base stations to transmit time synchronized data using the same scrambling code to provide significant signal-to-noise ratio (SNR) improvements, better spectral efficiency and higher data rates at the handset.

Together, these improvements in data rates, power consumption and spectral efficiency drive an “always connected” experience that brings faster, richer consumer electronics features to the palm of your hand (Figure 1).

More Substantial Advancements: MIMO and HOM

The majority of the changes discussed thus far address the DBB in the handset, enhance control and timing requirements, and add additional silicon area to the phone design. Given the progress in fabrication technology—where newer technology nodes are available every 18 months or so—these features provide significant advantages with a relatively small increase in cost, and are therefore more likely to be implemented earlier. There are additional features, however, that take more time to evolve and impact handset costs more substantially.

One such feature that has a larger, more longterm impact on handset costs is multiple-input multiple-output (MIMO). MIMO encompasses three different flavors: Spatial multiplexing: In spatial multiplexing, each antenna carries different data to increase throughput, either through a single user

wireless communications

or multiple users. Spatial multiplexing requires extremely efficient channel conditions.

Transmit diversity: Transmit diversity is the scenario where the same data is sent through each antenna stream to improve SNR at the receiver by combining the diverse streams.

Beamforming: Beamforming is the case where the antenna pattern is changed to optimize communication to the intended receiver.

MIMO requires channel rank to be transmitted back to the base station on the uplink to determine the number of streams the channel can support at any given time, along with precoding control Information (PCI) since 3GPP implements MIMO with precoding. This adds to the signaling overhead.

While MIMO introduces significantly higher data rates and other “pluses,” there are challenges to successful implementation. For operators, MIMO means better spectral efficiency and support for new user applications, which drives data revenue. However, manufacturers must subsidize handsets at a higher level because of cost increases associated with upgrades. Since MIMO requires multiple antennas, multiple receive and transmit chains and more complex algorithms in the DBB, the handset bill of material (BOM) increases a fair amount. In addition, antennas must be well spaced with the spacing inversely proportional to the frequency for each MIMO channel to be uncorrelated to gain maximum benefit from this technique, which can be difficult for the form factor of a handset.

In addition to MIMO technology, higher order modulation (HOM) support is included in HSPA+ by including 64 quadrature amplitude modulation (QAM) in the downlink and 16 QAM in the uplink. Peak achievable rates heighten as technologies move to higher-order modulations, since each transmitted symbol translates to a greater number of bits. For example, moving from 16 QAM to 64 QAM on the downlink means a single symbol translates into six (64 QAM) bits instead of four bits (16 QAM). This adds two additional bits, showing that we can transmit 50 percent more data using the same bandwidth, which allows for much more spectral efficiency. Similarly, for a single receive and transmit antenna or singleinput single-output (SISO) case with 64 QAM modulation, a peak rate of 21.6 Mbits/s can be achieved; but, introducing MIMO with 64 QAM doubles that peak rate to 43.2 Mbits/s.

Parallel to MIMO advantages, this increase in data rates with HOM support does not come

without effort. HOM requires better channel conditions and tighter requirements for handsets’ radio frequency (RF) sections. As technology moves to higher-order modulations, it packs the signal constellation with more and more symbols, enhancing the need for advanced RF components that accurately receive and interpret symbols.

The challenges posed by MIMO and HOM are being met by advancements in RF technology and greater integration in the form of system-on-chip (SOC) solutions, which pack all major components of a phone into a single chip. These two important factors bring forth the benefits of MIMO and HOM, and help keep handset costs low.

In addition to the features mentioned above, 3GPP is also considering the integration of more advanced, “type-3i” receivers that support interference cancellation. In the past, 3GPP specified rake-based (type-1) receivers, equalizer-based receivers (type-2) and equalizer-based receivers that support receive diversity (type-3). When properly implemented, the addition of type-3i receivers increases the potential to provide significant cell-edge performance improvement.

Exciting Opportunities Ahead

As industry experts solve data rate challenges and the always-connected experience continues to unfold, applications support unique mobile advancements across the globe in all sectors, including business, education, government, medical and personal. Mobile devices will allow for remote patient monitoring and record keeping. They will enable long distance learning and expand the classroom boundaries beyond villages and homes. With GPS and cameras, mobile phones will become the center of the social networking universe, the key to location-based services and the real-time tool for user-generated media.

The possibilities are both limitless and exciting, and driven greatly by the offerings that HSPA+ adds to the handset. The “+” brings the always-connected experience to par with a desktop Web browsing experience and enables a whole new world of personalized user features. With faster data rates, proficient power features and better spectral efficiency, this is more than just a mathematical symbol. The “+” of HSPA+ is the addition that makes handsets more ubiquitous, functionality-packed, personal and more indispensable than ever before.

Texas Instruments Inc., Dallas, TX. (800) 336-5236. [www.ti.com].

NOVEMBER 2008

45

product focus FET-Plus-Driver module Delivers >92% Peak Efficiency in Industry’s Smallest Package

DC/DC Converter Is Optimized for Powering Cell Phone RF Power Amplifiers

Fairchild Semiconductor has introduced XS DrMOS, the industry’s first high-performance and space-efficient 6 mm x 6 mm DrMOS solution for synchronous DC/DC buck regulators for computing, game console and consumer Point-of-Load (POL) applications.

The FDMF6704 is a FET-Plus-Driver module that replaces one driver IC, one high-side MOSFET, two low-side MOSFETS and one bootstrap Schottky diode in an ultra-compact package. The thermally enhanced 6 mm x 6 mm MLP package saves 84 percent board space compared to discrete solutions and 44 percent compared to 8 mm x 8 mm MLP packaged DrMOS modules. It delivers 92 percent peak efficiency, enabling applications to meet stringent energy-efficiency specifications such as ENERGY STAR, Climate Savers and Green Grid.

Packed with advanced features, the FDMF6704 has been designed and optimized to work with a wide variety of controllers in the market. It is compatible with both Tri-State and Non-Tri-State PWM controllers. To further ensure compatibility, the FDMF6704 has its PWM threshold levels tailored to meet a broad range of controllers available in the market. A 5V gate driver circuit and an improved PCB interface guarantee higher performance from this compact module. Fairchild’s advanced SyncFET technology is integrated within the module’s low-side MOSFET further ensuring higher performance. The module is also furnished with a diode emulation (SMOD) function for increased light loading efficiency.

Fairchild Semiconductor’s DrMOS, the FDMFxxxx series, is a complete family of fully optimized, integrated FET-plus-Driver multichip power stage modules designed for multiple synchronous buck converter applications. These multichip modules are designed to achieve the optimal solution for a given application by using components that are matched electrically, thermally and mechanically.

The FDMF6704 utilizes lead-free (Pb-free) terminals and has been characterized for moisture sensitivity in accordance with the Pb-free reflow requirements of the joint IPC/JEDEC standard J-STD-020. All of Fairchild’s products are designed to meet the requirements of the European Union’s Directive on the restriction of the use of certain substances (RoHS).

The FDMF6704 is sampling now, priced at $1.50 in 1000-lot quantities.

Intersil Corporation has announced a new DC/DC converter for RF power amplifiers that provides the industry’s fastest start up from standby mode with very low current and excellent transient load response.

The new ISL9109 is a 1.6 MHz synchronous step-down regulator designed to resolve the inefficiencies often seen with mobile RF power amps, particularly at low output levels. The device incorporates power switches that deliver 1.5A output and features a standby mode that enables rapid startup.

This rapid start up is achieved even though the part draws only 22 microamps standby current (typical) and provides the highest possible light load efficiency while reducing power draw and maximizing battery. When powered from a Li-ion battery, the ISL9109 operates at 9095% efficiency in powering an RF PA. The ISL9109’s supply voltage ranges from 2.7V to 5.5V to enable designers to use a single Li+ cell, three NiMH cells or a regulated 5V input. The ISL9109’s 1.6 MHz pulse-width modulation (PWM) switching frequency also allows the use of small external components. When in standby, the IC’s band-gap reference is powered up, which assists in a rapid power-up when the EN (enable) pin is reasserted high.

Other features of the ISL9109 include soft-start, overcurrent protection and thermal shutdown. In addition, its small 2 mm x 3 mm DFN form factor saves space in any cell phone or modem card design. The complete converter occupies less than one centimeter squared.

The ISL9109 is available now in 8-Ld DFN packages and are priced at $1.93 each in 1,000-piece quantities.

Intersil Corporation, Milpitas, CA. (408) 432-8888. [www.intersil.com].

Fairchild Semiconductor Corporation, South Portland, ME. (207) 775-8100. [www.fairchildsemi.com].

Multifunction PMICs for Li-Ion/Polymer Battery-Based Applications Linear Technology Corporation has announced the LTC3576, the newest member in a family of multifunction power management ICs for Li-Ion/Polymer battery-based applications including HDD-based media players, digital cameras, personal navigation devices, PDAs, smart phones and automotive-compatible portable electronics. The LTC3576 features a bidirectional switching power manager with input overvoltage protection and USB On-The-Go (OTG) functionality, a stand-alone battery charger, three high-efficiency synchronous buck regulators, an ideal diode, I2C control, plus an always-on LDO, all in a compact, low-profile 4 mm x 6 mm QFN package.

The LTC3576’s USB-compatible bidirectional switching regulator features programmable input current limits of 100 mA and 500 mA, as well as a 1A wall adapter input current limit. For fast charging, the LTC3576 converts nearly all of the 2.5W available from the USB port to charging current, enabling up to 700 mA from a 500 mA limited USB supply and up to 1.5A from a wall adapter. The bidirectional switching regulator can also take power from the battery to generate 5V and deliver up to 500 mA for USB OTG applications without any additional components. The IC provides an overvoltage protection (OVP) control circuit that prevents damage to its input from the accidental application of voltages as high as 66V. The OVP circuit can protect the USB port even when the IC is providing power for USB OTG. The LTC3576’s PowerPath control with automatic load prioritization seamlessly manages power flow between a variety of input power sources such as a wall adapter or USB port and the Li-Ion/Polymer battery while preferentially providing power to the system load. The IC’s “instant-ON” operation ensures system load power even with a discharged battery. An internal 180 mOhm ideal diode plus optional external ideal diode controller provide a low loss power path from the battery to the load when input power is limited or unavailable.

The LTC3576 is available from stock in a compact, low-profile (0.75 mm) 4 mm x 6 mm 38-lead QFN package. Pricing starts at $4.80 each for 1,000-piece quantities.

Linear Technology Corporation, Milpitas, CA. (408) 432-1900. [www.linear.com].

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Maxim Integrated Products has introduced the MAX8819A highly integrated powermanagement IC (PMIC). This device integrates a singlecell, lithium-ion (Li+)/lithiumpolymer (Li-Poly) charger with proprietary Smart Power Selector circuitry that seamlessly distributes power within the system. To reduce BOM cost, the MAX8819A integrates three 2 MHz step-down converters and one step-up converter with serial-step dimming control for powering two to six WLEDs. Offering a solution footprint of less than 90 mm2 with a low 1 mm height, the MAX8819A is the smallest complete power-management solution for battery-operated devices. This device is ideal for use in portable media players, MP3 players, GPS devices, and other handheld applications.

The MAX8819A’s Smart Power Selector circuitry manages power distribution between a battery, USB/AC-to-DC adapter and system load.

When a USB or AC-to-DC adapter is connected, the input power that is not used by the system load is used to charge the battery. In addition, Smart Power Selector circuitry allows the system to operate with no battery or a deeply discharged battery. The Smart Power Selector also provides thermal-limiting circuitry that reduces the battery-charge rate to prevent the charger from overheating. All necessary power switches and current-sense circuitry are included on the chip—no external MOSFETs are required.

Integrating one 28V step-up and three fully synchronous, step-down switching regulators, the MAX8819A offers up to 95% efficiency for the full load range to maximize standby and runtime operation. The stepdown regulator’s high 2 MHz switching frequency allows the use of small capacitors and inductors with a low 1 mm profile.

The MAX8819A is available in a thermally enhanced, space-saving, 4 mm x 4 mm x 0.8 mm, 28-pin TQFN package that is fully specified over the -40° to +85°C extended temperature range. Prices start at $3.65 (1000-up, FOB USA). An evaluation kit is available to speed designs.

Maxim Integrated Products, Inc., Sunnyvale, CA (408) 737-7600 [www.maxim-ic.com]

Lighting Management IC for Smart Phones and PMPs ON Semiconductor has introduced the NCP5890—a unique lighting management device that integrates LCD backlighting, fun light controls and ambient light sensing into a tiny 3 mm x 3 mm x 0.5 mm package.

With its 30V output capability, the device drives LEDs in series to achieve homogeneous backlight over the LCD screen. In addition, the NCP5890 controls three sets of white LEDs or RGB LEDs to create fun light patterns on keypads or chassis in a unique combination with backlighting. The driver also extends battery life by adjusting the backlight current according to the ambient light level. The NCP5890 is a dedicated solution for compact smart phone and portable media player applications.

“Larger LCD screens and LED lighting effects are popular features in today’s portable electronics,” said Manor Narayanan, vice president and general manager of ON Semiconductor’s Digital and Consumer Products Group. “To meet all these illumination requirements, hardware designers commonly need to utilize several LED drivers. With restricted board space, achieving these more sophisticated lighting effects has often required extensive software programming and microcontroller resources. ON Semiconductor now provides a simpler, single chip, silicon solution with multiple command-based light effects that enable hardware engineers to meet their specific lighting and power design targets.”

Featuring high overall power efficiency of up to 90 percent at 1.3 MHz oscillator frequency, the NCP5890 inductive boost LED driver delivers up to 30V at output. It can drive up to eight LEDs in series for LCD backlight and fun lighting. The device supports ambient light sensing, a feature required in smart phones to reduce power consumption and increase user comfort.

The NCP5890 also features built-in gradual dimming that creates fade-in and fade-out effects. Both ambient light sensing and gradual dimming are automated built-in functions that can be activated with simple I²C commands. The device supports the I²C protocol with two separate address options. The integrated driver also extends battery power with a true cut-off function that limits the leakage output current in shut-down mode.

Available in the ultra-thin 3.0 mm x 3.0 mm x 0.55 mm µQFN-16 package, the NCP5890 is budgetary priced at $1.30 per unit in 3,000 unit quantities.

ON Semiconductor, Phoenix, AZ. (602) 244-6600. [www.onsemi.com].

Industry’s Smallest 1A, 4 MHz Synchronous Step-Down DC/DC Converter for Portable Applications National Semiconductor Corp. has introduced the industry’s smallest 4 MHz synchronous step-down DC/DC converter that provides up to a 1A output current over an input voltage range of 2.3V to 5.5V. The LM3691 DC/DC converter is optimized for powering high-performance processors from a single Li-Ion cell battery in mobile phones, personal media players and other mobile devices. A member of National’s PowerWise energy-efficient product family, the LM3691 features peak efficiency of 95 percent, low quiescent current to maximize battery life and output voltage precision of ±1 percent to power baseband and nextgeneration applications processors.

National’s new LM3691 DC/DC converter is offered in a micro SMD package and features high switching frequency up to 4 MHz that enables use of miniature 1 μH multilayer inductors and tiny 4.7 μF capacitors for a solution size of less than 15 mm squared. Several fixed output voltage options are also available.

National’s LM3691 DC/DC converter features excellent transient performance of ±40 mV for stable output voltages. An integrated mode-control pin allows the design engineer to select forced pulse-width modulation (PWM) mode or auto mode, which changes modes between economy or ECO (gated PWM mode) and PWM automatically, depending on the load. In ECO mode, the LM3691 offers superior efficiency and very low quiescent current at 63 μA under light load conditions. ECO mode extends the battery life through reduction of the quiescent current during light load currents and system standby. The LM3691 is offered in a 6-pin, 1.26 mm by 1.56 mm micro SMD package.

National Semiconductor Corporation, Santa Clara, CA. (408) 721-5000. [www.national.com].

NOVEMBER 2008

47

product focus

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48

PORTABLE DESIGN

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PMICs for OMAP35x Processor-Based Designs Building on its power management portfolio targeting embedded processor designs, Texas Instruments Incorporated has introduced three fully integrated power management and signal chain companion chips to support all system power requirements of an OMAP35x processor-based design. Combining leading power management circuits with TI’s low-power embedded processors results in optimized power and performance, leading to longer battery life and system run-time.

The TPS65920, TPS65930 and TPS65950 devices reduce board space and efficiently manage system power and control for an OMAP35x processor. The TPS65950 supports up to 14 channels of power management conversion. In addition to integrated 3 MHz DC/DC converters and low-noise LDOs, it includes a dual audio codec and drivers, monitor and control features, a battery charger, an LED driver, a 10-bit, 3-input analog-to-digital converter, vibra and keypad functionality, a high-speed USB transceiver with integrated 5V power supply and an I2C communications interface—all in a 7 mm x 7 mm BGA package. The TPS65920 and TPS65930 devices, which offer a subset of features of the TPS65950, come in a 10 mm x 10 mm package and support up to 8 voltage rails.

The new power companion devices add to the company’s growing number of single- and multiple-output voltage regulators that meet the needs of OMAP35x processors. In addition to its TPS659xx family, TI has shipped millions of its tiny, single-output TPS6235x family of 3 MHz DC/ DC converters and its multi-output TPS65023 converter, which provide increased flexibility in system optimization for OMAP35x designers.

The TPS659xx, TPS65023 and TPS6235x devices use a dedicated I2C communications interface to enable TI’s SmartReflex power and performance management technologies, resulting in additional power savings.

Texas Instruments Inc., Dallas, TX. (800) 336-5236. [www.ti.com].

Step-Down Regulators Target Portable Designs Micrel Inc. has announced the MIC23030 and MIC23031, the newest additions to the HyperLight Load family of synchronous step-down regulators. The patented architecture implemented in the MIC23030/1 delivers state-of-the-art transient performance and just 3 mV of output voltage ripple for portable products.

The regulators have internal MOSFETs able to deliver up to 400 mA output current while consuming just 21 μA of quiescent current inside a tiny 1.6 mm x 1.6 mm Thin MLF package. These HyperLight Load step-down regulators achieve up to 93 percent peak efficiency and an impressive 88 percent efficiency under a 1 mA load.

“Portable system designers continue to optimize power efficiency to extend battery life while delivering high-performance features customers demand,” noted Andy Khayat, Micrel’s director of marketing for portable products. “Micrel’s patented HyperLight Load architecture provides very high efficiency for low power modes and fast load transient response to maintain the precise supply rail voltages when power demand increases.”

The MIC23030 and MIC23031 require just three external components and operate at 8 MHz and 4 MHz respectively. These devices support a solution footprint of just 27 mm2 and 29 mm2 both under 0.6 mm in height. Featuring an operating input supply range from 2.7V to 5.5V, both regulators are suitable for applications powered by single cell Li-Ion battery or 5 VDC source such as a USB port. Output accuracy is an impressive +/- 2.5 percent over the operating junction temperature range of -40° Untitled-16 to +125°C. Internal protection features include under voltage lockout, current limit and thermal shutdown.

The MIC23030/1 are currently available in adjustable and fixed output options of 1.0V, 1.2V, 1.5V and 1.8V with pricing starting at $0.55 for 1K quantities.

1

8/11/08 5:46:38 PM

Micrel, Inc., San Jose, CA. (408) 944-0800. [www.micrel.com].

Untitled-1 1

NOVEMBER 4/13/08 2008 3:57:29 49 PM

products for designers TI Rolls Out Low-Cost 32-bit MCU Family Texas Instruments has announced a new series of 32-bit TMS320F280xx microcontrollers (MCU) starting at less than $2 in volume. Developed under the code name “Piccolo,” the new F280xx MCUs feature architectural advancements and enhanced peripherals in package sizes starting at 38 pins to bring the benefits of 32-bit real-time control to applications typically unable to justify the associated cost.

Real-time control implements advanced algorithms, fast interrupt response times and minimal latency for greater system efficiency and precision in industrial, consumer and automotive applications such as solar power micro-inverters, LED lighting, white goods appliances and hybrid automotive batteries.

The F280xx series of Piccolo MCUs will feature advancements such as a programmable, floating-point control law accelerator (CLA) designed to offload complex high-speed control algorithms from the main C28x CPU. The CLA, which will be available starting with the F2803x series, frees the CPU to handle I/O and feedback loop metrics—resulting in up to a 5x performance increase for common closed-loop applications.

TI’s enhanced pulse width modulators (ePWM) support the industry’s highest resolution with frequency modulation down to 150 pico-seconds to enable more control over harmonics and reduce sample-to-output delay—a critical factor to avoid missing the falling edges of signals. At 4 MSPS, Piccolo devices’ on-chip, 12-bit ADC is up to four times faster than the closest competitor, allowing designers to reduce the complexity and cost of the design process, while achieving excellent accuracy and performance.

The first Piccolo microcontrollers, the F2802x series, will be available for sampling in December and will include 40 to 60 MHz variations, up to 128 Kbyte flash memory, 12-bit ADC, ePWM and peripherals such as: communications protocols, on-chip oscillators, analog comparators and general-purpose I/Os. F2802x devices will be priced at sub $2 each in volume.

Texas Instruments Inc., Dallas, TX. (800) 336-5236. [www.ti.com].

SoC Processor for Digital Content Management

LEDs for Ultra-Compact Projectors

MosChip Semiconductor has announced a new processor for digital content management, which it claims is the only AV 1394 secure storage controller with a flash card interface and support for multiple storage interfaces. MosChip’s System-on-a-Chip (SoC) is based on an ARM9 processor and is designed as a next-generation digital content manager and AV stream router to manage AV streams over 1394 / FireWire and USB connections for fast and reliable storage.

MosChip’s MCS60C80 Digital Content Management Processor is the only AV 1394 secure storage controller with a flash card interface and support for multiple storage interfaces: Secure Digital, Compact Flash and Memory Stick. Many of the functions required to move video content are handled directly in on-chip hardware functions controlled by the processor. The MCS60C80 performs the majority of the work requiring only minimal servicing, which leaves the device’s main processor free for other chores.

The MCS60C80 also allows recording to an attached ATA, USB or flash card device or to an external (1394) optical or disk device. Advanced AES encryption / decryption engines allow for protection of content while it is flowing through the MCS60C80 without the need of the main processor’s intervention. It also incorporates the Digital Transmission Content Protection (DTCP) Specification, which defines a cryptographic protocol for protecting AV entertainment content.

Embedded designers/engineers can use the MCS60C80 as host processor or a coprocessor to enable its various features in target applications. Integration of MosChip’s new processor empowers designers with a truly low power and portable application to design consumer AV devices that perform direct video playback and editing through a PC file system.

The new processor also uses field-proven firmware thus limiting design obstacles and speeding time to market.

The MCS60C80 will be available for sampling in October 2008. Pricing will be $30 in quantities of 10,000.

Luminus Devices has announced that its PhlatLight LEDs are powering two of the newest portable LED-based projectors, the Samsung P400 Pocket Imager and LG Electronics’ HS-102 Ultra-Mobile Projector.

Both projectors are lamp-free, weigh less than two pounds and fit in the palm of a hand.

The PhlatLight PT54 LEDs used in both units enable brightness to reach and exceed 150 lumens, a breakthrough for pocket projectors. The pure RGB color from the PhlatLight LEDs produces a brighter more vivid image than the ANSI brightness specs would suggest, for a picture that’s easily viewable when projected to a 40” size even in a well-lit office.

Environmentally friendly, PhlatLight LEDs are free of hazardous materials such as mercury or lead and are leading the way for energy-efficient LEDs to be used in high-brightness applications never before possible with LEDs. These projectors consume approximately one-third the power of comparable lamp-based projectors and produce an instant-on image at full brightness without the cost and inconvenience of lamp replacement. Both projectors were recently demonstrated at IFA in Berlin and are launching to worldwide distribution. The Samsung P400 is now shipping in the U.S. Luminus began manufacturing its patented PhlatLight LEDs for TVs in 2006, and PhlatLight LEDs remain the only LEDs bright enough to replace arc lamps. PhlatLight LEDs are unique in that they are larger than conventional LEDs and designed to operate at significantly higher intensity.

Projectors illuminated by PhlatLight LEDs produce more than fifty percent wider color gamut than the NTSC standard, and the pure, primary colors sequentially pulsed at high speeds, provide ultra-fast color refresh for stable, accurate colors and a smooth picture with superior motion quality.

Moschip Semiconductor USA, Santa Clara, CA. (408) 737-7141. [www.moschip.com].

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Luminus Devices, Inc., Billerica, MA. (978) 528-8000. [www.luminus.com].

Keithley Instruments has introduced the Model 2308 Portable Device Battery/Charger Simulator, a dual-channel battery- and charger-simulating power supply designed to provide the lowest cost testing of both the growing range of mobile phones with new, complex transmission schemes and other types of new portable devices that consume extremely low amounts of power.

The Model 2308’s fast transient output response maximizes production yields by maintaining a stable voltage level under dynamic loading conditions. In addition, its measurement engine enables more accurate characterization of both full power operation and low current sleep modes for quantifying power consumption so that design and manufacturing can ensure that battery life of the latest portable electronic devices is maximized.

The Model 2308 is optimized for ultra-fast test times, allowing manufacturers to lower their cost of test.

Unlike conventional power supplies, the Model 2308 features extremely fast recovery even when load currents change by a factor of 10 or greater.

This can happen when a portable device or component transitions near-instantaneously from a sleep or standby state to a full power operating state and then returns to the original state. If the load pulse is too short, the conventional power supply may never return to its stable output level during the pulse. Even with long test leads, which add substantial inductance to the load circuit between the power supply and the device under test (DUT), the Model 2308 maintains a stable output voltage in response to pulse loads with a transient voltage drop of under 90 mV and a transient recovery time of under 35 µs. This is critical for mobile phones with pulsed-mode operation such as new EDGE, WiMAX and future LTE mobile devices.

Maintaining a constant output voltage ensures that the DUT does not turn off during testing and that it draws sufficient power to operate properly, thus avoiding false failures due to inadequate sourcing. Furthermore, an excessive overshoot voltage transient can damage components leading to premature device failures. The unique, specialized, Model 2308 has the fast transient response essential for maximizing production yield and product quality by preventing false failures related to conventional sourcing, which cannot provide the high-speed response necessary to maintain a constant output under fast-changing loads.

The Model 2308 Portable Device Battery/Charger Simulator is priced at $2,795, and availability is three weeks.

Keithley Instruments, Inc., Cleveland, OH. (440) 248-0400. [www.keithley.com].

Ultra-Small Portable Audio Codec Improves Battery Life up to Two Hours

NanoPOWER and nanoSIZE FPGAs Target Global Portable Designs

Consuming only 5.1 mW quiescent power in playback mode and featuring a unique bimodal, patent-pending Class H technology, Cirrus Logic’s 24-bit CS42L55 portable audio codec reduces power consumption by nearly 50 percent compared to Class A/B amplification found in portable applications today. This innovation helps to increase battery life operating at standard audio sample rates and delivering power into headphones in real-world audio playback conditions by as much as two additional hours while maintaining high audio quality. The CS42L55 features an ultra-small 5x5 mm footprint, and at 0.45 millimeters in height, it is one of the thinnest portable audio codec available today.

The CS42L55 features automatic, supply-adjusting bimodal Class H headphone driver technology and an innovative charge pump architecture with ground-centered outputs. These technologies have become the innovative foundation for Cirrus’ line of portable audio products and allow its codecs to achieve ultra-low power consumption and EMI performance well below industry requirements.

Based on 24-bit advanced multibit Delta-Sigma technology, the CS42L55 operates from a single 1.8V or 2.5V power supply and can deliver 1 VRMS line output from a 1.8V supply. When driving headphones from the same supply it can deliver 17 milliwatts per channel of highquality, 96 dB dynamic range audio. The CS42L55 also provides a 2:1 stereo input multiplexer and a USB master clock input and supports sample rates up to 48 kHz. The CS42L55 also features analog volume control that helps to increase performance and reduce the overall noise floor. Further, pseudo differential outputs allow for routing signals while reducing noise coupling in analog signals.

The CS42L55 is available today in a 36-pin xQFN package, priced at $1.73 in quantities of 10,000.

Actel Corporation has introduced nano versions of its IGLOO and ProASIC3 FPGAs, targeted at the high-volume portable consumer market.

The new devices take power consumption down to as low as 2 µW, and package size to as small as 3x3 mm; extend the commercial temperature range to sub-zero; and offer zero lead time delivery of packaged goods. Actel is offering over 50 variants of its nano FPGAs for less than $1.

The company is also offering support for known good die business to meet the lead times and volume demands of portable applications, such as smart phones, PDAs, personal medical monitoring devices, personal navigation devices, eBooks and portable point-of-sale tools.

With power consumption as low as 2 µW, IGLOO nano FPGAs range in densities from 10k to 250k system gates. These devices support 1.2V to 1.5V core and I/O operation, ultra-low-power Flash*Freeze mode with bus hold capability, as well as advanced I/O features, such as hot swapping and Schmitt trigger inputs.

Actel will offer its low-power IGLOO nano FPGAs in a 3x3 mm package, the smallest package for any programmable logic device on the market.

Complementing its existing portfolio of small 4x4 mm, 5x5 mm, 6x6 mm and 8x8 mm packages, the new tiny package makes IGLOO nano FPGAs an even more compelling choice for power-sensitive, space-constrained handheld devices.

Both IGLOO nano and ProASIC3 nano FPGAs, in densities of 60k, 125k and 250k gates, are immediately available in volume. Additional densities will be available in volume in early 2009.

In high volume, pricing for the 10k-gate A3PN010 starts at $0.69 in a QNG48 package and $0.49 in known good die.

Cirrus Logic, Austin, TX. (512) 851-4000. [www.cirruslogic.com].

Actel Corporation, Mountain View, CA. (650) 318-4200. [www.actel.com].

NOVEMBER 2008

51

products for designers

Power Supply Optimized for Testing of Portable Battery-Powered Devices

products for designers

High-Performance Floating-Point DSPs with Dedicated Hardware Accelerators Analog Devices, Inc. has broadened its new fourth-generation SHARC family, the industry’s highest-performance floating-point digital signal processors, by introducing a series of processors for industrial and instrumentation, automotive audio and home theater applications.

Sharing the same higher-performance design as the pro audio version of the SHARC 21469 (commercial temperature range) introduced in October, at up to 450 MHz/2700 MFLOPS these newest offerings more than double the computational performance of the previous SHARC generation. Key features across the lineup include hardware accelerators, increased on-chip SRAM, a high-speed DDR2 SDRAM external memory interface and link ports.

The SHARC processors introduced at Electronica include: the 21469 (industrial temperature range packaging) for industrial and instrumentation; the 21469W, 21465W and 21462W for automotive audio; and the 21467 for home theater. Like their predecessors, this newest generation of SHARC is based on a single-instruction multiple-data (SIMD) core that supports 32-bit fixed-point as well as 32-/40-bit floating-point arithmetic formats, making them particularly suitable for high-performance applications.

Like the pro-audio-optimized version that debuted last month, these new fourth-generation SHARC processors offer more than two times the 32-bit floating-point family’s performance compared with earlier SHARC offerings. A key contributor to this performance increase is the addition of hardware accelerators for widely used signal processing operations: FIR (Finite Impulse Response), IIR (Infinite Impulse Response) and FFT (Fast Fourier Transform).

Additional performance-boosting features include: an increase of 60 percent in on-chip SRAM up to 5 Mbits; a new Variable Instruction Set Architecture (VISA) feature that allows a reduction in instruction opcode size, freeing up as much as 30 percent of memory space for application code; and a high-speed DDR2 SDRAM external memory interface. Link ports enable data transfers between two SHARC processors, and provide a parallel command interface for faster data movement than is enabled by the processors’ serial peripheral interface (SPI).

The new SHARC processors will be available to sample in Q1 2009.

Pricing will range from the 450 MHz version of the 21469 for $31.50, to the 400 MHz version of the 21467 for $28.50. All prices are based on 1,000-unit quantities.

High-Resolution, Low-Power Delta-Sigma ADCs Microchip Technology Inc. has announced a new series of lowpower, high-resolution Delta-Sigma Analog-to-Digital Converters (ADCs). The MCP3422, MCP3423 and MCP3424 (MCP3422/3/4) ADCs provide 18-bits of resolution and consume only 135 μA at 3V continuous conversion. The multi-channel devices have an integrated voltage reference, Programmable Gain Amplifier (PGA) and oscillator on board, and are available in packages as small as a 2 mm x 3 mm DFN. They are ideal for portable measurement applications in the industrial, medical, consumer and automotive markets, among others.

The MCP3422/3/4 ADCs’ low current consumption enables the end application to use less power, which results in longer battery life. With their integrated PGA, voltage reference and oscillator, the ADCs eliminate the need for numerous external components, providing a smaller overall design footprint and making it easy for designers to create smaller applications.

Example applications for which the MCP3422/3/4 ADCs are appropriate include those in the industrial (portable weigh scales, instrumentation, handheld meters and multimeters); medical (portable heart-rate monitors, blood-pressure monitors and glucose meters); consumer (weigh scales, handheld meters); and automotive markets (sensor interfaces, fuel gauges), among others.

Microchip also announced the MCP3424 Evaluation Board (Part # MCP3424EV), to help designers get started using the new ADCs in their designs. The board enables the user to evaluate the performance of the MCP3424 ADC by interfacing to the PICkit Serial Analyzer (Part # DV164122). It is available at www.microchipdirect.com today for $15.

The MCP3422 ADC is available in 8-pin SOIC, MSOP and 2 mm x 3 mm DFN packages today, for $2.06 each in 10,000-unit quantities. The MCP3423 ADC is available today in 10-pin MSOP and 3 mm x 3 mm DFN packages, for $2.22 each in 10,000-unit quantities. Production quantities of the MCP3424 ADC are available today in 14-pin TSSOP and SOIC packages for $2.80 each in 10,000-unit quantities.

Microchip Technology Inc., Chandler, AZ. (480) 792-7200. [www.microchip.com].

Analog Devices, Norwood, MA. (781) 329-4700. [www.analog.com].

3G/4G Femtocell PAs ANADIGICS, Inc. has announced immediate availability of its AWB7220 power amplifier (PA), the first in the company’s new line of products targeted at the 3G and 4G femtocell markets. ANADIGICS’ new AWB7220 PA is a highly isolated, fully matched, multi-chip module (MCM) designed and engineered specifically for use in femtocell and customer premises equipment (CPE) worldwide.

Femtocells solve the problem of weak or nonexistent wireless broadband signals in SOHO environments by connecting users’ mobile devices to their carrier’s network through a high-speed Internet link. Because they are inexpensive and easy to install and operate, sales of femtocells are expected to ramp up significantly in 2009. Industry analyst firm ABI Research sees the femtocell market increasing to double-digit millions in volume during 2010. ABI’s Stuart Carlaw, vice president and research director, states, “We expect cellular-based femtocells to take the baton from UMA- and SiP-based Wi-Fi solutions by 2013, seizing 62% of the 103 million unit access point market.” ABI Research also expects femtocell prices to drop to the range of wireless routers in 2010.

ANADIGICS’ first femtocell product, the AWB7220, is a 4.5-volt module that operates from 2.5 GHz to 2.7 GHz with extended operational capability between 2.3 GHz and 2.5 GHz. Designed specifically for OFDMA waveforms such as 802.16 WiMAX, the new module delivers 28 dBm (P1dB = 35 dBm) output power with 30 dB of gain.

The AWB7220 is manufactured using ANADIGICS proprietary InGaP-Plus technology that provides state-of-the-art reliability, temperature stability and ruggedness. Its self-contained 7 mm x 7 mm x 1 mm surface mount package incorporates matching networks optimized for output power, efficiency and linearity in a 50Ω system.

Anadigics, Inc., Warren, NJ. (908) 668-5000. [www.anadigics.com].

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SMT Discrete Semiconductors for High-Performance Mixer and Detector Applications

Austin Semiconductor, Inc. has introduced a smaller, more compact 7.5 cm3 (31 mm sq x 7.8 mm max height) ruggedized Solid State Disk (SSD). The newly redesigned Solid State Disk (SSD) supports an embedded Integrated Drive Interface (IDE), PIO/4 interface, has MTBF of more than two million hours and is ideal for harsh environment operation (0-70°C operations with future -40° to +85°C).

“Our unique SSD is designed for use in low-power, ruggedized environments. The device is intended for direct board mounting and has redundant board interconnects to increase the overall product reliability, which makes it ideal for handheld applications,” says Frank Muscolino, president of Austin Semiconductor.

The solid state disk is based on a proprietary package (die) stacking technology to create an extremely space-conscious, robust Solid State Disk. The SSD is capable of operating in harsh, vibration-prone product platforms such embedded computing applications, heavy transportation, ultra portables, handhelds, mobile computing, digital radio, high-speed networking & enterprise applications, as well as military, aerospace and industrial applications.

Skyworks Solutions, Inc. has introduced the industry’s smallest and lowest-profile packaged silicon radio frequency (RF) Schottky diodes in a 0201 surface mount technology (SMT) footprint. This new family of ultra-miniature and high-performance packaged diodes, which is priced comparably to traditional plastic packages, is ideal for a wide range of high-volume and cost-sensitive applications including CATV/DBS set-top boxes, microwave radios, RFID tags, wireless infrastructure and embedded WLAN 802.11a/b/g/n modules.

The SMS7621-096 is a low barrier silicon RF Schottky diode that is well suited for a variety of applications including high-sensitivity RF power detection, video sampling circuits and low conversion loss balanced mixers. The SMS7630-093 is a very low barrier zero bias silicon RF Schottky diode that is ideal for ultra-sensitive video detectors and sampling applications. Very low package parasitic impedance, forward voltage and junction capacitance makes both devices well suited for RF and microwave signal detection applications up to 26 gigahertz (GHz)—traditional plastic packaging is typically only specified up to 10 GHz. Skyworks’ low-cost packaging technology results in an ultra-miniature 0201 form factor diode with overall height of less than 0.3 millimeters— able to fit into a board area that is over 30 percent smaller than other packaged diode solutions. The devices are protected with a stress absorbent passivation for high reliability, and are compatible with existing high-speed 0201 surface mount assembly equipment. Leadless diode packaging also allows for greatly improved high-frequency operation and tighter parameter distribution when compared to plastic-packaged alternatives. Both diodes can operate over a wide temperature range of -65° to +150°C and are well suited for both military and commercial applications.

Sample quantities are available now in bulk and tape and reel packaging with volume production release scheduled for November 2008.

Features include: • SLC NAND Flash Controller • (2) stacks, each containing (1, 2 or 4) NAND components • Each NAND component, either a 4, 8 or 16 Gb device, based on the use of single silicon and stacked silicon solutions • Providing a total bit density of either 4,8 or 16 GB • Controller contained in base interposer • Fast ATA host to buffer transfer rates supporting True IDE, PIO/4 mode support • 512 byte Sector Buffers • Flash Memory power-down logic • ECC correction = 6 bytes within a 512 byte sector • Automatic Sleep Mode • Burst Transfer rate, 16.67 MB per second • Sustained Transfer rate: 6.7 MB per second • Built-In Wear Leveling

Skyworks Solutions Inc., Woburn, MA. (781) 376-3000. [www.skyworksinc.com].

Austin Semiconductor, Inc., Austin, TX. (512) 339-1188. [www.austinsemiconductor.com].

Quartus II Version 8.1 Adds Speed, Features Altera Corporation has released Quartus II software version 8.1, delivering high-density FPGA compile times three times faster than other FPGA-vendor supplied development software, based on internal benchmarks. The enhanced productivity features within Quartus II software enable design teams to close timing and power faster, lower R&D costs and shorten time-to-market.

Quartus II software version 8.1 helps speed development times by automating traditionally time-consuming features. The design partition planner, introduced in the previous version of Quartus II software, now provides automated partitioning in version 8.1, allowing more designers to leverage the productivity benefits of incremental compilation. Quartus II software now also eliminates the need to modify gated clocks manually by automatically converting gated clocks to functionally equivalent logic supported by the FPGA architecture. Automating these features allows design teams to focus more effort on value-added portions of the design.

Quartus II Version 8.1 adds Stratix IV pin-outs and support for a new Stratix IV FPGA speed grade offered in a low-cost package. The software provides added transceiver timing-model support, as well as support for 8.5 Gbit/ss transceivers, 1.6 Gbit/s LVDS and 400 MHz DDR memory. For designers targeting a HardCopy ASIC implementation, Quartus II software provides initial support for HardCopy IV ASICs. New features in Quartus II Software Version 8.1 include: SignalTap II Embedded Logic Analyzer; Enhanced SOPC Builder Tool; new operating system support; new Pin-Out Advisor; Real Intent Verification Support; new and enhanced IP cores and megafunctions; physical synthesis engine enhancements; and Synopsys Design Constraints (SDC).

Both the subscription edition and the free Web edition of Quartus II software version 8.1 are now available for download. The Subscription Edition is also available in DVD format by request.

Altera Corporation, San Jose, CA. (408) 544-7000. [www.altera.com].

NOVEMBER 2008

53

products for designers

Compact, Ruggedized SSD for Handheld Applications

product feature Synopsys Enters Mixed-Signal Implementation Market Galaxy Custom Designer offers a complete AMS design environment with OpenAccess/IPL support.

by John Donovan, Editor-in-Chief Portable designs are a continuing challenge for the EDA community. Thanks to the demand for multimedia in handsets, almost all designs are now analog/mixed signal (AMS), but the proprietary toolsets used to implement them have been fragmented and often poorly integrated.

The leader to date in custom AMS design has been Cadence with its Virtuoso, Assura and Encounter tool suites. Synopsys has now countered with the introduction of Galaxy Custom Designer, a mixed-signal implementation solution that leverages Synopsys’ Galaxy Design Platform to provide a unified solution for custom and digital designs, thereby enhancing designer efficiency. According to Graham Etchells, director of marketing for Synopsys’ Analog/Mixed-Signal Group, “Everything you need to do a modern AMS chip is now available from Synopsys.”

Custom Designer delivers a familiar user interface while integrating a common use model for simulation, analysis, parasitic extraction and physical verification. It is the first-ever implementation solution built natively on the OpenAccess database for legacy designs, as well as a new componentized infrastructure offering unprecedented openness and interoperability with process design kits (PDKs) from leading foundries.

In addition to facilitating innovation with the open architecture, Custom Designer bridges the gap between the historically disparate worlds of digital and custom design. Custom Designer enables complete data transparency with Synopsys’ IC Compiler physical implementation solution, allowing the exchange of vital information during floor planning, placement, routing and final chip editing to reduce time-consuming design iterations.

Built from the ground up, Custom Designer was architected for productivity. Key modules include a schematic editor featuring on-canvas editing and dynamic net highlighting. The simulation environment provides a common use model allowing access to Synopsys simulators, including HSPICE, HSIM XA, NanoSim XA and WaveView Analyzer. The layout editor features a real-time preview of PCell parameter changes.

In addition, the results from Hercules DRC/LVS and Star-RCXT parasitic extraction are dynamically available within Custom Designer.

Compounding the problem is the lack of interoperable process design kits (PDKs) from foundries, which creates a bottleneck in multi-vendor AMS design flows. A PDK is a comprehensive set of foundry-verified data files

54

PORTABLE DESIGN

including PCells (parameterized cells) used in a complete analog and mixed signal design flow.

Since Cadence has long dominated the AMS EDA tool market, the first PDK from a foundry would almost invariably support only their tools.

Other vendors would have to wait 12, 24 or 36 weeks for a PDK that supported their toolsets— and only their toolsets. If you’re several months late jumping onto a new process node, you’ve got a problem.

Over the past couple of years, all the major EDA vendors have started to support an OpenAccess database structure, which enables designers to mix and match best-in-class tools for different parts of the design flow; a database created in one vendor’s OpenAccess tools can be read and edited by another OpenAccess tool without intermediate translation or streaming.

The problem is that foundries still distribute PCell libraries in formats that support the layout tools of only one vendor, which precludes tool interoperability.

At Si2’s Open Access Conference in April 2007, Synopsys and four smaller partners announced an alliance to collaborate on the creation and distribution of an interoperable and open PCell library, dubbed IPL. Magma and Virage Logic have since joined the IPL Alliance; Mentor Graphics is a ‘supporting member’; and TSMC is the lone foundry member to date, though Chartered has reportedly expressed interest.

While vendors would clearly benefit from interoperable PCell libraries, so too would the average SoC designer. When making early decisions about the design flow, they would not be limited to the tools from a single vendor; they would also benefit from a flow with fewer translation steps. From the foundry’s standpoint as well as the designer’s, an interoperable standard promotes reuse and reduces PDK development cost.

Synopsys’ Galaxy Custom Designer is a capable and welcome new entry into the AMS design field, for which it certainly deserves to be Portable Design’s Featured Product this month. Its support for OpenAccess and IPL is just the frosting on the cake.

Synopsys, Inc., Mountain View, CA. (650) 584-5000. [www.synopsys.com].

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ceo interview Warren East ARM

While the number and variety of portable consumer electronics devices have exploded in recent years, one thing that most of them have in common is an ARM core. Over 90% of the 1.2 billion cell phones sold each year contain at least one ARM-based microprocessor. As of January 2008, over 10 billion ARM cores have been built, with 2.7 billion shipping in 2007 alone. According to iSuppli, by 2011 five billion ARM-based processors will be shipping per year. ARM devices currently account for 75% of all embedded 32-bit RISC processors, making it without a doubt the 700-lb. gorilla of exploration the portable space. er your goal eak directly Unlike some companies that were late page, the converts to low power, ARM set out in 1983 resource. hnology, to build a small, low-power RISC CPU; the and products ARM2, introduced in 1985, outperformed the then-dominant 80286 while drawing far less d power. Over the years ARM has retained its focus on low power while increasing the speed and sophistication of its cores. In order to become the world’s largest silicon IP provider, it set out to become a ‘one-stop shop’ for IP, mpanies providing solutions now adding software, tools and systems expertise oration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, both growth and acquisition.

Its ecoto a company's technical page, the goal of Get Connected is to put you in touchthrough with the right resource.

Whichever level of Get Connected will help you connect with the companies and products you aresystem searchingof for.semiconductor and software partners nected is the largest in the industry, as is its network of FAEs. Portable Design sat down recently with ARM CEO Warren East to ask about its products, its business model and its plans for the future.

End of Article Get Connected

with companies mentioned in this article. www.portabledesign.com/getconnected

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PORTABLE DESIGN

Portable Design: A number of analysts are predicting that the semiconductor IP industry will continue to grow faster than the semiconductor industry as a whole for the next several years. To what do you attribute that growth?

East: I think it’s a structural shift in the

semiconductor industry. To look at certain portions of the process and say all the costs that we’re putting into that it is (a) increasing and (b) quite a lot of it undifferentiating so we can’t really monetize all that cost, so there must be a better way of doing it.

The IP model is outsourcing, but it’s outsourcing and sharing. A company that wishes to take some of that cost and basically turn it from a fixed cost into a variable cost can outsource it. But if they outsource it to an IP company, that IP company can basically…what we do is do the same thing and license it to multiple people because the type of IP that we design is very generic and therefore applicable to a wide range of applications. Therefore the semiconductor company has not only turned the fixed cost into a variable cost, they’ve reduced it as well. That is a very compelling argument, and that’s why I think in the long run IP can grow faster than the semiconductor industry.

Portable Design: Isn’t the ‘outsourcing’ of R&D to IP vendors a somewhat risky venture, given the lack of quality metrics and standards in the IP industry?

East: I think as with outsourcing anything, you have to be careful about who your partners are. ARM has a history of outsourcing, and we recognize that we’re not going to get customers to come back time and time again unless we’re actually performing better than their inhouse solutions. Therefore I think it’s up to the IP companies to maintain their quality and up to the semiconductor companies to select their IP partners carefully.

Portable Design: ARM processors have long held a dominant position in the cell phone market. What is your take on Intel’s entrée into the nascent mobile Internet device (MID) market with its lowpower Silverthorne processor? Is that an attempted end run around ARM? East: Clearly the cell phone market is a very attractive market to be in because I think we can see a billion or so phones per annum continuing to be the number for some time; and within the cell phone space we can see an ongoing shift

to smarter and smarter phones. It’s actually the smart phones and the applications processor within the smart phones that Intel is targeting.

The difference between what is a smart phone what is a PC becomes somewhat blurred, so it’s a very logical place for Intel to want to go.

That said, my take is that ARM is there already; ARM has been there for a long time; and ARM has a collection of semiconductor partners with years of experience at putting together low-power system-on-chip devices at the right sort of price points for these products.

So I would say—I would say this, wouldn’t I?—that Intel has an uphill struggle.

Portable Design: Do you expect that MIDs will replace Internet-enabled smart phones for Web browsing, or will the latter improve so rapidly that MIDs never really take off?

East: I think it’s all in the definition of ‘What is a smart phone?’ and ‘What is a mobile Internet device?’ Something like a year or so ago the launch of the Apple iPhone made a big difference to the small phone world; however, I’ve seen that referred to as essentially a mobile Internet device. What is a mobile Internet device?

At the end of the day I think what we’re really talking about is something that offers one the functionality that you get with a PC in terms of interacting with the Internet, but with the battery life and convenience of a mobile phone, so that you can certainly put in your pocket.

But then there are many consumers out there—with hundreds of millions of smart phones sold every year—I’m sure with all those consumers there are a lot of different choices being made about what sort of product suits you and what sort of product suits me.

The market is probably big enough for what we might want to call smart phones and for what we might want to call Internet devices.

Portable Design: Fabless semiconductor companies have shown that their business model is scalable, with a number of them earning revenues of over $1B per year.

Is the semiconductor IP business model similarly scalable?

East: I think you can certainly scale, as I said a moment ago. I think the IP industry will grow faster than the overall semiconductor industry, but no, I don’t think that’s the same scale as a fabless semiconductor company.

That’s because what we’re actually doing with IP is very different. The particular slice of the overall value chain that the semiconductor IP supplier is targeting is a much smaller slice— and it needs to be to make the IP model work.

Back to the business about it being something that is generic, and therefore by definition there is a lot of non-generic stuff on the system-onchip device that is application-specific, which is customer-specific, which is differentiating.

That’s what the fabless semiconductor company does. They’re taking a bigger slice of the value chain, and therefore that business model is more scalable.

Portable Design: What is your vision for ARM five years from now?

East: Well, we want to benefit from that structural growth opportunity that I talked about. So ARM’s vision is to be at the center of all things digital and have consumers like you and I going into shops and not being able to buy electronic products without them being based on ARM’s low-power technology. So that’s where we’re going.

ARM Inc. Sunnyvale, CA. (408) 734-5600. [www.arm.com].

Portable Design: How do you expect the semiconductor IP industry to change over the next few years?

East: We’re in a fortunate position as ARM because we see in the electronic product area a big shift going on where more and more of the functionality is moving from dedicated hardware into software; and therefore the type of IP that we supply—which is all centered around the ARM microprocessor—is a good place for us to be. So I can see a lot of in-built structural growth for ARM over the next 5-10 years. Notwithstanding economic cycles, and notwithstanding cycles in the semiconductor industry—and assuming that we execute correctly—that growth will happen.

Other trends going on in the IP space: I can see non-microprocessor type of semiconductor IP evolving. People have looked for mixed-signal IP for many years, and there are companies out there that are starting to make headway in that. Right now it’s a bit early to develop scale in that because there’s still a lot of case-by-case customization work to do in mixed-signal. But as the number of semiconductor processors out reduces, as the cost of wafer fabs increases, then an opportunity will emerge for that type of IP.

NOVEMBER 2008

57

The RTC Group is a media services company specializing in bringing companies and their products to a focused group of electronic and computer manufacturers. RTC is proud of its track record of blazing new trails in search of marketing value for our clients. Portable Design magazine is the newest addition to RTC Groupâ&#x20AC;&#x2122;s collection of publications.

advertiser index Actel Corporation

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12/09-11/08

Mouser Electronic

event calendar 12/08-10/08

12/09/08

Real-Time & Embedded Computing Conference

FPGA Summit

21,43

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San Jose, CA www.fpgasummit.com

Peregrine Semiconductor

59

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12/11/08

Rogers Corporation

55

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Real-Time & Embedded Computing Conference

Sequoia Communications

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Storage Visions

33

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Xilinx, Inc.

9

01/08-11/09

Consumer Electronics-CES Las Vegas, NV www.cesweb.org 01/29/09

Real-Time & Embedded Computing Conference Santa Clara, CA www.rtecc.com/santaclara2009 02/11-13/09

West 2009 San Diego, CA www.afcea.org 02/24/09

Real-Time & Embedded Computing Conference Huntsville, AL www.rtecc.com 02/26/09

Real-Time & Embedded Computing Conference Melbourne, FL www.rtecc.com If you wish to have your industry event listed, contact Sally Bixby with The RTC Group at sallyb@rtcgroup.com

58

PORTABLE DESIGN

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For more than a decade, Peregrine Semiconductor has engineered leading-edge RF CMOS solutions on sapphire for the most demanding rad-hard applications. Today, its UltraCMOS technology enables monolithic integration throughout a broad portfolio of commercial RF and mixed signal ICs, including Mixers, DSAs, PLLs and Prescalers, and performance that can’t be touched. So if you want an RF solution that will get you from design to money in no time, it’s time to switch.

Call us or visit www.psemi.com to locate your local sales representative for samples, pricing or technical documentation.

Changing how you design RF. Forever. psemi.com Peregrine Semiconductor Corporation Europe: +33-1-4741-9173 China/ROA: +86-21-5836-8276 USA/Canada 858-731-9400 Japan: +81-3-3502-5211 Korea: +82-31-728-4300 Web: www.psemi.com The Peregrine name and logo are registered trademarks and UltraCMOS, HaRP and MultiSwitch are trademarks of Peregrine Semiconductor Corp. ©2008 All rights reserved.

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