Also in this issue by RTC Media

Also in this issue RoHS - Weathering the Storm Power Management and Conversion The magazine of record for the embedded computing industry

October 2006 www.rtcmagazine.com

FPGAs

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XMB The XMB is part of Octagon’s line of Core Systems™ that offer out–of–the–box solutions for transportation, military and security applications. The XMB is a “no compromise” design for a mobile server that optimizes the electrical, thermal and mechanical components for maximum reliability. The result is a powerful, yet fanless system in a rugged extrusion that provides 24/7 service even in harsh environments. The basic unit includes the processing power, power supply, memory and I/O for most applications.Yet, it can be easily expanded using PC/104 I/O function blocks or Octagon’s XBLOK™ half–size PC/104 expansion modules. Generated heat is effectively channeled directly to the case to help prevent internal hot spots.

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Imagine what we can do for you now. Our vision is to offer you the kind of products and services you’ve only dreamed of. If you could build the perfect embedded products company, it might be something like the one we’ve created by combining the imagination, energy, and expertise of the people at GE Fanuc Embedded Systems, Condor Engineering and SBS Technologies. It would be a company with the experience, resources and courage to develop truly innovative products — which is a cornerstone of the General Electric Company. It would be a company with a wide range of available products — everything from avionics and industrial controls to networking,

communications, and fully integrated systems — which is exactly what Condor Engineering, SBS Technologies, and GE Fanuc bring to the table. By creating this new company, we’ve taken a giant step toward our vision of a different and better kind of embedded company. So we invite you to open your mind and let your imagination run wild. Because our goal is to be right there with you helping make your inspirations into realities. www.gefanucembedded.com

Departments 9

Editorial: The Future of Parallelism www.rtcmagazine.com

11 Industry Insider

CoSine 2VP70

18 Choosing the Right FPGA Board: More Features Mean Tougher Decisions Rodger H. Hosking, Pentek

Solutions Engineering

RoHS

24 RoHS: After the Deadline

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14 Utilizing FPGA DSP Slices with Serial Fabrics

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74 Products&Technology

128MB DDR Array

Tempe VME320

The MM-1500 combines Xilinx V-4 SX55 FPGAs with DSP slices and Serial Rapid IO fabric connectivity in a VxS VITA 41 carrier • Pg. 14

Ann R. Thryft

26 Weathering the RoHS Storm Norm Hartig, VersaLogic Corp.

Industry Insight Power Management and Conversion

OS Microkernel

File System

Client Application

32 High Voltage Strikes CompactPCI Sandeep Babel, Bi Ra Systems

Executive Interview

Threads File system operation uses client application’s budget.

36 ...An Exciting Time to be an Embedded Systems Developer RTC Interviews Rob McKeel, CEO, GE Fanuc Embedded Systems

Software Supplement

Threads

Software Tools and Techniques

45 Using Resource Partitioning to Build Secure, Survivable Embedded Systems

With partition inheritance, any work that a file system (or other service) performs for a client is charged to the client’s budget. That way, a runaway client can’t monopolize services needed by other applications • Pg. 45

Paul N. Leroux and Kerry Johnson, QNX Software Systems

50 TimeMachines: The Future of Debuggers Michael Lindahl, Green Hills Software

54 An RTOS for an SMP Multicore Processor John A. Carbone, Express Logic

58 “Not Your Father’s CORBA”—An Architecture for Embedded and Real-Time Systems Victor Giddings, Objective Interface Systems

62 Enterprise-Strength Solutions Meet the Demands of Today’s Embedded Systems Robert Day, LynuxWorks

66 Implementing High-Availability Middleware on ATCA—Step-by-Step Jim Ewel, GoAhead Software

70 Open Architecture Network Software Platforms Speed Complex Development Terry Pearson, Enea

Cover Photo: The Z machine, one of the research machines that offer the possibility of achieving controlled nuclear fusion, has created a hot dense plasma that produces thermonuclear neutrons using X-rays created by extremely huge electric pulses. The Z machine incorporates high-voltage PXI modules from Bi Ra Systems. Courtesy Sandia National Laboratories

7U Cube MicroTCA Chassis Supports 6 AMC Cards at Full Height, Double Width • Pg. 74 October 2006

October 2006 Publisher PRESIDENT John Reardon, johnr@r tcgroup.com VICE PRESIDENT, European Operations Zoltan Hunor, zoltanh@r tcgroup.com EDITORIAL DIRECTOR/ASSOCIATE PUBLISHER Warren Andrews, warrena@r tcgroup.com

Editorial

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October 2006

Published by The RTC Group Copyright 2006, The RTC Group. Printed in the United States. All rights reserved. All related graphics are trademarks of The RTC Group. All other brand and product names are the property of their holders.

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Editorial October 2006

The Future of Parallelism by Tom Williams, Editor-in-Chief

or many years, the computer industry has been built on parallel bus technologies: VMEbus, CompactPCI bus, EISA bus, and so on. Why, I even remember something called the S-100 bus. Others of us are trying to forget something called Futurebus. Now, however, the pendulum has shifted and we are seeing high-speed serial switched fabrics starting to take over the role of system interconnect technology. The reasons are clear and have been discussed at length. There is a limited number of elements you can put on a parallel bus because for any two to communicate, they have to “own” the bus for a certain amount of time, shutting out other elements. Switched fabrics can set up communications between multiple elements simultaneously without interfering. It is possible to implement a form of parallelism in a serial switched fabric by setting up “by-x” lanes in which a number of bits flow in parallel (x2, x4, x8, etc.) along a multiple-line serial link. The communication architecture is still inherently serial, however. The growing success of switched fabrics such as PCI Express, RapidIO, InfiniBand and others promises to add a new factor of speed to system design, of that there now seems little doubt. But just as this serial interconnect wave is taking place, we see a new surge in parallelism with the advent of a whole host of multicore processor designs. The basic idea here is also fairly familiar. Increasing performance by cranking up the clock speed has a growing set of negative consequences in the form of power consumption and heat generation. Dissipating that heat has become a major barrier to that route of development. Instead, one takes advantage of the continuing advance of Moore’s Law to put multiple cores on the same die, distribute the processing load among them thus increasing the computing throughput at acceptable clock/power parameters. At present, these designs take the form of dual, quad or even eight-element implementations, or they appear as a matrix of perhaps 256 computing elements arranged as a flow-through architecture. In the case of the dual, quad and eight-core designs, however, a look at the block diagram bears an eerie resemblance

to a parallel backplane architecture. It would appear that attempts to come up with a large number of, say, 32-bit processor cores on a single die will eventually run into the same sort of bus contention problem that is present in board-level design. Vastly expensive supercomputers rely on a large matrix of CPUs running at rather modest clock speeds to perform enormous computing tasks in particle physics, astrophysics and a whole host of scientific simulations and computations. One design—and definitely not the most advanced—has 65,536 compute nodes with a top performance of 360 TeraFLOPS, consumes about 1 Megawatt of power and takes about 2,500 square feet of floor space. Now we all know we can do better than that. Recent developments coming out of Intel and the University of California at Santa Barbara (where the above mentioned supercomputer is located) may point the way to greatly increased multicore possibilities on a single die as well as high-speed interchip connections on a single board. The ability to integrate indium phosphide lasers onto silicon chips for on-chip data transfer could greatly enhance the ability to build high-speed multicore processors—in effect creating virtual parallelism with serial connections. Where that will lead is, of course, anybody’s guess. At this point, I doubt it will shrink a massive 65,536-node supercomputer onto a chip, but stranger things have happened. The upshot is that parallel buses may be dead but parallelism is alive and well and is leading us to higher levels of performance. Even the first generation of multicore processors such as the Cell chip have shown immense gains in compute power. If the optical interconnect leads to orders of magnitude performance leaps on a single die, we will see applications we may never have dreamed of. Of course in big research institutions there will still be that behemoth that draws a Megawatt and takes up 2,500 square feet. But just imagine what will be inside each one of those 65,536 nodes.

October 2006

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Industry Insider

October 2006

Futuristic Advertising Debuts with EPIC SBC Onboard—with GPS VersaLogic has announced that the company’s AMD GX 500-based single board computer, the Gecko, has been designed into an innovative advertising medium that integrates video, Internet and GPS technology. Vert Inc.’s “VID,” or Vert Intelligent Display, is a mobile video graphics display module that mounts to the top of taxicabs and receives advertising media through a wireless Internet connection. The VID uses GPS to identify its location and change advertising messages to correspond with advertiser’s geographic selections. This technology Get Connected with technology and allows, for instance, ads displayed the financial companies in providing solutions now district to be different than those displayed Get Connected is a newwhen resource for further exploration the taxi is in a university into neighborhood. This futuristic device brings products, technologies and companies. Whether your us goalcloser to advertising one might to research theas latest datasheet from a company, speakElement,” directly find in science fictionis films such Sony Picture’s “The Fifth and Ridley Scott’s “Blade with an Application jump to company'sand technical Runner.” The displays are nowEngineer, being orused ina Boston will page, soonthebe in use in Philadelphia, New goal of Get Connected is to put you in touch with the right resource. Orleans, New York, Las Vegas, and you other major cities. type of technology, Whichever level of service require for whatever The Gecko single board computer integrated into display Get Connected will help you connect with the the companies andcontrols products the ultra-bright LCD and coyou are searching ordinates communication withfor. the central server and GPS system. The Gecko is an EPIC-format single board computerwww.rtcmagazine.com/getconnected with an AMD GX 500 processor, ideal for mobile applications due to its low power consumption (less than 5 watts) and lack of moving parts (such as a fan). Features of the board include integrated video and audio, up to 512 Mbyte RAM, 10/100 Ethernet, four USB ports, four COM ports, analog/digital I/O, and a CompactFlash socket for onboard media storage.

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Products

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www.rtcmagazine.com/getconnected

October 2006

Industry Insider

Event Calendar 11/06-09/06 TechNet Asia-Pacific Honolulu, HI www.afcea.org

11/07/06 Real-Time & Embedded Computing Conference Montréal, PQ www.rtecc.com/montreal

11/09/06 Real-Time & Embedded Computing Conference Ottawa, ON www.rtecc.com/otttawa

11/13/06 AFCEA TechForum Fairfax, VA www.afcea.org

11/13-17/06 Software Defined Radio Tech Conference Orlando, FL www.sdrform.org

11/14-16/06 Aerospace Testing Expo 2006 Anaheim, CA www.aerospacetesting-expo.com

11/14-17/06 Electronica 2006 Munich, Germany www.global-electronics.net

12/06/06 Real-Time & Embedded Computing Conference Portland, OR www.rtecc.com/portland

12/08/06 Real-Time & Embedded Computing Conference Seattle, WA www.rtecc.com/seattle

If your company produces any type of industry event, you can get your event listed by contacting sallyb@rtcgroup.com. This is a FREE industry-wide listing.

October 2006

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Lantronix Announces Second Annual Wireless Design Contest

Lantronix has announced its second annual Wireless Design Contest. With more categories and larger cash prizes, this contest challenges engineers worldwide to use their imaginations to wirelessly network-enable a machine or device using Lantronix WiPort, an embedded 802.11 b/g wireless Device Server. To qualify for nearly $20,000 in prizes, contestants must register their product on the Lantronix Web site and submit a working prototype board design complete with a documented summary of the project and its operation. All entries must be received on or before March 1, 2007 and winners will be announced at the Embedded Systems Conference (April 3-7, 2007) in San Jose, Calif. First place will receive $6,000; second place, $4,000; and third place, $2,000. Additional awards will be given for the best entry from a student or educational institute, for the one using the lowest power usage and for the one utilizing 802.11 b/g and Ethernetswappable combination. Contest entries will be judged on technical merit, originality, business value, cost-effectiveness

and design optimization. For the full list of contest rules and the online entry form, visit: http://www.lantronix.com/info/ wirelesscontest/rules.html.

RTI Enters Modeling Partnership With Sparx Systems

Real-Time Innovations and Sparx Systems have announced that they are partnering on the integration of RTI’s Data Distribution Service with Sparx Systems Enterprise Architect modeling environment that utilizes the Unified Modeling Language (UML). The goal is to enable design engineers building complex data-driven applications to model critical elements of the application and generate code that can integrate into the RTI Data Distribution System. RTI Data Distribution Service is an implementation of the Object Management Group (OMG) Data Distribution Service for Real-Time Systems (DDS) specification. RTI Data Distribution Service allows networked applications to easily connect with multiple data sources for communication of real-time data via an easy-touse application programming interface. The technology is well proven and provides deterministic data delivery over standard networks while offering services for monitoring and control. Sparx Systems Enterprise Architect is a comprehensive UML analysis and design tool, covering software development from requirements gathering through analysis, design, testing and maintenance. Enterprise Architect lets RTI Data Distribution Service engineers employ UML in the design and implementation of complex applications utilizing data across large distributed systems. Designers of distributed data systems across large networks will be able to model their network architecture and data flow using Enterprise Architect and automate the process of creating

application elements within the RTI Development Platform.

Hardi Provides ASIC Prototyping for Tensilica’s Diamond Standard Processors

Tensilica and Hardi Electronics have announced that ASIC designs using Tensilica’s Diamond Standard processor cores can now be prototyped and verified on the Hardi ASIC Prototyping System (HAPS). Hardi Electronics is now part of Tensilica’s Diamond Standard partners program. Tensilica’s Diamond Standard processors are a set of six off-theshelf synthesizable cores that range from area-efficient, low-power controllers to an audio processor and a high-performance DSP, all of which lead the industry in their respective categories both in lowest power and highest performance. The Diamond Standard processors are supported by an optimized set of Diamond Standard software tools and a wide range of industry infrastructure partners. They are available directly from Tensilica and through a growing list of ASIC and foundry partners. HAPS is the first modular FPGA board system providing high speed, high capacity, realtime debugging and full ASIC functionality for ASIC prototyping designers. The system is composed of singleor multi-FPGA motherboards and standard or userdeveloped daughter boards. To accommodate very large designs, designers can connect a number of motherboards in many different ways. HAPS gives designers virtually the same functionality as the ASIC.

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TechnologyInContext FPGA Platform Boards

Utilizing FPGA DSP Slices with Serial Fabrics Harnessing specialized FPGA blocks and serial fabrics creates impressive possibilities for signal processing. by M ike Jadon Micro Memory

Ad Index Get Connected with technology and companies providing solutions now

ow in the twilight of 2006, the con- Get tion. As an example, to maximize benConnected is a new resource for furtherthe exploration cept of utilizing FPGAs for DSP op- intoefits thattechnologies FPGAs can provide, Whether DSP operaproducts, and companies. your goal is to research latest datasheet from a company, speak directly erations is fairly well understood, estions the should, if possible, be implemented with an Application Engineer, or jump to a company's technical page, the tablished, and recognized within the signal in fixed point arithmetic. While floating goal of Get Connected is to put you in touch with the right resource. processing industry. However, the Whichever degree levelpoint functions canforalso be implemented in of service you require whatever type of technology, of benefits that FPGAs can provide Get for speFPGAs and has made Connected will help youdoing connectso with thebeen companies andmuch products you areof searching for. cific applications is still debated in terms simpler with advanced compliers, implewww.rtcmagazine.com/getconnected constraints such as development time, ef- menting those same operations in fixed fective heat dissipation, and the actual DSP point will yield higher performance beoperations being performed. Many of these cause fixed point is inherently well suited factors depend on an optimal implementa- for execution in hardware circuits.

BCOUT 18 A B

18 18

48 18

Along these lines, Xilinx has further increased the proposition of utilizing FPGAs for DSP applications by providing specialized programmable logic blocks for DSP operations in its new Virtex-4 and Virtex-5 devices, named Xtreme DSP Slices. It should be noted that Altera also offers specialized DSP blocks in their Stratix II devices. However, unless otherwise stated, the remainder of this article will limit discussion to Xilinx’s V-4 family. What exactly is a DSP slice? Xilinx defines a V-4 DSP48 slice as having … Get Connected Cascade Out to Nextwith Slice technology and companies providing solutions now “…a two-input multiplier followed Get Connected is a new resource for further exploration PCOUT into products, technologies and companies. Whether your goal is to research byjump multiplexers and a three-input datasheet from a company, speak directly with an Application Engineer, or to a company's technical page, the goal of Get Connec The multiplier acin touch with the right whatever type of technology, 36resource. Whichever level of service you require foradder/subtracter. 18 Get Connected will help youX connect are searching for. two’s complement cepts two 18-bit, 48 with the companies and products you 18 48 48 www.rtcmagazine.com/getconnected 36 operands producing a 36-bit, two’s CIN complement result. The result is sign 72 36 Y extended to 48 bits and can optionP 48 48 ally be fed to the adder/subtracter. SUBTRACT The adder/subtracter accepts three 48 ZERO 48-bit, two’s complement operands, Z 48 and produces a 48-bit two’s complement result.” – Xilinx XtremeDSP 48 for Virtex-4 User Guide

End of Article

Products

Wire Shift Right by 17 Bits

BCIN

PCIN

Cascade In from Previous Slice

Get Connected with companies and Figure 1

products featured in this section. A single Xilinx V-4 Xtreme DSP48 Slice. Two DSP slices are combined www.rtcmagazine.com/getconnected with logic to form a DSP tile.

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with companies mentioned in this article. www.rtcmagazine.com/getconnected

October 2006

Get Connected with companies mentioned in this www.rtcmagazine.com/getconnected

Mathematical Functions

The DSP48 slice can efficiently perform a wide range of mathematical functions commonly utilized in DSP applications, ranging from adders, subtracters, accumulators, MACCs, multiply multiplexers, counters, dividers, square-root

DDR Controller

Multi-port DDR Controller Corner Turning DMA Serial RapidIO x4

Figure 2

DDR Controller

Mailbox DMA

405 PPC

DMA Controller

Interconnect

User Programmable Logic

Interconnect

PCI-X 64/133MHz

QDRII Controller

In simpler terms, a DSP48 slice is a multiplier and multiply-accumulator with several specialized features provided in a dedicated circuit. As many DSP operations follow a multiply with an addition, the basic functionality is immediately apparent. However, the elements also contain several subtle yet equally valuable capabilities. Various DSP functional blocks such as barrel shifters, add-subtract functions, cascading, muxes, counters, compares, ANDs, and XOR functions can either be implemented entirely in DSP slices or with minimal additional logic. A diagram of a DSP48 slice is shown in Figure 1. The DSP slices are found in pairs that are called DSP tiles. Connected by a shared 48-bit bus, the DSP tiles are stacked vertically with block RAM and high-speed interconnects for maximum bandwidth between elements. The net result is that the DSP slices provide increased performance with reduced power and logic utilization. Regardless of the FPGA vendor, marketing literature for FPGAs generally states maximum frequency rates. It should be understood that attaining these clock rates is only practically possible when implementing the smallest and simplest logical functions. As an example, the Xilinx V-4 devices are capable of running at 500 MHz but implementing a complex module such as a PCI DMA engine at such a speed in the FPGA fabric is highly unlikely. These types of complicated functional blocks will generally have a maximum running frequency of approximately one-half to two-thirds of the device’s theoretical maximum rate, i.e., 250 MHz to 333 MHz for a V-4 device. However, unlike the FPGA fabric, these specialized V-4 DSP slices can in fact reach theoretical maximum clock rates with relatively complex operations.

405 PPC

TechnologyInContext

The combination of the V-4 SX55 and V-II Pro 2VP70 provides the maximum FPGA DSP slices for user-programmable logic while still providing for serial switch fabric connectivity.

functions and shifters. As DSP applications such as Radar, SigInt and EO/IR continuously push sampling rates, these mathematical functions must be implemented utilizing parallel pipelining in the FPGAs. Pipeline registers found in the DSP48 slices provide the ability to achieve maximum clock frequencies, where additional stages can be added to further increase throughput, albeit at the expense of additional latency. However, this is often an acceptable tradeoff for these highbandwidth, streaming data applications. Utilizing this technique, the objective is for inputs to enter and outputs to be computed on every clock cycle. This is made possible through the DSP48 slice’s excellent balance between its internal elements. The result is that mathematical operations are principally kept within the DSP slice, avoiding the use of the FPGA fabric. The DSP48 slices have several other practical and useful features for real-world DSP implementations. A common issue that occurs when implementing DSP operations involves bit growth, where more bits are output than input. This is typically addressed through the use of rounding where the granularity of precision will be degraded but is necessary to manage the width of the output. Another alternative would involve truncation but that can produce problematic data shifts. Through the use of symmetric rounding, and an input port and carry-in port that have been

implemented into the DSP48 slice to maintain performance and accuracy, positive numbers can be rounded up and negative numbers can be rounded down to provide the best results. Another clever feature of the paired DSP48 slices (DSP tile) is their ability to “cascade” results from one tile to the next without utilizing the FPGA’s general fabric. This path supports a “right-wireshift,” where a partial product from one DSP48 slice can be right-justified and added to the next partial product computed in an adjacent slice, resulting in the DSP slices being able to support any size operand. Functions ranging from input streams to high-level DSP operations can take advantage of this cascading capability going from column to column, inputting samples and outputting results with maximum performance. For comparison purposes, by examining an off-the-shelf Xilinx 1024 FFT IP core, it can be seen that utilizing the V-4 DSP slices resulted in a logic utilization savings of approximately 15% over the equivalent implementation that did not utilize the DSP slices. And with a concentrated design effort it is believed this gain could be far greater. In comparison to a more general purpose-processor, a 33-element FIR filter in a Xilinx V-4 device utilizing DSP slices, running at just 250 MHz has 10x the throughput of a 1.42 GHz Altivec-based October 2006

Crossbar

Virtex-4 SX55

Figure 3

32MB QDR II Array

A, C

32MB QDR II Array

PCI-X 64-bit/133MHz

Ethernet CoSine 2VP70

1GB DDR Array 128MB DDR Array

Virtex-4 SX55

128MB DDR Array

Tempe VME320

The MM-1500 combines Xilinx V-4 SX55 FPGAs with DSP slices and Serial Rapid IO fabric connectivity in a VxS VITA 41 carrier.

PowerPC, and this is assuming that the Altivec code has been optimally written to execute four operations simultaneously and that there are no cache misses. FPGA DSP developers have found good success utilizing The Mathworks Simulink, the industry’s leading tool for graphical DSP modeling, and interfacing it to Xilinx’s System Generator to compile functions directly into VHDL. An especially powerful aspect of these tools is that System Generator is “aware” of DSP slices for specific Xilinx devices, providing it the ability to take full advantage of these resources where available. For the fastest development time, various Xilinx DSP IP cores for functions such as FFTs and FIR filters are preconfigured and utilize these V-4 DSP slices. The Xilinx Virtex-4 family includes three domain-optimized platforms: the FX, the SX and the LX. The SX device is specifically optimized for DSP applications and is particularly unique in its number of DSP slices. While the SX55 is the largest device in the SX family and the richest of any of the V-4 devices in terms of DSP resources with eight columns and 512 DSP48 slices, its logic resources are relatively limited at 25K total FPGA slices. Implementing bus interfaces (e.g., PCI-X), associated DMA engines, system DDR memory controllers, etc., therefore 16

Aurora

sRIO x4

sRTO x4

D, Z

sRIO x4

Ethernet

sRIO x4

VITA 35

128MB DDR Array

CoSine 2VP70

XMC/PMC Site 2

VITA 35

128MB DDR Array

Aurora

sRIO x4

1GB DDR Array

XMC/PMC Site 1

sRTO x4

64-bit/133MHz PCI-X

TechnologyInContext

October 2006

comes at a significant cost as these modules can each consume a meaningful portion of the device’s total slices. Even if these modules do not utilize DSP slices, practically accessing DSP slices directly adjacent to the aforementioned logical blocks can be especially challenging.

DSP Slices with Serial Fabrics

Another obstacle to realistically utilizing DSP slices is within the context of new serial fabric systems with interconnects such as PCI Express and Serial RapidIO, or even Gigabit Ethernet, InfiniBand or Aurora. Each of these interconnects requires SerDes transceivers. While Xilinx provides a built-in SerDes known as Rocket IO transceivers in the V-II Pro and V-4 FX platform, the V-4 LX and V-4 SX do not include such functionality. Therefore to utilize these devices directly with serial interconnects, external SerDes would be required. This approach is further complicated as powerful Xilinx IP cores for PCI Express, Serial Rapid IO and Aurora are each based on utilizing Rocket IO transceivers, and in effect utilizing the V-4 FX or V-II Pro series of devices. The most effective method of leveraging these powerful DSP slices, and the DSP-slice-rich V-4 SX55 device, into serial fabrics is to combine the device with

another FPGA that does include native Rocket IO SerDes, such as the V-4 FX series or the well proven V-II Pro series. This relegates the necessary infrastructure, not just for the serial interconnect but also for other modules such as DMA engines, DDR system controllers, and system processors to a discrete FPGA and reserves the precious DSP slices for user programmable logic. An example of this combination can be seen in Figure 2, where a V-II Pro is utilized as a “primary” device for system-on-chip infrastructure and a “companion” device rich with DSP slices is utilized for user-programmable logic. A related benefit to this approach involves reconfigurable processing. New FPGA bit streams with different DSP functions can be reloaded into the FPGA while the larger system is still operating, providing the ability to perform different DSP operations on a given stream of data. These functions can even be possibly chosen based on the characteristics of that data. At issue here is that during reconfiguration, serial interconnect links such as PCI Express or Serial Rapid IO will be taken down if the entire device is reconfigured. The fabric interconnect links will then have to train again after the new bit stream is loaded. This can take time and is subject to variability and error. Assuming hard core processors in the FPGA are being utilized for larger system management, reconfiguration can pose additional risks. Alternatively, by separating the infrastructure into a separate device, only the Companion FPGA device with the user-programmable logic needs to be reconfigured, and the Primary FPGA can continue to reliably operate as it is not being reconfigured. An example VxS board based with Serial RapidIO interconnects is shown in Figure 3. Micro Memory Chatsworth, CA. (818) 998-0070. [www.micromemory.com].

TechnologyInContext FPGA Platform Boards

Choosing the Right FPGA Board: More Features Mean Tougher Decisions Today’s board-level products increasingly include FPGA technology. Selecting the right mix of features and the ability to accommodate user-developed functions can be critical in hitting the cost/performance sweet spot.

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Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal ince FPGAs are now mainstream for absorbing the brick mortar of directly emis to research the latest datasheet fromand a company, speak components in virtually all embedbedded boards, including conwith an Application Engineer, or jump to a company'smemory technical page, the goal ofare Get Connected to put you layer in touchinterface with the rightdrivers, resource. ded systems, silicon vendors trollers, isphysical Whichever level of service you require for whatever type of technology, competing heavily on features, resources clock management and distribution, and Get Connected will help you connect with the companies and products and performance levels to secureyou design discrete parts like termination resistors. are searching for.

forced to offer different families of parts with different resource mixes targeted for various classes of applications. Embedded system board vendors face an even more difficult challenge wins for their parts. Digital signal proTo meet these diverse needs, FPGAs since each customer has a different miswww.rtcmagazine.com/getconnected cessing horsepower, often the main moti- strive to be the “Swiss Army knife” of sion unknown to the board designer at vation for using FPGAs, stems from nu- electronic devices by sporting dozens of the time FPGA component selection is merous parallel processing elements that different features. However, each applica- made. Successful new product definition tackle compute-intensive algorithms that tion presents a unique requirement for spe- requires an intimate knowledge of availwould overwhelm general-purpose pro- cific ratios of FPGA resources to be cost- able device features, insights into market Get Connected technology andvendors companies solutions now trends, and an apprecessors. But FPGAs also score high points effective. Aswith a result, FPGA areproviding space application Get Connected is a new resource for further exploration into products, technologies companies. Whether map your goal is to research ciation of howand FPGA resources into datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get Connec those applications. in touch with the right resource. Whichever level of service you require for whatever type of technology, LX Devices SX Devices Get Connected will help you connectFX withDevices the companies and products you are searching for. FPGA Family Example www.rtcmagazine.com/getconnected To illustrate the range of FPGA reLogic sources available in current offerings, we Memory look at the Xilinx Virtex-4 devices. UnDSP Blocks like the predecessor Virtex-II Pro family, Xilinx has split the seventeen Virtex-4 I/O Pins product offerings into three families, each Clock Managers targeting different requirements. Before Processors looking at how these families are defined, we will briefly discuss the major types of Gigabit XCVRs Virtex-4 resources and functions.

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Figure 1 18

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TechnologyInContext

IF Input

A/D Converter

D/A Converter

IF Output

IF Input

A/D Converter

D/A Converter

IF Output

Clock Sync Trigger

Clocking & Timing

Figure 2

XILINX VIRTEX-4 SX-55

2GB DDR2 SDRAM

8GB QDR RAM

1000 base T Ethernet

XILINX VIRTEX-4 FX-100

Front Panel RJ-45

Dual 4x Serial Fabric 1.25 GB/sec

VITA-42 XMC Connector

PCIbus 2.2 64/66 MHz

PMC IEEE 1386.1

Virtex-4 software radio PMC/XMC mezzanine module candidate.

Logic resources are arranged in “slices” consisting of a look-up table (LUT), multiplexers, a Boolean logic block and an adder/subtracter with carry functions. Four slices make up a configurable logic block (CLB), the basic element used for creating state machines, combinatorial logic, controllers and sequential circuits. Memory has become much more flexible in the latest-generation FPGAs and comes in different forms. Distributed

memory is used for LUTs, FIFOs, singleand dual-port RAMs and shift registers. For larger memory structures, 18 Kbit block RAMs can be used for deep FIFOs, large circular delay memory buffers and deep caches, as well as for bigger singleand dual port RAMs. One of the more significant advances in the Virtex-4 family is the new “XtremeDSP” slice. Following the market demand for more powerful signal processing structures, Xilinx has surrounded the

LX Devices Product No.

popular 18x18 hardware multipliers first introduced in the Virtex-II series with a 48-bit adder/subtracter capable of acting as a registered accumulator. Due to tight, dedicated logic, this facility can operate at clock speeds up to 500 MHz and can propagate the results between DSP slices with 48-bit precision at the same rate. The 48-bit path allows this fast, fixed-point hardware to rival the precision of floating-point engines by preserving the 36-bit multiplier outputs with plenty of overhead for bit growth as results propagate through cascaded slices. Each DSP slice features 40 dynamically controlled logical and arithmetic modes and supports mode changes during run-time without the need to recompile the FPGA. In this way, each XtremeDSP slice behaves like a miniature DSP processor, and there are as many as 512 of these in a single FPGA. Connections to a diverse range of external hardware devices are well accommodated with 20 different userconfigurable interface standards for the device I/O pins. New in the Virtex-4 is the XCITE active termination feature that not only provides programmable

SX Devices

FX Devices

4VLX60

4VLX100

4VLX200

4VSX35

4VSX55

4VFX60

4VFX100

4VFX140

59,904

110,592

200,448

34,560

55,296

56,880

94,896

142,128

Block RAM/FIFO (18 kbits each)

160

240

336

192

320

232

376

552

Block RAM (kbits)

2,880

4,320

6,048

3,456

5,760

4,176

6,768

9,936

Digital Clock Managers (DCM)

Phase-matched Clock Dividers (PMCD)

Max Differential I/O Pairs

320

480

224

320

288

384

448

XtremeDSP Slices

192

512

128

160

192

PowerPC Processor Blocks

—

10/100/1000 Ethernet MAC Blocks

—

RocketIO Serial Transreceivers

—

Configuration Memory Bits

18351K

31818K

50648K

14476K

24088K

22262K

35122K

50900K

Max SelectIO

640

960

448

640

576

768

896

Logic Cells

Figure 3

Representative members of the three Virtex-4 families.

October 2006

TechnologyInContext

termination within the FPGA to drastically reduce the number of external discrete resistors, but also dynamically adjusts termination impedance to track changes in drive levels due to process, temperature and device variations. Source-synchronous interfaces include serializer/deserializer blocks that match faster data rates (up to 1 GHz) on external data buses to slower, wider buses inside the FPGA to help reduce power. Interfaces to a wealth of fast external memory devices, including DDR and QDR, are made easier with programmable clock and data skew circuitry to match complex setup and hold time requirements. Digital clock managers allow different regions of the FPGA to be operated at different clock frequencies that can be synchronized from various external clock references. Frequency synthesizers with multipliers and phased-matched clock dividers precisely align external timing signals with data sources and destinations. All of the resources described so far are available in all Virtex-4 parts, but the ratio of these resources differs significantly among the three families. Figure 1 shows the relative strengths of resources for each of the three classes of devices for the larger devices in each class. The LX family delivers the most logic and I/O, the SX family aims at DSP with 512 XtremeDSP slices, and the FX class offers generous memory and three other important resources found only in that family. The first is onboard IBM 405 PowerPC processor cores that can be used as local microcontrollers to implement complete systems on a chip, often eliminating the need for an external CPU for high-level supervisory functions. The second resource is a set of serial gigabit transceivers capable of handling bit rates up to 10 GHz and backed up with serializer/deserializer logic. By configuring these interfaces through available IP cores, the FPGA supports popular high-speed serial standards and switched serial fabrics including Serial RapidIO, PCI Express, Fibre Channel, SATA, SONET and many others.

The third resource unique to the FX family is a set of 802.3-compliant Ethernet media access controllers (MACs). These support 10/100/1000 Base-x transmit/receive interfaces to system peripherals, and are especially useful to the embedded PowerPC processors as a standard communication link to the outside world.

Embedded System Board Design

Virtually all board-level products for open-architecture embedded systems introduced in the last few years have taken advantage of FPGAs for the many features and benefits outlined above. FPGAs not only handle multiple types of interfaces to components, buses and communication links, they can also perform realtime DSP tasks required in demanding

October 2006

TechnologyInContext applications such as data acquisition, software radio, secure communication and radar systems. When embarking upon a new product design, the two main questions product managers and design engineers must answer when selecting the most appropriate FPGA are: 1. Which FPGA best implements the board hardware design requirements? 2. Which FPGA best suits the extra

features expected to be added by the customer? The first question has many facets but is often easier to answer. Usually, all of the components and interfaces on the board are either handled by the FPGA or else connected to the FPGA. This includes memory, clock and timing signals, ASICs, A/D and D/A converters, digital interfaces, buses and communication

links. The FPGA also incorporates several control and status features like registers, data multiplexers, counters and state machines to instrument the control software libraries and drivers supplied with the product. In some applications, the customer can use the product as is, without adding any custom IP to the FPGA. This, of course, makes the second question entirely moot. However, in this case, the unused resources in the FPGA become extra baggage and add to the product cost. Fortunately, different density FPGA devices within a family often share a common package or printed circuit board pattern. This allows a single board design to use a simpler and less expensive FPGA for the customer who needs no additional IP and yet still accommodate a larger device when extra FPGA resources are needed When the customer does want to add IP, the second question above can be even more difficult to answer than the first because each customer invariably wants to implement something unique to his application.

Software Radio Board Example

As mentioned above, software radio products are a natural fit for FPGA technology. The PMC module shown in Figure 2 illustrates a product encompassing many essential features for software radio. Two A/D converters and two D/A converters provide analog IF (intermediate frequency) signal interfaces to external analog RF up- and down-converters and RF amplifiers for ultimate connection to the antenna. Real-time digital signal processing tasks such as digital up- and down-conversion, modulation and demodulation, encoding and decoding and other operations are often all performed by the FPGA. Large memory offered by the DDR2 SDRAM supports a circular buffer for implementing a digital delay memory, which is very useful in signal intelligence applications. In this mode, the accesses are sequential so efficient block transfers can be used to deliver real-time storage and readback at the full sample rate for both channels. The 22

October 2006

TechnologyInContext QDR memory is a smaller SRAM with fast access to non-sequential memory locations. This type of memory is ideal for two-dimensional array processing where rows and columns of matrices need to be accessed equally fast. As a PMC module, a PCIbus interface must be included along with DMA controllers and FIFO buffers. As an XMC module, the unit must include gigabit serial transceivers and some facility for implementing a serial fabric and/or protocol. Lastly, a front panel Ethernet port is extremely useful for control, status and communication functions to virtually any external computer system. The FX family of Virtex-4 devices has all of the necessary features required for these board functions. Therefore, it becomes an obvious choice for this product. Nevertheless, the FX family is quite limited in DSP capability compared to the SX family. Figure 3 shows exact quantities of resources for 8 representatives from the 17 parts in the three families. Even the largest member of the FX family has only the same number of ExtremeDSP slices as one of the smaller SX devices. Since customer access to ample DSP horsepower is a critical factor, an SX55 device is added to the PMC module, significantly boosting the total quantity of DSP slices by 512 from 192 to 704. Since the SX55 must perform digital signal processing on real-time signals to and from the A/D, D/A, QDRAM and SDRAM, those components are attached directly to it. The FX100 is the natural choice for the PCI interface, the gigabit serial interface and the Ethernet port. The PCI interface uses an off-theshelf IP core installed in the FX100. It offers a fully compliant PCI 2.2 PCIbus interface using appropriate Virtex I/O pin interfaces. The local side of the PCI core is augmented with a custom 9-channel DMA engine and FIFO buffers, all tailored to the specific needs of the resources on the module. The XMC interface utilizes the gigabit transceivers (called RocketIO) by grouping four serial bit lanes to form a “4x” port. Operating at a bit rate of 3.125 GHz, the resulting transfer rate is

1.25 Gbytes/s in and out for each port. A second 4x port doubles this rate for the module, providing an extremely fast path to the carrier board. Two 64-bit data buses joining the two FPGAs utilize the source-synchronous digital interfaces for moving data between them at extremely high rates. This supports direct streaming transfers for the XMC ports, which then become fully capable of delivering full rate data to and from A/D and D/A at the maximum sampling rate. The resulting module design offers a highly configurable software radio building block because of the wealth of FPGA resources. Since the FPGA devices share common footprints with other family members, it is possible to substitute parts to tailor the board for a range of processing, cost and power requirements. Selecting a new board product with the appropriate FPGAs requires a thorough understanding of the resources offered by each FPGA device, an appreciation for new architectures used in embedded systems, and good insights into

how the board will be used and what kind of custom FPGA code will be developed to fit the applications. With so many variables, it is essential that FPGA selection not be driven by design engineers alone, but must also involve significant inputs from field applications engineers, sales personnel and key customers. Pentek Upper Saddle River, NJ. (201) 818-5900. [www.pentek.com].

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F CUS On Success

October 2006

SolutionsEngineering RoHS

RoHS: After the Deadline Although manufacturers are on their own when it comes to implementing a RoHS transition strategy, everyone is in the same boat. by A nn R. Thryft Senior Editor

ince July 1, the restrictions in component finishes, component mandated by the European packaging, chip attachments and Restriction of Hazardous SubPCBs. stances (RoHS) directive have gone Consequently, most component into effect. But the transition to an manufacturers have not found it costelectronics industry free of lead and effective to maintain separate but other restricted materials is by no parallel production and assembly means complete, nor will the paths lines to produce both lead-free and leading to that goal be either simple leaded components. In some cases, or easy. it has not proven profitable to conAs most in the industry are by vert a non-compliant component to now aware, the RoHS directive rean RoHS-compliant version, so many stricts the allowable amounts of lead, components are being obsoleted. cadmium, mercury, hexavalent chroAs a result, many subsystemmium, polybrominated biphenyl and and board-level manufacturers have polybrominated diphenyl ether. Since also decided not to maintain separate lead is everywhere in electronics, RoHS-compliant and non-compliant most of the focus has been on this product lines. On the plus side, alFigure 1 Design respins that make subsystem- and material and there are multiple exthough it can be expensive to convert board-level-products compliant with RoHS emptions to the restriction. a product to RoHS-compliant materirestrictions can offer an opportunity for Potentially, the transition from als and components, the redesign opimprovements. Kontron’s MOPSlcdLX non-RoHS to RoHS-compliant elecportunity can bring additional benCPU board, a RoHS-compliant design for tronics manufacturing and assembly efits in improved performance or new PC/104-Plus with ISA and PCI, performs is a major upheaval. At the compofeatures (Figure 1). significantly better, is more thoroughly integrated and supports more economical nent level, the change in solder mateMeanwhile, another major set DDR-RAM memory, yet can be offered rials has proven to be complex. The of complications for subsystem- and at a similar price level to previous lead-free replacement solder materiboard-level manufacturers has been assemblies. als and processes used in component not only maintaining and demonpackaging and board-attach methstrating the company’s own product ods, as well as the higher temperatures traditional tin-lead soldering are 180° to compliance, but deciding how to ensure they require, have demanded changes 200°C. the compliance of incoming materials and throughout component manufacturing By contrast, the temperatures used parts from suppliers. Since this could beand assembly lines. for soldering the most common lead-free come a potential logistical nightmare in Alternative materials, especially for alloys, such as tin-copper for wave solder- terms of part numbering systems and the lead, still have a ways to go. Component ing and tin-silver-copper for reflow sol- fact that the RoHS directive sets no predefinishes must be lead-free and solderable, dering, are much higher at 200° to 260°C. termined standards, the answer seems to as well as capable of withstanding the Soldering process temperature also has a lie in careful internal documentation and higher temperatures required by lead-free direct, sometimes negative impact on the lots of testing. How compliance will be solder materials. Temperatures used for reliability of materials traditionally used enforced remains to be seen. 24

October 2006

SolutionsEngineering RoHS

Weathering the RoHS Storm Implementing RoHS compliance is a complex and potentially confusing process. But with planning, foresight and good communication, it can be done successfully while continuing to ship products. by N orm Hartig VersaLogic Corp.

he much-anticipated enforcement are directly affected by this legislation, date for the European Restriction the changes each company must make to of Hazardous Substances (RoHS) its affected products cause a ripple effect. directive has passed quietly and unevent- These changes cannot be limited solely to fully. But, even though RoHS went into ef- the products directly affected, since RoHS fect without the industry coming to a halt, regulations apply to the “finished goods,” many companies are still facing RoHS-re- or end-user products, and those finished lated challenges. Confusion is widespread goods are manufactured with parts and Get Connected technology and about the initiative, how it is being en- companies processes sharedwith with other products not providing solutions now forced and what is meant by compliance. within the scope of the directive. Get Connected is a new resource for further exploration The effects of this legislation are broader into products, technologies and companies. Whether your goal than what was originally anticipated, and We the Alllatest Know What RoHSspeak Is, directly is to research datasheet from a company, with an Application Engineer, or jump to a company's technical page, the some companies are only now realizing Right? goal of Get Connected is to put you in touch with the right resource. the impacts of RoHS on their ability to RoHS applies to certain finished Whichever level of service you require for whatever type of technology, manufacture and sell their products. goods, with exceptions certain Get Connected will help you connect with thefor companies andkinds products Even though it has been estimated that offor.goods and some sub-assemblies of you are searching www.rtcmagazine.com/getconnected only about one-fifth of electronic products products. The list of finished goods that

must adhere to the directive is limited (“Making the RoHS Transition,” see, pg29). RoHS regulations do not apply unless the product either falls within certain categories defined by the legislation, or fits the directive’s definition of “electrical or electronic equipment” (EEE). A product is not affected unless it is imported into one of the countries in the EU or those in the associated European Economic Area. Despite what appears to be a small selection of products directly impacted by the restrictions, it is apparent now that the question is not whether to address RoHS but how to address it. Perhaps due to industry-wide confusion over the scope of the directive, many executives who thought that RoHS would not apply to their companies are now realizing the need for their products’ compliance. Manufacturers of finished goods continue to have difficulty in determining whether the direcGet Connected with technology and companies providing solutions now tive affects their products. This is because of Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research th the many exemptions that apply to different datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get Connect industries, raw materials and different uses in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and productsofyouthe are searching bannedfor.substances. The confusion www.rtcmagazine.com/getconnected about these exemptions affects component manufacturers, assembly houses and other suppliers identified by RoHS as producers, since they must manufacture products for all of their customers, not just those that require RoHS compliance. Even after the deadline, how compliance with the RoHS directive will be enforced is still unclear. The directive delegates enforcement to the individual

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SolutionsEngineering

Metals prices (in $)

September 05

September 06

% Increase

Peak Price

Tin (per ton)

6900

9000

30%

9700 (May 06)

Copper (per ton)

3750

7600

103%

8800 ( May 06)

Silver (per oz)

7.03

11.1

58%

14.94 (May 06)

Gold (per oz)

454.8

590

30%

725 (May 06)

Source: Compiled from data at www.Kitco.com

Table 1

Metal price changes from September 2005 to September 2006.

October 2006

countries in the EU and the European Economic Area. At first, this raised questions about whether enforcement regulations would be different in each country and, if so, how companies would be able to meet all of them. The focus now is centered on self-enforcement through paper documentation. This approach seems to be gaining acceptance throughout the industry and in Europe. A variety of materials declarations forms may be used. The IPC, an international organization that is a leading source for standards in the electronics industry, has developed materials declarations standards that address the collecting, tracking and disclosing of compliance information. What remains to be determined is when and how to test whether products actually conform to the documentation and who will do such testing. Before the influx of RoHS-related changes can be fully realized, the industry will have to wade through some additional, unforeseen manufacturing challenges. Since the middle of 2005, metals prices worldwide have skyrocketed. The prices of gold, silver, tin and copper, all extensively used in the electronics industry, peaked simultaneously in May just before RoHS went into effect (Table 1). This can be attributed, at least in part, to a rise in demand for metals that replace lead in electronics manufacturing. It is also probably due, in part, to a large number of RoHS-compliant products being introduced to replace non-RoHS parts. Whether because of raw materials shortages or RoHS-related changes, component manufacturers are having difficulty supplying the industry demand for parts. Some components are being obsoleted to make way for RoHS-compliant replacements that are not yet available. Other components are just simply going away, either because the conversion to a RoHScompliant version is not cost-effective, or because they were nearing the end of their product life anyway and RoHS legislation just hastened their demise. Components, of course, are only a fraction of the solution. For board-level electronics, both PCB finishes and solder materials must change to accommodate RoHS requirements. Given these challenges, it is no wonder that many companies do not yet have a clear picture of their RoHS plans.

SolutionsEngineering

Substance

Where found

Alternatives

Lead

Solder, PCB etching processes, PCB finishes

Lead-free HASL PCBs, ENIG finish PCBs, lead-free PCB etching, lead-free solders

Cadmium

As a pigment in plastics, and in some components such as infra-red detectors

Alternative pigments, gallium arsenide infra-red detectors, possible exemption status if used in medical devices

Mercury

Flat panel displays, some button-cell batteries

Mercury-free xenon-based fluorescent discharges for flat panel backlighting, mercury-free batteries

Hexavalent Chromium

Chrome-plated metals such as screws, connectors and steel enclosures

Non-plated metals; nickel-iron-cobalt platings, tri-valent and 0-valent chromiums are acceptable.

Brominated flame retardants (polybrominated biphenols, pentabromodiphenol ether, and octobromodiphenol ether)

Semiconductor encapsulants, PCBs, cables, connectors and housings

Alternative flame retardants, plastics without flame retardant additives. Some exceptions have been granted for flame retardants used in electronics.

laminate materials must withstand alternative soldering processes without bending and warping. Lead-free solderable finishes must be used to replace those that contain lead. Solderable finish alternatives need to be compatible with the soldering process used. Components must use a lead-free solderable finish and be able to withstand the higher soldering temperatures required by lead-free solders. Solder material options include tin-zinc, tin-silver, tin-copper, tin-silver-copper and other alloys. Melting temperatures for these alternatives range from 183°C, slightly higher than that the melting temperature of tinlead, up to 240°C.

Source: E3

Table 2

Substances banned by RoHS and where they are found.

Some RoHS Transition Strategies and Issues

There really are no easy methods for switching over a company’s entire inventory to RoHS-compliant versions, and anyone who tries to say otherwise may need to spend more time out on the factory floor. However, some steps can be taken to make this transition as smooth as possible. With proper research, good planning and clear communication, it is possible to launch RoHS-compliant products successfully while simultaneously continuing to produce and sell products. Not all of the strategies suggested are applicable to every organization, and success does not depend on their implementation in any particular order. One key strategy is to assemble a RoHS team. Its purpose is to bring together people from various areas in the organization to work specifically on the transition. By forming a team, a company facilitates communication and makes sure that concerns are addressed at all stages. These team members should be the company’s experts in R&D, manufacturing, engineering, procurement and logistics, for example. Their key responsibility to the organization is to develop a RoHS plan. To do so, team members will need to draw upon existing knowledge and further research to become the company’s experts in RoHS. Making all departments aware of the challenges faced elsewhere in the company also helps broaden the views of those

involved in implementing the changes, so that no department is left with an unfair burden. For instance, if the R&D department is aware of components that are currently difficult for the buyers to get, they can select alternate components that are easier to obtain. The changes faced by each company will vary depending on what type of product is manufactured, the size of the organization and how much of the inventory, if any, will be transitioned. In all cases, inventory management systems, manufacturing and purchasing will be affected. Departments that have direct contact with these areas will need to understand what the changes will be and how to implement them. Another key strategy is to research all of the options. For all levels of electronics manufacturing, there are multiple options for compliance with RoHS. Choosing which materials and processes are best takes time and effort. In making these decisions, the RoHS team will be a valuable resource. Alternatives are available for most substances restricted by RoHS (Table 2). For many electronics manufacturers, the greatest concern has been replacing the lead used in the manufacture of PCBs and in the soldering process. This is typically done by using PCBs with a non-leaded solderable finish, such as an ENIG finish (Figure 1), and soldering them with lead-free solder. In order to produce electronic boardlevel products without using lead, a number of concerns must be addressed. PCB

Making the RoHS Transition The categories of finished goods identified by the RoHS directive include large household appliances, small household appliances, IT and telecommunications equipment, consumer equipment, lighting equipment, electrical and electronic tools, toys/leisure/sports equipment and automatic dispensers. Categories not covered within the scope of the directive include medical and monitoring equipment intended to protect national security or used by the military, and spare parts used for repair or reuse of equipment sold before July 1, 2006. According to the UK’s National Weights and Measures Laboratory, RoHS applies to “producers of EEE,” or those organizations that manufacture and distribute spares, subassemblies, components, accessories and finished goods that require electricity to perform their primary function. The IPC’s standard materials declaration forms are available at http://www.ipc.org. Other Web sites useful as sources for additional information include http://www.pbfree.info, http://leadfree.ipc.org, http://www.nemi.org/cms/newsroom/PR/2005/PR052405.html, http://www.rohs.gov.uk and http:// www.netregs.gov.uk. October 2006

SolutionsEngineering

0-3 months

3-6 months

Research component replacements.

Purchase and evaluate sample components and materials for use in RoHS-compliant products.

Begin RoHS-compliant product designs.

Create an RoHS team, begin staff education, identify staffing resource needs.

Hire additional staff needed, communicate RoHS plan.

Train staff on new processes and procedures.

Evaluate RoHScompliant manufacturing and testing processes.

Identify equipment and space requirements.

Purchase equipment and create RoHS-specific areas within departments.

Evaluate software and documentation systems and identify changes needed.

Update or replace systems to accommodate RoHS-compliant products and documentation.

Forecast expected component purchases further out and purchase additional stock of those that may be facing early obsolescence or longterm shortages.

Table 3

Suggested RoHS timeline for completion

Tin whiskers have been a concern to manufacturers that are transitioning to RoHS, as well as to those that are not making the transition. Without the inclusion of lead, tin develops hair-like projections that can grow long enough to produce electrical shorts. Some manufacturers that do not want to adhere to RoHS need to ensure that the parts they receive have solderable finishes that mitigate against tin whiskers, because they do not want any risk of compromising the quality of their products. In such cases, knowledge is important. Having a RoHS team to address these kinds of concerns can help. For those that are making the switch, research into the prevention or mitigation of tin whiskers is ongoing. Additionally, there have been great strides in producing components with finishes that are less prone to whiskering, and these have proved durable enough to last for the expected lifespan of most products. Some finishes are highly resistant to whiskering while others are not. Organizations such as iNEMI have done much research into various finishes and have ranked their resistance to whiskers. This research can be used as a guideline for 30

6-12 months

October 2006

12-18 months Perform test runs of products through new processes.

selecting finishes. Keeping track of component finishes and using only those that are whisker-resistant is a good method of ensuring durable, long-lasting electronics.

Forecasting and Testing

Even if a company has not planned to migrate a product to RoHS compliance, that product may still require a redesign. Unfortunately, one of the side effects of RoHS transitions is that manufacturers must make some tough decisions about what they can afford to continue manufacturing. For example, buyers may discover that parts they have been buying for a specific product over several years are now in limited supply from the manufacturer, which will not be producing any more of them, ever. The product based on those parts will therefore need a redesign soon. Worse yet, those parts may be integrated into half a dozen or more product designs that just went into production last year. If the component forecast had come out just a few months earlier, the supplier might have been able to increase their last production run. The secret to avoiding this situation is knowing what weak points may exist and building relationships with vendors. In addition, it helps to keep track of those key components for which there are no ready alternatives, and periodically ask for notification from suppliers when they know about shortages or discontinuations. Although some companies have resorted to buying gray-market parts to

supplement their stock of components facing end-of-life and these parts may appear genuine, many have proved to be faulty. Companies should know their suppliers and be wary of gray-market parts.

Paperwork Alone Is Not Enough: Testing Pays Off

In addition to keeping track of materials declarations to confirm a productâ&#x20AC;&#x2122;s RoHS compliance, it is valuable for a company to do its own testing. Given the confusion vendors are facing, it is not surprising that some components are being sold as RoHS-compliant that do not really meet the directiveâ&#x20AC;&#x2122;s requirements. If there are concerns about a solderable finish, it should be tested. Likewise, it is not wise to depend on the new processes to be problem-free in their first run. They should be tested and re-tested until it is clear that all problems with components, finishes, laminates, solder bonds and temperature tolerances have been worked out and products are meeting quality objectives. Even though lead-free processes have been known about and used for years, the overwhelming majority of components, materials and processes are designed to be compatible with the highly popular and cheap tin-lead solder processes. Now that the industry is changing, assumptions are, too. Eventually, components and materials will be able to be used in RoHS-compliant processes without question, but until then, in-house testing will save headaches as well as dollars.

Itâ&#x20AC;&#x2122;s Going to Take a Lot of Time

One of the most important strategies for handling the RoHS transition is to allow an adequate amount of time. It is not easy to hold off product redesigns and new products while waiting for new software systems to be installed, or to make time for testing a component that has taken weeks to arrive. When well planned, the majority of time and resources spent in a typical timeline for RoHS integration occur in the early stages of the transition (Table 3). Progressively less work is required as the company draws nearer to full RoHS capability. VersaLogic Eugene, OR. (541) 485-8575. [www.versalogic.com].

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IndustryInsight Power Management and Conversion

High Voltage Strikes CompactPCI A high-voltage system in a CompactPCI architecture can offer modularity, tight integration, low cost and remote control and monitoring functionalities for many scientific research projects. by S andeep Babel Bi Ra Systems

roviding high voltage that can be remotely controlled in a small, exploration confined area is a problem faced er your goal eak directly by many laboratories around the world. al page, the This problem became apparent for Sanresource. dia National Laboratories (SNL) when chnology, and products working with the world’s most powerful X-ray generator named the Z-Machine. The Z-Machine is capable of releasing 290 trillion watts for a billionth of a second. That’s 80 times the world’s electrical power usage. Due to the nature of these large scientific machines, the systems need to be placed behind panies providing solutions now Faraday shield screen boxes inside the ration into products, technologies and companies. Whether your goal is to research the latest Z-machine. And because of the limlication Engineer, or jump to a company's technical page, the goal of Get Connected is to put you ited space,type Sandia needed a power soice you require for whatever of technology, ies and productslution you arethat searching for. stack 20 channels of could Figure 1 A PXI chassis with high-voltage high-voltage power in an area no larger boards to meet the needs of the scientific community. than 19” x 40” x 20” and be controlled and monitored remotely via computer control. etc. In the past, this has often required a Physics experiments often require variety of units from different manufacmany (up to 1000) continuously variable turers with different voltage-current rathigh-voltage (2kV to 6kV), low-current ings, control interfaces, voltage, current power supplies for various types of ex- and state monitoring circuitry and output perimental apparatus, such as photo mul- protection features. tipliers, ion chambers, tracking chambers, The physical packaging and I/O connections were also dissimilar. Such lack of uniformity has caused problems with Get Connected with companies mentioned in this article. system implementation, maintainability www.rtcmagazine.com/getconnected and control/monitor software because of

End of Article

October 2006 Get Connected with companies mentioned in this article. www.rtcmagazine.com/getconnected

the need to custom-tailor for each type. The work required to implement large, multi-channel high voltage systems with these system was often difficult and expensive. Traditional high-voltage power systems were offered in NIM, VME or CAMAC architecture. Implementing a full 64-bit bus in VME requires a 6U form-factor, where in CompactPCI, both 32-bit and 64-bit can be implemented using a 3U form-factor. Unlike the older VME-based high-voltage power systems, where the main electronic design constraint was cost, newer designs must meet additional requirements for size, power consumption, remote control and monitoring capability. Newer designs should also be able to seamlessly integrate with other manufacturers off-the-shelf products in an environment containing a large variety of electronic equipment. The CompactPCI architecture allows easy integration of needed functionalities into a single system. Instrumentation, data acquisition, machine vision, motion control and bus interface modules are just a few types of CompactPCI modules available. It also provides a high-performance and rugged industrial form-factor along with high compute density and

IndustryInsight

higher-quality components. Taking these points into consideration, the CompactPCI architecture has been found to meet Sandiaâ&#x20AC;&#x2122;s high-voltage system requirements. Major system requirements are as follows: 1) DC supplies should be modular with the modules supplying an array of voltage ranges (typically -100V to -5KV) 2) Current draw in a quiescent state should be very small (typically < 1 mA) 3) Individual modules should be stable to 5% of the set value over a period of time 4) The ability to control and monitor the voltage and current characteristics remotely using a computer 5) Small and robust design, which is easy to maintain 6) Scalable in nature

System Architecture

Bi Ra Systems has three versions of these high-voltage module boards. Model 4720 has four high-voltage channels each having a voltage range from 0 to -300 volts; Model 4720A (Figure 2) has three channels with each channel having a range of 0 to -300 volts and Model 4730 has two channels, each having a range of 0 to -5KV. Since robustness and remote control and monitoring of these high-voltage systems were a priority, the next consideration was the selection of an appropriate, modular computer-interface bus system. Once again CompactPCI proved to be the bus backplane of choice. The chassis selected for this purpose is National Instruments PXI-1044, which accepts both PXI and CompactPCI 3U modules. The PXI-1044 offers 467W of available power across 14 slots with 25W of cooling for each slot provided by three fans running at 140 cfm. The chassis is PXI specification Revision 2.1-compliant. It is equipped with NI-8196, which is a high-performance Pentium M 760-based embedded controller for use in PXI and CompactPCI systems. The PXI-8196 includes high-performance peripheral I/O

3IMPLIFY 9OUR $EVELOPMENT 0ROCESS

Figure 2

Model 4720A HV board produces 0 to -300 volts in a CompactPCI package.

such as 10/100/1000 Base TX Ethernet, four USB ports, an RS-232 Port and an IEEE 1284 ECP/EPP parallel port. This allows the user to have a choice in selecting the peripheral for remote communications with the chassis. Additionally, it comes with 512 Mbyte dual-channel DDR2 RAM and Windows XP Professional already installed. At the heart of the system for control and monitoring is Quicklogicâ&#x20AC;&#x2122;s 32-bit PCI chip running at 33 MHz, with 14 RAM blocks comprising 32,256 RAM bits and 97 I/O pins. The chip is PCI v2.3-compliant with zero wait states to provide up to 264 Mbyte/s transfer rates. It also offers full PCI Configuration Space and flexible target addressing. It supports retry, disconnect with/without data transfer and target abort requested by the user-programmable logic. Any number of 32-bit BARs may be configured as either memory or I/O space. The boards also have a CMOS FLASHbased 8-bit microcontroller chip from Microchip that acts as a slave, and assists in controlling and monitoring the feedback voltage. The microcontroller features 256 bytes of EEPROM data memory (self-programming), a USART and a synchronous serial port, which can be configured as either 3-wire Serial Peripheral Interface

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two-slot-wide 3U form-factor board. The output voltage is brought down to a more manageable range of 0 to 5 volts using a 60:1 voltage divider in the case of 4720 and 4720A, and 1000:1 divider in the case of 4730, which was then monitored using 10-bit ADCs. The boards also use many of Linear Technology’s Power Management chips to juggle the available power to be used on the board. Figure 3 A LabVIEW setup for testing the boards. To control the power supply cards, (SPI) or the 2-wire Inter-Integrated Cir- LabVIEW from National Instruments was cuit (I²C) bus. chosen because of its easy to understand The Models 4720 and 4720A utilize graphical interface controls. LabVIEW DC to high-voltage DC converters that re- also provides a deterministic, real-time quire an input current of 70 mA, with an performance along with LabVIEW Real input impedance of 10K ohm. These mod- Time for data acquisition and control. ules have less than 10 mV peak to peak of LabVIEW can be readily deployed and ripple and are protected against continu- the cards can easily be controlled and ous output short circuits. These supplies monitored over Ethernet (Figure 3). do not have Input/Output isolation; hence The intensive computing prowess of Isolation amplifiers were used to effec- today’s chips implies that fewer discrete tively isolate the high voltage. At full run- components need to be used to achieve ning capacity, each of these high-voltage almost identical results, which results in modules uses 0.7 watts of power. a drastic reduction of PCB real estate and On the other hand, Model 4730 uti- cost. Apart from that, it is much easier to lizes DC to high-voltage DC converters maintain and scale these systems. that require 380 mA of input current and Possible applications of these highsupply 3W of output power with a 5% typ- voltage power modules will be in Photo ical regulation. The modules also have a Multiplier Tubes (PMT), which are used 6KV input/output isolation. The finished for analytical applications like emisModel 4720 and 4730 boards have eight sion-spectroscopy, fluoroscopy, atomiclayers with impedance-controlled traces absorption-spectroscopy as well as bio and split ground planes for high and low and chemo-luminescence. Ionization voltages respectively. Special care has chambers, CRT systems testing, highbeen taken to prevent noise from cou- voltage biasing for Avalanche Photodipling onto the digital data, address and odes and Photo detectors, X-ray tubes control lines, which interface with the and pulse generators (used in radars, CompactPCI bus. lasers, EMC testing and other imaging A 3U form-factor of these boards applications) are other potential users of presents significant challenges for noise this technology. coupling, heat dissipation and arcing. When running at full capacity, the 4730 Bi Ra Systems boards produce 384 volts/inch-sq’ even Albuquerque, NM. at low output current; this has a poten- (505) 881-8887. tial of arcing over the air. The 4730 is a [www.bira.com].

Executive Interview

. . . An Exciting Time to be an Embedded Systems Developer RTC Interviews Rob McKeel, CEO, GE Fanuc Embedded Systems

RTC: Just to make sure what it is brand: GE Fanuc Embedded Systems, we’re talking about, can you give our headquartered in Albuquerque, NM. readers some idea of exactly what the structure of GE Fanuc is? We RTC: At this time, the mid- and highunderstand that GE Fanuc is a joint end embedded computer business—as venture of GE and Fanuc (from Facmeasured by RTC’s research team— tory Automation Numeric Control) will top out at about $7 billion this and that GE Fanuc Embedded Sysyear. If we do our best to add up GE tems is a wholly owned subsidiary. Fanuc’s acquisitions so far and make Are all the recent acquisitions of GE estimates for growth of the VMIC, Fanuc (SBS, Condor, VMIC, Ramix, Ramix and Computer Dynamics acComputer Dynamics) now under GE quisitions, we’re looking at somewhat Fanuc Embedded Systems’ control? over $300 million in revenue. In orDidsolutions I miss now any? Will you have a sepader to capture any significant market mpanies providing rate brand in the future, or will it reshare, GE Fanuc Embedded Systems oration into products, technologies and companies. Whether your goal is to research the latest is goingis to plication Engineer,main or jumpGE to a Fanuc? company's technical page, the goal of Get Connected to puthave you to grow some five vice you require for whatever type of technology, times or more. How does GE expect nies and productsMcKeel: you are searching GE for. Fanuc Embedded Systo expand its embedded computer tems is part of GE Fanuc Automation, business? How much does it expect to a joint venture between GE and Fanuc expand with organic growth, and how Ltd of Japan. GE Fanuc Embedded much through acquisition? Systems is made up of the acquisitions made by GE Fanuc Automation McKeel: We do not disclose our diviover the past several years. GE Fanuc sional revenues, so I cannot comment Embedded Systems is organized as a on your revenue assumptions. While the division within GE Fanuc Automation. embedded market is very fragmented, All of the recent acquisitions that serve there is definitely a need for resourcethe embedded industry are under one ful, stable suppliers who can become long time development partners. We will continue to look for all opportuniGet Connected with companies mentioned in this article. ties to meet our customers’ needs.

r exploration her your goal peak directly cal page, the ht resource. echnology, and products

End of Article

www.rtcmagazine.com/getconnected

October 2006 Get Connected with companies mentioned in this article. www.rtcmagazine.com/getconnected

RTC: GE Fanuc Embedded Systems’ last two acquisitions were predominately in the military and aerospace area: SBS did about 60% of its revenue in the military and Condor 100%. 1) Is there expected to be any synergy with GE’s other military business such as its engine division? And 2) The military and aerospace portion of the $7+ billion overall embedded computer market is expected to top out at about $2.75 billion if it continues at its current pace. Does GE Fanuc Embedded Systems plan to capture a larger portion of that market segment or will it go after the other markets (medical electronics, industrial control, transportation, etc.) equally? McKeel: The divisions of GE have been and will continue to be a customer for GE Fanuc Embedded Systems. The value proposition for the divisions of GE is the same as for our external customers. Our focus is on three major segments: military/aerospace, communications and commercial. We will focus our investments to service each of these segments based on the demands from the customer base. Several of the

ExecutiveInterview

technologies and standards translate across each of these segments. Our diverse portfolio of products and extensive technical capabilities allow us to effectively service each segment. RTC: The embedded computer market has always been technically driven. New products, new architectures and higher performance, lower price and lower power have been key drivers for successive generations of products. Does GE Fanuc Embedded Systems have any corporate goals to move in new directions? For example, a company known for large form-factor boards and systems recently had an internal contest among its engineers to design clever PC/104 products. Does GE Fanuc Embedded Systems plan any moves into small form-factor boards? Into other architectures? McKeel: We put a significant emphasis on innovation. One of the reasons we have collected these companies together is to have the engineering resources to develop products beyond what any of them could have developed alone. This is an exciting time to be an embedded systems developer with many new bus architectures, form-factors and switch fabrics. GE Fanuc Embedded Systems will invest in the technologies that have the most merit and customer interest. Embedded electronics will continue to get smaller, more dense and faster. We are ready to take advantage of those trends. As an example, our ASLP10 AdvancedMC processor board is more capable than 6U VME boards from only a couple years ago, and at a fraction of the size. RTC: The embedded computer industry is gradually moving from parallel backplane architectures to serial and pseudo-serial approaches using Ethernet, PCI Express and other serial buses. What are GE Fanuc Embedded Systems’ plans to move into some of the newer architectures such as CompactPCI express?

McKeel: We will develop some of the newer architectures, like CompactPCI Express, as it becomes clear there is real customer demand. There are too many new architecture for each of them to be a commercial success. Also, in the defense space, customers are reluctant to take on new technologies simply because it’s today’s latest and greatest commercial technology. Military and aerospace developers want to see a commitment to the product far into the future since those applications may have to be supported for many years. A case in point is military’s use of VMEbus technology, which is now celebrating its 25th anniversary. Every year there are stories predicting the demise of VMEbus but that hasn’t happened yet—many military systems that depend on VMEbus are still going strong. Many of the technologies that were predicted to displace it are themselves already in decline. RTC: VITA’s VSO and PICMG have been busy looking at what the nextgeneration embedded computers are going to look like. The VSO, driven largely by the perceived requirements of the military, is rushing ahead with its VITA 58 (cans) standard while a splinter group of PICMG is looking at an alternative addressing the need of speed and closely packed, highperformance semiconductors for the development of a liquid-cooled, fully enclosed package. Is GE Fanuc Embedded Systems involved in working in any of these camps and does it currently have an approach that it’s backing? McKeel: GE Fanuc Embedded Systems, as well our recent acquisitions, has long been a participant in both VITA and PICMG. As an industry, we have been a bit reckless in creating many specifications with many variations and then creating a new standard before the previous one sees wide adoption. We will continue to invest in unique ways to solve our customers’ problems, focusing on solutions that have longer-term commercial viability.

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ExecutiveInterview RTC: With the acquisition of SBS, GE Fanuc Embedded Systems acquired what remained of SBS’s acquisition of SDL. Currently this operation makes a variety of telecom-related mezzanine or daughter boards in both the PMC and AMC form-factors. Many—including groups at Lucent and Motorola—believe all future communications systems will be based on AMC both as mezzanine to AdvancedTCA and as the heart of

MicroTCA systems. Does GE Fanuc Embedded Systems plan to expand its presence in the communications arena? Will it continue to support its current products such as the AMC cards used in the IBM servers? McKeel: GE Fanuc Embedded Systems is committed to AdvancedTCA, AdvancedMC and MicroTCA architectures. We are developing additional AMCs in most of our locations. It has

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October 2006

1/11/2006 1:24:11 PM

ExecutiveInterview been truly a company-wide endeavor. Today, we believe our Telum AdvancedMC product offerings are the broadest in the industry and we plan to build upon the variety and depth of communications products we currently have. We saw the merits of AdvancedMC early and were one of the first companies to significantly invest in this technology. Our relationships with our partners and customers continue to strengthen as we mutually see these deployed in successful OEM products.

Every year there are stories predicting the demise of VMEbus but that hasnâ&#x20AC;&#x2122;t happened yet

RTC: More and more embedded computer makers are moving from the board to the system business. Companies such as Curtiss-Wright and Mercury Computers, and SBS prior to the acquisition, made strategic acquisitions to position themselves to produce more of a system and move further up on the food chain. What is GE Fanuc Embedded Systemsâ&#x20AC;&#x2122; plan to offer higher levels of integration, and what is it planning to do in order not to compete directly with its customers? McKeel: GE Fanuc Embedded Systems is excited about the portfolio and internal ecosystem we have to support the rugged systems business. We do not compete with our customers since we do not create the applications that run on our systems. Like our board products, we offer systems based on open standards, but add the additional value of integration and interoperability. RTC: With all its recent acquisitions, GE Fanuc Embedded Systems addresses applications across the board from military to industrial control to medicine. Which area do you believe will demonstrate the greatest growth over the next 12 months? Why?

communications segment. The communications segment can quickly ramp or under-perform expectations without a lot of leading indicators. RTC: There are many analysts who claim the communications business is on the verge of explosive growth. For example, a recent Wall Street Journal article said that a report indicated that the Cable industry was going to have to spend mega-billions of dollars to keep up with the performance that Verizon is now beginning to deliver with its fiber-to-the home initiative (which by itself will take some $20+billion of infrastructure dollars). And, 3G wireless is starting to take hold globally and eventually here in the U.S., adding more billions to the infrastructure bill. Perhaps not all, but some percentage is expected to be in the standard form-factor, embedded computer business. Does GE Fanuc Embedded Systems intend to participate in this potentially explosive market? How? With what product families? McKeel: We are already participating in the embedded communication products segment with our extensive line of AdvancedMC modules, AdvancedTCA boards and our IBM BladeCenterT AdvancedMC carrier blade, and we have every intention of continuing to expand these lines of products. We also are working with key communications customers to meet their next generation of product requirements. Open standard embedded systems offer a cost-effective means for telecom equipment providers to bring their solutions to market quickly, as well as offer them a way to use modular technology to migrate and update that equipment after it is deployed.

McKeel: As you know, product lifecycles in this business are very long. Nothing significant will change in the next 12 months that has not been in development for the last couple years. We are anticipating solid growth across the embedded space. If there is going to be a surprise, it will come from the October 2006

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SOFTWARE

TOOLS & TECHNIQUES 45 U sing Resource Partitioning to Build Secure, Survivable Embedded Systems Paul N. Leroux and Kerry Johnson, QNX Software Systems

50 TimeMachines: The Future of Debuggers Michael Lindahl, Green Hills Software

54 An RTOS for an SMP Multicore Processor John A. Carbone, Express Logic

58 “ Not Your Father’s CORBA” — An Architecture for Embedded and Real-Time Systems Victor Giddings, Objective Interface Systems

62 E nterprise-Strength Solutions Meet the Demands of Today’s Embedded Systems Robert Day, LynuxWorks

66 I mplementing High-Availability Middleware on ATCA— Step-by-Step Jim Ewel, GoAhead Software

70 O pen Architecture Network Software Platforms Speed Complex Development Terry Pearson, Enea

The National Ignition Facility (NIF) under construction at the Lawrence Livermore National Laboratory is a stadium-sized facility that will contain a 192-beam, 1.8-Megajoule, 500-Terawatt, ultraviolet laser system together with a 10-meter diameter target chamber with room for multiple experimental diagnostics to study inertial confinement fusion (ICF) and matter at extreme energy densities and pressures. Photo Courtesy of University of California, Lawrence Livermore National Laboratory, and the Department of Energy.

SoftwareTools&Techniques

Using Resource Partitioning to Build Secure, Survivable Embedded Systems Adproviding IndexCPU guarantees for each software By subsystem, resource partitioning can thwart cyber attacks and thewithavailability Getensure Connected technology and of critical services. companies providing solutions now

Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal Paul N. isLeroux and Kerry Johnson to research the latest datasheet from a company, speak directly QNX withSoftware an ApplicationSystems Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for.

irtually every embedded system today is connected, either points. Unfortunately, no amount of testing can fully eliminate www.rtcmagazine.com/getconnected physically or wirelessly, to the outside world. This net- bugs and security holes, as no test suite can possibly anticipate work connectivity creates untold possibilities for remote every scenario that a complex software system may encounter. monitoring and control, and enables systems to download new applications or content on the fly. However, it also makes systems Secure Compartments vulnerable to infiltration by a growing cadre of cyber terrorists To address these reliability and security issues, some designs Get Connected with technology and companies providing solutions now and cyber extortionists. In fact, malicious hackers have already place virtual compartments, or partitions, around groups of softGet Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research the latest compromised a variety of SCADA systems, HVAC control sys- ware processes and allocate a predetermined set of resources, datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you tems, mobile devices, nuclear systems, usingyou vi-requireincluding to each partition (Figure 1). The system can in touchand with even the right resource.safety Whichever level of service for whateverCPU type oftime, technology, ruses, denial-of-service (DoS)willattacks, and other network-based Get Connected help you connect with the companies and products you are searching for. exploits. www.rtcmagazine.com/getconnected Remote Device Core User Given these threats, embedded developers must seriously Interface Drivers Application Interface consider security when designing any new system. However, given the huge number of embedded systems already deployed, Microkernel Message Passing Bus developers need techniques that can also make legacy designs resistant to cyber attack, preferably without software redesign or File Core Fault Networking recoding. Moreover, these techniques must work within the strict System Application Recovery CPU and memory constraints that characterize the majority of Partitions embedded designs, both old and new. Security may be key, but minimizing resource consumption remains as important as ever. Figure 1 With resource partitioning, a system designer can place software processes into separate Achieving secure operation while satisfying these constraints compartments and allocate each compartment represents a significant challenge, Get Connected with companies and which is made all the more Get Connected guaranteed portion ofarticle. memory and CPU time. products featured in this section. difficult by the growing complexity of embedded software. This witha companies mentioned in this This approach prevents malicious or poorly written www.rtcmagazine.com/getconnected www.rtcmagazine.com/getconnected complexity can undermine reliability for the simple reason that processes from monopolizing resources needed the more code a system contains, the greater the probability that by other processes. coding errors or unanticipated software interactions will make their way into the field. Even well written software can contain Get Connected with companies mentioned in this article. an average of one error per thousand lines of code. Such errors www.rtcmagazine.com/getconnected Get Connected with companies and products featured in this section. also compromise security, since they often serve as hacker entry

Products

End of Article

www.rtcmagazine.com/getconnected

October 2006

SoftwareTools&Techniques

10% I/O Partition OS Microkernel

File System

70% Application Partition

Device Drivers

Core Application

Add-On

Core Application

Networking

No idle time

Add-On

Enforce CPU Guarantees

Allocate idle cycles based on task priority

Idle time available

Figure 2

20% Untrusted Partition

50%

100%

Adaptive partitioning enforces CPU budgets when the system is loaded and allocates free CPU cycles during periods of lower processor utilization. For instance, processes in the Untrusted Partition can run in time allocated to the I/O and Application partitions when processes in those partitions don’t consume all of their budgeted CPU cycles.

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October 2006

path from PowerPC Altivec™-based platforms as well as a software insulation layer common with previous versions your legacy software investments are preserved. Choose between board component versions (the PowerNode5) or the pre-integrated PowerMP5. Transport and management software are standards-based and both products run Red Hat Linux or Wind River VxWorks. To improve our end-user software productivity, the PowerNode5 features the Gedae Workbench development tool, providing all the capability required to develop application graphs and validate their functionality. No wonder more blue-chip companies are turning to ruggedized solutions from Thales Computers to meet their critical computing needs.

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SoftwareTools&Techniques thus prevent processes in any partition from erroneously or maliciously monopolizing resources needed by processes in other partitions. In the defense and aerospace industry, for example, many partitioned systems comply with the ARINC 653 specification, which provides a well-known, though somewhat rigid and inefficient, approach to resource partitioning. Among other things, partitions can provide memory protection, where the OS uses the memory management unit (MMU) to control all memory access. A microkernel operating system, for instance, can partition applications, device drivers, protocol stacks and file systems into separate, memory-protected processes. If any process, such as a device driver, attempts to access memory outside of its process container, the MMU will notify the OS, which can then terminate and restart the process. This approach offers an immediate and measurable improvement to system reliability. First, it prevents coding errors in any process from corrupting other processes or the OS kernel. Second, it makes such errors much easier to pinpoint and correct, before they make their way into final product. And third, it reduces fault-recovery times dramatically. Rather than having to reboot when a memory violation occurs—a procedure that can take seconds to minutes—the system can simply restart the offending process, which may require only a few milliseconds. Nonetheless, building a reliable system involves more than partitioning functionality into separate memory domains. For many systems, ensuring resource availability is also critical. If a 98390_2p4c_Analog.qxd 8:20 Pagethe 1 services key subsystem is deprived of 1/4/06 memory or CPUAMcycles,

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provided by that subsystem will become unavailable to users. In a DoS attack, for instance, an external system could bombard a device with requests that need to be handled by a high-priority process. That process will then overload the CPU and starve other processes of CPU cycles, making the system unavailable to users. A security breach isn’t the only cause of process starvation. In many cases, adding software functionality to a system can push it “over the brink” and starve existing applications of CPU time. Historically, the only solution was to either retrofit hardware or redesign software.

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October 2006

SoftwareTools&Techniques Fixed Partition Schedulers

To address these problems, some operating systems offer a fixed-cycle partition scheduler, typically based on ARINC, which allows the system designer to group processes into partitions and to allocate a percentage of CPU time to each partition. With this approach, no process in any given partition can consume more than the partition’s statically defined percentage of CPU time. For instance, let’s say a partition is allocated 30% of the CPU. If a process in that partition subsequently becomes the target of a DoS attack, it will consume no more than 30% of the total available CPU time. Other partitions can continue to access the remaining CPU cycles. Fixed-cycle schedulers have their drawbacks, however. Since the scheduling algorithm is fixed, partitions that aren’t busy consume their allocated CPU cycles in an idle state. Meanwhile, other partitions can’t access those unused cycles, even if those partitions are busy and could benefit from the extra processing time. This approach squanders valuable (and available) CPU cycles and prevents the system from handling bursty demands. Because of this “use it or lose it” approach, fixed partition schedulers can achieve only 70% CPU utilization. This cap on CPU utilization presents several undesirable choices to the system designer: use a faster, hotter, more expensive processor; limit the amount of software functionality that the system can handle; or simply tolerate slower performance. As a further problem, developers must modify the software configuration to implement or change each partition. Also, to request OS

services, or to communicate with other processes, applications must use the APEX interface, as defined in the ARINC standard. This restriction prohibits legacy applications from leveraging the benefits of secure partitioning.

Adaptive Partitioning Schedulers

Another approach, called adaptive partitioning, addresses these drawbacks by providing a more dynamic scheduling algorithm. Like fixed-cycle partitioning, adaptive partitioning allows the system designer to reserve CPU cycles and memory for a process or group of processes. The designer can thus guarantee that the load on one software subsystem won’t affect the availability of other subsystems. Unlike fixed approaches, however, adaptive partitioning recognizes that CPU utilization is sporadic and that one or more partitions can often have idle time available. Consequently, an adaptive partitioning scheduler will dynamically reallocate those idle CPU cycles to partitions that can benefit from the extra processing time. This approach offers the best of both worlds. For guaranteed availability of applications and services, it can enforce CPU guarantees when the system runs out of excess cycles. Alternatively, for maximum CPU utilization and performance, it can dispense free CPU cycles when they become available (Figure 2). Adaptive partitioning offers several advantages, including the ability to: • Use real-time, priority-based scheduling when the system is

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SoftwareTools&Techniques lightly loaded—this allows systems to use the same scheduling behavior that they do today • Overlay the partitioning scheduler onto existing systems without code changes—users can launch existing POSIX-based applications in a partition, and the scheduler will ensure that partitions receive their allocated budget • Achieve 100% CPU utilization—this allows integrators to realize the benefits of time partitioning, but without the need for faster, more expensive processors • Guarantee that fault-detection and recovery operations have the CPU cycles they need to repair software faults, thereby improving mean time to repair (MTTR) • Allow operators to remotely monitor, troubleshoot or upgrade the system, without interrupting the availability of critical applications • Ensure rapid, predictable response to user actions (e.g., button push, remote console command, voice command), no matter how busy the system may become • Stop malware and DoS attacks from stealing all available CPU time While adaptive partitioning offers greater flexibility, fixedcycle scheduling may be desirable in some situations. To address this requirement, an implementation of adaptive partitioning should allow the system designer to configure a system with fixed partition budgets and no CPU time “borrowing.” This approach frees system designers to choose the most appropriate scheduling behavior for their application requirements. To further enforce CPU budgets, a partitioning scheduler can also provide partition inheritance. The principle behind this mechanism is simple: Whenever a server process, such as a networking driver or a file system, executes requests on behalf of a client application, the client is billed for the server’s time. As a result, runaway clients can’t monopolize drivers and services needed by other applications. Moreover, server processes can run with a minimal CPU budget—only the budget required to perform background tasks. Consequently, system designers don’t have to re-engineer the server budget when more client applications are added (Figure 3). Partitioning can also avoid the performance and reliability problems that inevitably arise when integrating multiple software subsystems. An OEM may, for example, need to integrate application programs from one vendor, protocol stacks from another, multimedia middleware from yet another, and an embedded database from still another. The manufacturer must then combine those components with multiple software subsystems developed in-house, each written by a separate development group. Given the parallel development paths, performance problems invariably arise at the integration phase, when, for the first time, the various subsystems begin vying with one other for CPU time and other system resources. Subsystems that worked well in isolation now respond slowly, if at all. Solving such problems is inherently time-consuming. Once the cause has been identified, system designers must juggle task priorities, possibly change thread behavior across the system, and then retest and refine their modifications. This iterative process

can easily take several calendar weeks, resulting in increased costs and delayed product. Adaptive partitioning can head off this problem at the design stage, by allowing systems designers to allocate a predetermined CPU budget for each partition. When subsequently testing processes in their partition, developers can launch a simple, CPU-intensive program into other partitions to simulate a heavily loaded CPU. They can then test the operation and performance of their partition under a simulated worst-case condition. As a result, developers can resolve potential performance and CPU-contention issues well before the integration phase. In almost every industry, embedded systems are growing in complexity, with a voracious appetite for computational power. Multicore processors offer the ideal performance upgrade for such systems by delivering significantly greater performance per watt, per ounce, and per square inch than conventional uniprocessor chips. In fact, system designers will have little choice but to embrace multicore technology, as it is quickly becoming the basis of most new processor designs. Thus, an OS must be able to support resource partitioning on multicore hardware. Unfortunately, most legacy RTOSs, including those with partitioning schedulers, can control only one CPU or processor core at a time. Developers must, as a result, run a separate copy of the RTOS on each core of the multicore chip. Because neither copy “owns” the entire system, the application designer, not the OS, must handle the complex task of managing shared hardware resources on the multicore chip, including physical memory, peripheral usage and interrupt handling. To avoid these problems, systems designers should choose an RTOS that can control multiple cores simultaneously, manage shared resources, and provide dynamic load balancing across cores— while still enforcing resource guarantees. Embedded software is becoming so complex that, without some form of partitioning, system designers and software engineers will be hard-pressed to satisfy the conflicting demands for reliability, performance, security, time-to-market and new features. Resource partitioning goes a long way toward addressing these requirements by providing each subsystem with a guaranteed portion of memory and CPU cycles, while still delivering the deterministic, real-time response that embedded systems require. Vendors can, as a result, contain the effects of DoS attacks and other network-based exploits; allow new and upgraded components to run without compromising existing system behavior; and readily integrate subsystems from multiple software teams, subcontractors and third-party developers. If the partitioning solution also provides a flexible, efficient scheduler that allows 100% CPU utilization, then vendors can realize these various benefits without having to incur the cost of faster, more expensive hardware. QNX Software Systems Ottawa, Canada. (613) 591-0931. [www.qnx.com].

October 2006

exploration er your goal eak directly l page, the resource. hnology, and products

SoftwareTools&Techniques

TimeMachines: The Future of Debuggers There are a wide variety of problems in software development that most debuggers don’t allow you to easily fix. Real-time trace and debuggers that run backward as well as forward can help ease this pain and lead to a much more efficient debugging environment.

by M ichael Lindahl Green Hills Software

etting a product to market earlier can mean the difference between wild success and complete failure for a device software project. Yet many projects are delayed for software quality reasons, and even if they are not delayed, the schedules are often padded to allow for unexpected bumps and bugs in the panies providing solutions now the software. road to shipping What is the one factor that ration into products, technologies andnumber companies. Whether your goaldeis to research the latest ication Engineer,lays or jump to a company's technical the goalthem of Get Connected is to put you software projects andpage, prevents ce you require for whatever type of technology, from shipping earlier? Once the software es and products you are searching for. is written and integration and testing have begun, only one thing prevents the product from shipping—bugs. At this point, the vast majority of a software development team’s time is spent debugging software problems, and shipping delays are almost always due to unfixed bugs or glitches. Sometimes these problems are bugs that reproduce easily and can be fixed quickly. However, the bugs that usually take up the

End of Article Get Connected

Figure 1

with companies mentioned in this article. www.rtcmagazine.com/getconnected

October 2006 Get Connected with companies mentioned in this article.

A trace probe connected to an ARM 9 target.

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SoftwareTools&Techniques majority of this time are difficult to reproduce or only occur under certain circumstances. Sometimes the bugs only occur on the tester’s machine; sometimes the bugs can’t be reproduced in the lab—but these bugs must be fixed before a reliable product can be shipped. Whereas simple bugs can be fixed by running them in the debugger, stepping through the code and understanding the flow, these hard to reproduce bugs take the majority of debugging time and are very difficult to fix because the bug cannot be easily reproduced with the debugger attached. This leads to a very inefficient, trial-and-error process where engineers speculate about the cause of bugs, study the code and generally guess at where the problem may lie. They may add print statements or other manual instrumentation in an attempt to corner the bug, but this process is often a matter of guesswork more than anything else. And as device software continues to grow in complexity, the amount of time that developers have to spend debugging their software will only continue to grow. Today, innovations in debugging technology are working in the software engineer’s favor to help bring this problem of shipping reliable software in a reasonable amount of time under control by making these bugs easier to trap and eliminate. Debuggers that allow you to stop when a bug occurs and then step and run backward to the source of the bug, are becoming a reality and can help eliminate these nasty bugs. This allows you to capture a bug, and once it is captured, to replay the sequence of events that led up to the bug, essentially allowing you to turn a very difficultto-reproduce bug into a simple, easy-to-reproduce bug. The technology that is enabling these debuggers is real-time trace, and it is enabling debugging that can make software projects more predictable and manageable.

formation as the processor runs at full speed, enabling an external device—called a trace probe—to collect this information non-intrusively as the system runs (Figure 1). Some examples of microprocessors that are equipped with a real-time trace port include many ARM7, ARM9 and ARM11 processors, which include the Embedded Trace Macrocell (ETM) from ARM, as well as the AMCC PowerPC 4xx family, the PowerPC 54xx family and the ColdFire family of processors from Freescale. The trace probe collects this information using a circular buffer that enables you to collect detailed information about the execution of your software over relatively long periods of time. The circular buffer means that the trace probe is always storing the most recently executed instructions, so when your software encounters a bug, you can stop the trace collection and store the sequence of instructions and memory accesses that led up to that bug (Figure 2). The trace probe’s collection of trace data can either be stopped manually, when the user presses a button—either on the probe or on a host machine—or by using flexible triggers that allow you to configure the location of a bug, so that trace can be retrieved without altering the system behavior in any way. For instance, you can trigger when a specific line of code is hit or when a variable is written to with a specific value. Once you have captured the sequence of instructions that precede a software glitch, you have essentially captured the bug and you can analyze the data to find the root cause of the problem. Trace analysis software can be used to reconstruct the state of the microprocessor for every point in time that you have captured trace data using a standard instruction-set simulator. Thus you can now know the sequence of instructions and the value of most register and memory values that led up to the bug.

Real-Time Trace

Once the trace analysis tools know the sequence of instructions and the memory values, this information can be used as the back-end of a standard software debugging session. Essentially, the debugger simply replays the instructions from the trace data rather than talking to a live target. The debugger translates the raw instructions into source code lines and the raw memory values into variable values. This enables you to easily browse the state of the system at any point back in time using a familiar interface. However, you can also use the debugger to fully replay the system along the same path that led to the bug you have captured. The debugger lets you step forward from one instruction to the next, and all of the state variables will update to display the new values. In addition, the debugger allows you to run forward to a breakpoint by searching forward through the instructions for any address where you have set a breakpoint. You can even set watchpoints and data breakpoints, and again, the debugger will search forward for the next access to a memory location when you run the program. The real power of such a tool, however, rests in its ability to run backward as well as forward. This is accomplished using the same techniques described above, except instead of stepping forward, the tool simply searches backward for instances in the trace data where breakpoints or watch points are hit. Stepping and running backward enables you to quickly step

Real-time trace refers to special debug ports built into many embedded microprocessors, which provide detailed information about what instructions the processor executes as well as the sequence of memory loads and stores caused by these instructions. Processors equipped with this special debug port output this inTrace-Enabled Microprocessor

Trace Port

Trace Probe

Figure 2

USB, Ethernet, etc.

Host PC

A block diagram of a trace probe collecting trace data from an ARM 9 system. The trace data is transferred from the trace port on the microprocessor and stored in the circular buffer in the trace probe. It is then transferred to the PC where the debugger can examine it in both backward and forward execution.

October 2006

Debugging Forward and Backward

SoftwareTools&Techniques or run backward to the source of the bug after encountering an error condition. You can investigate various possible solutions and find exactly what conditions led up to the error. Because you have stored the trace data, you can easily replay your software both forward and backward in time to understand its behavior and track down any type of bug (Figure 3). This enables you to quickly track down the types of bugs that are otherwise extraordinarily difficult to reproduce using traditional debugging techniques, because traditional techniques require you to reproduce the error under the debugger. Some bugs may take several minutes to reproduce, simply because you have to restart the system and go through a complicated procedure to reach the buggy code. Other bugs donâ&#x20AC;&#x2122;t even reproduce reliably and you have to try a certain sequence many times before the bug reproduces. And then, if you step past the bug in the debugger, you have to start all over again. But with stored trace data, you can eliminate all of these problems, because you know exactly what code paths were executed and what caused the glitch. If you can capture a bug in the trace data once, then you can spend as much time as necessary tracking down the problem and fixing it. You can even attach a trace probe to testing and verification units in the quality department or to the first units shipped to help capture detailed information about glitches that occur rather than having to rely on bug reports and reproducing the problem in the lab. Capturing difficult-to-reproduce bugs during testing can eliminate weeks or months from the schedule of device software projects because so much time is often spent tracking down these types of bugs, especially as the software gets closer and closer to being released.

Aiming at Multicore

As embedded systems continue to grow in complexity, more and more systems will employ multicore designs. This may involve many identical cores running at the same clock frequency or different processor architectures running at vastly different speeds. Regardless of the specific multicore design, the problem of synchronization and communication between various processing elements remains daunting for software designers. A small timing delay at any point can potentially cause drastically different results if the software has a minor glitch. Tracking down these types of problems with traditional tools is very difficult, because reliably reproducing these bugs may be nearly impossible. However, if you could collect synchronized real-time trace information from each of these processing elements, you would be able to replay the sequence of instructions on each processor to determine the exact interactions between the various cores and their software. Thus, if a timing error causes a failure in the system, you could find the bug in the software that did not properly handle the specific timing condition. Alternatively, if a shared resource, such as shared memory or a shared device, is not properly locked, you could find the offending code quickly and easily rather than having to rely on trial-and-error debugging techniques to find the problem. In addition, system peripheral and coprocessor registers often heavily influence device software implementations, so adding trace support for these devices to enable software-level access

Figure 3

A screen shot of the TimeMachine debugger with both forward and backward run-control buttons enabled. You can also see the state of variables, registers and other processor information at any point in time through the TimeMachine debugger.

and understanding of these devices over time would greatly simplify the process of tracking down various device-level problems caused by errors in the software. Technology for solving both of the above sets of problems is beginning to emerge. ARM is moving toward multicore and multi-device trace with their new CoreSight technology. This technology includes modules to multiplex data from various onchip sources into a single, synchronized trace stream that can be captured and replayed. In addition, other processor companies are embracing real-time trace technology to make the difficult job of releasing high-quality software in a predictable amount of time easier. While todayâ&#x20AC;&#x2122;s software is much larger and more complicated than five or ten years ago, most engineers still rely primarily on debugging technology that does not solve some of the hardest problems facing software engineers today. Traditional debuggers do not provide enough visibility into the inner workings of your software to maximize your productivity when tracking down and debugging software errors. However, leveraging real-time trace technology and the most advanced software debuggers can greatly increase programmer productivity, helping eliminate some of the biggest schedule delays in software development. Green Hills Software Santa Barbara, CA. (805) 965-6044. [www.ghs.com]. October 2006

SoftwareTools&Techniques

An RTOS for an SMP Multicore Processor The advent of multicore processors is putting greater demands on applications and the programmers who build them. In a symmetrical multi-processing model, certain mechanisms built into the RTOS can greatly ease that burden.

and

er exploration ether your goal speak directly ical page, the ght resource. technology, es and products

by J ohn A. Carbone Express Logic

or years, processor performance has increased, following Moore’s Law, at a rate of 2x every 18 months. But, in October 2004, Intel acknowledged that power consumption was making it more and more difficult to continue to boost clock speed, and canceled plans for a 4.0 GHz Pentium 4. Instead, it announced that it was working on two other methods that it called “dual core” and “hyper threading.” The former combines two microprocessors onto one piece of silicon, while the latter breaks ompanies providing solutions now down processing jobs into multiple parts. Intel was not the first to ploration into products, technologies and companies. Whether your goal is to research the latest embrace multiple processors as a way to increase performance, pplication Engineer, or jump to a company's technical page, the goal of Get Connected is to put you and their in 2004, other manufacturers have ervice you require for since whatever type announcement of technology, released anies and products you are products searching for.that incorporate multiple processors and multithreading. While Intel’s focus has been ultra-high-performance desktop and server systems, the embedded world has consumed billions of processors for electronic products ranging from cell phones to automotive controllers. These processors also benefit from increased performance, but they are even more sensitive to power consumption than Intel’s big Pentiums. Hence, a lower power approach to increased performance makes even more sense for embedded processors, and this driving force has helped to usher in a variety of multiprocessor architectures for embedded applications. Multiprocessors can be configured in a variety of forms, from loosely coupled computing grids that use the Internet for Get Connected communication, to tightly coupled Symmetric Multiprocessors with companies mentioned in this article. www.rtcmagazine.com/getconnected (SMP). As shown in Figure 1, all processors in an SMP system have access to the same physical memory. Since they all have

End of Article

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on.

October 2006

Local Memory

Core-1

Core-2

Local Memory

Memory

DMA I/O

Figure 1

I/O

In a simplified SMP architecture, multiple, identical processors have access to common memory, and (optionally) also to private local memory that generally can be accessed with lower latency.

identical instruction sets as well, a process or thread can run on any processor from the same memory location. This is key to adapting an application to an SMP architecture.

How Do I Program This Thing?

But while multiprocessors offer exciting opportunities for power-efficient performance increase, achieving the goals of code reuse and fast development times are serious challenges. Traditional programming paradigms are single-processor-oriented, with logic that isn’t easily split among processors. Even when the workload is divided among multiple processors, the

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SoftwareTools&Techniques Processor-1

Processor-2

Shared Memory

Interrupt-1

Input Buffer-1 Thread-1 Input Buffer-2

Interrupt-2

Thread-2

Figure 2

In this example, two processors are allocated by the RTOS to work on separate data sets as they arrive in the system.

need for the programmer to coordinate work among processors can be demanding. Programming tools to assist in the mapping of applications to multiple processors are not generally available. However, there’s a golden opportunity to use software that lies between the application and the multiprocessor to help abstract the hardware for the application—the operating system. In embedded applications, this means the real-time operating system (RTOS) that’s found in most intelligent devices to help manage multiple tasks or threads of operation. The RTOS can help an embedded application in a number of ways. Typically, the RTOS is used to handle interrupts and manage the scheduling of application threads. A thread is a sequence of logically complete code that performs a particular role. Embedded real-time applications generally are made up of multiple threads, each performing its intended function, scheduled according to priorities or in response to external events (interrupts). In a multiprocessor system, in addition to these services, the RTOS can also distribute processing across all processors—this frees the application from deciding what should be programmed to run where. The RTOS also can respond to variations in processing load. This enables all processors to be utilized during periods of maximum demand without requiring explicit assignment by the application. To achieve minimum power consumption, the RTOS can adjust clock frequency or shut down individual processors to conserve power during periods of light demand. By using an RTOS to interface with the underlying SMP architecture, applications are kept hardware-agnostic and this enables a “write once, run anywhere” approach that maximizes code reuse across multiple architectures, whether they are single processor or multiple processor. These RTOS capabilities combine to make the developer’s job easier. And that is key to enabling shorter, less risky development projects with faster time-to-market, while still reaping the benefits of a complex multiprocessor architecture.

SMP RTOS Goals

While SMP architectures have been used in enterprise computing for a long time, and SMP operating systems abound, SMPs 56

October 2006

are relatively new to embedded computing. Currently, Linux supports SMP architectures, and can be adapted to support many embedded applications. But for applications that demand more real-time responsiveness than Linux is able to provide, or that require a smaller memory footprint than that required by Linux, an RTOS would have to be adapted to manage and exploit the facilities of an SMP A typical application domain that could be addressed by an SMP RTOS is that of handling a stream of data where there is a requirement for substantial real-time processing of the data in each packet in the stream. This is the case with streaming audio, video or multimedia data that requires compression/decompression, encryption/de-encryption, rendering, filtering, scaling and other CPU-intensive processing. In a typical system—a cell phone for example—data might be placed via DMA into buffers sized to suit the target display or other system characteristics. Once a buffer is full, an interrupt is generated to alert the application, and that buffer is targeted for processing while data streams into a new buffer. This particular model describes a data flow that is continuous, but varying in intensity. In such a model, real-time response to data arrival is important and overall throughput is the goal, but programming convenience is key. An RTOS that is designed to manage and utilize the resources of an SMP system can be beneficial in such applications. The RTOS must be adapted to run on the SMP architecture. This means that it must be ported to work with the SMP and the underlying processor architecture. Development tools must exist to support the RTOS for that architecture. Next, the RTOS must enable utilization of both processors, enabling both processors to work on data simultaneously, and manage operation of multiple instruction streams on independent processors. Ideally, some automation of processor utilization can be provided to avoid forcing the programmer to manage load balancing or processor switching from within the application. The RTOS can automatically, transparently and dynamically determine when to assign certain processing to certain processor resources. The RTOS also must handle interprocessor communication, allowing the programmer to focus as much as possible on the algorithm rather than the architecture. The RTOS must enable synchronization among the processors, and provide a mechanism for interprocessor communication (IPC). If derived from an existing RTOS, the SMP RTOS should use and retain as much of that existing RTOS as possible, which will help provide easy migration of legacy (single processor) applications to the SMP. A familiar RTOS makes it easier to learn to manage an SMP.

Automatic Load Balancing

One of the most intriguing aspects of delivering a performance increase from an SMP is the ability to do so without requiring programmer intervention. This not only makes it easier for the developer but, more importantly, it also makes it possible to use legacy application code in an SMP system without modification. One method of achieving programming transparency in a multiprocessor system is to assign individual threads to run on

SoftwareTools&Techniques specific processors based on the availability of the processor. This way, the processing load can be shared among processors with work automatically assigned to a free processor. The RTOS must determine whether a processor is free and if it is, then a thread can be run on that processor even though the other processors may already be running other threads. This enables a more complete utilization of resources, yet remains transparent to the number of processors and to the programmer, and enables legacy code to be used intact. In order to utilize such an approach, the developer must set up multiple, identical threads, allocate threads to process portions of the data stream, and set equal priorities. Priorities are important to consider because the RTOS scheduler is designed to maintain priority execution of all threads, such that higher priority threads get executed before lower priority threads. This way, threads can safely assume that while they are executing, no lower priority thread can also be executing. The RTOS must preserve this rule even in the case of an SMP, or the underlying logic upon which a legacy application might be based could falter, and the application may not perform as intended. Priority-based, preemptive scheduling uses multiple cores to run threads that are ready. The scheduler automatically runs threads on available cores. A thread that is “READY” can run on processor-n if and only if it is of the same priority as the Thread(s) running on processor(s)-(n-1). After initialization, the RTOS scheduler determines the highest priority thread that is READY to run. It sets the context for that thread, and runs the thread on processor-1. The scheduler determines if an additional thread of equal priority also is READY. If so, that thread is run on processor-2, and so on. If no additional threads are ready to run, the scheduler goes idle awaiting an external event or service request, such as an interrupt causing preemption, or a thread resume, sleep, relinquish or exit. Preemption occurs when a thread is made READY to run while a lower priority thread is already running. In this event, the lower priority thread is suspended (context saved), the higher priority thread is started (context restored or initialized), and any lower priority threads on other processors are suspended. This is critical to maintain the priority order of executing threads. Within this automatic load-balancing approach to managing the resources of an SMP like ARM’s MPCore, additional features are beneficial to overall performance. One processor can be made responsible for all external interrupt handling (this does not include interprocessor interrupts needed for synchronization or communication). This leaves the other processor(s) with virtually zero overhead from interrupt handling, enabling it (them) to focus all of its (their) cycles on application processing, even during periods of intense interrupt activity that otherwise might degrade performance As an example, consider Figure 2, which shows a two-processor system that is intended to

handle a continuous stream of incoming data, such as streaming video. The data must be decompressed in real time. This is a typical data flow and processing model using an RTOS with automatic load-balancing support for an SMP. Input is set up to fill Buffer 1 in memory, with an interrupt generated upon a buffer-full condition (or based on input of a specified number of bytes). As Buffer 1 reaches a full condition, Interrupt 1 is generated. In response, the ISR handling Interrupt 1 marks Thread 1 READY-TO-RUN, and the scheduler runs Thread 1 on Processor 1. Simultaneously, data is directed to Buffer 2, and processor 2 remains idle for the moment. Then, as more data arrives while Thread 1 is active, Buffer 2 fills up, generating Interrupt 2. The ISR handling Interrupt 2 marks Thread 2 READY-TO-RUN, and the scheduler runs Thread 2 on Processor 2, while Thread 1 continues to run on Processor 1. An RTOS that can manage an SMP system can provide increased performance compared to a single processor system, while minimizing demand on the development of applications. This delivers the benefit of greater performance with little effort, making SMP architectures very attractive for embedded applications requiring high performance, but with stringent demands on fast time-to-market. Express Logic San Diego, CA. (858) 613-6640. [www.rtos.com].

October 2006

SoftwareTools&Techniques

“Not Your Father’s CORBA”— A n Architecture for Embedded and Real-Time Ad Index Systems Get Connected with technology and companies providing solutions now Get Connected is is a new for further exploration The new CORBA/e theresource high-performance architecture of into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly choice for distributed real-time and embedded environments. with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for.

by Victor Giddings, Senior Scientist www.rtcmagazine.com/getconnected Objective Interface Systems

problems www.rtcmagazine.com/getconnected for a $1.2 billion nuclear fusion facility. They required a high-performance systems architecture to enable maximum code reuse, accelerated performance and real-time application integration. The NIF’s Integrated Computer Control System (ICCS) had to manage more than 40,000 control points to operate 192 of the world’s most powerful laser beamlines. These lasers deliver 2 MegaJoule pulses of optical energy onto a BB-sized deuterium fusion fuel capsule in a pulse 25 nanoseconds long, which results in an energy-producing inertial confinement fusion reaction similar to the ignition of a small sun. For this demanding engineering task, NIF depends the Common Object Request Broker Get Connected with on companies and products featured in this section. Architecture (CORBA). www.rtcmagazine.com/getconnected Yes, that’s right. CORBA. This might surprise those who remember CORBA from its earlier incarnations in the enterprise software industry when it was typically characterized as “big, fat and slow.” The development of real-time and embedded CORBA offers major improvements over earlier implementations of CORBA. Connectedmeets with companies and products in this section. ItsGet performance or exceeds users’featured most stringent require-

Products

www.rtcmagazine.com/getconnected

October 2006

Sockets (TCP)

Average Round-Trip (microseconds)

Get Connected with technology and companies providing solutions now Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research the latest cientists atdatasheet Lawrence Livermore National Laboratory’s from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you Performance Comparison of National Ignition Facility (NIF) Whichever needed to oneyouofrequire for whatever type of technology, in touch with the right resource. levelsolve of service CORBA/e vs. Enterprise CORBA the world’s most challenging system control Get Connected will help youdistributed connect with the companies and products you are searching for. ORBexpress C++ (TCP)

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End of Article 2,000 1,000

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Get Connected with companies mentioned in this article. www.rtcmagazine.com/getconnected

SoftwareTools&Techniques ments and allows programmers to develop source code that is reusable across multiple platforms, applications and projects— which maximizes an investment in CORBA across generations of applications. Today CORBA has become the middleware of choice for the world’s most demanding applications and harshest environments in defense, aerospace, communications, banking/finance, industrial controls, robotics, medical equipment and multiple other industries.

The New CORBA CORBA/e Micro CORBA/e Compact Full CORBA

What is CORBA/e?

For systems that need small memory footprint and deterministic execution, embedded developers can use the latest generation of CORBA: CORBA/e (CORBA for embedded). An Object Management Group (OMG) standard, CORBA/e provides an architecture for distributed processing that fits systems from the largest server farms to the smallest networked Digital Signal Processors (DSPs). The OMG has merged the static aspects of industry standard CORBA with the essential Real-Time CORBA features into two new profiles grouped under the banner of CORBA/e. The CORBA/e Compact Profile fits easily on a typical 32-bit microprocessor, running a standard Real-Time Operating System (RTOS); these systems may run such applications as communications, signal or image processing with real-time dependability. The CORBA/e Micro Profile is even smaller and fits on the kind of low-powered microprocessor or high-end DSP found on mobile or handheld equipment.

Why CORBA/e?

Embedded system software development is an expensive and time-consuming task. But with a sound middleware architecture, this investment can pay dividends across many generations of technology. For developers of real-time and embedded systems, CORBA/e is ideally suited to the challenges of today’s missioncritical environments. In today’s world, stand-alone systems are becoming a thing of the past. Embedded processor environments are networked and highly interconnected. Software must cope with communications and interoperability issues, while delivering the same reliability and performance as the isolated embedded systems of the past. Even systems that appear to be stand-alone need a communications infrastructure to merely report their status. CORBA/e provides easy access to a variety of sophisticated transports including Shared Memory, RapidIO and FireWire, as well as Ethernet. Embedded software development is no longer confined to a specific processor model on a particular board—if it ever was. A developer may need to support many different processors at the same time, or migrate to new environments as the initially targeted compilers, operating systems and processors change. There is increased pressure to preserve investment through development of “reusable product lines.” Developers writing their own infrastructure are more susceptible to increased cost due to code changes accommodating inevitable environment changes. CORBA/e insulates embedded developers from the headaches of rewriting code with every processor and system change. In addition, embedded systems will increasingly use multicore processors, and developers will need to migrate their applications from single core processors to processors containing two or more

Figure 2

The CORBA profiles for a continuum of size, interoperability and compatibility.

CORBA/e Real-Time Predictability Real-time systems are concerned with both the timeliness and the correctness of responses. Features are needed to propagate priorities across the network and deal with networked resources consistently. Network priorities must be managed in real time, respecting scheduling and deadlines. Predictability is critical to ensure the system will meet the most stringent demands and meet deadlines. The primary goal of real-time CORBA is end-to-end predictability. Real-time systems achieve this through prioritybased scheduling. Because the remote system doesn’t know about the originating priority, the system is indeterminate. Real-time Object Request Brokers (ORBs) solve this problem by propagating the priority to the server. The result is distributed priority inheritance and the ability to correct schedule-distributed processes. The heterogeneous nature of CORBA is important in priority propagation. Most Real-Time Operating Systems (RTOSs) have different ranges of priorities. For example, in one RTOS, the priority range is 0 to 255, where 255 is the highest precedence. Another RTOS may have a range from 0 to 127. In some cases, 0 may be the highest. If different operating systems are on different network nodes in an application, your code has to know which operating system you’re using. The Real-time CORBA standard, upon which CORBA/e is based, defines a universal priority range — just one more way CORBA provides a portable and transparent approach to building distributed systems. Priority propagation ensures that the RTOS can schedule correctly end-to-end. However, the network can still be a source of priority inversions. A high-priority message may have to await the completion of a large low-priority message. That represents a message-based priority inversion. To avoid this bottleneck, Real-Time CORBA supports Priority-Banded Connections. The ORB sends messages over user-specified bands based on the priorities and QoS involved. Developers can trade off network and OS resource usage against priority inversions. October 2006

SoftwareTools&Techniques cores. CORBA/e enables a seamless migration to multiple cores through the benefits of location transparency. With this kind of increase in complexity, applications gain flexibility through refactoring. Developers can build a CORBA/e application as if it were a stand-alone application. They can then spread and re-spread the application logic across multiple resources in a way that doesn’t create any extra work. Deferring deployment decisions enables optimized resource allocation and the flexibility to adjust to changing conditions. In the embedded world, as we all know, systems and devices interact with the real world in real time (see sidebar “CORBA/e Real-Time Predictability”). Devices require interactions that are predictable in time as well as in function. CORBA/e provides distributed predictability by recognizing and propagating priority in its own processing and across the system. The real world also has constraints on power, weight, size and speed. CORBA/e is specifically designed to support board-based and networked systems with the smallest footprint and the highest performance requirements. CORBA/e focuses on providing just the most useful features of previous versions of CORBA, paring away those that bloat footprint and processing requirements. With the increased use of embedded devices in applications that are mission-critical and/or involve the possibility of injury or death, reliability must be built in. Real-time and embedded developers are rightly skeptical about adopting code they don’t write themselves. Robust implementations of CORBA/e, field-tested in the harshest environments, have proven their reliability time and time again. Porta-

bility among implementations ensures the longevity of the solution. And, of course, there are always economic pressures requiring greater productivity from systems development, so time-to-market is critical. By supplying a high-performance communications framework, CORBA/e enables greater productivity because it is no longer necessary for developers to write their own protocols. CORBA/e solves the tedious and time-consuming part of distributed applications by establishing a reliable, flexible architecture. To the embedded system architect, CORBA/e levels the interoperability playing field, allowing board-based systems and micro systems to interoperate not only with each other, but also with existing systems using the CORBA standard. At the same time, it allows developers to use their existing CORBA skills to code at full speed from the start and allows projects to hire from a large pool of skilled CORBA developers. CORBA/e systems are fully interoperable and support the OMG’s mature interoperability standards: GIOP (General InterORB Protocol) and IIOP (Internet Inter-ORB Protocol). In addition, some CORBA/e implementations also offer additional transports tuned to embedded targets and allow embedded developers to plug in their own custom transports. This flexibility allows embedded devices to interoperate with systems ranging from the largest server array installations to small chip-based sensors.

CORBA/e Profiles

The CORBA/e profiles—Compact and Micro—package the static features of CORBA middleware and real-time capabili-

Technical Features of CORBA/e CORBA/e Compact Profile: • Compact yet powerful: Fits resource-constrained systems (32-bit processor running an RTOS), but supports sophisticated applications such as signal or image processing in real-time. • Interoperable: › Compiles all OMG IDL (although dynamic aspects of CORBA—IFR, DII, DSI, recursive Valuetypes, dynamic Any—do not execute). › Integrates with applications running full CORBA, CORBA/i, CORBA/e Compact Profile and CORBA/e Micro Profile. › Supports native IIOP (all versions through the current GIOP 1.4 and IIOP 1.4). • Deterministic: › Supports Real-Time CORBA with static scheduling. › Propagates Real-Time CORBA priorities over the wire. › Disallows dynamic aspects of CORBA—IFR, DII, DSI, dynamic Any, recursive Valuetypes. • Server-side: POA supporting transient or persistent objects; retained servants (disallows implicit activation); prioritized multithreading under ORB control. • Does not support CORBA components. • Complete: includes Naming, Events and Lightweight Logging Services.

October 2006

CORBA/e Micro Profile: • Truly Micro: Fits on a mobile or similar device with a lowpower microprocessor, or high-end DSP. • Interoperable: › Compiles all OMG IDL (Dynamic aspects of CORBA— IFR, DII, DSI, Any, Valuetypes, transient servants—do not execute). › Integrates with applications running full CORBA, CORBA/i, CORBA/e Compact Profile and CORBA/e Micro Profile. › Supports native IIOP (all versions through the current GIOP 1.4 and IIOP 1.4). • Deterministic: › Supports only statically defined Interfaces, Interactions and Scheduling. › Supports Real-Time CORBA Mutex interfaces. • Server-side: For compactness and deterministic behavior, supports exactly one POA; allows only transient, retained servants with unique, system-assigned IDs and multi-threading under ORB control.

SoftwareTools&Techniques

What Do NASA’s Deep Impact ties into a small footprint. Figure 2 shows the relationship beMission and 80 Million Cellular tween the CORBA/e profiles and standard CORBA. Designed by the most experienced providers of Distributed, Real-time Phones Have in Common? and Embedded (DRE) software, both profiles fulfill the range EASILY adding a failsafe of industry requirements. Flash Memory File System! The CORBA/e Compact Profile merges the key features of standard CORBA 2.6 and Real-Time CORBA into a powerful Get a copy of Tim Stoutamore’s yet compact middleware package that interoperates with other 2006 Flash Memory Summit Presentation CORBA clients and servers of every scale, executes with the de“Flash File Systems” terministic characteristics required of a true real-time platform, “Making NAND and NOR Flash Memory Easy” and leverages the knowledge and skills of software development From Jay Kramer teams through industry standard architecture. Shedding the dyHost/Moderator − 2006 Flash Memory Summit: namic aspects of CORBA and support for the CORBA Compo“Tim Stoutamore’s Flash Memory Summit nent Model (with their unpredictable response times and unlimpresentation was excellent. Companies like ited potential memory usage), CORBA/e Compact Profile retains Blunk Microsystems have delivered major interoperability by retaining the full IIOP protocol. It also pretechnical innovations that enable serves many server-side implementation options through the Porflash memory solutions in today’s marketplace.” table Object Adapter (POA) policies, and a rich type model that TO GET YOUR COPY includes a lightweight version of “Valuetypes” and Type Any. www.BlunkMicro.com/Flash-Presentation For even more compact systems, the CORBA/e Micro Profile or email request to info@BlunkMicro.com shrinks the footprint even more, small enough to fit low-powered or call (408) 323-1758 microprocessors or DSPs. This profile further trims features and constrains options that increase footprint, such as the Valuetype, the Type Any, most of the POA options, and all of the real-time functions except the real-time Mutex interface. In exchange for these limitations, the profile defines a CORBA executable that vendors have fit into only tens of kilobytes of memory—small enough to fit onto a high-end DSP or microprocessor on a handheld device. Even at this small size, the CORBA/e Micro Profile blunkv1.indd 1 10/10/06 9:52:26 AM retains full IIOP interoperability (Figure 2). CORBA/e middleware is available now. Based on vendor experience with military, industrial and consumer DRE appliMass Storage Modules cations, CORBA/e blends the standard and real-time specificafor VMEbus and CompactPCI® tions that the industry needs (see sidebar “Technical Features of CORBA/e”). CORBA, as a standard, has continued to evolve over the last decade, and is adopted by many industries as the preferred middleware solution as evidenced by the large industry involvement within the OMG. Some of the most exciting standards development has come from the Real-Time Embedded and Specialized Systems (RTESS) Task Force in the form of CORBA enhancements designed for the real-time and embedded developer. A team of diverse companies, including representatives from telecommunications, aerospace and CORBA vendors, jointly authored the CORBA/e specification. Objective Interface was a key contributor in this initiative, taking a leading role in driving the specification to completion. CORBA/e offers an architectural solution to keep up with Ultra SCSI Flash Drive ever-changing technology—in processors, models and particuUp to 128GB in VMEbus Form Factor larly communications bus types. CORBA/e lets developers pro-40C to +85C Operating tect their investment in development work despite rapidly accelSee the full line of VMEbus single and erating change. multi-slot mass storage module products at Objective Interface Systems Herndon, VA. (703) 295-6500. [www.ois.com].

www.RedRockTech.com

or call Toll-Free: 800-808-7837 Red Rock Technologies, Inc. 480-483-3777

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SoftwareTools&Techniques

Enterprise-Strength Solutions Meet the Demands of Today’s Embedded Systems An open, integrated software development environment offers embedded developers a framework to use their choice of tools that can communicate and provide a common user interface experience.

er exploration ther your goal speak directly cal page, the ht resource. echnology, s and products

by R obert Day LynuxWorks

s the expanding demands of the embedded device market are being enabled by cheaper memory and faster processors, the software in today’s embedded systems is exploding. This dynamic of code explosion, larger project teams and integration of many embedded software applications, from proprietary code to purchased or open source software IP, is a much mpanies providing solutions now than we faced 10 years ago. And now we are bigger challenge loration into products, technologies and companies. Whetheremulators your goal is toto research latest them. without the benefit of in-circuit help the debug pplication Engineer, or jump to a company's technical page, the goal of Get Connected to puttake you But there is an answer. Embedded software engineersiscan rvice you require for whatever type of technology, advantage of today’s enterprise design and development tools as anies and products you are searching for. they come together with embedded debugging tools to provide a complex yet robust embedded development environment. Until recently, embedded tools were typically provided by either embedded tools vendors or RTOS vendors. In today’s embedded world, they are either provided by chip companies, RTOS companies or come from the open source community. The chip companies provide tools that can help boost the performance of and offer early support for their latest architectures. The RTOS companies provide tools that allow users to easily build applications for a given RTOS and offer awareness of that RTOS when debugging. And the open source community offers compilers, debuggers and now integrated development environments (IDEs) Get Connected for embedded debugging. The latter category is having a very with companies mentioned in this article. interesting effect on the embedded development landscape as it www.rtcmagazine.com/getconnected offers a common platform that embedded developers can use regardless of RTOS, debugger, compiler or processor.

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October 2006

This common platform is called Eclipse. Over the past couple years, Eclipse has gradually become the de facto standard IDE and framework for embedded systems development. There are a number of reasons for this, and looking back at the history of IDEs in the world of embedded is a good start toward understanding them. The first real IDEs for embedded software emerged in the early 90s. Then, through the following 10 years, most RTOS, tools and a number of processor companies brought out IDE products. Many of the IDEs were proprietary, which caused issues for the embedded vendors, as they were forced to develop large software suites that were really not specific to embedded. This also posed an issue for embedded developers, as they were forced to learn a new IDE interface every time a new RTOS or processor was selected. Some embedded vendors decided to take an IDE licensing approach. In this approach, Microsoft’s Visual Studio was viewed as a good starting point due to the large user base and also the large number of developers that Microsoft has to maintain it. Unfortunately, it left the embedded vendors at the mercy of Microsoft’s release schedule and feature set—and forced them to do a lot of work to make Visual Studio appropriate for embedded. The other obvious issue was the fact that Visual Studio is only Windows-based and therefore would not offer easy support for Solaris or Linux hosted development. Enter Eclipse. Eclipse is an enterprise-strength, open source framework that allows tools vendors to re-use the open source parts, as well as seamlessly plug in their own software tools. Its Eclipse Public License (EPL) allows embedded vendors to pro-

SoftwareTools&Techniques

duce commercial products based on the open source software. Eclipse also supports multiple host platforms and, since it is written in Java, offers portability to easily migrate to other hosts. Although the Eclipse platform was born from the enterprise world, and is still driven by the needs of enterprise developers, the expansion of Eclipse is governed by a number of projects. Several of these projects are either aimed at embedded development, or have enough synergy with what embedded developers require that they become a very good starting point for building an embedded development environment (Figure 1). One project, the C/C++ development tools project (CDT), brings compilation tools, a graphical build environment, an editor and a debugger to the embedded vendors. RTOS companies, for example, find this a very good place to build an RTOS-specific build system and RTOS-aware debug solution. Another project, the Device Software Development Project (DSDP), is focusing on standardization in embedded areas such as host/target management and debugging. DSDP will be working closely to integrate with the CDT project. So, Eclipse has been shown to be a great starting point for embedded vendors. What about embedded software developers? Eclipse offers many benefits that have never been realized before in the embedded world. First, the Eclipse platform is a common part of all Eclipsebased solutions and offers a common user interface. Although

Eclipse is very flexible with regard to plug-in applications and tools, it enforces these plug-ins to adhere to a set of rules and APIs. For the embedded developer, it means that whatever RTOS or processor is being used, the overall IDE and the way tools interact with it is very consistent and allows easier migration across projects. Second, being born from enterprise offers some huge benefits: the user base and hence quality of code is far greater than traditional embedded IDEs; the interface is more modern; and embedded projects can take advantage of a wide range of plugins from the enterprise world. For example, source code management and version control systems are not specific to embedded, so embedded engineers can really take advantage of products such as ClearCase, CVS and Subversion, all integrated within Eclipse. Third, Eclipse allows different embedded products to â&#x20AC;&#x153;playâ&#x20AC;? together under one IDE and with a common look and feel. So, compilers from one company, debuggers from another and test and validation tools from yet another can all work seamlessly together. Eclipse also offers an opportunity for these separate companies or products to actually interact with each other, as the plug-in mechanism has integration and expansion points to allow close interaction between plug-ins. Finally, the open environment of Eclipse allows embedded developers to actually write their own plug-ins. This offers the

October 2006

SoftwareTools&Techniques

Eclipse Platform

Another Tool

Workbench Help Java Development Tools (JDT)

JFace

SWT

Team Your Tool

Plug-In Development Environment (PDE)

Workspace

Debug

Platform Runtime

Their Tool

Eclipse Project

Figure 1

The plug-in architecture of the Eclipse framework offers great flexibility.

ability to build company- or application-specific tools and have them interact with the IDE from the embedded vendor(s) of their choice. Eclipse also allows embedded software developers to take advantage of software design tools, advanced code management and build systems, and swap out different tools and components without changing environment. This becomes more and more important with the larger and more complex systems—and as more software IP is either purchased or obtained from the open source community. High-level design languages have been around in the embedded software industry for many years, but only recently have they become more usable, more standard and more needed. As code size explodes, coding in traditional programming languages such as C and C++ becomes too inefficient for the number of debugged lines of code that can be written in a day. These languages also cannot show multiprocess and multiprocessor solutions very adequately. Moving up a level of abstraction to a high-level design tool allows system engineers to describe a system and the interactions in a system in a standard design language—the Unified Modeling Language (UML). Most UML tools have an Eclipse interface that lets them fit into the standard embedded IDE and also generate C or C++ code (usually linked in with the RTOS of choice) that can then go into the traditional build and debug system of the embedded user. This offers a huge productivity gain, as one line of UML can equate to tens of lines of embedded C or 64

October 2006

C++. Hence, the number of lines of code that can be generated in a day goes up dramatically. By offering a standard interface to the embedded build system, Eclipse also abstracts away the interface to compilation tools. This means that bringing a new or different compiler into the build process is relatively easy as Eclipse offers the interface to it. This allows embedded software developers to either change compilers to increase performance of the code generated or easily migrate to a different processor architecture. The compiler has always been the last tool an embedded engineer is willing to change, as it is often very closely tied to the processor. But now, with C++ and UML being more widely used, the interaction between the embedded software engineer and his compiler is growing more distant. Embedded debuggers have always had their own look and feel, and moving between them has always been a challenge— even if they were being used on the same project as each other. With Eclipse, the functionality of different debuggers now has a more uniform feel, and they all plug in to the standard IDE. In Eclipse, moving between different tools often means a change of “perspective” (an Eclipse term). This generally changes all the windows in the Eclipse IDE to match whatever tool is being used and is achieved via a single button click. This means that the embedded developer can have a whole arsenal of tools (including multiple debuggers) that have their own perspective.

SoftwareTools&Techniques For complex embedded systems, this means that very specific tools (such as JTAG emulation, simulation and other complex debugging products) can be available—but without having the cost of one per user. If the tools are closely integrated with one another, then they may well share a perspective, with each one having different views or windows within it. They can also share communication channels, thus providing an even greater integration between debug products. Another increasing requirement of modern debuggers is the ability to debug multiple processors. This has traditionally been very difficult for most debuggers because they have often needed to spawn clone copies of themselves for each processor being debugged. This soon eats up screen real estate and doesn’t allow easy communication between debug sessions. The flexibility of the Eclipse framework allows multicore-aware debuggers to enhance their user interface with a single perspective and then communicate within the views (windows) with each other. This can make for a simple yet powerful debugging interface for large, complex systems. The embedded software explosion is requiring that the tools and methodologies for building and debugging systems are closer to those found in the enterprise space. For the embedded world, the Eclipse platform offers a consistent, enterprise-strength IDE that can bring tools together that are open source, enterprise and embedded-specific in order to help embedded software engineers meet both their projects requirements and deadlines. LynuxWorks embraces open standards and provides Real Time Operating Systems based on POSIX and Linux standards and a com-

Figure 2

An embedded debug perspective within the Eclipse framework.

prehensive embedded tool suite based on the Eclipse framework. For more information please visit www.lynuxworks.com. LynuxWorks San Jose, CA. (408) 979-3900. [www.lynuxworks.com].

See

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SoftwareTools&Techniques

Implementing High-Availability Middleware on ATCA— Step-by-Step Mixing and matching ATCA, carrier-grade Linux and Service Availability Forum-compatible middleware to create a ready-to-go platform can be done, but learn from the experience of others and heed these practical steps. by J im Ewel GoAhead Software

October 2006

Applications AIS APIs Systems Management Interfaces (SNMP, CLI)

ne of the promises of standards like ATCA, Carrier-Grade Linux (CGL) and the Service Availability Forum’s Hardware Platform Interface is that you can mix and match implementations that adhere to the standards, and everything will work seamlessly. The reality is much more complex. While the standards unquestionably make it easier to mix and match, each platform requires work to produce a highly integrated solution. This article will describe the practical realities of integration using the example of integrating GoAhead SelfReliant with RadiSys Promentum ATCA chassis and boards. While some of the detail is specific to GoAhead and RadiSys products, most of the lessons and the overall approach are applicable across implementations of SA Forum-compatible middleware and ATCA hardware. The SA Forum has published two important specifications, the Hardware Platform Interface (HPI) and the Application Interface Specification (AIS). HPI provides a single interface for applications and middleware to access and manage hardware components in a heterogeneous environment (Figure 1). Its goal is to promote portability of applications, operating systems and middleware across hardware platforms. The latest version of the specification is HPI B.01.01 and was released in 2004. In addition to the interface itself, there is an HPI to ATCA mapping specification, which outlines how HPI maps to common ATCA sensors and controls, as well as an HPI simple network management protocol (SNMP) management information base (MIB). The HPI implementation is generally provided by the hardware manufacturer in three pieces: a header file, a linkable client library and a software daemon tailored to the specific hardware platform. There is also an open source HPI implementation available on www.sourceforge.net, which can provide a good starting point for a more complete implementation. AIS provides a consistent interface between applications and high-availability (HA) middleware, abstracting one from

Systems Management Services (Messaging, Replication) SA Forum-Compatible HA Middleware Platform/Resource Management HPI & OS Interfaces O/S (Linux, Solaris, etc.) Hardware (ATCA and others)

Figure 1

A carrier-grade, application-ready platform architecture.

the other and promoting application reuse while allowing for underlying middleware changes. AIS consists of the Availability Management Framework (AMF), which coordinates the use of redundant resources to avoid loss of service, and a set of services (cluster membership, checkpoint, event, message, lock, information model management, notification and log) that provide necessary functionality for both applications and the AMF itself. The latest version of this specification, AIS B.02.01, was published as a part of the Consolidated Release launched in January of this year. For more information visit www.saforum.org.

Overview of Steps

A rough outline of the steps necessary to implement a carrier-grade, application-ready platform is as follows: • Obtain a working HPI implementation • Test your HA middleware against the HPI implementation • Create reference hardware configurations

SoftwareTools&Techniques Run defined extraction grant policy Policy Result Run custom extraction grant policy (if any) Policy Result Grant extraction request?

Yes

Perform extraction request rejection actions

Drive resource hot swap state to ACTIVE

Perform resource-level extraction actions (phase 1)

Perform defined system-level extraction action

Perform custom system-level extraction action (if any)

Perform resource-level extraction actions (phase 2)

Drive resource hot swap state to INACTIVE

Figure 2

Legend: Selectable pre-defined HSMS policy / action Custom hot swap policy / action

Hot swap policies; extracting a hardware resource.

• Integrate with specific hardware controls and sensors • Implement hot swap for field-replaceable units (FRUs) • Implement appropriate alarms and policies • Enable external systems management • Deliver the platform to a happy user These steps may vary slightly from implementation to implementation, but will generally follow this outline. Here’s a description of each step, along with some comments from our experience implementing these steps on several platforms.

Getting Started

The first question to ask is does your hardware manufacturer provide an HPI implementation for your target platform? Today, some manufacturers (RadiSys, Motorola and others) provide their own HPI libraries. Other manufacturers do not yet provide HPI libraries, in which case you’ll need to begin with OpenHPI or use the middleware vendor’s proprietary hardware interface. Obviously, using OpenHPI should be the preferred approach, both because it is vendor-independent, and because it is reasonably fully functional and should take less time to implement. In our experience, getting OpenHPI to work correctly on a given hardware configuration can present some challenges. HPI makes extensive use of Intel’s Intelligent Platform Management Interface (IPMI). The IPMI implementation must be robust enough and perform well enough to handle the increased traffic flows of IPMI calls generated by HPI. We have also seen some HPI implementations, including OpenHPI, lose HPI messages 68

October 2006

during failover. Some vendors, including RadiSys, have implemented data synchronization between multiple instances of HPI running on redundant shelf managers. Data synchronization checkpoints the latest HPI messages and ensures that no messages are lost during failover. Once you have a working HPI library, either provided by the hardware vendor or by installing and possibly modifying OpenHPI, the next step is to test your HA middleware against this HPI library. In the case of GoAhead SelfReliant HA middleware, this meant performing a “smoke test” of SelfReliant Platform Resource Management Service (PRMS). PRMS provides management and monitoring of hardware resources, including alarm management and hot swap management. PRMS functions by making calls to HPI and handling HPI events and alarms. (While PRMS is specific to GoAhead’s implementation, every implementation of HA middleware will have some equivalent.) An automated testing facility should then be run to perform resource discovery, manipulate sensors, controls and inventory records, set thresholds, generate user alarms based on custom policies and test the hot swap functionality, including custom hot swap policies. This generates light load on the system, although at this point in the process we are not performing load or performance testing. When these automated tests have confirmed that the basic capabilities are functioning correctly, you can move on to creating reference configurations and integrating with the specific sensors and controls that are part of your hardware configurations.

Creating Reference Configurations

When creating a highly integrated, application-ready platform, it is generally advisable to create a configuration file for each of the anticipated reference configurations. In our experience, most users have multiple configurations, whether for capacity reasons or functionality. For example, an equipment manufacturer may have several different models, each one using the same basic platform and chassis, but with varying number or type of boards in each configuration. Configuration information, also known as the system model, is held in GoAhead’s in-memory database. It supports managed objects, object classes, hierarchies and dependencies, service groups, service units, and a whole host of other functionality provided by the Availability Management Framework (AMF). Provisioning of this system model may occur in one of two ways, known as static provisioning and dynamic managed objects. Both methods may be used in a single system. Static provisioning establishes a preferred configuration, which is persisted to local storage and distributed to every manager-capable node in the cluster. In the case of a cluster-wide failure, this allows any node to restore the system to this preferred configuration. On start-up, PRMS calls HPI to enumerate all of the objects in the node. These objects are then compared to the reference configuration. If there are differences, perhaps due to faulty or missing modules, an alarm can be raised. Dynamic managed objects are not pre-provisioned, but are discovered on the fly. Managed objects are dynamically created and bound to a particular resource (a newly inserted board, for example). Dynamic managed objects provide more flexibility but do not help identify exceptions to the system’s expected configuration.

SoftwareTools&Techniques For our integration with the RadiSys Promentum line, we chose several different configurations (based on customer feedback) and shipped configuration files for those combinations. The configuration files are in XML format, so they can be easily modified by the user.

Integration with Hardware Controls and Sensors

As mentioned earlier, the SA Forum has provided an HPIto-ATCA mapping specification that outlines how HPI maps to common ATCA sensors and controls—for example, temperature sensors or power state controls. Ideally, the middleware provider provides support for HPI-to-ATCA mapping. This will cover 8090% of the sensors and controls for any given manufacturer’s ATCA implementation and will save you a lot of work. For each specific platform, there are always OEM-specific controls and sensors. GoAhead addresses this by providing a Platform Specific Library (PSL) for each platform, as well as a generic PSL that may be modified for new platforms. This PSL provides functionality in three areas: hot swap management, alarm management and access of OEM-specific controls and sensors. OEM management instruments are self-described by HPI’s OEM entity capability. For example, RadiSys supports a shelf display panel with an LCD panel, LEDs and an audible alarm. RadiSys provides an OEM-specific entity, referred to as SDP (shelf display panel), as part of their HPI implementation. Each OEM-specific entity must be mapped to the system model, supported, and provided with default policies in the event of a failure. If the manufacturers have not provided this, you will need to do this on your own.

Hot Swap Management

The extraction or insertion of a board on a running system requires that the high-availability middleware manage the process. This includes determining if the extraction will be allowed, initiating switchover of processes onto a standby resource and shutting down the resource gracefully. For example during extraction, a sequence of events and decisions takes place within the middleware and HPI while the hardware resource is in the extraction pending state (Figure 2). The HA middleware should allow the developer to easily define and customize policies and actions for each step of this sequence. When integrating hot swap with a specific platform, a number of actions must be supported. For example, if an extraction is rejected, an appropriate message must be displayed on the hardware status display. In SelfReliant, if the extraction is granted our Hot Swap Management Service (HSMS) performs a shutdown operation on the object to allow any programs that are dependant on that hardware resource to switchover gracefully to the associated standby resource. After all programs are successfully switched over, the power to the resource is shut down, and the hot swap LED for the resource is constantly illuminated. Our implementation of hot swap through HPI found minor differences between platforms. For example, for one vendor we had to set only the hot swap indicator during the extraction process, while for another vendor we had to set the hot swap indicator as well as switch the power off. These actions are pre-programmed into the PSL for each resource in a supported platform. An automatic test suite for hot swap management is also available.

Alarm Management

Every system must be monitored for conditions that might jeopardize the health of the system. Alarms, which signal the occurrence of potential problems, can be classified as to severity, and policies can be applied to determine appropriate actions. For example, an alarm management service (ALMS) should provide a number of functions to make it easier to manage alarms: • Maintain an active alarm list for the system • Allow a user to create and/or delete application-specific alarms • Detect, generate and annunciate alarms for hardware resources undergoing a state transition to a state of failed or no resource • Provide configurable severity levels—critical, major and minor—to adjust how the system reacts to an alarm condition ALMS should also provide the ability to filter alarms by severity level, resource ID and/or sensor ID to get to root causes. Again, each platform is slightly different in terms of the annunciation and processing of alarms. In particular, OEM values must be converted to generic values that more accurately represent the current state of the resource. For example, the generic string “0x0008” that is returned by an OEM sensor and could be displayed would be more accurately represented as “Processor disabled.” The console also provides platform-independent write access to OEM-specific management instruments.

External Management Interfaces

HA middleware often acts autonomously to recover from failures and respond to alarms. However, you’ll want to let the operator know there was a failure, and sometimes it is necessary for an operator to intervene. External systems management is a two-way street, passing information about the equipment to an element manager or operations console, and conveying queries or commands to the equipment from an operator. The most common systems management interfaces today are the command line interface (CLI) and SNMP, with the Distributed Management Task Force’s Common Information Model (CIM) on the horizon. In order to enable access from an SNMP browser, a MIB specific to each configuration must be created. GoAhead provides three MIB modules out of the box. One provides access to the system model, a second provides access to HPI information, including the ability to initiate and monitor hot swap sequences, and the last provides access to any in-memory SelfReliant management database. SelfReliant also provides SNMP trap notifications on object state change and service group’s state change. SelfReliant also allows the creation of a custom MIB module for access to other manageable resources, and provides a tool, called MIBparse, to generate a management database from a native syntax MIB file. Once you’ve created a comprehensive MIB for your platform, you are then ready to move on to the final step, handing over the fully functional platform to a happy user. GoAhead Software Bellevue, WA. (425) 453-1900. [www.goahead.com]. October 2006

SoftwareTools&Techniques

Open Architecture Network Software Platforms Speed Complex Development Ad Index A new generation of middleware and system management software is Get Connected with technology and coming online to providing help network companies solutions now equipment providers get their increasingly complex platforms they can concentrate on adding unique value. Get Connected running is a new resourceso for further exploration

into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Pearson Connected will help you connect with the companies and products T erry you are searching for.

Enea www.rtcmagazine.com/getconnected

www.rtcmagazine.com/getconnected

October 2006

Eclipse Tools

End of Article

Third-Party Tools

Products

Element Platform Management

Get Connected with technology and companies providing solutions now he amount of software needed for today’s converged netGet Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research the latest Customer works and smart devices is increasing at an alarming rate, datasheet from a company, speak directly with an Application Engineer, or jump to a company's technicalApplications page, the goal of Get Connected is to put you with the latest setwithtop (STBs), mobile andrequire for whatever type of technology, in touch the boxes right resource. Whichever levelphones, of service you other telecommunications devices of linesandofproducts you are searching for. Get Connected will helprequiring you connectmillions with the companies Third-Party code. Software demand, in fact, is quickly outpacing the number www.rtcmagazine.com/getconnected Applications & Stacks of programmers available to do the work, making it increasingly Polyhedra difficult for equipment makers to introduce new products and Element HA Framework & In-Memory Embedded Management features in a timely fashion. According to one industry analyst, DB the amount of code deployed in today’s high-tech equipment is Element Core (Log, Debug) growing exponentially, while the number of available developers, LINX Transparent Communication presently about 600,000 worldwide, is growing at a relatively flat pace. CG Linux OSE RTOS OSEck (DSP) To cope with this impending crisis, equipment makers are Hardware Platforms - ATCA, Reference boards, etc. beginning to rethink their development process. The days of creating custom operating systems, middleware, protocols, database technology and otherwithplatform from scratch in-house Get Connected companies software and Figure 1GetTelecom software platforms provide the core Connected featuredthat in thissoftware section. from one project to the next are and products reinventing withservices companiesneeded mentionedtoin integrate this article. standard hardware www.rtcmagazine.com/getconnected over.www.rtcmagazine.com/getconnected Increasingly, designers are utilizing more productive applatforms, third-party tools and the equipment maker’s proprietary application software. proaches that embrace reusable code, open standards and preintegrated off-the-shelf technology. Pre-integrated telecom platforms transform the lengthy platGet Connected with companies mentioned in this article. form design/integration process into an evaluation and purchaswww.rtcmagazine.com/getconnected Get Connected with companies and products featured in this section. ing process that can take as little as two months. All told, this

SoftwareTools&Techniques

COTS approach can shorten the application development cycle by up to 50%. It also enables equipment makers to trim their platform teams by up to 80%, thereby reducing manpower cost and enabling network equipment providers (NEPs) to reallocate precious engineering resources to value-added application and service development. Open architecture platforms further enhance productivity by providing a layer of abstraction that enables a clear separation between telecom applications and the underlying hardware and system software. This layer of abstraction, coupled with the use of standard interfaces, enables designers to use best-of-breed COTS hardware and software from multiple vendors. It also enhances portability, allowing NEPs to upgrade hardware and software at later dates with minimal disruption to their proprietary applications.

Telecom Software Platform Basics

Open architecture telecom platforms provide the basic components needed to develop and host telecom applications and services. These components typically include an operating system, interprocess communications (IPC), a high-availability (HA) middleware framework, and a database management system (Figure 1). The operating system (OS) provides essential multitasking, program loading, memory management, I/O, storage and network

access services. Ideally, the telecom platform should support multiple operating systems in both homogeneous (e.g., Linux or an RTOS deployed throughout the system) and heterogeneous (e.g., a combination of Linux and one or more RTOS deployed on multiple CPUs, shelves and blades) configurations. This flexibility enables developers to select the OS or processor combination best suited to their application. For example, some NEPs may prefer to run Linux on one set of blades to host IT-oriented supervisory and enterprise management functions, while using an RTOS on another set of blades to host DSP-based media processing applications with tight size and performance constraints.

Interprocess Communications

The interprocess communication (IPC) framework provides the glue needed to connect platform components and application processes, providing dependable, high-speed transport for both the control and data plane over reliable and less reliable media. To maximize performance, the IPC framework should utilize direct message passing. This enables application processes to communicate directly with each other on a peer-to-peer basis without having to synchronize through intermediate mechanisms such as mailboxes, semaphores/mutexes, event flags, Unix-style signals, or even sockets. This direct approach also simplifies communications and makes it easy to logically separate processes. The result

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9/11/06 4:06:08 PM

SoftwareTools&Techniques

is enhanced reliability and simpler fault recovery, particularly in distributed systems utilizing multicore devices and complex network topologies. To maximize scalability and portability, the IPC framework should provide a high degree of transparency. Transparency enables processes residing on multiple processors and operating systems to communicate with each other in a seamless fashion across any media, as if they were running on the same processor under the same operating system. When combined with the ability to dynamically discover communication endpoints, this transparency enables developers to locate applications on any node in the system, and change the configuration in real time. With these advanced features, developers and service providers can dynamically change and scale the system configuration, redistribute applications across multiple blades, and upgrade the hardware with minimal changes to the application code.

Middleware

The flexibility provided by the network platform’s IPC layer lays the foundation for more advanced distributed communications, instrumentation, monitoring and high-availability services, collectively referred to as middleware. The middleware extends the IPC’s process-to-process communications services, providing one-to-many communications that facilitate system-wide communications, instrumentation and event notification. These extended communications services, in turn, lay the groundwork for high-availability monitoring, detection, recovery and reporting services that are essential for building a true non-stop computing platform. The middleware’s event logging services, for example, enhance visibility into application operation by enabling processes to log and report events and state transitions such as start-up sequences, slot/service availability, diagnostics and critical network events (i.e., alarm conditions). These services enable developers and network operators to interactively inspect these logs through an HTTP browser. They also make it possible to aggregate the logs system-wide and archive them to persistent media, including remote file systems, for live or postmortem analysis. To simplify configuration and management at the slot, blade and chassis level, COTS middleware provides shelf management services, typically utilizing standard interfaces like Service Availability Forum’s Hardware Platform Interface (HPI). Shelf management performs a hardware inventory each time a system powers up to ensure that all the cards, blades and chassis have been properly activated and initialized. It also tracks revision numbers and ensures that the correct software is running on each card. Once the system is initialized, shelf management monitors key parameters like temperature, voltage, fan speed, power consumption and memory/CPU utilization. It also provides alarm management and hot swap services, which enable individual blades to be inserted and removed from a live chassis. Complementing the middleware’s shelf management services are heuristic fault management services, which provide

monitoring, detection, recovery (i.e., restarting a failed application or failing over to a redundant blade) and reporting for every resource in the system. Active heartbeat monitoring and passive error detection allow the fault management system to ensure the health of key hardware and software components at the system, slot and application levels. The fault management system can also handle upgrade management, treating in-service upgrades as a special fault/failover case.

Database Management

Telecom network platforms must have a way to manage and share data across multiple nodes deployed in the network. One way to facilitate that data management and sharing is to utilize an embedded relational database management system (RDBMS). Unlike a desktop database, an embedded RDBMS can work in a diskless environment. It can also offer a higher level of performance and availability than traditional desktop databases. Enea’s Polyhedra RDBMS, for example, boosts performance by using an event-driven push technology that immediately notifies applications of relevant data changes. Because this approach eliminates the need for polling, it can improve performance by up to 10x compared to a disk- or flash-based RDBMS. Polyhedra also provides journaling and fault-tolerant mechanisms such as failover control and fast reconnection, which enhance data persistence and system availability Until now, network equipment makers have been content to roll their own OS, middleware and database solutions. But a growing number are recognizing that they can no longer remain competitive by creating, maintaining and porting platform software in-house. To gain a competitive advantage, NEPs are beginning to embrace open architecture, standard interfaces and layered pre-integrated platforms. These platforms make it easy to outsource basic hardware and software design and utilize best-of-breed COTS technology, thereby reducing development time and cost. They also facilitate the design of portable, reusable software, which makes devices easier and less expensive to service and upgrade. With the emergence of field-proven, pre-integrated COTS platforms, NEPs can now outsource their platform design, focus their engineering resources on value-added applications and service development, and get their products to market on time and on budget. Enea San Jose, CA. (408) 383-9480. [www.enea.com].

October 2006

Products&Technology SBC Fits Two Dual-Core ULV Xeons on SingleSlot 6U Module

PCI Express Embedded Mini-ITX Motherboard

Mercury Computer Systems, Chelmsford, MA. (978) 256-1300. [www.mc.com].

Ampro Computer, San Jose, CA. (408) 360-0200. [www.ampro.com].

Top performance density and ease of programming for symmetric multiprocessing are two things really needed by engineers developing computationally challenging applications, such as telecom and defense electronics. Both are now available in a family of SBCs from Mercury Computer Systems that incorporate one or two 1.66 GHz Dual-Core Intel Xeon ULV processors in a 6U single-slot module. The board’s density is made possible by the ULV processor, with a thermal design power of only 15W. First in the family of CompactPCI or VME boards is the cPCI Momentum Series CX6200. On each board, both dual-core processors are connected in a symmetric multiprocessing (SMP) configuration, so each processor core has easy access to 8 Gbytes of shared memory. PCI Express technology minimizes internal data-flow bottlenecks and maximizes external I/O throughput for onboard interconnects. I/O interfaces include quad Gigabit Ethernet, RS-232 serial I/O, highspeed serial ATA-150, USB 2.0 and SVGA, with most available at the front panel for easy connectivity. A single-wide PMC/XMC expansion site supports both front and rear I/O. Pricing for the Momentum Series CX6-200 starts at $6,295 each. Discounts are available for higher volumes.

CompactFlash Cards Operate Over Extended Temp Range

Two new CompactFlash cards that operate from -40° to +85°C are available in densities of 4 Gbytes and 8 Gbytes. The cards from WinSystems are targeted for applications that need industrial-grade reliability, industry-standard compatibility and IDE hard disk drive emulation for program and data storage. Both cards are designed to work with SBCs, instruments, cameras or computer systems with a CompactFlash socket for solid-state program and data storage. They incorporate onboard error detection and correction algorithms coupled with dynamic wear leveling techniques to deliver more than two million program/ erase cycles for most applications. The cards are True IDE Mode-capable, including PIO Mode 0-4 and DMA Mode 0-2, as well as ATA-3-compliant. Consequently, they are compatible with operating systems such as Linux, Windows CE and Windows XP Embedded, ROM-DOS and others without requiring a special software driver. List price of the CFLASH-G-8G-I, an 8 Gbyte industrial temperature RoHS-compliant unit, is $479. The 4 Gbyte version is priced at $389. WinSystems, Arlington, TX. (817) 274-7553. [www.winsystems.com]. 74

October 2006

An embedded Mini-ITX motherboard from Ampro, the MightyBoard 821, allows embedded system manufacturers to greatly improve graphics, communications and data processing bandwidth while reducing overall system footprint. For applications that do not need a custom carrier board, the board uses Intel processors to 2.0 GHz with PCI Express graphics and I/O, Gigabit Ethernet, Serial ATA (SATA) storage, USB 2.0, up to 2 Gbyte DDR2 RAM and ACPI power management. At 170 mm x 170 mm (6.75” x 6.75”), MightyBoard 821 offers a choice of 2.0 GHz Pentium M 760 or 1.5 GHz Celeron M 370 processor, along with the Intel 915GM chipset and up to 2 Gbyte DDR2 533 RAM using two DIMM slots. A rich set of I/O includes six USB 2.0 ports, both EIDE and Serial ATA interfaces, two Intel 82573 PCI Express Gigabit Ethernet ports, x16 (“by-sixteen”) PCI Express slot for high-end graphics, as well as integrated chipset graphics. MightyBoard 821 supports VGA and LVDS video interfaces, plus ACPI power management functionality including S3 Suspend-to-RAM. The product is RoHS-compliant and fits in standard Mini-ITX and ATX enclosures. A QuickStart kit includes drivers and board support packages (BSPs) for Windows XP, Windows XP Embedded, Windows CE and a full Linux 2.6 distribution. Prices start in the low $500s in production quantities including CPU.

Multiprocessor Computers for High-Performance Defense and Aerospace

A family of fully configured, high-performance/high-density systems from Curtiss-Wright Controls Embedded Computing offers a wide range of configuration flexibility with versions supporting from 10 to 48 processors. The PowerMatrix-48 DSP, a 21-slot rackmount system supports up to 48 PowerPC 1.25 GHz processors and delivers up to 480 GFLOPS peak performance. The PowerMatrix-10 SMP, an 8-slot rackmount system supports up to 20 PowerPC 1.0 GHz processors for peak performance up to 160 GFLOPS. The PowerMatrix-20 SMP is housed in an 8-slot, 19” rack mount chassis. It supports five quad PowerPC Manta QX3 single board computers, one PSTN StarFabric PMC and one PGR8 Gigabit Ethernet Switch PMC. The PowerMatrix-20 SMP system uses onboard StarFabric bridges and the PSTN PMC card to deliver 600 Mbytes/s aggregate distributed switch throughput. The Gigabit Ethernet Switch card is also provided to connect all of the Manta QX3 cards to the Gigabit Ethernet backplane. PowerMatrix systems will be offered with independent node architecture boards running VxWorks real-time software and symmetrical processing (SMP) architecture boards running Linux. The PowerMatrix systems are highly modular and may be easily customized to meet specific processing and I/O requirements. Pricing varies widely depending on system and configuration. Curtiss-Wright Controls Embedded Computing, Leasburg, VA. (613) 254-5112. [www.cwcembedded.com].

Storage Module Brings Fibre Channel SAN to Rugged Environments

Using commercial Fibre Channel disks for high-speed, streaming data recording applications in harsh environments such as aircraft would allow the power, flexibility and ease of use of the Fibre Channel Storage Area Network (SAN) to be fully exploited. Now this is possible, with VMetro’s SANbric storage system. The SANbric is a rugged, removable storage device providing 1.8 terabytes of storage capacity in a JBOD (Just a Bunch of Disks) configuration in only 4U of shelf space. The SANbric connects to the Fibre Channel SAN via dual 2 Gbit/s Fibre Channel interfaces. Each interface connects to a loop on the SANbric’s backplane, which is split for the dual-loop operation necessary for 400 Mbyte/ s sustained throughput (300 Mbytes/s on the inner tracks). The backplane connects to six 3.5-in. Fibre Channel disk drives. Utilizing a shock isolation frame, the SANbric is designed to tolerate the shock, vibration, altitude and temperatures of extreme environments such as image processing and sensor processing applications in UAVs and other aircraft. Price is $49,900. VMetro, Houston, TX. (281) 584-0728. [www.vmetro.com].

MPEG/MJPEG Frame Grabber Captures Video at 30 Frames/sec

Storing full-motion video requires a lot of memory and transmitting it takes a lot of bandwidth unless the data is compressed into MPEG and MJPEG formats. The Model 314 MPEG-1/2/4 and MJPEG frame grabber from Sensoray compresses images, capturing full-frame (720 x 480) video at 30 frames/second. Uncompressed video is available for previewing through the PC/104Plus bus. A 96-character buffer is available for adding text to each frame. The 314 can supply real-time uncompressed video and snapshots of single frames. The hardware compression circuit uses a motion estimation algorithm to produce smooth images from interlaced cameras. The board has two synchronized audio input channels, audio encoder and onscreen display of text (OSD). It performs motion detection in three user-programmable regions of interest. Digitized audio from the 314 is multiplexed into MPEG streams by Sensoray-supplied software in the SDK. External signals connect to the 314 via a 24-pin header. The opConnected with connections technology and tional 311TA video terminationGet board provides BNC for companies providing solutions now the 314’s composite video inputs. The 314 comes with an SDK includGet Connected is a new resource for further exploration ing drivers and demo applications for Windows-XP, Linux 2.4 and 2.6, into products, technologies and companies. Whether your goal Windows Embedded XP and QNX. is $328. is to researchPrice the latest datasheet from a company, speak directly

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withOR. an Application Engineer, or jump to a company's technical page, the Sensoray, Portland, (503) 684-8005. [www.sensoray.com].

PMC Modules Combine Configurable FPGA with Interchangeable Digital I/O Front-Ends

A family of new PMC-LX and PMC-SX modules from Acromag supports a variety of AXM plug-in I/O extension modules to interface different signal types to a user-configurable Xilinx Virtex-4 FPGA. The Virtex-4 FPGA can process user-defined algorithms and custom logic routines on RS-485 differential, CMOS, or LVDS digital I/O signals depending on the AXM I/O module inserted. The PMC base card has 32 LVDS I/O channels available via P4 for rear connection I/O and conduction-cooled applications. PMC-LX models are optimized for high-performance logic with a choice of LX40 or LX60 Virtex-4 FPGAs, while the PMC-SX model uses the SX35 FPGA designed for high-speed digital signal processing. Typical uses include sonar/radar, military servers, hardware simulators, communication processing and automated test equipment. I/O processing is handled on a separate mezzanine card that plugs into the FPGA baseboard. A variety of these AXM extension I/O modules offer an interface for your analog and digital I/O signals. Additionally, 64 I/O lines are supported via the rear (P4) connector. The PCI bus interface is handled by a PLX PCI 9056 device, which provides 32-bit 66 MHz bus mastering with dual-channel DMA support. For easy integration of the boards with embedded Windows applications, Acromag developed a DLL driver software package for compatibility with Microsoft Visual C++ and Visual Basic. Sample files with “C” source demonstration programs provide easy-to-use tools to test operation of the module. For connectivity with real-time application programs, Acromag offers C libraries for VxWorks, QNX and other operating systems. FPGA modules start at $3,200 with varying performance levels plus $350 for the optional AXM digital I/O extension modules. Acromag International, Wixom, MI. products, (248) 624-1541. [www.acromag.com].

goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Dual-Processor 4.3 will SBC Runs Get VXS Connected help you connectTwo with the companies and products you are searching for.

Independent M-760 Pentiums

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A new dual processor Single Board Computer (SBC) for aerospace and military applications incorporates a high-performance dual independent processor architecture. The V469 Patriot from General Micro Systems utilizes two independent M-760 Pentium M processors that are completely decoupled and offer 100 percent redundancy including power, cooling and I/O. Each half, operating at 2.0 GHz with 2 Mbytes of L2 Get Connected with technology and companies providin cache and 533 MHz FSB, has its own Fibre Channel connection with boot Get Connected is a new resource for further exploration into produc capability. The two halves communicate via a direct Gigabit Ethernet datasheet from a company, speak directly with an Application Engineer, link. Independent high-speed communication by either half to the rest in touch with the right resource. Whichever level of service you require fo of the system or multiple is also GetPatriots Connected will accomplished help you connect via withindependent the companies and products Gigabit Ethernet www.rtcmagazine.com/getconnected facilities through the VITA 41.3 VXS connector. Stacking Patriot modules within a system or in clusters of systems, can achieve a huge array of processing power while still preserving Patriot’s status as a low-power-consuming SBC (70 watts typically). Other features on each side include up to 8 Gbytes of 266 MHz RDDR memory with ECC configured in 128-bit wide, compared to the standard 64-bit-wide DDR 200 MHz of other Pentium M designs. This unique memory design supports fast DMA operations between the system memory and the board’s highspeed I/O devices. Support the Patriot with is available GetforConnected companiesunder and Windows XP/2000, Vxproducts in thisAn section. Works-Tornado II featured and Linux. array of off-the-shelf “Mirroring Softwww.rtcmagazine.com/getconnected ware” for use with Gigabit Ethernet is available from multiple sources. Pricing starts at $4,700 in quantities of 100 units.

Products

General Micro Systems, Rancho Cucamonga, CA. (909) 980-4863. [www.gms4sbc.com]. Get Connected with companies and products featured in this section. www.rtcmagazine.com/getconnected

October 2006

Products&Technology

7U Cube MicroTCA Chassis Supports 6 AMC Cards at Full Height, Double Width

A new 7U Cube MicroTCA chassis is the latest in the line of 4U and 7U Cube and Subrack MicroTCA Chassis from Elma Electronic. The 7U MicroTCA Cube is suitable as a portable development chassis. It allows up to six AdvancedMCs in the full-height, double-width format. With two MicroTCA carrier hubs, the backplane has a Dual Star architecture. There are also redundant power modules, connections for two cooling units and M4 power bolts. The MCH slots come in 1-4 tongue styles. MicroTCA defines a modular backplane architecture designed to support redundant “pods” of AdvancedMC (AMC) modules. The AMC modules (AMC0/.1 /.2/.3) are front removable mezzanine modules first designed to be used on AdvancedTCA (ATCA) cards. The MicroTCA architecture allows large arrays of AMC modules to be used in a wide array of applications where a lower cost solution is required than could be achieved by the standard ATCA architecture. The MicroTCA backplane allows single or redundant virtual carriers to provide power management, platform management and fabric connections to greater numbers of modules than a single physical carrier card could support in a classic ATCA application. Each module may dissipate between 20 and 60 watts each, and the platform management scheme is designed to support applications from 99.99% to 99.999% availability. Pricing starts under $1,500, depending on options.

Core 2 Duo SBC is Backward ProcessorCompatible

A new Intel Core 2 Duo SBC from American Portwell Technologies aimed at medical equipment, industrial automation and process control also supports Pentium D, Pentium 4 or Celeron D processors in an LGA775 socket. The ROBO-8717VG2A utilizes the 1.066 GHz Core 2 Duo’s energysaving advantages, at up to 65W thermal design power. The Core 2 Duo’s other advantages include wide dynamic execution, intelligent memory access, advanced power capability, multicore optimized cache and single-cycle SSE/2/3. Its LGA775 socket is equipped with dual-core, hyper-threading, EM64T, EIST, XD and VT technologies. The ROBO-8717VG2A is a PICMG 1.0 PCI/ISA single host board equipped with 4 Gbytes of DDR2-800 memory, the Intel Q965 Express chipset, integrated graphics controller and a Graphics Media Accelerator 3000 that supports DirectX 9.0, Shader Model 2.0 and 256 Mbytes of video memory. The board’s I/O includes PCI Express x1, dual Gigabit Ethernet ports, four SATA 300 connectors for increased bandwidth, six USB 2.0 ports, dual serial ports, a parallel port and GPIO. List price is $499. American Portwell Technology, Newark, CA. (510) 790-9192. [www.portwell.com].

Elma Electronic, Fremont, CA. (510) 656-5829. [www.elma.com].

1U PCI Express-Based SATA/SAS RAID Array

Digital RCVR Board Eliminates FPGA Development Tasks

One Stop Systems, Escondido, CA. (760) 745-9883. [www.onestopsystems.com].

Pentek, Upper Saddle River, NJ. (201) 818-5900. [www.pentek.com].

What may be the first 1U PCI Express-based RAID storage system has been introduced by One Stop Systems. It is a robust rackmount system providing four hot-swappable SATA II / SAS drives with a total storage capacity of up to 2 terabytes. The RAID system operates from a host PC on either a PCI Express x4 or x8 cable (included) when the PCIe adapter card (also included) is inserted into the host PC’s PCIe x4, x8, or x16 slot. The system supports RAID levels 0, 1, 5, 6, 10 and JBOD, and Intelligent “multiple logical drive” architecture allows the combination of different RAID levels on one set of disks. Hot-swap ability facilitates the replacement of failed drives. Disk arrays provide reliability and a higher data transfer rate through multiple channel access. The RAID controller organizes data on the drives and controls the flow of data to and from the host computer. This allows the user to write/ read data to the drive array from the host PC at speeds up to 40 Gbits/s by simply installing the attached PCIe x8 adaptor board into a PCIe slot in the host PC and cabling it to the RAID system. Now any PC with a PCI Express slot can support up to two terabytes of data in a 1U storage system and access that data at speeds of up to 40 Gbits per second. The 1U, 4-drive PCIe x4 RAID Array lists for $1,595 and the PCIe x8 RAID Array lists for $1,695 (drives not included).

October 2006

Developers of wideband recording and systems, real-time DSP and software radio systems, and data-acquisition applications for wideband communication signals often want to avoid the lengthy, complex programming that can accompany the use of FPGAs. With a high-speed A/D digital downconverter (DDC) board from Pentek, now they can. The GateFlow Model 6821-422 includes a factoryinstalled wideband digital downconverter FPGA IP core operating at frequencies of up to 296 MHz. This DDC is a highly optimized, dual-channel version of Pentek’s GateFlow IP Core 422 that has been tailored precisely to the board’s various resources. The result is a preconfigured, fully tested digital software radio subsystem that accepts a front-panel analog RF input and delivers real or complex digital output samples translated to baseband from any frequency slice of the input signal. The board has a 12-bit sample rate at 215 MHz and four sets of user-programmable FIR coefficients for custom filtering. The Model 6821-422 is supported by Pentek’s Ccallable ReadyFlow Board Support Libraries. ReadyFlow provides development tools for quick start-up through application completion, allows programming at high, intermediate and low levels to meet various needs, and includes complete source code for all functions. Ruggedized and conduction-cooled versions of the board are available. Pricing starts at $17,495.

EPIC Board Sports AMD Geode LX800

An embedded computer platform based on the open embedded platform for industrial computing (EPIC) standard of the PC/104 consortium uses a fan-less Geode LX800@0.9W processor running at 500 MHz. The MSEP800 from Digital-Logic has a main memory that can be equipped with DDR SDRAMs from 256 Mbytes up to 1 Gbyte. A panel of converters provides all standard PC interfaces such as four USB V2.0 ports, two serial interfaces as RS-232C/422/485, dual LAN with 100/10Base-T-Ethernet and 1 Gbit Ethernet, and VGA. Inside the board are connections for one floppy disk, one P-ATA hard disk, two other serial interfaces as RS-232C, LPT1, two PS2, 24 digital I/O channels and eight channels of 10-bit analog input. A slot IDE CompactFlash type I/II serves for assembly with solidstate memory cards instead of the hard disk. The Geode LX800 offers, especially for the application in networks, a 128-bit AES Crypto Accelerator with a performance up to 44 Mbits/s. For display, the board uses the UMA graphic controller of the Geode LX with up to 16 Mbytes VRAM for VGA and 18/24-bit LCD. This controller can display the same image on two monitors. With the optional multimedia module MSEP800CONM, an AC97-compatible stereo sound and DVID are available. With another option this board provides three channels CVBS video input. The MSEP800 is compatible with every standard Pentium PC and runs all common operating systems, such as Windows XP, QNX, Linux, etc. Digital-Logic, San Diego, CA (858) 490-0597. [www.digitallogic.com].

Probe Offers Full Control in ST10F27x Development

Full development support for the four new advanced STMicroelectronics 16-bit microcontrollers of the ST10 family (ST10F27x) is now offered by the new DProbeST10 from Hitex. Especially for industrial applications such as motor control, power converters and positioning systems, the new advanced 16-bit microcontrollers offer a variety of interesting features. The new ST10F271, ST10F272, ST10F273 and ST10F276 provide a range of flash memory densities from 128 to 832 Kbytes, enabling developers to choose the optimum configuration for their application, and offering the possibility of reducing costs with a single-chip design where external flash devices might previously have been required. The DProbeST10 gives the developer full access to all the internal activities of the microcontroller and thus eliminates the most demanding problems. At every operating voltage and up to the maximum processor speed, the in-circuit emulator supports all ST10-specific features, e.g., the MAC unit or the interruptible power-down mode. Using the stand-alone operation mode the development can even be started when the target hardware should not yet be available. The high-speed download is essential during the development of larger applications. A full-featured trace with timestamps not only simplifies debugging but also, together with performance analysis functions, assists in optimizing the performance of any application. For testing safety-critical applications, the system can be extended by an optional hardware-based code coverage or a unit test software for regression testing. Hitex Development Tools, Irvine, CA. (949) 863-0320. [www.hitex.com].

.NET Micro Framework Development Kit Features iPac 524 SBC

Engineers developing deeply embedded applications that require a low-cost hardware platform will benefit from the .NET Micro Framework development kit (NDK), created jointly by SJJ Embedded Micro Solutions and EMAC. The kit includes EMACâ&#x20AC;&#x2122;s iPac 524 SBC running the .NET Micro Framework, as well as source code, instruction manual and other tools, including step-by-step exercises. The NDK can be used to develop a variety of applications from robotics to industrial controls. The .NET Micro Framework contains a tiny CLR that acts as a mini-kernel to run managed code applications. Developers can write C# applications in Visual Studio and download them to the iPac 524. The board features the Sharp 79524 ARM processor in a PC/104 form-factor. The iPac 524 is equipped with a wide variety of I/O to meet multiple Connected with technology and applications, including ten A/DGet channels, 16 digital GPIO lines, eight providing solutions High-Drive digital output lines,companies three multi-purpose I/O lines,now SD/MMC Get Connected is a new for further exploration flash, a graphic LCD interface, 10/100 Ethernet, USBresource 2.0, RS-232 and into products, technologies and companies. Whether your goal 2 five synchronous serial I/O lines (GP/SPP/SPI/I S). Price is $129.

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is to research the latest datasheet from a company, speak directly

SJJ Embedded Micro Solutions, San Diego, CA. 485-1059. with an Application Engineer, or jump to a(858) company's technical page, the [www.sjjmicro.com]. goal of Get Connected is to put you in touch with the right resource.

Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for.

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PLC Application Kit Targets Automation, Control Apps

Developers of programmable logic controllers used in automation and control can now easily incorporate lower-cost hardware with an embedded PLC development from GetkitConnected with technology and companies providin Rabbit Semiconductor. The Rabbit Get Connected is a new resource for further exploration into produc Embedded PLC Application Kit from in- a company, speak directly with an Application Engineer, datasheet cludes ISaGRAF programming softin touch with the right resource. Whichever level of service you require fo ware that has recentlyGet beenConnected upgraded will help you connect with the companies and products www.rtcmagazine.com/getconnected to support Rabbitâ&#x20AC;&#x2122;s products, the Rabbit BL2500 SBC and sample application programs. The ISaGRAF package supports all industrial programming environments listed in the IEC61131-3 standard, including Sequential Function Chart (SFC), Function Block Diagram (FBD), Ladder Diagram (LD), Instruction List (IL) and Structured Text (ST). Based on the Rabbit 3000 microprocessor, the BL2500 SBC incorporates flash memory, digital I/O, analog I/O, multiple serial ports and Get Connected with100 companies and mm board that can easily 10/100 Ethernet on a compact, mm x 100 products featured in this section. be mounted on a standard 100 mm DIN rail tray. Pricing for the Embedwww.rtcmagazine.com/getconnected ded PLC Application Kit is $599.

Products

Rabbit Semiconductor, Davis, CA. (530) 757-8400. [www.rabbit.com]. Get Connected with companies and products featured in this section. www.rtcmagazine.com/getconnected

October 2006

into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for.

www.rtcmagazine.com/getconnected

Advertiser Index

Get Connected with technology and companies providing solutions now Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for.

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Company

Page

Website

Company

Page

Website

ACCES I/O Products.............................. 47..............................www.accesio.com

End of Article

Acromag................................................27............................ www.acromag.com

Octagon Systems.................................2,3.................www.octagonsystems.com

Advanet Technologies............................28.......................www.advanettech.com

One Stop Systems................................. 71.................www.onestopsystems.com

Products

Get Connected with companies and

products featured in this section. www.rtcmagazine.com/getconnected

National Instruments.............................10.......................................www.ni.com

Get Connected

Altera Corporation.................................19.................................www.altera.com

with companies mentioned in this article. Performance Technologies. ....................13...................................... www.pt.com

American Arium ....................................21.................................www.arium.com

Phoenix International...............................6............................ www.phenxint.com

Application Acceleration Seminar........... 72..........................www.aaseminar.com

QNX Software Systems, Ltd...................42.................................... www.qnx.com

ARCOM.................................................63................................ www.arcom.com Get Connected with companies and products featured in this section.

Real-Time & Embedded

BitMicro Networks, Inc.............................6............................. www.bitmicro.com

Computing Conference ....................48,65..................................www.rtecc.com

Blunk Microsystems..............................61......................... www.blunkmicro.com

Red Rock Technologies, Inc...................61....................... www.redrocktech.com

ELMA Electronic, Inc..............................22.................................. www.elma.com

SBE, Inc................................................35................................... www.sbei.com

Embedded Planet..................................38................ www.embeddedplanet.com

Sealevel Systems..................................23............................. www.sealevel.com

GE Fanuc Embedded Systems............. 4,79............ www.gefanuc.com/embedded

Teligy....................................................33..................................www.teligy.com

General Micro Systems, Inc...................25............................www.gms4sbc.com

Thales Computers.................................46................ www.thalescomputers.com

Green Hills Software, Inc.......................44.................................... www.ghs.com

Tri-M Systems.......................................34.................................. www.tri-m.com

Interactive Circuits and Systems..............8................................ www.ics-ltd.com

Ultimate Solutions.................................37................................. www.ultsol.com

Kontron America.................................... 17...................www.FindDistinction.com

VadaTech................................................7............................www.vadatech.com

Micro Digital, Inc...................................57............................. www.smxrtos.com

WIN Enterprises/AMD............................67...............................www.win-ent.com

Micro Memory LLC.................................80..................... www.micromemory.com

Wind River Systems, Inc........................55............................ www.windriver.com

Microsoft Windows Embedded..........40,41..........www.microsoft.com/embedded

WinSystems..........................................51........................ www.winsystems.com

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MVACEC................................................31.............................. www.mvacec.com

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October 2006

GE Fanuc Embedded Systems

Making AdvancedMC a reality. ™

Choose from our large selection of real, available products. GE Fanuc Embedded Systems, as part of our acquisition of SBS Technologies, is in the forefront of the industry, offering a broad range of real AdvancedMC products. Our goal is to preserve and extend our existing AdvancedMC product line offering. Over the last 12 months we have designed and launched more than a dozen AdvancedMCs, as well as a number of carriers. If you are interested in keeping up with AdvancedMC technology we invite you to subscribe to the AdvancedMC Insider monthly newsletter. It’s easy to subscribe, just go to www.advancedmcinsider.com

NAME

DESCRIPTION

AMC.1

TELUM TSPE01

Processor AMC module with PowerPC 7447A processor

TELUM ASLP10

Intel® Pentium® M processor AMC module

•

TELUM 624/628-TEJ

WAN Edge Access I/O, 4 or 8 port T1/E1/J1, ITDM option

•

TELUM 1001-O12M/S

WAN OC-12 module

•

TELUM 1001-O3

WAN OC-3 module

•

TELUM 1004-O3M/S

WAN OC-3 module

•

TELUM 1001-DE

WAN DS3/E3 module

•

TELUM 1204-O3

WAN intelligent AMC.2 multi-service 4-port OC-3 module

TELUM GE-QT

Gigabit Ethernet AMC 4 port NIC

•

TELUM FC2312-FF

Fibre Channel HBA cards (fiber-optic media)

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TELUM FC2312-CC

Fibre Channel HBA cards (copper media)

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AT-AMC1

AdvancedTCA carrier for 2-4 AMC.1 modules

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AT-AMC2

AdvancedTCA ® carrier for 2-4 AMC.2 modules

BCT4-AMC1

IBM® BladeCenter® T carrier for 4 AMC modules

TELUM GPSTC-AMC

GPS-based clock AMC module

TELUM 2001-VGA

AMC VGA module

AMC.2

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