RTC magazine

The magazine of record for the embedded computing industry

July 2013

Developing for Integrated CPU/FPGA Devices Optical Interconnects Race to Keep up with Data Getting a Hand on Multicore Development

An RTC Group Publication

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Transportation Management Grows Toward the Cloud

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TABLEOF CONTENTS

46 Ethernet Device Uses Precise Algorithms for Counting Passengers

VOLUME 22, ISSUE 7

Departments

6Editorial The World of Intelligent Systems Belongs to the World 8

Industry Insider Latest Developments in the Embedded Marketplace

Technology in Context

TECHNOLOGY IN SYSTEMS

Devices Integrate CPUs with FPGAs

Fleet Management and Transportation

Hardware/Software 16 Simplifying Co-Design on Programmable Devices Mark Saunders, Cypress Semiconductor

20

How Fast Can You Design an Embedded System with SoC FPGAs?

Form Factor Forum Too Hot to Handle 10Small & Technology Newest Embedded Technology Used by 42Products Industry Leaders

TECHNOLOGY CONNECTED

EDITOR’S REPORT

24

A Look at Some Developments

and JTAG—A Look at Some Developments 12FPGAs

Wendy Lockhart, Microsemi

Optical Interconnects: Keeping Up with Data Speed VPX at Light Speed—Optical Brings 100 Gigabits to Backplane Architectures

of an M2M 28Development Ecosystem Benefits Fleet and Transportation Management: What Do Fish Have to Do with It? William Andrew Albano, Lilee Systems

Safety through 34Functional CompactPCI in Mass Transit Computing Systems Susanne Bornschlegl, MEN Micro

TECHNOLOGY DEPLOYED Multicore System Development

Going on in My Multicore System?

38What’s John Carbone, Express Logic

Michael Munroe, Elma Bustronic

Tom Williams

Digital Subscriptions Available at http://rtcmagazine.com/home/subscribe.php RTC MAGAZINE JULY 2013

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JULY 2013 Publisher EMBEDDED SOLUTIONS R-SERIES APU

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PRESIDENT John Reardon, johnr@rtcgroup.com

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To Contact RTC magazine: HOME OFFICE The RTC Group, 905 Calle Amanecer, Suite 250, San Clemente, CA 92673 Phone: (949) 226-2000 Fax: (949) 226-2050, www.rtcgroup.com Editorial Office Tom Williams, Editor-in-Chief 1669 Nelson Road, No. 2, Scotts Valley, CA 95066 Phone: (831) 335-1509

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Published by The RTC Group Copyright 2013, The RTC Group. Printed in the United States. All rights reserved. All related graphics are trademarks of The RTC Group. All other brand and product names are the property of their holders.

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JULY 2013 RTC MAGAZINE

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EDITORIAL JULY 2013

The World of Intelligent Systems Belongs to the World

I

n these pages, we have increasingly been talking about what is becoming a buzz word in the industry, “Intelligent Systems.” The name has been coined—amid some dispute about who invented it—and appears to be sticking as a description of what is actually a worldwide phenomenon. Whatever one might think of the name, it is here and we’re stuck with it. No one is going to own it or copyright it, although there appear to be some attempts to establish a mental association with the term. The fact is that it is too big for any one company or group and is beyond any single company’s marketing strategy or branding effort. In my humble opinion, it’s not even that great a name.

But as I said, we’re stuck with it. So let us embrace it and share it and continue to define it as the nature of this entity becomes clearer.

It is also apparent that different segments of the industry have different perspectives on Intelligent Systems—those from the view of the Cloud, IT, telecom and embedded systems. From our perspective, we have the view that what is coming to be known as Intelligent Systems is actually being driven by the explosive growth of intelligence and connectivity—and sheer numbers—of embedded and mobile devices. One certainly would not refer to a bunch of networked IT data centers as Intelligent Systems. For that we need connection to the real world through sensors and actuators and through the participation of millions of users. It consists of both autonomous and human nodes based on a simple formula: intelligence + connectivity = greater intelligence It has been interesting to watch the evolution of embedded systems over the years going from individual devices such as process controllers that have then been networked into SCADA systems for better human access and coordination. From there they have developed into machine-to-machine (M2M) systems where devices operate and communicate with a high degree of autonomy among each other in a common application such as a fleet management system.

We had such systems in mind when we set up the section for this issue on fleet management and transportation. To our delight, the article in this issue by William Andrew Albano of Lilee Systems takes the notion of fleet management into the realm of Intelligent Systems by suggesting connections between management of vehicles for, say, a freight company, to a wider realm including real-time communications with other vehicles on the road, traffic signals, law enforcement, weather and other traffic data to name a few.

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JULY 2013 RTC MAGAZINE

Tom Williams Editor-in-Chief

Such connectivity and data flow may include the proprietary application (a cloud within the Cloud) but link it to other public and in some cases private data to encompass a transportation infrastructure. We can expect this pattern to be replicated in a vast number of application scenarios, and we at RTC are expanding our coverage to recognize this from the perspective of the developers of embedded systems who will be ever more involved in this emerging universe.

The RTC Group has also just completed its first successful Intelligent Systems Conference and Pavilion in conjunction with the Sensors Expo in Chicago. The participants and presenters at that conference contributed a wealth of insights and perspectives that serve to reinforce our views of this phenomenon. As a result of this experience, we will also be expanding the scope of our well-established RTECC shows that have been a staple of the industry for 25 years. They will now carry additional sessions and presentations that put the activities of our participants into the larger context of Intelligent Systems, demonstrating how the products and technologies they offer can enhance the applications their customers are building by working within this worldwide context. Here too, the perspective remains firmly rooted in the realm of the embedded developer but looking beyond to the wider world of Intelligent Systems in which we live and the world of Big Data.

That world of Big Data, it turns out, is mostly generated by billions of small devices—some predict over 50 billion by 2020. That data presents a huge challenge—not only through its sheer volume but also by its diverse nature. Some of it must be acted on in real time while other data must be routed and stored for analysis. In addition, real-time reaction to data creates data about the results of such actions that must be interpreted further. Thus the connection of devices to each other as well as to aggregation gateways and ultimately the Cloud ties them all together. And we haven’t even mentioned the world of consumer devices that gets drawn into the picture.

That involves such things as home networks with smart appliances that connect to the smart grid where energy distribution must be monitored and managed. People are increasingly migrating toward a unified way that they want to interact with the whole world of automation via graphical touch screens on tablets and smartphones.

That means that not just engineers and specialists but also most ordinary people are also active participants. This is a world that will continue to grow and we will be its reporters and its champions.

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Intel, the Intel logo, Xeon, and Xeon Inside are trademarks or registered trademarks of Intel Corporation in the U.S. and/or other countries.

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INDUSTRY

INSIDER JULY 2013 Cisco Drives Security in Modernizing the Connected Grid The core mission of utilities, as well as their regulatory mandate, is to provide safe and reliable power. Cisco has announced expanded solutions and services to help utilities enhance grid operations with greater levels of automation and security and changing regulatory requirements. Cisco’s strong security knowledge and history combines a security strategy that addresses both the physical and cyber security layers, coupled with utility-specific service offerings for the electric grid based on Cisco’s Connected Grid Security Architecture. Cisco also extended its hardened network solutions for substations to allow utilities better visibility and management of the grid.

The Cisco Connected Grid Security Architecture is a blueprint that simplifies policy administration, strengthens security controls and gives businesses more flexibility and increased visibility into operations via a layered security architecture in which the communication network serves as a platform tool to detect, control, alert and mitigate against threats. Contextaware policies are enforced across the entire utility infrastructure network to meet rapidly evolving regulatory requirements and correlate directly with potential threats and business rules.

In addition, physical security solutions include integrated video surveillance along with physical access control tools such as card readers and sensor networks, for monitoring the status and location of assets and users. Cisco Services for Grid Security assists utilities in defining security requirements, developing future-state grid security architectures, coordinating the deployment and integration of security solutions, and delivering ongoing optimization and managed services.

Digi International Deploys 500-Node Internet of Things Network for the Data Sensing Lab at Google I/O

Digi International has taken part in deploying over 500 sensor nodes at Google’s recent developer conference. The Data Sensing Lab project demonstrates how real-time machine-to-machine (M2M) data can provide insight into customer behavior and preferences. Utilizing Digi’s XBee ZigBee modules and ConnectPort wireless gateways to connect the nodes, sensor data was then collected and managed via Device Cloud by Etherios, Digi’s platform for managing large populations of devices and connecting devices to applications.

Google used the Internet of Things to get a global view of their

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JULY 2013 RTC MAGAZINE

entire multimillion dollar event as it played out in real time. They learned where people are going and when, how loud the applause was for each presentation, where it was figuratively hot and where it was literally cool. But the exercise also demonstrated how easy it is to integrate M2M data, via Device Cloud’s APIs, with their own cloudbased business systems. Google and Digi collaborated to create a complete end-to-end solution in just a few weeks, one that was able to hand over 40 million data points.

The sensor network’s 4,000 data streams running over Device Cloud utilized over 500 XBee modules connecting Arduinobased sensors to provide continuous updates on temperature, pressure, light, air quality, motion and

noise levels in San Francisco’s Moscone Center during the conference. The Google Cloud Platform team gathered, transformed and analyzed the information and then shared heat maps and other data visualizations in collaboration with the Google Maps team.

EEMBC and Volkswagen to Develop Benchmarking Standards for Microcontroller Energy Efficiency

The Embedded Microprocessor Benchmark Consortium (EEMBC) has announced an expanded working group project with the Volkswagen Group to establish an energy-efficiency benchmark for microcontrollers aimed at making automotive end products more energy aware and more robust.

With increasing fuel costs, there is a growing emphasis on reducing energy consumption and improving fuel economy in automobiles.

Simultaneously, there is also an on-going requirement to ensure the highest levels of robustness in any automotive product. Microcontroller efficiency (optimizing both performance and energy) is a critical parameter with far-reaching consequences, especially with the rising number of microcontrollers in the car. The working group project, to augment results originally produced in 2011, is being chaired by Volkswagen and currently joined by eleven top-tier semiconductor vendors including Freescale, Fujitsu, Infineon, Microchip, NXP, Renesas, STMicroelectronics and TI. Already, the effort has yielded a full working specification for measuring performance and energy efficiency of automotive microcontrollers under various low-power operating conditions.

EEMBC has also developed a prototype of this benchmark implemented on several key semiconductor evaluation boards.

EEMBC’s first-generation automotive benchmark suite, AutoBench, was designed to focus on the CPU’s processing power, measuring the time required to complete specific algorithms. The new benchmark suite adds new tests to measure CPU performance while simultaneously monitoring peripherals and energy usage. Individual tests of the microcontroller measure the power consumption of the CPU and peripherals under various loads, the amount of time that it spends in low-power modes under various CPU/peripheral loads, and the time required to wake the MCU from its various low-power states to resume processing. Moreover, the working group will align this benchmark suite with the AUTOSAR development partnership, utilizing the Microcontroller Abstraction Layer (MCAL) to interface to the underlying microcontroller hardware.

This benchmark specification will be open to all worldwide car manufacturers and tier 1 suppliers, and EEMBC encourages everyone in the ecosystem to join the effort to develop subsequent phases of this benchmark.

Micro Sensors and MEMS Components in Mobile Devices to Generate Almost $8 Billion by 2018

A new report finds that the market for mobile Micro-ElectroMechanical Systems (MEMS) sensors and components will reach almost $8 billion in 2018.

Such components include microphone and camera devices embedded within smartphones, tablets, eReaders and wearable devices. MEMS sensors are crucial to mobile device functionality and enable services such as augmented reality, context awareness and navigation. They drive applications such as gaming, imaging and videography.

The report from Juniper Research, “Mobile Sensors & MEMS: Market Prospects 2013-2018,” examines how this high growth sector will be further driven by the emergence of wearable technology.

Health and fitness will play a key role as it will rely heavily on MEMS sensor technology to measure temperature, pressure, physical activity and other key aspects of the body.

The report also identifies the next wave of sensors in the mobile device area—MEMS cameras.

MEMS cameras will offer new levels of functionality such as multiple points of focus that will allow viewers to choose which points within the image have the main focus.

“With Apple and Samsung paving the way, device manufacturers are integrating multiple sensors, and combining these to enable future services. The need for better performance and stronger device specifications, in order to provide service differentiation, are driving the demand for sensor integration.

This means the industry will witness greater levels of innovation in terms of MEMS-based components and sensors in the mobile device area,” noted report author Nitin Bhas.

As components such as accelerometers, gyroscopes, magnetometers and microphones reach high levels of adoption, MEMS cameras will begin to hit the market in the next 12-24 months. Recently, DigitalOptics demonstrated a camera module based on a MEMS actuator capable of multiple points of focus at the Mobile World Congress 2013 in Barcelona.

by the Boards of Directors of each company. The transaction is expected to close in early June 2013 and is expected to be immediately accretive on a non-GAAP basis.

“We are pleased to announce the acquisition of Novocell and are expecting great things as we integrate the technology into our everexpanding portfolio of IP solutions,” said Mark Reiten, vice president of Technology Licensing for SST, a wholly owned subsidiary of Microchip. “This acquisition provides our customers with valuable and differentiated technology and helps us to enable their designs with an even more comprehensive set of solutions, expanding our position as a leading memory IP supplier.”

“We are extremely happy to become part of SST and the Microchip family and are excited by the strategic possibilities available to us, moving forward, from both a business as well as a technology perspective,” stated Walter Novosel, Novocell’s president and chief technical officer. “Novocell has continued to grow its portfolio of nonvolatile-memory IP solutions since its inception, and we fully expect the technology to see an increased adoption from joining a leader like SST in the memory IP market. With SST’s offerings in the high-density arena, we can concentrate on not only expanding our customer base, but also growing the footprint that SST has built with customers worldwide in low-density OTP and MTP memory.” Under the acquisition agreement, Novocell will become a wholly owned subsidiary of SST, a Microchip company.

Microchip Technology Announces Acquisition of Novocell Semiconductor by SST

TQ-Systems Announces Hardware Collaboration with Wind River

Microchip Technology and Novocell Semiconductor have announced that Microchip and its subsidiary SST have signed a definitive agreement to acquire Novocell. The acquisition was approved

TQ-Systems, electronics service provider and module manufacturer, has announced a hardware collaboration with Wind River. As part of the Wind River Hardware Partner Alliance Program, TQ will

offer solution packages aimed at applications in the medical device market segment.

The solution packages will include state-of-the art CPU modules, suited to match requirements of various applications, as well as Wind River VxWorks real-time operating system or Wind River Linux for ARM and PowerPC applications.

The current versions of VxWorks and Wind River Linux are running on the TQ star product TQMa28 and are in preparation to be implemented onto the latest Minimodules based on Freescale i.MX6 and PowerPC. Wolfgang Heinz-Fischer, head of marketing and PR at TQGroup, explains: “With Wind River we have a strong partner at our side with which we can continue the expansion of our solution components. As part of our collaboration framework we put together attractive packages for our customers using TQ modules and Wind River software. The customer can then immediately begin using the package as a basis for creating its own product quickly and cost-effectively.”

“This collaboration will offer medical device manufacturers up-to-date technology platforms with documents related to certification, allowing them to start with the system evaluation right away, thereby meeting regulatory requirements,” said Gerhard Zehethofer, sales director, EMEA at Wind River. “The combination of TQ’s high-performance, robust modules and Wind River’s industry-leading operating systems, provides a very compelling offering to the market.”

GENIVI Alliance Teams with W3C to Accelerate Adoption of Web Technologies in the Automotive Industry

The GENIVI Alliance has joined the World Wide Web Consortium (W3C) to bring its

automotive expertise into W3C’s Automotive and Web Platform Business Group.

The GENIVI Alliance, an automotive and consumer electronics industry association driving the development and adoption of an open in-vehicle infotainment (IVI) reference platform, will focus on accelerating the process of defining APIs for HTML5 web applications to interface to the hardware of the car, vehicle bus interfaces, etc.

W3C’s Automotive and Web Platform Business Group, launched in February, convenes developers, automotive manufacturers and suppliers, browser vendors, operators and others to discuss how to enhance driving, safety and passenger entertainment with the Open Web Platform.

“The auto industry and W3C are exploring the ways in which the Open Web Platform can enhance the experience of drivers and passengers, while increasing safety,” said Jeff Jaffe, W3C CEO. “GENIVI’s participation plays an important role in ensuring representation of the diverse players within the auto industry.

Given the Web’s overarching role in our lives, we see huge opportunity for society and the automotive industry to benefit from this partnership, and welcome GENIVI as a new W3C Member.”

HTML5 API for automotive promises to become a widely used set of technologies to build applications across platforms. In time, these applications could quickly be adapted from tablets to smartphones and now to cars.

Eventually it will be the turning point as to when developers will start being able to create new concepts for the vehicle rapidly in a way that is standardized across multiple brands.

RTC MAGAZINE JULY 2013

9

SMALL FORM FACTOR

FORUM Colin McCracken

Too Hot to Handle

E

ngineers everywhere are trying to beat the heat this summer. Some have contracts to fulfill, held up only by the thermal design and qualification. The 45 watt 2 GHz+ quad core processors have impressive performance specs, but try not to touch them with your finger unless a second degree burn is part of the cooling solution. You can’t ship with cooling spray, either. Perhaps some of us were mesmerized with the topless COMe (COM Express) module photo shoot and forgot to buy the massive fansink required to remove heat. Or maybe the active cooler is so bulky or heavy that it requires its own shipping container and simply hasn’t arrived yet. Ever wonder why the thermal solution is not included with the slim product photos on the website and datasheet?

Replacement modules (“upgrades”) are already in production with 3rd-generation Core i7 processors that knock 10W right off the top without sacrificing speed (still 2.1 GHz quad core).

Tick tock, just like clockwork. Some are even available in the same late-lifecycle COMe Type 2 pinout as your existing carrier board for easy drop-in. Impressive. Those who research new product announcements will be rewarded. For everyone else, be prepared to spin your carrier to be able to access a lower power CPU with a Type 6 pinout.

OEMs who must always have the highest speed available are stuck with the highest power envelope as well, and they must put the pedal to the metal for cooling solutions that improve overall system reliability by channeling heat outside of the system more efficiently, rather than sharing that heat with other sensitive electronics inside.

“Caveat emptor” applies to OEMs looking at a quad core processor shoe-horned into the 95 x 95 mm Compact size. Evaluate these carefully, not just from the perspective of whether everything you need actually fits on the COMe module, but also according to how your system will dissipate the 45W through a smaller heatspreader than for other 125 x 95 mm quad core module alternatives. The long-term reliability issue might be

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hard to measure initially. The more metal mass closer to the CPU, the better.

Just as you would add up signal losses in your RF link budget or IR drops in your power circuit, it’s imperative to sum the temperature rises through the various components of the thermal solution. Air gaps or bubbles in the thermal interface material only get in the way. Inserting a very thick gap pad is a brute-force approach to the very wide Z-axis tolerance of processor packages themselves. But this type of pad comes with a high thermal resistance, and it is difficult to build up enough pressure as required by the processor manufacturers for proper heat removal. Instead, some creative approaches involve high-compliance metal blocks with springs and heat pipes and so on, although usually at a higher cost. Such heatspreaders with integrated heat pipes are available now, with or without fins and fans. The goal is to reduce the overall effective thermal resistance. Again, rewards are available to engineers who scour trade journals and websites rather than simply “drinking the KoolAid” of the first pretty datasheet atop the search engines. Each OEM can carefully choose its system’s total cost of quality destiny.

The recent launch of 4th-gen 22nm Core i7 “Haswell” processors offers some relief from the summer heat as well. Early samples are available now from COMe manufacturers for those who can test with a Type 6 carrier board. Whether for medical, communications or military applications, Haswell modules advance the performance possible at that highest power envelope, and even offer lower-power SKUs where power is a higher priority than performance. In this latter category, AMD has surprised the market with its recent introduction of eKabini SoC (system on chip) processors with up to a 2 GHz quad core rated at only 25W. Intel has good reason for concern, as AMD overcame significant odds to pull this off. Whether with Intel or AMD processor, COM Express offers multiple ways to beat the quad core heat through timely availability of the latest CPUs and advanced cooling solutions alike.

editor’s report A Look at Some Developments

FPGAs and JTAG—A Look at Some Developments This month’s Report looks at two different developments that can signal important directions for the embedded industry.

by Tom Williams, Editor-in-Chief

T

aking a short break from what may be seen as our tendency to concentrate on the “snazziest” looking developments in technology, let’s look at some interesting developments in the world of mid- to lowerrange FPGAs. By that we mean devices with 150k or fewer logic elements that are in growing demand for an increasing variety of system uses. Far from the “glue logic” of old, these devices are taking on roles in aerospace and defense and industrial automation as well as wireline and wireless infrastructure.

Their roles include a rich variety of I/O processing and translation, packet switching, traffic management, system management and security.

A relatively new player in this arena is Microsemi, which is adding to its portfolio with the introduction of its IGLOO2 line of devices ranging from 6k to 150k logic elements. But the devices add some new features to the mix in the form of hard-wired interfaces, a memory subsystem and security elements.

In addition, the devices are flash-based, which means that they do not require configuration from an external device such as flash memory or an EPROM.

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JULY 2013 RTC MAGAZINE

Rather, once their configuration is programmed into the FPGA fabric, they are nonvolatile and retain their programming when powered off and thus are instant-on without having to load from an external device.

With this market segment currently estimated at about $1.2 billion, we can expect some pretty fierce competition with the emphasis not so much on the simple number of logic elements but rather on cost, performance, power consumption and ease of use. For starters, Microsemi is boasting of a static power as low as 45 mW thanks to its Flash*Freeze technology, and a 3x increase in performance over its previous IGLOO family.

The identification of the main application areas for devices of this class has made it possible to hard wire a number of functions and peripherals rather than implement them in programmable logic, resulting in space savings over a given die area, or a higher number of logic elements that can be utilized for custom design. This has resulted in several on-chip function blocks, which offer up to 16 serial/deserializer (SERDES) lanes and

include some standard interfaces such as 10/100/1000 Ethernet and up to four PCI Express endpoints. In addition, there are up to almost 200 lines each of 3.3V and 2.5V user I/O (Figure 1).

The availability of so much readymade yet user-configurable I/O along with fabric-based programmability and DSP blocks suit the IGLOO2 to one of its major roles in I/O expansion and bridging in a vast number of networked devices. For example, a system management application must communicate over a number of different interfaces— including I 2C and PCIe as well as userdefined I/O—to sense temperatures, control fans and communicate with the main CPU and the management subsystem. It helps to have such things as PCIe and I 2C predefined as well as to have the ability to configure other user I/O. In addition, it is definitely desirable to have the management card come up before the main CPU, which is where the flash-based instant on features can be an advantage.

The ability to do I/O bridging and I/O expansion in applications such as communications and industrial control with a small, low-cost device will become increasingly important as the Internet of Things continues to grow, incorporating ever more small, specialized devices that ultimately need to have their individually small contributions of data join the realm of Big Data in the Cloud. Once again, the SERDES section can offer ready-made PCIe, GbE and 10GbE interfaces that can bridge through the fabric to all kinds of specialized protocols such as Profibus, Fieldbus, CAN, Modbus, CAN, DeviceNet and more implemented through use of the fabric (Figure 2).

Again, with the rise of the Internet of Things, M2M authentication is becoming a big issue as is security in both wired and wireless communications. While security has always been an important consideration, that concern has tended to concentrate on larger systems. The question now is how to implement it easily, reliably

editor’s report

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10-236

SRAM-PUF Math Blocks (18x18)

Micro SRAM (64x18)

Large SRAM (1024x18)

PDMA HPDMA

FIC

ECC

FIC

FPGA Fabric

Up to 150K Logic Elements

eSRAM_1

DDR Bridge

AXI/AHB

667 Mb/s DDR Controller/PHY

AXI/AHB

667 Mb/s DDR Controller/PHY

Multi-Standard GPIO

(1.2 – 3.3 V, LVDS, HSTL/SSTL)

Figure 1 The Microsemi IGLOO2 family implements classes of elements that are common to the needs of a great many designs on-chip as standard cells, many of which, such as SERDES and GPIO, are configurable.

and cost-effectively on individual small devices. Hard-wired 256-bit encryption engines for Advanced Encryption Standard (AES256) and the Secure Hash Algorithm (SHA256) are provided on-chip along with system and memory integrity functions such as ECC. Since almost every FPGA design requires “someplace to put stuff,” they all need some sort of on-chip memory as well as access to external memory.

This is provided on the IGLOO2 via a memory subsystem that includes a nonvolatile eNVM-flash memory for storing things like Ethernet MAC IDs, user information keys or other system configuration data. It can also be used for secure boot of external application processors. Also included are embedded SRAMs for local zero wait state memory for time-critical applications. For

Application Processor SPI

SGMII SGMII

PCIe

Memory Subsystem

Real TIme Fieldbus Concentrator

10/100/1000 Ethernet 1588 Timestamp

System Monitor and Control

PHY PHY PHY PHY Profibus Modbus DeviceNet

IGLOO2 Figure 2 The use of small, moderately priced FPGAs is becoming increasingly attractive for bridging between different I/O ports, networks and protocols.

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editor’s report

access to memory outside the device, there are two DMA engines as well as a DDR bridge.

Developments such as these in the realm of FPGAs appear to be the result of the needs for small, cost-effective, low-power devices that can serve in small systems and devices with widely divergent I/O requirements that must fit into the growing world of universal connectivity. The availability of devices that can easily serve the subset of common requirements (e.g., Ethernet, PCIe,

GPIO, security) while also being configurable enough to adapt these common needs to specialized requirements using a single platform, could well indicate a trend for the future.

Revised IEEE 1149.1 to Allow Test Reuse Throughout Integrated Circuit Lifecycle

A new enhancement to a wellestablished standard promises to significantly improve testing of not only integrated circuits such as ASICs and

BOUNDARY REGISTER INIT-DATA REGISTER Register Segmentation and Power domain control

USB

DC Input 1

0

0 1

DAC

ADC

User Defined Chain(s)

AC/DC

PLL Swing

Volt.

Mon

0 1

PRBS Logic BIST

CMMV

Protocol On-chip Reset via TAP SysReset

Unique ECID

Memory BIST

IR & Decode & Muxing IC1

TAP

Figure 3 The addition of built-in self-test elements and elements that have a mission mode and can also be queried can now be done according to a standard that offers machine readable test set up and test reuse from the IP to the system test level. Source: Intellitech/C.J Clark

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SoCs, but also to allow testing based on internal functions to be made easily available to testers at the board and system level.

The revision of IEEE 1149.1— commonly known in the industry as “JTAG,” for “Joint Test Action Group”—is intended to dramatically lower electronics industry costs by enabling test reuse across all phases of the integrated circuit (IC) lifecycle via vendor-independent, hierarchical test languages. This will allow critical domain expertise for intellectual property (IP)—how to configure a serializer/deserializer (SERDES) for loopback testing, for example—to be transferred in a computer-readable format from the IP designer to IC designers and, in turn, to designers of printed circuit boards (PCBs) and to test engineers, gradually magnifying industry cost savings along the supply chain.

The cost savings for the electronics industry that IEEE 1149.1-2013 is intended to unlock are estimated to be in the billions of dollars.

“IEEE 1149.1-2013 is poised to have a major impact on how business is done across the electronics industry— from IP providers to silicon vendors to system integrators—as it is designed to eliminate inefficient engineering,” said C.J. Clark, chair of the IEEE 1149.1 working group and CEO of Intellitech.

“The IP provider can document the IP test interface and how to operate the IP in an English-like language—just once, for all ICs. Software tools then re-target this documentation at the IC and board level for tests. In revising IEEE 1149.1, the working group focused on two things: lowering industry costs through the new PDL language and enabling test reuse over the lifecycle of an integrated circuit.”

The test features are specified in IP that is incorporated into the chip design IP and can take the form of built-in self-test (BIST) devices or mission mode devices that can be queried for data. For example, an ADC could be queried to obtain the digital representation of the current analog value (Figure 3).

editor’s report

IEEE 1149.1-2013 specifies a new hierarchical Procedural Definition Language (PDL)—a standard test language based on Tcl, and hierarchical extensions to the original Boundary Scan Description Language (BSDL) to describe on-chip IP test data registers. Eight new optional IC instructions provide a foundation for configuring I/ Os for board test, mitigating false failures when re-testing the IC at the board level, and correlating the results back to wafer level test through an Electronic Chip ID. That chip ID will specify not only the device, but also the wafer, the lot number, the foundry and even the X-Y coordinates of the die on the wafer. Clark cites an example of a chip whose failure in the field was traced back to its position on the wafer where the optics somehow caused similar problems for all dies in that position. It was found that it made better sense simply to discard those particular dies.

IEEE 1149.1-2013 provides critical synergy with two other important industry standards. IEEE 1149.1-2013 supports segmented on-chip test data registers that cross power domains specified by IEEE 1801-2013 “Standard for Design and Verification of Low Power Integrated Circuits”.

IEEE1149.1-2013 enables descriptions and operation of IP accessible via IEEE 1500-2005 “Standard Testability Method for Embedded Core-Based Integrated Circuits” structures; IEEE 1500 is frequently used for production IC testing. IEEE 1149.1-2013 domain segmentation adds new capability to the IEEE 1500 Wrapper Serial Ports.

“The new features of IEEE 1149.12013 address the many challenges in describing and managing chips with complex programmable I/Os or chips with multiple power domains. Private instructions and test data registers can be documented and tool support for them can be automated,” said Carol Pyron, vice chair of the IEEE 1149.1 working group and senior member of technical staff with Freescale Semiconductor.

With the announcement of the re-

vised standard, IC designers will be able to incorporate the new test IP into new designs. Designers using FPGAs can almost immediately obtain the test IP to incorporate with the IP they are building into new FPGA-based designs.

Q

Q

Q

Q

Q

Untitled-1 1

Safe computers for rail, road and air, up to SIL 4/DAL-A Modular box and panel PCs for industry & transportation Powerful system solutions on CompactPCI®/PlusIO/Serial Rugged, standard Computer-On-Modules (ESMexpress®, ESMini™) EN 50155- and e1-certified Ethernet switches and fieldbus interfaces

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7/9/13 10:55 AM

Technology in

context

Devices Integrate CPUs with FPGAs

Simplifying Hardware/Software Co-Design on Programmable Devices Programmable devices with embedded CPU cores provide an effective means for addressing a wide range of design challenges that are difficult or costly to solve with just hardware or software alone. These devices combine digital and analog hardware resources that can be reprogrammed to provide the exact functionality you need.

by Mark Saunders, Cypress Semiconductor

T

he PSoC Creator tool from Cypress Semiconductor was designed specifically to make straightforward hardware/software co-design easy. Rather than forcing you to complete electrically perfect circuits, it lets you draw only the relevant part of the design, just like you would do on a whiteboard. It then figures out the best placement and routing of peripheral blocks (which are called components), sets up the required clocking and power configuration, and optimizes the design for you.

Figure 1 is an example of how designing in PSoC Creator facilitates software/ hardware codesign without requiring software engineers to become hardware experts. Being a mixed-signal device, PSoC includes integrated digital-to-analog converters (DACs) and these can be used to output a voltage (or current) to a pin or somewhere else on the device. You can connect a DAC to a pin by dragging and dropping two the components onto a sheet, called a schematic, and wiring them together. It takes just a few seconds to locate the components and copy them into the schematic.

Notice that there are no “inputs” to the DAC—no power line, no Vref input, no scary bus interface—just a single volt-

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DAC VDAC8

VDAC

0[3]

P0_3

Figure 1 Connecting a DAC output to an analog pin with PSoC Creator.

age source that is wired to a pin. And the pin is equally simple too. In reality, PSoC pins can support a dizzying combination of GPIO, SIO and analog functionality with various drive modes, plus enable and synchronization features. But the analog pin we used here has already configured the physical pin just the way you need it,

so you don’t need to be concerned with how to safely turn those features off without impacting the signal from the DAC.

High Level Design Is the Key

This idea of isolating designers from potentially confusing low-level implementation details so they can focus on func-

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keep forcing the design work onto the user?

Design choices should be presented as options, not obstacles. Silicon-centric design methodologies are simply too low level and engineers do not have time to keep doing it. Programmable SoC users need to design at a higher level than traditional tools allow. In PSoC Creator, you lay out the functionality you need logically and let the tool translate that into the specific device configuration. You set up peripheral behavior via straightforward parameters.

UART UART P6_6

tx

rx

6[6]

6[0]

tx_interrupt rx_interrupt 0

reset

Figure 2 Configuring a UART component. Notice that the options relate to the function, not the implementation of the peripheral.

Figure 3 The PSoC Creator IDE showing the Workspace Explorer (left), schematic editor (center) and the Component Catalog (right). These are all views that are used by the engineer to develop the application.

tionality is central to the PSoC Creator approach. The tool ships with a fully validated suite of nearly 200 components— things like analog-to-digital converters (ADC), DAC and amplifiers; UART and I2C, PWMs and timers—which are much easier to use than the raw IP blocks found in traditional schematic capture tools. In components, the implementation details are abstracted away and designs are errorfree the first time. You choose functionality in a parameter editor (called a customizer dialog) and the tool determines the device configuration needed to achieve your requirements. All you need to do is drop the component onto the page and

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double-click to make your selections in the customizer.

Consider a UART as shown in Figure 2. This is typically a firmware-oriented component and so the customizer presents the configuration options in a way that is natural to engineers working in this discipline. You are not asked for a clock input and over-sampling rate. You are just asked what baud rate you want to use and the tool automatically creates a clock source that will supply the appropriate frequency to the component.

Why don’t all tools work this way? As the manufacturers of the device, we already know how to solve those problems. So why

An Integrated Tool for Both Hardware and Software Engineers

Programmable devices with integrated CPUs need to be supported by tools that also integrate the hardware and software development tasks. Another legacy of silicon-centric tools is that the software engineers are typically forced to use tools they do not particularly like and have to deal with raw memory and register-level interfaces to the peripherals.

In other words, without the right software tools, a programmable SoC empowers the hardware designer to the detriment of the software team. The hardware schedule is greatly accelerated and risk is minimized, especially when compared to an ASIC flow, but the burden of getting things to work is really just being pushed onto the software development team.

In Figure 3, the tool also frees engineers from having to develop their own interfaces to the SoC functionality and gives them a choice of integrated development environments (IDE) for application development. Almost all components have a software interface that makes it easy to drive the peripherals from C code.

The exceptions are low-level components like LUTs, logic gates and multiplexers.

Rather than presenting a set of memorymapped registers with esoteric bit fields and often undocumented side-effects, components bundle the typical functionality into C-language API calls.

To start a timer running you call an API like Timer_1_Start(). (You’ll never guess how to stop it.) Reading the current value of the timer is achieved by using the return value from Timer_1_ReadCounter().

Once you get used to the style of the APIs, you can often guess the API names for a

technology in context

component that you have never used. If you don’t guess right, a complete datasheet is always available from the customizer dialog or by right-clicking on the component.

You may have noticed the “_1_” in the API example above. It’s a clue to how the APIs are generated in the tool. Every component you drag (or copy-paste) into a design is given a unique name. The name defaults to the component base name, e.g.

“UART”, with “_n” appended to distinguish multiple instances of the same component. You can change this name from the customizer dialog if you wish. In the example above, I removed the underscore part because there is only one UART in the project, making the number superfluous. When you press the build button, or the F6 key, the tool generates API files for all the components in the schematic. The component instance name is always prepended to the generated API. Once the hardware design is complete, the built-in debugger supports firmware development. You connect to the target device via the usual JTAG or SWD interfaces. Cypress development kits include an onboard debug chip—another PSoC of course—that replaces the traditional debugger probe. You just connect a USB cable and start debugging. For your own hardware you can purchase an inexpensive MiniProg3 debugger probe that connects to a standard 10-pin header. Figure 4 is an example of the PSoC Creator debugger environment.

Design Documentation Is Key to a Successful Project

All of the component APIs are provided as source code in C. This makes debugging the software-hardware interaction very simple. There are no libraries to include in the build and you do not need to go hunting through web pages to find device drivers that always seem to be for another device anyway. There are no restrictions on where you place breakpoints or what code you can step through while debugging. You rarely need to switch to an assembler view when troubleshooting a component’s behavior.

Cypress recognizes that not every software engineer wants, or is able, to switch to the PSoC Creator environment.

Independent vendors of software IDEs for

Figure 4 The ARM µVision IDE debugging a PSoC project.

embedded development have been perfecting their tools for years, and they provide many high-end features that accelerate the design cycle, reduce risk and increase test coverage. Great examples of these tools are the Microcontroller Development Kit (MDK) from ARM Ltd. and the Embedded Workbench tool from IAR Systems.

These days, development is often split into hardware and software teams.

The software group is not always located in the same building (or country) as their colleagues, and they certainly do not want to have their tools selection dictated by the hardware team. This is not just a personal preference issue. Companies have invested significant time and money into these tools, debug solutions, maintenance contracts and so on. They are very well established parts of the engineering development flow with high levels of integration into company systems like source control and documentation management.

Switching to a new software development environment is often impractical.

A better approach in these environments is to consider PSoC Creator as a chip configuration tool, rather than a replacement IDE. The hardware engineers can use the tool to generate the design and generate all the configuration data and APIs. The software team merely integrates these files into their IDE of choice and follows a familiar edit-build-debug cycle. The hardware team is free to use PSoC Creator

to build test benches for their designs and the boards on which they are used. You can even create board support packages (BSP) or hardware abstraction layers (HAL) to share with the software team, which makes their interaction with the device as easy and error-free as possible. It is entirely up to you how much software you want to include in the chip configuration.

The process of handing over a new board to the software engineers is infamously problematic. It has to happen, but no step in the whole product development is likely to generate more miscommunication and frustration. We have all heard, or been part of, the “it’s the hardware” and “no, it’s the software” arguments in our time. The root cause of this divergence of opinion is often misunderstanding about how the hardware should be used. To alleviate this problem, PSoC Creator includes a function to generate a datasheet for the PSoC design. The device configuration information, clock setup, pin selections and descriptions of all the generated component APIs can be output into a single datasheet file, straight from the tool.

There is no risk of a cut-paste error or a forgotten piece of information because the document is machine-generated.

Cypress Semiconductor San Jose, CA. (408) 943 2600. [www.cypress.com].

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Technology in

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Devices Integrate CPUs with FPGAs

How Fast Can You Design an Embedded System with SoC FPGAs? Recently developed System-on-Chip (SoC) FPGAs featuring on-chip MCUs and associated embedded peripherals provide an impressive set of hardware resources with which to construct embedded systems.

by Wendy Lockhart, Micosemi

A

new generation of devices integrates a popular microprocessor architecture—most popularly an ARM core— with its own extensive dedicated peripherals set, a large FPGA fabric with dedicated SRAM blocks and math blocks, and dedicated external interfaces for high-speed serial and high-speed parallel memory controllers.

SoC FPGA devices with these types of resources have complicated and interdependent design rules and use-models, which must be understood in detail to create a working solution. This requires considerable work by an experienced FPGA designer to construct a system that is capable of being used by the embedded programmer. As new peripheral features are required, the FPGA designer must “spin” the design to provide new features to the embedded programmer.

This dramatically extends the development cycle, and it requires that significant FPGA design resources be applied to the project for the entire development cycle. What’s needed is a design tool with a high level of abstraction that intuitively captures the designer’s intent and then generates correctly formed and connected designs.

Advanced Design Tool Requirements

The designer needs the ability to quickly and easily define the desired embedded components and their intercon-

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nections. A visual, high-level abstraction for system construction that generates a “correct by construction” implementation will dramatically simplify the designer’s experience and accelerate time-to-market. Using these tools, a traditional embedded system designer (one with little FPGA hardware design experience) would be able to construct a complete SoC-based embedded-system hardware platform using familiar embedded peripherals. These peripherals could be implemented in fixed function MCU blocks or in the FPGA fabric (using a library of predefined FPGA-based IT building blocks). Once the system is thus defined, embedded code can be rapidly developed.

An experienced FPGA designer would be required only when specialized functions, not already available from the FPGA library, need to be added to the embedded system. Microsemi supports these requirements with the System Builder GUI capability within the Libero SoC tool suite for Microsemi SmartFusion2 SoC FPGAs. As an example, let’s review the hardware capabilities of the SmartFusion2 SoC FPGAs, then we will explore the resulting requirements that drive the preferred development flow.

The SmartFusion2 SoC FPGA is a mix of hard IP blocks and FPGA fabric

on a single die. The key elements include: the Microcontroller Subsystem or MSS, the FPGA fabric, the dedicated external interfaces—high-speed serial and highspeed parallel memory, and the clock control elements (Figure 1).

The MSS includes a high-speed ARM Cortex-M3 MCU with: an instruction cache, eNVM program memory and eSRAM data memory, along with familiar peripherals like SPI, UART, I2C, CAN, WDT, RTC, USB, external DDR memory controller and Triple Speed Ethernet (TSE) blocks.

The MSS also has multiple interfaces to the FPGA to allow for peripheral expansion and algorithm acceleration via custom peripherals and coprocessing blocks within the FPGA fabric. A high-speed external DDR interface is available to provide off-chip data for the FPGA-based processing tasks.

High-speed serial interfaces, with up to 165 Gbit/s SERDES, also connect to the FPGA fabric and can operate in PCIe, XAUI/XGXS or native SERDES modes. Finally, the clock control blocks include the System Clock, PLL, on-chip RC oscillators and the external crystal oscillator. Separate clock domains are available for the MSS, MDDR, MSS APB, fabric interface and the fabric DDR to simplify clock distribution.

technology in context

JTAG I/O

SPI I/O

Multi-Standard User I/O (MISO)

SPI x 2 MMUART x 2 I 2C x 2 Timer x 2

System Controller AES256 SHA256 ECC

NRBG

Flash*Freeze

SRAM-PUF

CAN

In-Application Programming

WDT

DDR User I/O

APB

PCMA

RTC

Multi-Standard User I/O (MISO)

Interrupts

Micro SRAM (64x18)

FIC_1

DDR Bridge

eNVM

MSS DDR Controller + PHY

Serial 0 I/O

eSRAM

Large SRAM (1024x18)

Config

OSCs

TSE MAC

SMC_FIC

Config

AXI/AHB

Math Block MACC (18x18)

Math Block MACC (18x18)

AXI/AHB/XGXS

Serial Controller 1 (PCIe, XAUI/XGXS) + Native SERDES

HPDMA

AHB

Large SRAM (1024x18)

AXI/AHB/XGXS

Serial Controller 0 (PCIe, XAUI/XGXS) + Native SERDES

FIC_0

AHB AHB

Micro SRAM (64x18)

Config

SYSREG

Multi-Standard User I/O (MISO)

COMM_BLK

FPGA Fabric

HS USB OTG ULPI

Instruction Cache

AHB Bus Matrix (ABM)

FBC

Smart Fusion 2

D I S

ARM Cortex-M3 MPU ETM

Microcontroller Subsystem (MSS)

Config

PLLs

Serial 1 I/O

AXI/AHB

Fabric DDR Controller + PHY

Standard C+1/ SEU Immune Flash Based/ SEU Immune

DDR User I/O

Figure 1 SmartFusion2 Architectural Block Diagram.

SoC FPGA Embedded Development Key Features

To construct an easy to use embedded system development tool flow—one with which even an MCU proficient but inexperienced FPGA designer would be comfortable—a few key features need to be present. Supporting guided development of known good MCU subsystems is perhaps the single most important capability required of the front-end development process. Let’s look at how the System Builder wizard implements this key feature.

To simplify the development of a target SoC FPGA architecture (includ-

ing MCU, peripherals, memory interfaces, drives, peripherals/coprocessors designed with FPGA fabric, etc.), the System Builder wizard walks the architect through the steps of defining the elements of the target system. The steps are organized by function, and only the features available, based on previous selections, are presented as selections to the user.

This dramatically simplifies the process and creates a virtually error-free development environment. Two examples of System Builder GUI screens are shown in Figure 2.

Some sample categories and example selections that can be used within

the System Builder GUI are listed below.

Note that selection options are based on previous selections—thus this is a “guided” approach: Key Device Options: Select which memory features will be included in the design—MSS DDR, fabric DDR, highspeed serial interfaces and flash memory storage clients.

Memory Options: Define the characteristics of the previously selected memory elements. For example, specify the type of standard (DDR2, DDR3, LPDDR), the initialization time and the configuration options.

Peripheral Options: Define the charRTC MAGAZINE JULY 2013

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technology in context

Figure 2 System Builder GUI Example Screens.

Libero SoC System Builder Firmware and Project Settings

RTL and Constraints

FPGA Implementation

Application Development

consistent hardware interfaces, common driver structures and compatible software interfaces. The elimination of the requirement for an FPGA designer to “stitch together” inconsistent interfaces “by hand” dramatically reduces errors and the need for low-level verification and testing that can further extend development time. The System Builder wizard also automatically includes proven example designs that show how to use the generated blocks to further speed development. In many cases, the example designs require only minimal changes to create application ready code.

Parallel FPGA and Application Development

Program Device Figure 3 Libero SoC Development Flow.

acteristics of the available peripherals based on previous selections. Selections are grouped by MSS master, MSS peripherals, fabric slave and fabric master within which specific peripheral characteristics are selected.

MCU Options: Define the characteristics for microcontroller options, such as the Cortex-M3 processor, cache controller, AHB bus matrix, watchdog

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timer, real-time counter and peripheral DMA controller.

Once all the configuration options have been defined, the System Builder wizard creates a complete base system with IP blocks, associated device drivers and even includes relevant, proven example code blocks, all correct by construction. This is possible because all the configurable IP blocks have

Once the System Builder wizard has been run, the rest of the design flow is supported via the Libero tool flow (Figure 3) using familiar tools with no additional learning curve for both the FPGA implementation and MCU application development. RTL and constraints are made available for the FPGA implementation “leg” of the development process, while firmware and project settings are made available so embedded application development can progress. Each effort can progress independently, and when necessary, FPGA developed peripherals or acceleration coprocessors can be easily imported into the embedded platform. For

technology in context

Customer Secret Sauce

Application Layer

TCP/IP, HTTP, SMTP, DHCP, LCD

Middleware

Microsemi CMSIS-based HAL Microsemi SmartFusion2

eNVM Driver

OS/RTOS

Timer Driver

Ethernet Driver

USB Driver

CAN Driver

UART Driver

SPI Driver

μC/OS-III, uClinux, RTX, FreeRTOS

I22C Driver

example, the software developer might identify an “inner loop” function that might be more efficiently implemented in the FPGA fabric. The FPGA designer can construct the function in the FPGA and then the programmer can use this coprocessing hardware to replace the code, dramatically improving the speed of the inner loop function.

For the FPGA designer, the Libero SoC integrates synthesis, debug and DSP support from Synopsys, and simulation from Mentor Graphics with power analysis, timing analysis and push button design flow.

Using the Libero tool suite, embedded code development can be done via a familiar IDE, making code development even more efficient. For example, Libero SoC allows the designer to use the Keil Microcontroller Development Kit (MDK) or the IAR Embedded Workbench IDE. Because the SmartFusion2 SoC uses an ARM Cortex-M3 processor core and many standard ARM peripherals, previous development efforts can easily be leveraged to further speed the development cycle. Microsemi also supplies an Eclipse-based IDE, SoftConsole, with a GNU C/C++ compiler and GDB debugger.

The SmartFusion2 development environment includes higher-level software elements to make it easy for application developers to immediately use the underlying software layers. Figure 4 shows the software stack for a typical design and illustrates how various elements fit into the software hierarchy. The bottom layer is the actual hardware associated with the device and includes all the hardware components of the system. The next layer up is the Hardware Abstract Layer (HAL), which is based on the ARM Cortex Microcontroller Software Interface Standard (CMSIS). Each of the peripherals has its own driver, whether it is hard IP or soft IP added in the FPGA fabric.

Above the drivers is a real-time operating system (RTOS) with protocol Guided Development and the System Builder GUI stacks and interfaces provided by third-party vendors. At the top layer, the designer can add their own “secret sauce” or custom applications involving

Drivers

Hardware Abstraction Layer Hardware Platform

Figure 4 Typical Software Stack for SmartFusion2-based Embedded Designs.

all or none of the layers below. The use of an ARM processor allows designers to benefit from the extensive ARM ecosystem, established HAL and drivers. This also allows third-party vendors to easily port RTOS and middleware for SmartFusion2 devices.

All device drivers and peripheral initialization are auto-generated and correct by construction via the System Builder GUI selections. Devices are programmed and debugged via the Flashpro 4 programmer.

Because the System Builder GUI automatically provides drivers for SmartFusion2 peripherals, software development can focus on the differentiated features required by the target market. For example, an application developer can take the System Builder GUI output and immediately integrate an OS/RTOS along with the associated Middleware for a TCP/IP stack. Within minutes the design can be compiled, programmed and run so that it can exchange messages over an Ethernet network. This is a dramatic improvement over previous design flows where days and weeks of development, testing and debugging were required to get all the elements of the hardware and software working to-

gether to create a simple working Ethernet-enabled design.

The advanced capabilities of SoC FPGAs require accompanying advances in the tool flow for designers to reap the enormous benefits of using these devices. A high-level system constructor, like the System Builder GUI, uses a guided design approach to quickly create a, correct by construction, base system that encapsulates everything needed so that the development tasks of coding for the embedded MCU and coding for the FPGA fabric can be done independently.

Additionally, by incorporating all the key software elements (the hardware abstraction layer, drivers and even example code) into the base system, MCU application development can begin immediately, without the multitude of preliminary time-consuming steps required in less integrated flows. This significantly reduces the potential for false steps and development backtracking that previously plagued complex SoC designs.

Microsemi Aliso Viejo, CA. (949) 380-6100. [www.microsemi.com].

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Technology

connected Optical Interconnects: Keeping Up with Data Speed

VPX at Light Speed—Optical Brings 100 Gigabits to Backplane Architectures A new generation of connectors and interfaces is taking its place in the world of VPX to handle the growing demands of data transfer between cards and systems.

by Michael Munroe, Elma Bustronic

W

ith the emergence of backplane data communication at PCI Express (PCIe) Gen3 and 10/40 Gigabit Ethernet (GbE) speeds, it’s becoming more and more likely that backplane I/O will require support at similar bandwidths. Certainly chassis-to-chassis connections will need to be accomplished at the same bandwidth, and because copper cables of useful lengths are not practical above 3 Gbit/s, applications will be turning increasingly to optical cables for high-speed external data connections.

The need for high-speed I/O is not directly related to the communication from slot to slot within a backplane. Also, it is reasonable to point out that individual sensors do not yet have bandwidth requirements in the 8 to 10 Gbit/s range. What will drive the need for optical I/O will be arrays of sensors with local analog to digital conversion. In addition, this need will also be driven by the bandwidth requirements for attached storage and chassis-tochassis communication.

VPX is the first embedded backplane architecture specifically designed to allow optical I/O through the backplane.

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Figure 1 A typical rigid-flex-rigid ATR I/O Assembly used for I/O in an ATR enclosure.

The optical backplane connector is defined within ANSI-VITA 66.0 66.1 and 66.3. The VITA 66 base standard defines a suitable family of optical interconnects for use on VITA 46.0 plug-in modules and backplanes, with VITA 66.1 identifying the mechanical transfer (MT) style contact variant and VITA 66.3, the Mini Expanded Beam contact variant.

The VPX backplane’s optical I/O is capable of serving several different purposes such as card-to-card data connections, chassis-to-chassis data connections and I/O connectivity to sensors and sensor arrays. Until now, most signaling within and between backplanes was at speeds that could always be supported by copper cabling.

technology connected

Figure 2

(a)

(b)

(c)

Left to Right - MPO cable end (a), VITA 66.1 BP module (b) and proposed 3U VITA 66.4 module (c).

Cables from the Front Panel

One of the most popular optical interfaces today is the QSFP+, originally developed by the SFF committee that addresses storage industry needs. This interface supports a pluggable module inserted in a standard socket or cage that can be either an active optical cable or a copper cable.

QSFP+ active optical cables are in accordance with SFF-8436, which defines the QSFP+’s electrical (copper), optical and mechanical characteristics and are readily available from such suppliers as 3M, Amphenol, Finisar, Mellanox, Molex, Samtec and TE. The cables support 10 GbE as well as InfiniBand FDR and QDR, which are 14 Gbit/s and 28 Gbit/s, respectively. Each cable consists of two electrical-to-optical transponders that plug into a QSFP cage connected by optical fibers.

Similar active optical cables are available to support proprietary PCIe Gen3 solutions. The interfaces to these cables are almost exclusively on the front panel or the edge of integrated motherboards.

The locations of these interfaces were initially chosen to best serve the connection requirements common in the networking, telecom and storage industries.

Because cable PCIe is already an important feature of PCIe systems, the industry will be watching to see how PCIe cable I/O is accomplished for Gen3 speeds. At the present time, the PCI-SIG technical committee is making a decision regarding the format of a standard Gen3 optical connector.

This copper or optical interconnect will be called OCuLink, supporting 8 Giga transfers/second (GT/s) and

faster connection speeds. Although the mechanical implementation is still being decided, the electrical requirements have been established. There will be a strong bias toward an affordable interconnect, such as QSFP+, to ensure a successful PCI Express Gen3 optical interface.

No Place for Front Panel I/O

For most 19� rackmount installations, the front rack panel has long been an acceptable surface for optical interfaces.

However, this is not the case for typical industrial or military enclosures, such as Air Transport Rack (ATR) boxes per ARINC 404. These units always have provisions for front covers and any I/O is usually accommodated by a combination of MIL-C-38999 or other similar sealed cable end connectors arranged as bulkhead mounted I/O panels.

Backplane I/O can reach the bulkhead I/O panel in a number of ways, however. It can be cabled from separable cable connectors on the backplane. It can be routed through a riser board installed like a plug-in card, but at the very edge of the backplane. Or a rigid PCB supporting the bulkhead connectors can be connected with an integral, flexible PCB section that is part of the backplane, as well.

This rigid-flex-rigid method is favored because it is reliable, takes less labor to install and can handle a wide variety of signals. The optical fibers need to exit behind the backplane and terminate at the same bulkhead location as the circular electrical connectors (Figure 1).

Although rear panel optical I/O connectors are almost a necessity for ATRstyle enclosures with front covers, this

same arrangement could also simplify cabling for conventional installations.

Backplane optical I/O could help control the tangle of front panel cables that make replacing front cards more timeconsuming. Backplane-mounted connectors are also likely to be more reliable because there are no cables to flex when installing a card and no cable connectors to be handled.

MT Optical Ribbons to the Rescue

In contrast to the QSFP+ active optical cables, the VITA 66.1 solution moves the optical transducer onto the plug-in card or onto an XMC or FMC mezzanine module carried by a VPX plug-in card. VITA 66.1 defines the MT variant for backplane optical connections on 6U VPX cards. VITA 66.4 will define the same thing for 3U VPX cards when it is completed.

A fiber ribbon attaches directly to the optical transducer, but terminates in an MT ferrule positioned on the rear card edge, typically in the P6 position.

This arrangement moves the optical interface to the backplane and allows for inexpensive passive fiber ribbons rather than active optical cable assemblies. The VITA 66.1 module is the same size as the MultiGig module that populates the standard 6U VPX card edge positions P1 thru P5. This P6 VITA 66.1 module holds two MT ferrule assemblies that can contain between 8 and 24 optical fibers each (Figure 2).

With the optical transducer located on the card or a mezzanine, all that is needed to connect to the outside world is a passive optical ribbon terminated with an MT (MPO or MTO) ferrule on each end.

RTC MAGAZINE JULY 2013

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technology connected

Untangling the Standards Standard

Subject

Organization/Description

URL

FOCIS-5

MTP/MPO

Fiber Optic Connector Intermateability Standard

www.thefoa.org

EIA/TIA 604-5

MTP/MPO

Fiber Optic Connector Intermateability Standard

www.eciaonline.org

IEC 61754-7

MPO/MTP

IEC: Fiber Optic Connector Interface–Type MPO

www.iec.ch

IEC 61754-18

MT-RJ

IEC: Mechanical Transfer Registered Jack or Media TerminationRecommended Jack

www.iec.ch

PCI SIG OCuLink

Gen3 Cable

PCI Express OCuLink Express Specification

www.pcisig.com

SFF-8436

QSFP+ 10 Gb/s

QSFP+ 10 Gb/s 4X Pluggable Transceiver-Expired

ftp.seagate.com/sff

SFF-8665

QSFP+ 28 Gb/s

QSFP+ 28 Gb/s 4X Pluggable Transceiver

ftp.seagate.com/sff

ANSI-VITA 66.0

Base Standard

VSO: Optical Interconnect on VPX Standard

www.vita.com

ANSI-VITA 66.1

MT on 6U VPX

VSO: Optical Interconnect on 6U VPX–MT Variant

www.vita.com

VITA 66.4

MT on 6U VPX

Optical Interconnect on 3U VPX–MT (not released)

www.vita.com

ANSI-VITA 65

VPX Base Standard

VSO: OpenVPX System Specification

www.vita.com

PICMG CPCI-S.O

cPCI Serial

CompactPCI Serial

www.picmg.org

PICMG EXP0 R2

cPCI Express

CompactPCI Express

www.picmg.org

PICMG 3.0

AdvancedTCA

AdvancedTCA Base Standard

www.picmg.org

PICMG 3.1 R2

10 G Ethernet

Ethernet/Fibre Channel for AdvancedTCA Systems

www.picmg.org

ATR

ARINC 404A

Air Transport Equipment Cases and Racking

www.arinc.com

EIA 310D

19” Racks

Cabinets, Racks, Panels and Associated Equipment

www.eciaonline.org

ETSI 300 119-2

Racks, Cabinets

Equipment Engineering–European Telecom Standard for Equipment Practice

www.etsi.org

IEC 297-2

Cabinets, Racks

Dimensions of Mechanical Structures of the 482.6 mm (19”) Series – Part 2 Cabinets

www.iec.ch

TABLE 1 Untangling the Standards.

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technology connected

One end of the passive optical cable plugs into the VITA 66.1 backplane module and the other end typically plugs into a MILC-38999 MT housing on the bulkhead of an ATR enclosure.

A similar passive cable would then connect to the same MIL-C-38999 from the outside and extend from one or two meters up to 1,000 meters to another device equipped with an MT interface. Although VITA 66 defines MT ferrules with up to 24 fibers, MT ferrules are available today that support 72 fibers arranged in six VITA 66-compatible ribbons.

160 -0,3 Center Line of Row A

7,5 ±0,1 175,45 +1

VITA 66 Everywhere

There is one little noted aspect of the VITA 66 family of backplane mounted optical connectors. Because the VPX form factor conforms to an Enhanced Eurocard Standard (IEEE 1101.10) backplane and daughter card design and an IEEE 1101.11 rear transition module (RTM) design, any backplane connector developed for VPX can potentially be utilized in other Eurocard-based designs.

With PCIe Gen3 being targeted by both CompactPCI Serial and CompactPCI Express R2, the VITA 66.1 optical backplane connector is a potentially viable optical I/O in those architectures, as well. The VITA 66.1 module could also be used within the AdvancedTCA architecture. Although ATCA utilizes a unique mechanical form factor, the engagement and seating dimensions of the backplane connector are the same as the IEC 610764-101 and IEC 61076-4-113 connector families, which are used with IEEE 1101.10 Enhanced Eurocard architectures.

VITA 66.1 and 66.3 solutions could potentially find themselves in Zone 3 ATCA-based applications as well, since this user-defined area can hold a special backplane to interconnect boards with signals not defined in ATCA. This could be particularly inviting as PICMG 3.1 R2 brings ATCA applications firmly into the 40 GBase-KR4 world (Figure 3).

100 GbE Demands Optical

At the time of the writing of this article, IEEE 802.3bj is in negative ballot resolution; the first working group ballot having been successful.

M

Front Panel

Daughter card pcb

Backplane

Connector/Backplane System IEC 61076-4-101 2mm CompactPCI IEC 61076-4-113 VME64x (like VPX) PICMG 3.0 and 3.1R2 (ZD connector)

“M” 12.5mm 12.4mm 12.5mm

Figure 3 Edge of daughter card to backplane: The similarity between the mounting space for VPX, CompactPCI Serial and AdvancedTCA enables possible use of VITA 66 connectors across different platforms.

This Ethernet standard, the latest IEEE 802.3 standard, will define 100 GbE comprised of four 25 Gbit/s channels.

It is well on its way to a November 2013 sponsor ballot and a second quarter 2014 release.

It is a sobering thought to consider how much work will be required to implement 25 Gbit/s channels on a backplane.

With silicon available, however, there is no doubt that our industry will rise to the challenge. One thing is quite certain: I/O at this data rate will not be accomplished in copper cable.

For those who will try to predict when trans-backplane optical I/O will first appear in deployed systems, you might want to watch the defense industry. The requirement for enclosed systems with front covers will drive optical I/O to the backplane. VITA 66.1 is likely to be the vehicle.

When ANSI-VITA 66.1 becomes a familiar solution within VPX, we will probably see it next in AdvancedTCA applications, followed by ATCA extensions. CompactPCI Express and PXI

Express may then follow with CompactPCI Serial as well. After that, we may begin to see commercial 19” rackbased systems implement rear optical.

VITA 66.1 may eventually be used to implement slot-to-slot optical backplane connections.

The data processing demands made on backplanes will continue to increase, making it impossible for standard copper I/O interfaces to keep pace with these evolving requirements. Fortunately, VPX has made provisions for a backplane interface that supports backplane optical I/O, and can potentially be used in other technology platforms as well. This will serve as a great asset in system design requiring high-speed data communications. Table 1 presents links to details on the various standards and specifications mentioned in this article and beyond.

Elma Bustronic Fremont, CA. (510) 490-7388. [www.bustronic.com].

RTC MAGAZINE JULY 2013

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technology in

systems

Fleet Management and Transportation

Development of an M2M Ecosystem Benefits Fleet and Transportation Management: What Do Fish Have to Do with It? M2M systems for managing individual fleets of vehicles may be just the beginning. Expanding the concept and ecosystem to include connectivity to other vehicles, signals, road condition data, law enforcement and more may herald a transformation of the way we think of transportation.

by William Andrew Albano, Lilee Systems

H

ave you ever seen a photograph or video of a large, densely packed school of fish swimming as if they were a single organism? You probably have. You don’t have to go far to experience something of this nature in real life. You’ve probably even experienced something like it while driving a car on a busy highway when suddenly there is a significant bottleneck of cars that slows vehicles to a crawl.

Then, just as suddenly, the bottleneck of cars is off again at full speed as the congestion mysteriously disappears. A fully developed M2M communication ecosystem for transportation will allow vehicles to operate as a single, super-efficient organism.

The chief concerns for operators of fleets and their fleet managers for fleet management systems are: increasing efficiency, lowering costs, improving driver safety and ultimately increasing revenues. The solutions that fleet management systems can deliver through telematics (enabled by a complete end-to-end M2M communication system) to address these concerns ultimately cannot be limited to your fleet alone. The connected

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Application / Service Connectivity Device Access Figure 1 Basic layers for a complete endto-end M2M communication system architecture.

vehicle operating within a smart transportation ecosystem fully interconnected with the larger Internet of Things (IoT) promises to fully realize these concerns.

This large ecosystem will be enabled by a variety of technologies employed at the three basic layers of many interconnected networks of end-to-end M2M communication systems. Figure 1 illustrates a general architecture for a complete M2M communication system architecture. The Connectivity layer consists of network

infrastructure, wireless providers and network gateways that bridge the gap between the device and connectivity layers.

The application or service layer delivers the fleet or transportation services to endusers and also provides management of devices on board vehicles. The application layer provides APIs for the development of further services that can be used by both fleet managers and vehicle personnel, and by third-party entities like insurance companies, government compliance agencies, public safety authorities, or transportation departments. The device or access layer for fleet management and transportation systems includes in-vehicle sensors, GPS receivers and other technologies.

Fleet and Transportation Management at the Application Layer

The interoperability of complete endto-end M2M communication systems will be a significant challenge for the future connected fleet and transportation ecosystem. At the application level, either

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Hi-Speed USB 2.0, USB bus powered 24-bit Sigma-Delta ADC, built-in antialiasing filter 4-CH simultaneous sampling analog input, up to 128kS/s AC or DC input coupling, software selectable Analog or digital triggering 2mA excitation output on each analog input channel for IEPE sensor measurement Full auto-calibration Ready-to-use testing application (U-Test) provided E-mail: info@adlinktech.com Web: www.adlinktech.com

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USB 2.0 hot swappable interface Compatible with USB1.1 and USB2.0 host controllers Up to 300Mbps receive and 150Mbps transmit rate using 40MHz bandwidth Up to 150Mbps receive and 75Mbps transmit rate using 20MHz bandwidth 1 x 2 MIMO technology for exceptional reception and throughput 2 U.FL TX/RX antenna ports Wi-Fi security using WEP, WPA and WPA2 Compact size: 1.0” x 1.0” x 0.25” (Modules) Windows 2K, XP, Vista, Win7 support Linux 2.4/2.6 support

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Tech In Systems

Figure 2 Lilee Systems LMC-5500 mobility controller and relay messaging server.

Fleet and Transportation Management at the Connectivity Layer

Figure 3 Interoperability via ICTM and Federated Interchange at the Application Layer.

located in the fleet back office, central control, or service provider data center, the crucial technology is the system managing mobility of fleet vehicles and other fielded assets. In addition, in the case of service providers and transit/transportation authorities, controllers might also be responsible for translating data from one authority or another to achieve interoperability of systems. Through this translation a variety of service providers, transit authorities, public safety and large enterprise fleets share critical information that can affect the efficiency and safety of the whole ecosystem of connected vehicles and infrastructure.

One example of a solution is that proposed for interoperability of train control communications by the Interoperable Train Control Committee (ITC) as part of the Positive Train Control (PTC) requirements. A solution based on these

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JULY 2013 RTC MAGAZINE

Multiple LMC-5500s are linked to complete the solution. Figure 3 illustrates the basic system architecture from the view of a single railroad. One unit functions as mobility controller to provide radio device management with roaming control for locomotive radios and enables a conduit from the trackside network of base station and wayside station radios to the back office servers for a single railroad or transit authority. A second LMC-5500 takes on the role of ITCM server to provide a translator for interoperability with the networks operated by other railroads and commuter transit operators sharing the same tracks. Additional such devices can be employed for failover and backup redundancy to the LMCs deployed as mobility controller and ITCM server.

A similar concept could be devised for coordinating the communications between the varied interested entities to construct a future connected vehicle ecosystem consisting of fleet operators, service providers, transportation authorities and traffic infrastructure, public safety agencies and the driving public at large.

proposals provides interoperable train control systems to help freight railroads and transit operators share missioncritical rail communications and control information. Specifically engineered software and hardware platforms form a robust, integrated solution to provide interoperable train control communications. This Interoperable Train Control Messaging (ITCM)-based solution serves as a translator for the PTC solution by taking the appropriate information gathered and managed by a controller, such as the Lilee Systems LMC-5500 mobility controller (Figure 2), from the onboard and trackside systems from one rail entity and relaying it via the Federated Interchange links using ITCM messaging protocols to the other interested rail entity involved with the stretch of track where the train is currently or is about to be.

Fleet and transportation management system providers face the challenge of reliably transferring data to and from both mobile and fixed assets to data and control centers while at the same time giving the systems control over the devices. Network connectivity gateways can play a vital role in solving these challenges. Roadside communications gateways provide sophisticated communications management applications to dynamically select multiple communication paths (3G/4G, Wi-Fi, or other RF radios operating in both licensed and license-free spectrum) to provide reliable links between mobile assets and central control. These gateways also enable remote management and control of mobile and fixed assets via technologies like IP-based keyboard-video-mouse (KVM).

Furthermore, on-vehicle gateways can be designed to bind 3G/4G services from multiple carriers to enable high-bandwidth links for value-added services like passenger connectivity on public transit. For example, the Lilee Systems WMS-2000 se-

tech in systems

ries of gateway messaging servers enables gateway connectivity in both roadside and on-vehicle deployments (Figure 4).

Fleet and Transportation Management at the Device Layer

Another approach that could be used in tandem with coordinated communications at the application layer would employ the power of ad hoc mesh networking at the device or access layer to connect vehicles within range of other vehicles, as well as roadside and traffic infrastructure like bridges, overpasses, traffic lights and intersections. Figure 5 illustrates an example of an ad hoc mesh network between vehicles and road infrastructure. A dynamically constructed self-forming and self-healing mesh network could enable all connected transportation stakeholders to achieve their goals for increased efficiency and safety. Interoperability is still an important issue even at the device layer. Fortunately open standards, such as those from IEEE 802.11 to 802.15, and some industry specific ones like ETSI, provide the necessary engineering toolkit.

Inter-vehicle mesh networks will enable cars to traverse highways stretches in superefficient caravans of vehicles and vastly increase the efficiency of transit and utilization of resources within cities. Besides communications between the cars within schools, vehicle mesh networks will also communicate with transportation infrastructure like bridges, overpasses, traffic lights, and road crews engaged in road repair or construction.

These in turn will communicate with public safety authorities, departments of roads and transportation, and weather bureaus to check for vital safety, transportation and weather alerts that will affect transit.

On-vehicle mesh radios can also be employed to communicate with other valuable fielded or mobile assets at a job site as in the case of construction, mining, or agriculture. The radios serve to form a network bubble in the vicinity of the vehicle to collect data from on-vehicle sensors, freight and other assets. These on-vehicle networks can also communicate with crew using handheld devices or collect critical data from crew working in hazardous conditions including sensors in the uniforms of first responders that record temperature, radiation and vital

Figure 4 Lilee Systems WMS-2000 gateway messaging server.

Figure 5 Ad Hoc Vehicle and Road Infrastructure Mesh Network.

signs. They can also be used for voice or video data communications between the field and central control or dispatch.

Ad hoc mesh networks in use in an M2M ecosystem for transportation will connect vehicles with roadway and roadside infrastructure to increase the efficiency of the complete system and possibly lead to the development of new models of road use. Virtual toll booths will speed transportation and ensure revenues for road maintenance by use. Roadway use as a pay-as-you-go service might also apply to vehicle licensing and taxes, fuel taxes and alternative energy credits, and insurance. Violations of traffic regulations will also be automatically assessed with fees.

Together these automated processes, when constructively communicated to drivers, can influence driving behavior to produce actionable changes to increase safety, efficiency and resource utiliza-

tion. Ultimately these all reduce costs to fleet operators and individual drivers alike through reduced fuel consumption as well as the optimization of routing and scheduling. Smart transportation, as we move to increased use of alternative energies like electricity to power vehicles, will enhance smart grid operations and utilization. Vehicle data will provide critical data for greater efficiency in smart power and fossil fuel supply chain management.

Data Sharing Brings Value to Fleet Managers, Service Providers and Transportation Authorities

The data shared system-wide from onboard sensors both via the ad hoc mesh networks at the device layer or after being aggregated at the application layer—Big Data—holds valuable information. Data is RTC MAGAZINE JULY 2013

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Tech In Systems

not particularly useful if we don’t know if, when, or how to take action based upon it. The usefulness of data goes beyond the fleet manager, fleet executive and transit operator or transportation department.

When contextualized, the data becomes useful for a whole range of others like drivers, customers, insurance companies…in fact, everyone along the supply chain supporting transportation and freight. The availability of data, even if it

“

is stripped of valuable business or private information, can help to spur development of innovative ways to put it to use.

When analyzed, it will shed light on driving patterns and utilization of particular roads. This will enable departments of transportation and highways to better allocate resources and develop transit infrastructure that most closely reflects the needs of users. For example, sensor data from vehicles operating on a specific patch

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of road will report information about the development of road surface ruptures or potholes. This data will provide key decision-making information for establishing proactive road and infrastructure maintenance to improve the longevity and quality of vital highways and urban roads.

Future Fleet and Transportation Management Systems Enable an Ecosystem

While fleet management telematics and the connected vehicle in general have come a long way in the past decade or so, the most significant changes to come will occur in the next decade. These transformations, enabled by powerful technologies at the application, connectivity and device layers, will fundamentally change the way we commute, transport goods and conduct business via our vital roads and highways.

The constant communication of smart sensors throughout the transportation ecosystem will improve maintenance of vehicles, roads and infrastructure. These communications can increase system-wide efficiencies through automation of processes. Smart sensor proliferation within transportation will spark new innovations, the development of new capabilities, and enable new touch points for engagement between businesses, individual consumers, and public safety and transportation authorities. Network gateway technologies enable the communications of on-vehicle data and control of remote assets, and help to develop new revenue streams through passenger connectivity.

The future for fleet and transportation management systems will be to enable increased efficiency, more engagement and actionable decision making. Benefits of M2M connections in fleet management will only be fully realized when the entire transportation ecosystem adopts M2M, from private vehicles to public transit and road/ traffic infrastructure to all the interconnected services that support transportation or benefit from it. Ultimately, a fully developed ecosystem will enable a driverless one where vehicles become like a school of fish swimming as a single organism.

Lilee Systems Santa Clara, CA. (408) 988-8672. [www.lileesystems.com].

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7/9/13 10:56 AM

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technology in

systems

Fleet Management and Transportation

Functional Safety through CompactPCI in Mass Transit Computing Systems The widely used CompactPCI set of specifications gives system integrators the tools to build the safety-critical systems for today as well as tomorrow.

by Susanne Bornschlegl, MEN Micro

W

ith the ongoing shift from analog technologies to computer-driven operations, functional safety is becoming an increasingly more important element in the design of electronic systems.

Errors or failures in mass transportation can result in loss of life or cause major damage to the environment as well as to property. Each transportation industry segment, from railways and buses to ships and airplanes, has its own safety criteria, typically backed by mandated standards to ensure proper operation and passenger safety.

These safety-critical systems typically fall within two basic modes of error behavior. Fail-safe systems completely turn off in the event of a failure and go into a safe state. For example, a vehicle or a train can be stopped when the control system fails. However, autopilot systems in airplanes require a fail-operational, or fault-tolerant, system that would continue to operate when an error occurs. Managing the operation of a system as well as a cost-effective upgrade path is a key concern of embedded designers tasked with developing safety-critical systems.

A Balancing Act

Regardless of whether a vehicle is operating in the air or on the ground, the

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JULY 2013 RTC MAGAZINE

Up to 600Gb/s

Backward compatability across platforms

1Gb/s PCI 32-bit

2Gb/s PCI 64-bit

1Gb/s PCI 32-bit

10..25Gb/s 4x1 PCI-E

2Gb/s PCI 64-bit

“CompactPCI”

“CompactPCI”

PCMG2.0 (1999)

PCMG2.0 PICMG2.16 (2001)

PCI 32-bit

2xGE

parallel

up to Gen2

PCI 32-bit

2x8 PCI-E up to Gen3

“CompactPCI Plus I/O”

“CompactPCI Serial”

PICMG2.30 (2009)

PICMGxxx (in development)

Up to 4xGE

hybrid

6x4 PCI-E up to Gen3

Up to 10xGE

serial

Figure 1 Backward compatibility: The family of CompactPCI-based specifications forms a strong ecosystem for past and present systems using this robust technology platform.

computer hardware and software inside must work reliably, being at the same time safe and extremely robust. This causes a dilemma for vehicle manufacturers and transportation service providers to remain competitive. They must keep their rolling stock up-to-date in terms of data transmission, ensuring the proper operation of safety-critical systems, while integrating all the latest high-tech conveniences

such as Wi-Fi and up-to-date schedule information that passengers now expect in real time. However, the costs to implement these newer technologies can start to rise past the point where companies can remain profitable.

Passengers typically want all the latest technological conveniences without feeling as though the costs to implement these upgrades have been passed on to

tech in systems

them in fare increases or charges for additional services. The industry needs to keep technology costs low while meeting the expectations of today’s traveler.

Front panel Rear side Onboard connector

Weighing in on Industry Updates

Adding to the benefits noted above, these systems are both robust and based on a mature industry standard, while offering an upgrade path to newer, serialbased systems as data requirements in the mass transportation field continue to increase. In fact, any area where functional safety is an issue, such as automation or medical engineering, can benefit from CompactPCI-based technologies as these systems help lower costs in safety-critical applications as well as provide a reliable, stable architecture.

PICMG, the governing body for the family of CompactPCI specifications, has outlined a road map to accommodate the past, present and future needs of safety-

System Memory DDR2 SDRAM

VGA

CompactPCI Tips the Scales

The modularity and low footprint of 3U CompactPCI commercial off-the-shelf (COTS) boards have proven to be effective in keeping computing costs within reason, while offering advanced technologies that can handle the growing requirements of modern transportation systems.

CompactPCI’s ability to provide a redundant architecture is a key aspect to safety-critical systems. This feature can have various implementations with different goals and behaviors depending on the needed safety level, but in most cases, the critical components of a system use redundancy to fulfill safety requirements.

The interchangeable COTS boards are reasonably priced and easy to maintain. In a 3U CompactPCI system, you can build up a redundant system from two or three identical plug-in CPU cards, connected using network cables. Up to a certain level of application demands, this can be a perfect solution. The multiplied volume, weight and power may still be acceptable.

BIOS Flash

mSATA

PCIe to PCI

I/O Processor (IOP)

USB 2.0

PCI Express (2.5 Gb)

Intel Atom E6xx EG20T PCH

USB 2.0

SATA (3 Gb) USB 2.0 Cluster Link

Status LED Fast Ethernet

CPCI J2

Fast Ethernet

BMC Board Management

FRAM

Fast Ethernet

CPCI J1

PCIe x1 Reset

Supervisor

Inter-Communication FPGA PCIe x1

System Memory DDR2 SDRAM BIOS Flash

PCIe x1

Control Processor 1 (CP1)

Control Processor 2 (CP2)

Intel Atom E6xx

Intel Atom E6xx

Supervisor

System Memory DDR2 SDRAM BIOS Flash

Supervisor Power Control

Figure 2 Newer computing schemes can incorporate up to three processors on a single SBC with extensive front and rear I/O capabilities.

critical systems using this technology platform. It includes three ratified standards that link the old and the new, maximizing existing infrastructures, while offering a cost-effective path to updated technologies that can provide the operational safety requirements and expected passenger conveniences of modern mass transportation systems (Figure 1). The three standards are: • CompactPCI (PICMG 2.0) – existing legacy systems.

• CompactPCI PlusIO (PICMG 2.30) – integrates legacy systems with serial technologies.

• CompactPCI Serial (PICMG CPCIS.0) – new systems using only serial interfaces.

Managing the Data Load

So, mass transportation systems can salvage the infrastructure of legacy CompactPCI-based systems, while upgrading to serial technology as needs and costs allow. CompactPCI PlusIO is a bridge from older systems to CompactPCI Serial ones. It is backward compatible to the initial CompactPCI standard by staying true to most of the original mechanical requirements.

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Figure 3 The MEN F75P: CompactPCI-based designs offer flexible, deterministic layers of operation for safety-critical systems.

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CompactPCI Serial is for new systems being built and uses only the latest serial interfaces, such as PCI Express, SATA/SAS, USB 2.0/3.0 and 10GBASE-T Ethernet wired as full mesh, providing data transfers of up to 12 Gbit/s with less than 3% crosstalk. CompactPCI Serial does not require any switches or bridges in systems with up to nine slots.

With a bridge, up to 21 slots can be implemented in a standard 19� housing.

CompactPCI systems offer definite advantages in safety-critical systems for diagnosis, maintenance and service functions, but are also useful in managing passenger information and for surveillance and security purposes. SBCs in the same system can take over different control jobs and can exchange results, facilitating data management at all levels.

Stable communications: No matter where or why data is being transferred in a system, a reliable network connection is an absolute must to meet the demands of functional safety. As more data is moved within the network, the overhead of mitigating faults and maintaining system upkeep tends to increase, driving costs up. Some

6/26/13 1:17 PM

tech in systems

of the more expensive aspects in a computing system include the wiring and cabling of the components required to handle the increased data. Newer CompactPCI-based designs can take advantage of SBCs with up to three processors on a single board, two redundant control processors and one I/O processor, for exceptional reliability and computing redundancy.

Internal Ethernet connections save on wiring, and extensive rear I/O capabilities can support standardized CompactPCI PlusIO interfacing for fast backplane connections. Several front I/O options provide a solid base of networking, USB and graphics, allowing these flexible designs to implement functional safety (Figure 2).

A typical way to use two control processors on a single SBC for safety-critical computing would be to run the same application logic on each of the processors to detect discrepancies. To implement dissimilarity, you can also execute diverse software on the control processors. The I/O processor can then connect to control elements like sensors. In addition to its core function, this third processor can take over other non-safety-critical tasks, such as control of a fieldbus or graphical output of operational data.

Various levels of safe: Safety-critical systems have different levels of functional safety. While many CPU cards may just power off and restart, newer CompactPCI PlusIO boards can be configured to shut off completely, or restart, depending on the application requirements. This added level of design flexibility is crucial if the system must be “fail-safe” or even “fail-silent,” meaning it needs to go into a safe state where all CPUs are powered off, versus restarting (Figure 3).

Understanding the nuances of the system is essential with any mission-critical function, because everything must be predictable. Engineers need to consider worst-case scenarios in detail at an early stage of their design, detecting errors before they can harm the entire system.

Consequently, a COTS board claiming to be safe must also be deterministic, since even in the event of a system failure, some functions may still need to operate. Think of the lighting inside a train if the train should stop inside a tunnel.

To give certain critical functions higher availability, designers can create

a cluster configuration by multiplying the existing system and making it available as a safe back-up unit. One system is active, while the other runs in “stand-by mode.”

If the active channel fails, the system automatically switches to the second channel.

Data availability is becoming increasingly important in safety-critical systems, such as those used in mass transportation, as more electronics are integrated at all levels of operation. Reliability, robustness

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and high-speed data processing are crucial to ensuring operations run smoothly and passengers remain out of harm’s way, and these systems need to remain flexible for future data and computing requirements that may be coming down the line.

MEN Micro Ambler, PA. (215) 542-9575. [www.menmicro.com].

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technology deployed Multicore System Development

What’s Going on in My Multicore System?

Real-time event analysis is critical for multicore software development as is the ability to analyze the processing burden on multiple cores to even the load and improve overall performance.

by John Carbone, Express Logic

R

eal-time systems must react quickly to external and internal demands. When a system uses a multicore architecture, the speed and number of interactions rises sharply. While this improves the performance of a system, it complicates the real-time sequencing of application events since multicore system events can occur simultaneously over multiple independent processors instead of occurring sequentially as on a singleprocessor system.

For the multicore developer, the increased complexity of managing the number of events and their simultaneous nature represents an exponentially more challenging system to design. Diagnosing the cause of a system failure or inefficiency is much more difficult than with a single processor system. With few multicoreready tools, developers have been left with primitive “print statement” techniques to leave “bread crumbs” throughout the operation of the system, indicating certain data about various events of interest that have occurred. The developer must gather and make sense of the crumbs and infer the system’s state—a process often requiring subsequent re-instrumentation to gain a finer degree of granularity and a repeat of the process.

To gain more efficiency in unraveling the intricate sequence of operations on a multicore system, developers need a tool that enables them to examine the system’s individual operations that immediately

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precede an area of interest. Much like an airliner’s “black box,” such a tool can be invaluable in shedding light on the critical events leading up to a certain point, or even a system crash. This article will show how this is possible using TraceX, a development tool that displays real-time events that occurred on a multicore system. As shown by the example in Figure 1, developers

can see exactly what is going on in their multicore system across a particular period of time. A graphical analysis of all system events is displayed across a unified timescale, organized by application thread, and grouped by processor core.

The Traditional Approach to System-Event Analysis

Real-time programmers have long understood the importance of system behavior to the functionality and performance of their applications. The conventional approach addresses these issues by generating data on system behavior when the code reaches a certain stage by toggling an I/O pin, using printf, setting a variable, or writing a value to a file.

Inserting such responses requires a considerable amount of time, especially when you consider that the instrumentation code often doesn’t work exactly as expected the first time around and also needs to be debugged. Once that part of the application is verified, the

Figure 1 Express Logic’s TraceX offers a graphical view of real-time events in a multicore system. In this example, you can see Core-0 and Core-1 simultaneously executing different threads.

Technology deployed

instrumentation code needs to be removed and its removal also needs to be debugged. Since much of the instrumentation process is manual, the process is time-consuming and prone to additional errors.

Besides instrumenting the code, the developer also needs to find a way to interpret the data generated. The volume of information generated by the instrumentation code makes the task of determining what system events took place and in what sequence challenging. Modern debuggers can trace individual instruction execution, stop execution at a breakpoint, and show memory and register values at any point.

But they lack the ability to show RTOS actions, like context switches, or semaphore gets, which can be valuable clues to system behavior.

New Approach Offers Advantages

In contrast, TraceX automatically analyzes and graphically depicts system and application events captured on the target system during run-time. Events such as thread context switches, preemptions, suspensions, terminations and system interrupts leave a trail of “bread crumbs” in a target-resident “trace buffer” that is uploaded, interpreted and displayed graphically on the host. The bread crumbs describe each event that just happened, which thread was involved, which core that thread was running on, when the event occurred and other relevant information.

The user also can log any desired application events using an application programming interface (API). Event information is stored (“logged”) in a circular buffer on the target system with buffer size determined by the application. A circular buffer enables the most recent “n” events to be stored at all times and to be available for inspection in the case of a system malfunction or other significant event.

Event logging can be dynamically stopped and started by the application program, such as when an area of interest is encountered. This avoids cluttering the database and using up target

Figure 2 Individual event details can be displayed by clicking on an event icon.

memory when the system is performing correctly. The event log may be uploaded to the host for analysis at any time, either when encountering a breakpoint, a system crash, or after the application has finished running.

Once the event log is uploaded from target memory to the host, the events are displayed graphically on the horizontal axis which represents time (again, Figure 1). The various application threads and system routines related to events are listed along the vertical axis, and the events themselves are presented in the appropriate row. Events are represented by color-coded icons, located at the point of occurrence along the horizontal timeline as well as to the right of the relevant thread or system routine. Each event icon contains an abbreviation of the event itself, for example, “QS” is used to indicate a “Queue Send” operation. For multicore systems, the events are linked to their respective processor core and grouped to-

gether so that developers can easily see all the events for a particular core.

All events are also presented in the top “summary row,” regardless of core or thread. This provides developers with a handy way to obtain a complete picture of system events without scrolling down through all threads and cores. The axes may be expanded to show more event detail or collapsed to show more events.

The timescale can be panned left (back) or right (ahead) to show any point in the trace buffer. When an individual event is selected, as in Figure 2, detailed information is provided for that event, including the core, context, event, thread pointer, new state, stack pointer and next thread point.

Solving Priority Inversion Problems

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technology deployed

Figure 3 This display shows a non-deterministic priority inversion.

situations. Priority inversions arise because RTOSs employ a priority-based preemptive scheduler that ensures the highest priority thread that is ready to run actually runs. The scheduler may preempt a lower-priority thread in midexecution to meet this objective.

Problems can occur when high- and low-priority threads share resources, such as a memory buffer. If the lowerpriority thread is using the shared resource when the higher-priority thread is ready to run, the higher-priority thread must wait for the lower-priority thread to finish. If the higher-priority thread must meet a critical deadline, then it becomes necessary to calculate the maximum time it might have to wait for all its shared resources in determining its worst-case performance.

Priority inversions occur when a highpriority thread is forced to wait while the CPU serves a lower-priority thread. Worse yet is the situation where a mid-priority thread interrupts the low-priority thread that currently holds the shared resource.

In this case, the low-priority thread cannot continue, and hence, cannot finish its use of the shared resource. Thus, a highpriority thread needing that resource can be held up indefinitely if the mid-priority thread continues to run. This is unacceptable in a real-time system, since it prevents deterministic behavior.

Priority inversions are difficult to identify and correct. Their symptom is

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normally poor performance, but poor performance stems from many potential causes. Compounding the challenge of identifying the cause is the fact that priority inversion can also evade testing, only occurring infrequently and not in any test case that has been constructed for the system, which could mean that the system is non-deterministic.

With a systems event tool such as TraceX, it is possible to easily and automatically identify priority inversions.

The trace buffer clearly identifies which thread is running at any point in time and records any change in a thread’s readiness. It is therefore easy to go back in time to determine whether a higher-priority thread is ready to run, but blocked by a lower-priority thread that holds a resource needed by the higher-priority thread. The priority inversion shown in Figure 3 is non-deterministic.

In Figure 3, we can see that Low_ thread holds a mutex (guarding a shared resource) when it is preempted

by High_thread. High_thread then seeks the same mutex, but must wait for Low_thread to release it. However, Medium_thread has intervened and can run for an indeterminate length of time, delaying not only Low_thread, but also High_thread. Only when Medium_ thread yields enough time to Low_ thread for it to complete its processing and release the mutex can High_thread

Technology deployed

Figure 4 An execution profile, showing CPU time used by each thread.

resume. Since there is no way to determine how long Medium_thread might continue to run, the system becomes non-deterministic.

Of course, there are other ways to avoid priority inversions of this type. For instance, “priority inheritance� for mutexes would prevent the inversion in this example. With priority inheritance, when a mutex, held by a thread, is needed by a higher-priority thread, the priority of the thread holding the mutex is temporarily raised to that of the requesting, high-priority thread. Thus, the low-priority thread now can run until it releases the mutex, and then its priority is restored to its original level. As a result, the high-priority thread then can get the mutex and continue its work.

Improving Application Performance

While most developers begin using tools to understand and correct problems, gaining an execution profile is a potentially broader benefit derived from using the tool to analyze and improve systemlevel application performance. Using an execution profile, developers see the amount of CPU time used by each thread and by system services (Figure 4). The developer can easily drill down on specific events for diagnostic purposes.

Even more relevant to multicore system operation, balancing the processing load across all available cores can be very effective in achieving greater system throughput. If a system profile provides information about which cores have greater idle time, as is shown in Figure 4, it can give the developer a strong clue as to how to shift processing to an otherwise idle core.

In conclusion, a tool such as TraceX paints a graphical picture of the system in a way that standard debuggers cannot.

This enables developers to get a clear picture of interrupts, context switches and other system events that could otherwise only be detected through time-consuming instrumentation of code and tedious examination of the resulting data. The result is that developers can find and fix bugs and optimize application performance in substantially less time than would be required using standard debugging tools alone. With debugging taking up to 70% of application development, such tools offer the opportunity to significantly improve products while requiring less development time.

Express Logic San Diego, CA. (858) 613-6640. [www.rtos.com].

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products &

TECHNOLOGY Flexible Family of OpenVPX Pass-Through Backplanes A new series of OpenVPX pass-through backplanes speeds the development of custom OpenVPX system designs by passing all of the high-speed serial fabric connections directly to RTM connectors. These 3U and 6U OpenVPX backplanes, an addition to the Hybricon family by Curtiss-Wright Controls Defense Solutions, are designed for applications that require non-standard backplane interconnections. This approach can dramatically reduce development time and cost while mitigating design risk. It also provides the system designer with greater flexibility for development applications in which the final fabric connectivity needs are not yet fully defined. All Hybricon pass-through backplanes are compatible with RTMs or Meritec VPX+ cable systems, enabling the system integrator to easily and quickly make applicationspecific connections via cabling in a development environment.

Pass-through backplanes can save OpenVPX system developers time and money, freeing them to continue their system definition without locking them into a specific custom backplane, providing a COTS alternative to custom OpenVPX backplanes for development activities.

The Hybricon OpenVPX pass-through backplanes come in 3U and 6U versions. Both versions are VPX REDI 1” pitch (7 slots wide) and feature no data plane, control plane, or expansion plane fabric connectivity. All fabric signals pass through to RTM connectors for users. A Develop-to-Deploy (D2D ) ATR chassis is available and an air- or conduction-cooled development chassis is available.

Curtiss-Wright Controls Defense Solutions, Ashburn, VA. (613) 254-5112. [www.cwcdefense.com].

Carrier Cards Interface XMC Mezzanine Modules to PCI Express Bus A simple and cost-effective solution allows a PC to communicate with an XMC mezzanine module over a PCI Express (PCIe) bus. System developers can insert XMC modules on the carrier card to perform a variety of signal processing functions. The APCe8675 carrier card from Acromag has a PCIe x8 interface that supports up to eight serial lanes for rapid data transfer between the plug-in XMC module and the host PC computer. These carriers are suitable for high-performance industrial and scientific research computing systems. They are also useful to test advanced systems for defense and aerospace applications that will be deployed later on rugged embedded computer platforms such as VME, VPX, or CompactPCI. Now system developers can build powerful computers with an array of FPGA modules using a high-speed interconnect fabric similar to those of high-end VPX systems, but in a low-cost PC chassis. Several rear I/O connectors enable high-speed serial interfaces between neighboring carrier boards using XAUI or Aurora protocols. These ports simplify board-to-board connections with twinax or internal SCSI-3 cables to left and right adjacent carrier cards.

One XMC socket interfaces up to eight serial I/O lanes to the carrier’s PCIe x8 edge connector. The other XMC socket routes to a pair of 4-lane serial ports for board-to-board connections that support up to five high-speed (5 Gbit/s) transmit/receive differential or LVDS pairs. A 64-pin PMC rear I/O socket routes 32 LVDS I/O to a SCSI port for additional board-to-board communication.

An integrated fan provides a constant airflow across the XMC module since most PCs cannot provide sufficient cooling to dissipate heat generated by large FPGA devices. The carrier card is also ready for use with a conduction cooling thermal frame. Standard model, single unit pricing starts at $700.

Acromag, Wixom, MI. (248) 295-0301. [www.acromag.com].

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InfiniBand Switch Provides Higher Throughput A 6U OpenVPX InfiniBand switch fabric module is designed to bring leading-edge commercial data center connectivity and performance to the most demanding military and aerospace applications. The IBX400 from GE Intelligent Platforms also complements GE’s existing GBX460 10 Gigabit Ethernet Switch Fabric Module, offering an alternative, higher performance InfiniBand-based solution for customers who need increased data plane bandwidth with lower latency.

The IBX400 provides high-speed data connectivity to GE’s rugged Modular Open Systems Architecture (MOSA) board-level solution sets that include the latest RDMAenabled Intel Corei7 single board computers, multiprocessors, NVIDIA CUDA GPUs and PMC/ XMC carrier cards. Applications can easily be moved from Linux server or desk-top machines onto these deployable modules to provide greatly increased computing performance where it is needed most.

GE’s end-to-end solutions provide shorter time to solution, lower technical risk and lower cost of ownership. System integrators and end users can deploy tried and tested software building blocks such as the OpenFabrics Enterprise Distribution (OFED) Remote Direct Memory Access (RDMA) and OpenMPI high-performance interprocess communication (IPC) middlewares from the OpenFabrics Alliance as well as modules from other open source HPC (High Performance Computing) community projects.

Key features of the IBX400 include: DDR InfiniBand data plane with 20 fat pipes and inband subnet management; a Gigabit Ethernet control plane with 16 ultra-thin pipes and fully managed layer 2/3 Ethernet switch fabric; and GE’s OpenWare control plane switch management with QoS priority and support for IPv6 and IPv4 switching.

General Electric Intelligent Platforms, Huntsville, AL. (780) 401-7700. [http://defense.ge-ip.com].

PRODUCTS & TECHNOLOGY

Sandy Bridge-Powered Networking Platform with 14 GbE LAN A 1U rackmount hardware platform is designed for high-performance network service applications. The PL80470 from Win Enterprises supports Intel Sandy/Ivy Bridge Core i7/i5/i3 processors with Intel Advanced Vector Extensions and Turbo Boost Technology. The platform will support 6 to 14 GbE Ethernet LAN ports via PCIe x8.

The platform supports two DDR3 1066/1333 MHz unbuffered non-ECC DIMM sockets with memory up to 16 Gbytes.

Storage interfaces support one 3.5” or two 2.5” SATA HDD, one mSATA and one CompactFlash card. To prevent network problems during platform shut-downs, PL-80470 supports two segments of LAN bypass function through WDT and GPIO pin definitions.

The front panel also features dual USB 2.0 ports, one RJ-45 console port and LED indicators to monitor power and storage activities for local system management, maintenance and diagnostics. The choice of one PCIe x8 slot or one PCIe x8 Golden Finger connector enables additional Ethernet capacity or card-based features.

WIN Enterprises, North Andover, MA. (978) 688-2000. [www.win-ent.com].

LDRA Integration with Lauterbach TRACE32 Simplifies Code Analysis, Test and Certification

ATX Board with Fourth Generation Intel Core Processors Targets Industrial Applications

LDRA, a tool provider in standards compliance, automated software verification, source code analysis and test tools, has integrated the LDRA tool suite with the Lauterbach Trace32 Debugger and Simulator. Lauterbach’s hardware-assisted debug tools ease the interface to the embedded device, enabling developers to download and fully test an application on the target. Thanks to the interface, rigorous safety-critical testing and certification—a traditionally time-intensive, manual process—is automated, enabling a broad range of microcontroller and processor-based applications to achieve medical (IEC 62304), industrial safety (IEC 61508), automotive (ISO 26262) and avionics (DO-178B/C) compliance.

An extension to the LDRA tool suite uses the Trace32 Debugger to download the code being tested on the target and provide a mechanism for results capture back to the host via a one-click button added into the TRACE32 in-circuit debugger (ICD).

Given the limited resources of some embedded devices, the integration offers two options for dynamic analysis of executing code. If memory is limited, test results can be streamed back to the host via the ICD. However, if performance is important and memory available, test results can be compressed on the target and uploaded at a suitable time via the one-click upload button.

The LDRA-Lauterbach integration automates comprehensive, endto-end testing even on systems where memory and processor resources are limited. Rigorous safety-critical standards such as DO-178C Level A and ISO 26262 ASIL Levels A–D require bidirectional requirements traceability linking each requirement with the code and tests that fulfill it. In addition, every line of code must be fully tested. The LDRA tool suite makes this level of traceability possible, down to the object code.

Code that remains unexecuted by test data is highlighted graphically. The LDRA tool suite can then generate unit tests and execute this previously unexecuted code, ensuring comprehensive testing of the entire application.

For applications where the target is not yet available, the same integration has been achieved with TRACE32 Instruction Set Simulator.

Projects under tight timelines can fully test the application in a simulated environment to preserve budget and schedule limits. By doing this, teams produce better quality of code, significantly reducing the time required for on-target testing and debug. Project costs for certification can be kept to a minimum while preserving top-quality code.

A new ATX form factor utilizes the fourth generation Intel Core processors. The RUBY-D716VG2AR from American Portwell is designed to provide high performance and flexibility for functional expansions, and is ideal for applications in Industrial Automation and Control, Gaming, Medical/Healthcare and Military.

The fourth generation Intel Core processors are manufactured on the latest 22nm process technology and are the most powerful and energy-efficient CPUs from Intel to date. Portwell’s RUBY-D716VG2AR is based on the Intel Q87 chipset and the 4th generation Intel Core processors in an LGA1150 socket, which have integrated the memory and PCI Express controllers supporting two-channel DDR3 long DIMMs and PCI Express 3.0 to provide powerful graphics performance.

The Intel Q87 chipset continues to work with a new architecture to deliver quality, performance and industry-leading I/O technologies on most of the platforms powered by the 4th generation Intel Core processor family. RUBY-D716VG2AR is the first Portwell off-the-shelf industrial ATX motherboard utilizing the Intel Q87 chipset, and it is a good solution for customers to integrate into their industrial systems.

The RUBY-D716VG2AR offers numerous enhanced features, including SATA storage specification, up to 6 Gbit/s, within five SATA III interface connectors to allow RAID 0/1/5 and 10 modes, the latest PCIe 3.0 (one PCI Express x16 slot) to support devices for double speed and bandwidth, which enhances system performance and PCIe 2.0/PCI slots (two PCIe x1 slots, two PCIe x4 slots with PCIe x1 signal and two PCI slots). The latest USB 3.0 highspeed transmission technology supports 12 USB ports (four USB 3.0 ports and eight USB 2.0 ports). In addition there are four long DIMM memory slots for DDR3 SDRAM, up to 32 Gbyte and 1600 MT/s, triple display including VGA, HDMI and DVI-D available in both clone and extended modes, and dual Gigabit Ethernet connectors are the basic interfaces of the module.

RUBY-D716VG2AR is equipped with another two industry-oriented interfaces, six COM ports (optional up to 10 COM ports) and one CFEX slot. The implementation of numerous COM ports enables the board to provide multiple controls for legacy systems that are in use in power plants, for example. In addition, the board is also built with a CFEX slot, so that customers can choose flexible functions based on CFEX-specific interfaces for their different industrial demands. In addition to original storage functions, CFEX also provides advanced monitoring abilities, portable BIOS for security purpose and extensions based on CFEX interface definitions. Once again, Portwell demonstrates its expertise and experience in the IPC field through the developing of RUBYD716VG2AR that implements all the industry related requirements.

LDRA, Boston, MA. (855) 855-5372. [www.ldra.com].

Lauterbach, Höhenkirchen-Siegertsbrunn, Germany. +49 8102 9876 129. [www.lauterbach.com].

American Portwell Technology, Fremont, CA. (510) 403-3399. [www.portwell.com].

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PRODUCTS & TECHNOLOGY

Embedded Vision System with 3rd Generation i7 Quad-Core and GigE Vision Compliance A new GigE Vision-compliant embedded vision system, featuring 3rd generation Intel Core i7 quad-core processors, four independent power over Ethernet (PoE) ports, full compatibility with GigE Vision cameras and support for smart PoE APIs, allows remote switching of PoE status.

With high-end CPUs and multi-channel connectivity in a compact housing, the EOS-1220 from Adlink Technology is well suited to multicamera imaging applications such as 3D robot guidance.

Combining PoE and IEEE 1588 support, which enables single-cable transmission of power, signal and data synchronization, the EOS-1220 significantly cuts cabling requirements by as much as 60%, reducing maintenance burdens. In addition, the system further provides smart PoE APIs, allowing remote switching of PoE status. With this feature, camera power consumption is more easily monitored and controlled, stabilizing camera temperature and significantly extending system lifetime.

Additionally, the EOS-1220’s rich I/O interface, including four RS-232/422/485 ports, two USB 3.0 ports, 32 PNP/NPN isolation digital I/Os, dual storage (two SATA interface and one CFAST slot), an internal USB port and 1 Kbit programmable EEPROM, make the EOS-1220 simple to integrate and deploy, providing management of copy protection and software license authentication for system development. Driver support includes Windows 8/7/XP and Windows Embedded Standard 7, and File-Based Write Filter (FBWF), providing a stable, secure and high-performance software operating environment.

ADLINK Technology, San Jose, CA. (408) 360-0200. [www.adlinktech.com].

Basic COM Express Module Equipped with Fourth Generation Intel Core Processor A Type 6 COM Express Basic (125 mm x 95 mm) module is based on the fourth generation Intel Core processor and Mobile Intel QM87 Express chipset (3W). The PCOM-B630VG COM Express module from American Portwell includes Intel Turbo Boost Technology for faster processing, Intel vPro Technology for superior remote capabilities and Intel Hyper-Threading Technology for multithreaded processing. Along with three symmetric independent displays, the module also features the fourth generation Intel Core Processor, built on 22nm process technology utilizing multi-stream technology. These features translate into higher performance with reduced manageability costs, which along with new security features make it an attractive solution for Medical Healthcare Systems, Digital Signage and Retail Systems.

The PCOM-B630VG COM Express module supports up to 16 Gbyte ECC DDR3L 1333/1600 MT/s SDRAM on two 204-pin SODIMM sockets, making it faster than its predecessor. Its expansion interface supports one PCI Express x16 Gen3 (8.0 GT/s) with three controllers integrated into the processor for enhanced video performance and enhanced capabilities, which can also be configurable to 2 x8-lane or 1 x8-lane and 2 x4-lane PCI Express ports. The module supports three independent displays, DP (DisplayPort), HDMI or DVI and VGA, with up to 1.6x greater 3D performance compared to its previous generation.

Designed on a basic 125 mm x 95 mm platform, the PCOM-B630VG is backward compatible. In addition, the Mobile Intel QM87 chipset functions smoothly with the fourth generation Intel Core processors. These features allow customers to preserve their legacy components and subsequent investments while minimizing turn-around time—all of which ensures that the costs of inevitable upgrades are minimal.

American Portwell Technology, Fremont, CA. (510) 403-3399. [www.portwell.com].

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High-Speed Clock Generator for Cobalt Virtex-6 and Onyx Virtex-7 FPGA Board Families A high-speed clock generator in a PMC/ XMC form factor provides fixed frequency sample clocks to up to four Pentek analogto-digital Cobalt and Onyx modules in multiboard systems. The Model 7194 from Pentek enables synchronous sampling, playback and timing for a wide range of multichannel, highspeed data acquisition and software radio applications.

As a standard PMC/ XMC form factor module, the Model 7194 uses PMC P14 or XMC P15 connectors solely for power and can be mounted in any PMC or XMC site.

The optional PCIe style 6-pin power connector allows it to be powered without a PMC/XMC site and can be used in virtually any chassis or enclosure. Carriers adapt the Model 7194 for PCIe, AMC, CompactPCI, VME and VPX. The board requires no programming.

Delivering clock frequencies up to 2 GHz, the Model 7194 is a suitable companion clock generator to the following high-speed products and their commercial off-the-shelf (COTS) and rugged PCIe, AMC, Compact PCI, VME and VPX derivatives: Onyx Virtex-7 FPGA Models: • 71740 (1-Channel 3.6 GHz or 2-Channel 1.8 GHz 12-bit A/D XMC module) • 71741 (1-Channel 3.6 GHz or 2-Channel 1.8 GHz 12-bit A/D with DDC XMC module) Cobalt Virtex-6 FPGA Models: • 71640 (1-Channel 3.6 GHz or 2-Channel 1.8 GHz 12-bit A/D XMC module) • 71641 (1-Channel 3.6 GHz or 2-Channel 1.8 GHz 12-bit A/D with DDC XMC module) The Model 7194 starting price is $1,995.

Delivery is 8-10 weeks ARO. Options exist for power connection and sample clock rate.

Pentek, Upper Saddle River, NJ. (201) 818-5900. [www.pentek.com].

PRODUCTS & TECHNOLOGY

High-Security, Self-Encrypting Solid State Drives Store a Quarter Terabyte A next-generation family of self-encrypting solid state drives (SSDs) is targeted for applications requiring superior data security, outstanding reliability, ruggedization, large storage capacity and high sustained data throughput rates. The first new product in the TRRUST-Stor Series 200 family from Microsemi is a 256 Gbyte 2.5” SATA SSD that operates at sustained rates of 200 Mbytes/s using reliable, long-life SLC NAND flash. The company has secured multiple design wins for its new Series 200 SSD and initial shipments to customers are underway.

TRRUST-Stor Series 200 SSDs are ideal for high-bandwidth land-, air- and ship-based video streaming and surveillance applications where recording every second of data is important. The high-capacity Series 200 also provides ample storage for imaging applications such as those used in UAVs and vetronics.

The TRRUST-Stor Series 200 is powered by Microsemi’s second generation Armor processor. A full hardware-based erase takes less than eight seconds. The Series 200 SSDs also offer the ability to load encryption keys. Customers can input their own AES-256 keys, purge them and re-load as needed. Microsemi’s TRRUST-Purge technology destroys keys in less than 30 milliseconds when activated.

The self-encrypting drive (SED) features a built-in compact in-line encryptor with hardware-implemented AES 256 encryption using the XTS block cipher mode. The drives are manufactured in a trusted U.S. facility with full BOM and manufacturing control. They are also developed to SD’s ruggedized specifications that allow the disk drive to withstand up to 3000G shock and 30 Grms of vibration.

Microsemi, Mission Viejo, CA. (949) 380-6100. [www.microsemi.com].

System-on-Module Targets High Production Volume Embedded System Development

3U VPX Board with Quad-Core Freescale QorIQ CPU Supports Hypervisor Technologies

A small form factor system-on-module is designed to facilitate faster, lower risk development of smarter embedded systems that demand real-time hardware performance, all without sacrificing differentiation, integration or flexibility.

The eSi-ZM1 from EnSilica is the company’s first product in a new range of eSi-Modules and is built around the Xilinx Zynq Extensible Programming Platform. Combining a powerful dual core ARM Cortex A9 MPcore subsystem running embedded Linux together with the Xilinx Series-7 FPGA fabric, it is suitable for developing a range of commercial and industrial applications for automotive electronics, consumer electronics, industrial automation, broadcast, medical imaging and wired communications. However, the small form factor, low-cost, high pin count, robust connector, together with availability in commercial and industrial temperature grades, makes it attractive for both volume production and prototyping of a wide range of Xilinx Zynq-based products. The eSi-ZM1 measures just 82 mm by 50 mm and is currently being deployed in a number of production products including a radar and media server.

The eSi-ZM1 provides an exceptionally high I/O count through an MXM3.0 connector, delivering the full capability of the FPGA fabric without sacrificing signal integrity. It provides excellent connectivity through a broad range of advanced I/O including a Gigabit Ethernet PHY with 1588 time stamping, a 4-port USB 2.0 hub, I2C and micro SD-card holder. Additionally, the programmable logic provides unlimited possibilities to add virtually any peripheral or create custom accelerators to extend system performance to suit the target application.

EnSilica provides full firmware and software support for the eSiZM1, including a compatible BSP and embedded Linux build preloaded on SD-card. Although the module is ready to use out-of-thebox, EnSilica provides a range of complementary custom design and development services both for eSi-ZM1 integration and wider product development. EnSilica’s eSi-Module product roadmap also includes a System-on-Module based on the Altera Cyclone IV SoC.

A 3U VPX PowerPC processor board is targeted for rugged embedded systems that need to process compute-intensive applications using the lowest possible power consumption. To meet this requirement, the Kontron 3U VPX processor board VX3240 features the new, power optimized Freescale P2041 QorIQ quad-core processor. The headless VPX design has four 1.2 GHz Power Architecture e500mc cores, which helps engineers to successfully meet current and future challenges of Size, Weight & Power and Cooling (SWaP-C) requirements for constrained environments in the military, aerospace and transportation markets. Moreover, the integrated hypervisor support enabling the use of low-level safety-critical virtualization technologies from companies such as Wind River, RTS or Sysgo, makes the VX3240 the ideal SBC for consolidation of multiple applications into a single platform, further improving the SWaP-C balance.

Network-centric applications also benefit from the data path acceleration architecture (DPAA), which offloads packet handling tasks from the core, providing increased processor performance for critical tasks while the secure boot feature of the CPU can be used for trusted boot implementation, allowing only authenticated code to run on the board. Applications for the new 3U VPX processor board VX3240 include, C4ISR, software defined radio and networked applications that require rugged OpenVPX designs to operate in the most demanding environments. Safety-critical railway applications also benefit from this architecture.

Its wide range of I/Os, including Gigabit Ethernet, GPIOs, USB, SATA and serial interfaces, simplifies integration in new, data- intensive, low-power system designs. Furthermore, an onboard PMC/XMC slot offers engineers a space-saving extension option to integrate dedicated I/O, field bus or storage modules without occupying an additional VPX system slot. The multicore processor is also designed to execute application code written for legacy PowerPC versions, enabling simple upgrades of existing installations without the need to change the code basis. Backed up by Kontron’s Long Term Supply Program, the Kontron VX3240 is an attractive fit for long-term projects, providing 20+ years secured availability.

IO Power 1v8

DDR Power 1v35

Bank 33

Bank 502

MIO-0

ZYNQ Core

Bank 13

Bank 34

Bank 35

MIO-1

Core Power 1v10

NAND FLASH 1G Byte

QSPI Boot FLASH 16MB DDR3 1G Byte 32bit

uSD slot

1MB i2c EEPROM RTC

GbE PHY IEEE1588

USB 4 PORT HUB

Connector 314 pin MXM3.0

134 IO signals User levels

12 MIO signals 1v8 levels

EnSilica, Workingham, UK. +44 (0) 188 3217 310. [www.ensilica.com].

Kontron, Poway, CA. (888) 294-4558. [www.kontron.com].

RTC MAGAZINE JULY 2013

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Ethernet Device Uses Precise Algorithms for Counting Passengers A compact and fully integrated passenger counter with Ethernet communications is specifically designed for public vehicles. The DynaPCN 10-20 from Eurotech extends its family of DynaPCN products that are certified for railway applications, adding more precise algorithms for counting passengers as they enter and depart while easing integration with other onboard systems.

The DynaPCN 10-20, based on noncontact stereoscopic vision technology coupled with sophisticated real-time image analysis, results in the ability to count train, tram or bus passengers with high accuracy levels without the need for elaboration by other systems. The passenger counter provides reliable and dependable performance in a railway environment with a protected IP65 aluminum-alloy case, EN51055 T1 certification, and Ethernet communication channel to other systems and isolated power supply ports. The device is designed to be inconspicuous, with flush mounting near the entrance of the vehicle.

Benefits of deploying a passenger counting system based on the DynaPCN family include comparing and verifying fare collection figures with passenger counts, validating passenger counts to justify payments due to transportation companies, and scheduling maintenance and cleaning based on vehicle usage. It also helps optimize vehicle load across regions, time periods, or other factors while monitoring service quality.

Eurotech, Columbia, MD. (301) 490-4007 [www.eurotech.com].

Programmable USB2 Controller Hubs with Simultaneous Support for USB2 and HSIC, Low-Power Modes Microchip Technology has announced the expansion of its USB2 Controller Hub (UCH2) portfolio. The seven new UCH2 ICs across three families provide programmability, enabling the developers of PCs and mobile devices to configure their designs without external memory. Additionally, these are Microchip’s first UCH2s to support both USB2 and USB High Speed Interchip (HSIC) connectivity, maximum battery life via low-power modes such as Link Power Management (LPM), and the ability to replace wall chargers with advanced battery charging modes, such as BC1.2, Apple, SE1 and China charging. For applications that need to communicate over multiple protocols, these UCH2s feature direct I/O bridging to I2C, SPI, UART and general-purpose I/O. They also have the flexibility to support Direct I/O Bridging the behaviors of multiple operating systems, USB to I C™, SMbus, SPI, UART such as vendor-specific messaging and FlexI C™ from Master HSIC or USB Host Port Connect for simple port reversals.

Port Controller While the PC market is converting to 3.3V I C/SMB USB3, most market forecasts predict that Hub Controller Logic 24 MHz USB2 will remain predominant in mobile Embedded devices through at least 2015. This continued Controller use of both USB3 and USB2 challenges the GPIO I C/SMB designers of PCs and mobile devices to ensure Downstream Ports interoperability while providing new features USB and/or HSIC and maximum battery life. Microchip’s seven new UCH2s across three families address these needs for both PC and mobile manufacturers. Microchip’s new UCH2s integrate “Quad Page” configuration OTP Flash memory, which reserves space for interoperability and other customizations by the designer, including four separate configuration opportunities. Additionally, Microchip makes it easy to generate configuration settings and program the OTP memory, via its new ProTouch Configuration Editor software tool.

The aforementioned ProTouch Configuration Editor software tool is available via a free download from http://www.microchip.com/get/2M4E. It is bundled with the ProLink programming software. Also available is the USB2534 Eval Board, for $399. This board supports the development of USB charging designs using the new three-member USB253X UCH2 family for mainstream USB2 applications.

2

2

SPI

2

2

Microchip Technology, Chandler, AZ. (480) 792-7200. [www.microchip.com].

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Software PLC Technology Available for Altera Cyclone V SoCs ARM Cortex A architectures provide new cost-effective and flexible options for automation technology. The ProConOS embedded CLR (eCLR) runtime system from KW-Software provides all required functionalities to realize a complete high-performance control solution. Based on an embedded platform such as the Altera Cyclone V SoC, multitasking capability, support of online changes, provision of an interface for commissioning, debugging and monitoring of the control is available.

As a result of the processing of native machine code, control solutions based on Cyclone V SoC with its 800 MHz Dual-Core Cortex A9 processor become extremely fast.

ProConOS eCLR can be programmed both in C# and in IEC 61131 languages.

The Cortex A architecture, originating from the consumer world of mobile phones and touch pads, allows the development of cost-effective, high-performance embeddedsolutions. It will be an important standard platform for automation devices. The Altera Cyclone VSoC, based on Dual Core Cortex A9, is a flexible basis for these new designs.

The current solution is based on the Linux operating system. The integration of Profinet and Ethercat interfaces, as well as Motion Control functions, are already scheduled for 2013.

“Altera’s ongoing focus on the factory automation market makes our product the natural platform for vendors of IEC 61131 software,” said Suhel Dhanani, senior technical marketing manager, industrial business unit, Altera. “KW-Software and Altera have a longstanding strategic relationship that allows customers to evaluate KW-Software’s PLC runtime software and communication protocols on our ARM-based Cyclone V SoC platform.”

KW-Software, Lemgo, Germany. +49 52619373-829. [www.kw-software.com].

PRODUCTS & TECHNOLOGY

3U VPX Uses Fourth Generation Intel Core Processor for Performance Boost

RTOS Adds New Security Features to Protect Embedded Connected Devices

A new 3U VPX processor board is based on the quad-core fourth generation Intel Core processor family (previously codenamed “Haswell”). The TR B12/msd from Concurrent Technologies features the Intel Core i7-4700EQ processor and the associated mobile Intel QM87 Express chipset. With up to 16 Gbytes of DRAM and a rich assortment of I/O interfaces, this board is a suitable processor board for 3U VPX solutions requiring the latest in processing performance. 3U VPX is particularly well suited to high-end compute-intensive applications in military embedded, aerospace and transportation systems for data acquisition, control systems and video signal processing.

The fourth generation Intel Core processor family is based on 22nm process technology. This quad-core processor provides enhanced CPU and graphics performance over previous generations at TDP levels up to 47W. Additionally, new instructions are introduced, including: the Intel Advanced Vector Extensions 2.0 (Intel AVX) to provide a performance improvement in integer and floating-point-intensive computations particularly appropriate for image processing applications. It also features the Intel AES New Instructions (Intel AES-NI) enhancements to accelerate data encryption and decryption in hardware.

Additional features include 4 x SATA600 mass storage interfaces, onboard SATA Flash, serial and USB interfaces, graphics and stereo audio interfaces.

The wide range of I/O interfaces can be further expanded by the addition of an XMC module. The board supports a configurable control plane fabric interface (VITA 46.6) and a flexible PCI Express (PCIe) data plane fabric interface (VITA 46.4) supporting up to Gen 3 data rates and can be used in systems defined by OpenVPX (VITA 65).

Optional features include Built in Test (BIT) and a board level security package that provides a means to enhance the security of equipment to prevent access to sensitive data and key Intellectual Property.

The TR B12/msd can be integrated into systems together with Concurrent Technologies’ switches and mass storage boards. To ease integration, many of today’s leading embedded operating systems including Windows, Linux and VxWorks are supported. Systems using multiple processing boards will benefit from the optional Fabric Interconnect Networking Software (FIN-S), which provides a high-performance, low-latency, communications mechanism for multiple host boards to intercommunicate across the high-speed fabric interface. The TR B12/msd processor board is released as a commercial air-cooled board, while later releases will include dual-core processor options and ruggedized variants.

The next generation of the LynxOS real-time operating system (RTOS) from LynuxWorks, LynxOS 7.0, is designed to enable embedded developers to add security functionality to their connected devices.

The open standards-based LynxOS now adds significant new features to help meet the needs of the billions of next-generation connected devices.

Due to the ubiquity of the Internet, a network infrastructure is now in place for the “Internet of Things”—a new world of tens of billions of connected devices. The majority of those devices are expected to be hubs and sensor nodes, collecting data and transmitting it from machine-to-machine (M2M).

Application examples include aerospace and defense communication infrastructure, industrial automation, smart meters, fleet management, device monitoring, medical and patient monitoring, and situational awareness.

With cyber threats becoming more sophisticated, and more of the critical infrastructure being controlled by these embedded devices, security protection will be required on each device rather than just relying on the network protection that is in place today.

LynxOS 7.0 provides the ability for developers to embed militarygrade security directly into their devices by utilizing features such as access control lists, audit, quotas, local trusted path, account management, trusted menu manager and OpenPAM. It also contains networking support for long haul networks with TCP/IPV4, IPV6, 2G/3G/4G cellular and WiMax communication stacks. It also supports the shorthaul networks common with M2M applications such as 802.11 WiFi, ZigBee wireless mesh and BlueTooth.

In many market segments, a more advanced communication mechanism will be required to offer extremely low latency, high throughput and high availability for application-to-application communications to help satisfy demanding real-time Quality of Service (QoS) requirements. LynuxWorks partners with key middleware providers such as Real-Time Innovations, Inc. (RTI) to offer these advanced middleware products ported on the LynxOS operating system.

LynxOS 7.0 is a deterministic, hard real-time operating system that provides POSIX-conformant APIs in a small footprint embedded kernel. LynxOS provides symmetric multiprocessing support to fully take advantage of multicore/multithreaded processors. LynxOS 7.0 includes new tool chains, debuggers and cross development host support.

LynxOS 7.0 provides open APIs, including medium-assurance security per the general purpose operating-system protection profile (GPOSPP).

LynxOS 7.0 supports the most popular reference targets in the Intel and PowerPC architectures including the new Intel 4th Generation Core and the Freescale QorIQ processors. LynxOS 7.0 Board Support Packages are available for targets from GE Intelligent Systems, Curtiss Wright and Extreme Engineering.

Concurrent Technologies, Woburn, MA. (781)933-5900 [www.gocct.com].

Lynuxworks, San Jose, CA. (408) 979-3900. [www.lynuxworks.com].

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Design Tool for ARM-Based SmartFusion2 SoC FPGA Designs Users of Microsemi SmartFusion2 SoC FPGAs now have available a newly released design tool, System Builder. System Builder is a tool within the Libero System-on-Chip (SoC) Design Environment version 11.0 and is specifically targeted at accelerating customer definition and implementation of ARM-based systems using SmartFusion2 SoC FPGAs. The output from System Builder is automatically generated and correct-by-construction, thus eliminating the errors that are created when the architecture is specified “by hand” as in more traditional tool flows. Thus, System Builder dramatically shortens the design cycle time for complex SoC FPGAs. Additionally, software-oriented engineers can easily create an embedded architecture and begin code development all on their own.

This simplifies the adoption of Microsemi SmartFusion2 devices and provides a much broader set of design engineers with access to SoC FPGA technology. The enhanced System Builder flow also enables Microsemi to easily support more customers with its internal design services team that offers digital or mixed signal design for custom functional blocks, Soft IP, firmware development and even complete designs to end customers.

System Builder users are guided step-by-step through each of the main SoC FPGA architecture blocks. The design process uses a high-level graphical interface that reacts to previous architecture selections and guides the user through the process of selecting options and configuring only the required embedded system blocks.

The resulting system specification is automatically generated and correct-by-construction. It includes both the configuration and interconnects of the ARM processor and its related peripherals as well as other IP blocks implemented in the FPGA fabric. System Builder can also configure a growing set of IP blocks for highperformance interfaces including DDR2/DDR3/LPDDR memory controllers, and serial interfaces using 5Gbit/s SERDES for PCIe, XAUI (10 GbE) and SGMII. Libero SoC integrates synthesis, debug and DSP support from Synopsys, and simulation from Mentor Graphics with power analysis, timing analysis and push button design flow. Firmware development is fully integrated into Libero SoC with compile and debug available from GNU, IAR and Keil, and all device drivers and peripheral initialization are automatically generated based on System Builder selections. The ARM Cortex-M3 processor includes operating system support for embedded Linux from EmCraft Systems, FreeRTOS, SAFERTOS and uc/OS-III from Micrium.

Microsemi, Aliso Viejo, CA. (949) 380-6100. [www.microsemi.com].

Drag and Drop Platform To Design and Build Custom Embedded Computers A complete system for building and ordering custom embedded computers without the need for extensive knowledge of electrical engineering combines a powerful web application for easy design with manufacturing capabilities. The Geppetto system from Gumstix reduces the process of creating an affordable, high-end electronic device from the typical three months to less than three weeks.

The process of creating custom electronic devices has been technical and lengthy. Traditional solutions require an electrical engineer to design a schematic of a board and then have a printed circuit board (PCB) specialist lay it out. Instead, Geppetto’s web application simplifies the process by providing an intuitive solution where designers can create the board with a drag and drop approach and connect desired modules, USB plugs, network connectors, LEDs or even whole computer-on-modules to meet specifications. Geppetto provides intuitive color-based status indicators of design completion while managing lowlevel routing issues.

If a design needs additional features to function successfully, Geppetto suggests alternative modules to complete the design. Designing a custom device with Geppetto, ready for manufacturing, can take as little as 10 minutes depending on complexity. Designs can then be saved, optionally shared with the Geppetto developer community and ordered online from the gumstix.com catalog. Because Gumstix provides all modules in Geppetto’s module library, customers don’t need to arrange any manufacturing logistics, thus eliminating cumbersome and costly supply chain management. With no minimum quantity required, an affordable per-unit charge (based on components used) and a manufacturing setup fee of just $1,999.00, Geppetto also offers exceptional value to electronics designers.

Geppetto was designed for customers who want a device tailored to their specifications, without the cost of conventional electrical engineering, layout and manufacturing. To achieve maximum flexibility in cost and performance as well as ease-of-use, Geppetto relies on a comprehensive set of core features. A streamlined, web-based design interface allows users to drag, drop and connect modules without specialized knowledge of electrical design. There is a developer community for sharing designs, and the inspiration to create new ones. With the advantage of Gumstix’ existing manufacturing capabilities, Geppetto offers excellent value in electrical design, at any quantity and all Geppetto-manufactured devices are tested to verify functionality and are delivered in ready-to-use condition.

Gumstix, Redwood City, CA. [www.gumstix.com].

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