High speed interconnects

Towards High Speed Interconnects Dr. S. S. Verma, Department of Physics, S.L.I.E.T., Longowal, Distt.-Sangrur (Punjab)-148106 Interconnects Interconnects serve as the streets and highways of the integrated circuit (IC), connecting elements of the IC into a functioning whole and to the outside world. Interconnect levels (or metal layers) vary in numbers depending on the complexity of the device and are interconnected by etching holes, called vias. Fabricating these intricate structures is one of the most processintensive and cost-sensitive portions of chip manufacturing. The interconnect inflection revolves around the growing number of metal layers in devices and the effect that higher wiring densities have had on the evolution of insulating films and the new process steps these have required. Research into the limits of intra-chip electrical interconnects indicates that requirements for global communication in the coming generations of integrated circuits cannot be met with metal wires. Computing devices are made up of collections of elements (relays, vacuum tubes, transistors, gates, processors, and so on) which must be linked together if they are to cooperate in order to implement some larger computation or computational structure. The interconnect which links these elements has become one of the most important aspects of modern computing devices and has opened a rich engineering design space. The overall goal is to provide a scalable approach that extends the reach and impact of Moore’s Law for many generations to come. To achieve the required densities, the integrated sources are envisioned to be modulators that are powered by a few off-chip sources. This article reviews the status of possible intra-chip optical and plasmonic interconnect solutions that replace the global wiring layers with a high-density free-space and/or guided-wave interconnection fabric, in a manner that is compatible with established integrated circuit fabrication and packaging.

Conventional interconnects Semiconductor fabrication capabilities, currently based on a 22-nanometer (nm) process, will eventually reach the limits imposed by quantum mechanics, but parallelization will allow computational power to keep increasing at an exponential rate well into the future.

However, a stark disconnect has emerged between theoretical and actual computing performance. This disconnect is due to a communications speed limit between 1

processing cores, memory cache, and storage, and it is the primary performance bottleneck that prevents harnessing available computational power. Interconnects at the heart of today’s microprocessors consist of copper wires measuring several tens of nanometers to a few millimeters in dimension depending on their function. One successful strategy that has provided performance gains over the past 40 years has been to increase the clock speed of the microprocessor. Clock speeds have increased by three orders of magnitude in 40 years but have begun to level o, at around 4–5 gigahertz, within the past few years. This is due to the success of another strategy which involves reducing the size of the transistors themselves. As more transistors are crammed onto a chip, the dimensions of the transistors and the copper wires that supply power, clock, and instruction signaling must also be reduced. Unfortunately, as copper wires shrink in size and the signaling frequency increases, the wires exhibit both more electrical resistance and signal propagation delay. Chip designers have countered with lower signaling voltages and ingenious signaling network layouts, but the communications bottleneck will endure as long as copper wires remain the interconnect of choice.

The 2001 International Technology Roadmap for Semiconductors (ITRS) predicts that the number of transistors integrated on a single die will exceed one billion by 2010. This growing number of transistors and the increasing clock frequencies translate into an increasing fraction of the total power being consumed in clock distribution. In addition, the budgets for skew and jitter are rapidly decreasing with increasing frequency, typically as the inverse of the frequency. As a consequence of the increasing power and decreasing budgets for skew and jitter, the design of the on-die clock distribution network is an increasingly challenging task. The continuous scaling down of the physical dimensions of transistors, which has beneficial effects on their performance and enables a larger number of transistors per unit area, requires a growing number of interconnects. Unfortunately, since the performance of interconnects does not improve by scaling down their dimensions, they are becoming the performance limiter of high-performance microprocessors. Last place to compromise on signal integrity is at the interconnect. By managing nearly all critical technologies and processes in-house one can assure zero tradeoffs when it comes to insertion loss, phase stability, capacitance, velocity of propagation, and more.

The continued scaling of integrated circuits will require advances in intra-chip interconnect technology to minimize delay, density of energy dissipation and cross-talk. As the design rules drop below 200 nm, a variety of problems emerges such as RC delay, electromigration resistance and heat dissipation exacerbated by increasing chip power. The use of Copper should solve resistivity and electromigration problems but reliability issue with respect to an efficient diffusion barrier is a concern. Low- k dielectrics allowing capacitance reduction have low thermal conductivity thus poor heat dissipation capability. Integration of Copper and low- k dielectrics is intensively studied worldwide. Severe limitations of the conventional interconnect in the near future act as a technology push for alternative solutions such as optical and plasmonic interconnects.

Optical interconnects 2

The electrical current required for chip power and signaling will likely to exceed the material limits of copper metal according to the International Technology Roadmap for Semiconductors (ITRS) 2011 report. Although numerous efforts to identify potential copper material replacements are under way, retaining the same interconnect strategy is likely to gain only an order of magnitude increase in performance, representing a literal kicking the can down the road. Technologies have been proposed to replace electrical signaling with conventional interconnects. Optical interconnect is a way of communication by optical cables. Optical interconnects are progressively replacing wires at shorter and shorter distances in information processing machines. Compared to traditional cables, optical fibers are capable of a much higher bandwidth, from 10 Gbit/s up to 100 Gbit/s.

Optical interconnect is seen as a potential solution to meet the performance requirements of current and future generation of data processors. Optical interconnects have negligible frequency dependent loss, low cross talk and high band width. The technology is currently being introduced as a way to link computers to mobile devices, as well as on mother boards and devices within computers. Networks of optical fibers speed massive amounts of data around the world, enabling the Internet and changing the very nature of communications. Optical interconnect is seen as a potential solution to meet the performance requirements of current and future generation of data processors. Optical interconnects have negligible frequency dependent loss, low cross talk and high band width. Optical interconnects are not much used commercially since optical interconnects technology is incompatible with manufacturing processes and assembly methods that are currently used in the semiconductor industry. There are many promising optical interconnect technologies.

A prototype optical interconnect using wavelength-division multiplexing (WDM) has been developed which if successful, is suggested that this technology could lead to the first computer capable of exascale computing (a computer that can perform a billion computations per second).

A waveguide emits eight different colored beams into several different ports of a modulator, which allows eight signals to be transferred concurrently. This multi-wavelength beam travels through the chip, with optical switches controlling the direction. Now engineers and physicists are seeking ways to adapt optical systems to move data from point to point inside computers. If these so-called optical interconnects are successfully developed, they could allow computers to share more information among their components more quickly; without them, the continuous increases in computing speed and power that we now take for granted could abruptly level off.

Optical interconnects: replacing wires between chips with streams of photons could speed things up mightily.

Plasmonic interconnects 3

Plasmonics is a promising path for future interconnects to be generated easily, detected efficiently, and can have bandwidths three orders of magnitude greater than achievable with electrical signaling. Silicon photonics is often heralded as the next generation of interconnect technology, capable of relatively low-loss, high-bandwidth optical signaling using integrated waveguides with cross sections as small as 200 nm x 200 nm is size, while relatively small, is still an order of magnitude larger than today’s current semiconductor fabrication process. If photonics, or any other potential technology, is to be a realistic contender to replace copper interconnects, it must have comparable dimensions to the transistor. Photonics is constrained by the diffraction limit: no dielectric element, resonator, or waveguide can have dimension less than half of the wavelength.

Plasmonics is a multidisciplinary field combining optics and solid-state physics, the study of optical fields bound to metal surfaces. A Plasmon is a quantum mechanical quasi-particle consisting of collective oscillations of a metal’s conduction electrons. A surface Plasmon polariton (SPP) is a surfacebound propagating Plasmon mode. One of the most intriguing aspects of plasmonics is for devices that operate well below the optical diffraction limit. This is due to some of the electromagnetic field energy being coupled to the metal’s electron kinetic energy instead of being stored in the magnetic field. As a result, plasmonic devices can effectively “squeeze” light into metal structures tens of nanometers in size, exceeding the optical diffraction limit by factors of 10 or more, yet retaining the large optical bandwidth. This is what makes plasmonics a promising contender to replace the copper interconnects in current architectures. Future plasmonic interconnects will require 1) sources of plasmons, 2) low-loss and high-confinement waveguides, and 3) Plasmon detectors.

Current CMOS technology objection is to provide sufficient bandwidth and data rate at different levels of ON- and OFF-chip interconnection. Existing metallic interconnects are not capable of providing required bandwidth with minimum signal delay, cross-talk, and power dissipation.

Integration of optics with electronics is proposed as a solution in order to meet the desired properties. Nevertheless, the challenge is to overcome the size mismatch between these two technologies, since optical components’ size is limited to the law of diffraction (optical components cannot be smaller than several fractions of propagation wavelength), while electronics is already operating at nanoscale dimension. Plasmonics technology is a favorable approach to address this problem as well. Surface Plasmon Polaritons (SPPs) are defined as electromagnetic waves that propagate along an interface of two media with dielectric constants of opposite signs. Consequently, SPPs exist at dielectric-metal interface at optical frequencies (since ɛmetals < 0 and ɛdielectrics > 0 at optical frequencies), and decay exponentially into both media.

For a structure comprised of a thin metallic layer of finite width, embedded in a homogenous dielectric, corner modes and finite length edge modes of metal couple to each other and form two symmetric and asymmetric modes. The so-called long-range surface Plasmon (LR-SPP) is a symmetric mode, and its low attenuation constant leads to an increase in its propagation length.

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Additionally, since this structure is composed of metallic layer it has the potential to carry electrical signal as well as optical signal. Surface Plasmon wire waveguides have the potential to reduce signal delay, but the high confinement required for low cross-talk amongst high density Plasmon wire interconnects significantly increases energy dissipation per transmitted bit, above and beyond that required for electric charge/discharge interconnects at the same density.

Plasmonic devices are very short and present intrinsic large bandwidth. Many plasmonic structures allow an efficient bending of the light wave vector.

Acknowledgement: The use of information retrieved through various references/sources of internet in this article is highly acknowledged.

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