วิชา วงจรดิจิตอล หน่วยการเรียนที่ 3 ลอจิกเกท

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Logic Gates ลอจิกเกต

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INVERTER

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ตารางความจริงของ INVERTER

INVERTER TIMING DIAGRAM

Inverter operation with a pulse input.

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The inverter complements an input variable.

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INVERTER TIMING DIAGRAM

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AND GATE

AND Gate Operation

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FIGURE 3--9 ALL POSSIBLE LOGIC LEVELS FOR A 2-INPUT AND GATE.

Boolean expressions for AND gates with two, three, and four inputs.

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AND GATE TRUTH TABLE

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ตารางความจริงของ AND GATE แบบสามอินพุต

Example of pulsed AND gate operation with a timing diagram showing input and output relationships.

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AND GATE TIMING DIAGRAM

AND GATE TIMING DIAGRAM

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All must be high for the output to be high

AND Gate Application Example

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AN AND GATE PERFORMING AN ENABLE/INHIBIT FUNCTION FOR A FREQUENCY COUNTER.

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OR GATE

OR Gate Operation

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ALL POSSIBLE LOGIC LEVELS FOR A 2-INPUT OR GATE

Boolean expressions for OR gates with two, three, and four inputs.

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OR GATE TRUTH TABLE

Example of pulsed OR gate operation with a timing diagram showing input and output time relationships.

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OR GATE TIMING DIAGRAM

OR GATE TIMING DIAGRAM

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All must be low for the output to below

A simplified intrusion detection system using an OR gate.

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OR GATE APPLICATION EXAMPLE

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NAND GATE

NAND Gate Operation

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OPERATION OF A 2-INPUT NAND GATE.

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NAND GATE TRUTH TABLE

NAND GATE TIMING DIAGRAM

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X  AB

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FIGURE 3--29 STANDARD SYMBOLS REPRESENTING THE TWO EQUIVALENT OPERATIONS OF A NAND GATE.

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NOR GATE

NOR Gate Operation

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OPERATION OF A 2-INPUT NOR GATE.

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NOR GATE TRUTH TABLE

NOR GATE TIMING DIAGRAM

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X  A B

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STANDARD SYMBOLS REPRESENTING THE TWO EQUIVALENT OPERATIONS OF A NOR GATE.

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XOR GATE

XOR Gate Operation

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ALL POSSIBLE LOGIC LEVELS FOR AN EXCLUSIVE-OR GATE

XOR GATE TRUTH TABLE

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X  A B

An XOR gate used to add two bits.

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XOR GATE APPLICATION EXAMPLE

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XNOR GATE

XNOR Gate Operation

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ALL POSSIBLE LOGIC LEVELS FOR AN EXCLUSIVE-NOR GATE.

XNOR GATE TRUTH TABLE

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X  A B

FIXED-FUNCTION LOGIC : IC GATES CMOS (Complementary Metal-Oxide Semiconductor) TTL (Transistor-Transistor Logic)

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CMOS – lower power dissipation

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TYPICAL DUAL IN-LINE (DIP) AND SMALLOUTLINE (SOIC) PACKAGES SHOWING PIN NUMBERS AND BASIC DIMENSIONS.

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PIN CONFIGURATION DIAGRAMS FOR SOME COMMON FIXED-FUNCTION IC GATE CONFIGURATIONS.

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LOGIC SYMBOLS FOR HEX INVERTER (04 SUFFIX) AND QUAD 2-INPUT NAND (00 SUFFIX). THE SYMBOL APPLIES TO THE SAME DEVICE IN ANY CMOS OR TTL SERIES.

PERFORMANCE CHARACTERISTICS AND PARAMETERS Propagation delay Time DC Supply Voltage (VCC) Power Dissipation Input and Output Logic Levels Speed-Power product

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Fan-Out and Loading

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PROPAGATION DELAY

THE LS TTL NAND GATE OUTPUT FANS OUT TO A MAXIMUM OF 20 LS TTL GATE INPUTS.

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Higher fan-out = gate can be connected to more gate inputs.

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THE PARTIAL DATA SHEET FOR A 74LS00.

Troubleshooting

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THE EFFECT OF AN OPEN INPUT ON A NAND GATE.

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TROUBLESHOOTING A NAND GATE FOR AN OPEN INPUT WITH A LOGIC PULSER AND PROBE.

PROGRAMMABLE LOGIC Programmable Arrays

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Figure 3--65 An example of a basic programmable OR array.

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AN EXAMPLE OF A BASIC PROGRAMMABLE AND ARRAY.

4 Types of SPLDs

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BLOCK DIAGRAM OF A PROM (PROGRAMMABLE READ-ONLY MEMORY).

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BLOCK DIAGRAM OF A PLA (PROGRAMMABLE LOGIC ARRAY).

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BLOCK DIAGRAM OF A PAL (PROGRAMMABLE ARRAY LOGIC).

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BLOCK DIAGRAM OF A GAL (GENERIC ARRAY LOGIC)

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LOGIC GATE SUMMARY