SYSTEM DESIGN USING VHDL/VERILOG WITH EDA TOOLS (ALTERA QUARTUS II/XILINX ISE) Course Objectives: {Assessment Methods Shown in Braces} 1. Modeling and Analysis: Demonstrate the ability to analyze and create models of moderately complex digital electronics circuits and systems {tests, homework, Project} 2. Programming: Demonstrate the ability to use hardware description languages (HDLs) as representation medium for expressing digital electronic design
functionality and test bench functionality {tests, homework, and project} 3. Simulation Verification: Demonstrate the ability to subject models of digital circuits and systems to simulation verification in terms of function and timing verification, and to plan and devise test scenarios for design verification {tests,
homework, project} 4. Design & Architecture: Demonstrate the ability to use different architecture modeling styles (structural and behavioral), and to understand the differences of
when to use each, as well as to demonstrate ability to reuse design units as components {tests, project} 6. EDA Tool Design Flow: Demonstrate the ability to design high efficient digital systems and verify for the design for correct functionality using industry standard EDA tools XILINX ISE/ALTERA QUARTUS II. {Homework: design and
simulation results for a complex system} 7. Project Execution and Reporting: Demonstrate the ability to complete a significant Digital system design project having a set of objective criteria and design constraints {project}. TENET TECHNETRONICS,#582,1ST Floor, Sajjan Rao Road , VV.Puram, Opp to Hotel Trishala,Bangalore-4 PH:080-41606210
SYLLABUS: PHASE I: INTRODUCTION TO VLSI • Evolution of VLSI. • PROM, PAL, PLA. • Architecture of CPLDs. • Architecture of FPGAs (Case study of one Xilinx and one Altera FPGA) • Design Flow. • Fundamentals of digital logic. • PHASEII: AN OVERVIEW OF DIGITAL LOGIC. • Number Systems. • Combinational Logic • Introduction to sequential logic. PHASE III: HARDWARE DESCRIPTION LANGUAGE: VHDL /Verilog • Introduction to HDL. • Concurrent, sequential statements, data types. • Architecture modeling and examples. • Packages and subprograms. • State machines and test benches with examples. • Synthesizable constructs and examples. • Design of combinational and sequential logic circuits. • Synchronous and asynchronous circuit design. PHASE IV: DESIGN USING EDA TOOL. • Introduction to EDA tool • Overview of ALTERA’s QUARTUS II EDA TOOL FEATURES (Synthesis, Simulation, Programming and Real Time debugging using Signal Tapper). • ALTERA QUARTUS II design flow. • Overview of XILINX ISE EDA TOOL FEATURES (Synthesis, Simulation, Programming and Real Time debugging using CHIPSCOPE). TENET TECHNETRONICS,#582,1ST Floor, Sajjan Rao Road , VV.Puram, Opp to Hotel Trishala,Bangalore-4 PH:080-41606210
PHASE V: STUDY OF DEVELOPMENT BOARDS. • • • • •
MAX II CPLD KIT. Embedded System Development Kit (ESDK). ALTERA DE1& DE2 boards. Demo of various Programming modes (AS, PS, JTAG mode). XILINX DEVELOPMENT BOARDs.
PHASE VI: HARDWARE SOFTWARE CO-DESIGN. (OPTIONAL CASE STUDY DEPENDING ON THE CALIBER OF THE BATCH OF STUDENTS) • • • • • •
Tour to SOPC builder Introduction to NIOS II IDE Introduction to Software and hardware co-design with NIOS II processor A sample C code demo in NIOS II System NIOS II based system design. Case study “Adding Custom instructions to NIOS II Processor”.
TENET TECHNETRONICS,#582,1ST Floor, Sajjan Rao Road , VV.Puram, Opp to Hotel Trishala,Bangalore-4 PH:080-41606210