Fa of flip chip c4 cao and wallace istfa 2011 by ULTRA TEC

ISTFA 2011, Proceedings from the 37th International Symposium for Testing and Failure Analysis, November 13-17, 2011 San Jose, CA, USA

Failure Analysis of Flip Chip C4 Package Using Focused Ion Beam Milling Technique Lihong Cao, Loc Tran, Wallace Donna Advanced Micro Devices, Inc Austin, Texas, USA Lihong.cao@amd.com, Tel: 512-602-4272

Abstract

Experiment

This article describes how Focused Ion Beam (FIB) milling methodology enhances the capability of package-level failure analysis on flip-chip packages by eliminating the artifacts induced by using conventional mechanical techniques. DualBeam Focused Ion Beam (DB FIB) cross sections were successful in detecting failure mechanisms related either to the die/C4 bump or package defect inside the organic substrate. This paper outlines detailed sample preparation techniques prior to performing the DB FIB cross-sections, along with case studies of DB FIB cross-sections.

1. Fault isolation technique for package failure analysis The electrical characterization by using a parametric analyzer is the first step of the fault isolation. Time Domain Reflectometry (TDR) has been successfully used to isolate Open/Short package-level failures by generating a step signal which is transmitted through the device under test (DUT) [6]. When a discontinuity in the DUT is encountered, a part of the transmitted signal is reflected. In this paper, a comparative TDR method is used to quickly determine whether an Open/Short failure is within the package or within the silicon. The impedance profile of a failing signal is compared to the impedance profile of a “golden” unit and a bare package (without die attachment). Another non-destructive technique used to detect package level failures is C-Mode Scanning Acoustic Microscopy (CSAM). CSAM is widely used in flipchip devices to evaluate the chip-to-bump interface, the solder joint through the entire thickness of the solder ball, and the solder-to-substrate interface. In this work, CSAM with a 230MHz high frequency transducer is selected to perform scanning on the samples to identify the failure.

Introduction IC packages are becoming increasingly complex due to the increasing size, I/O numbers, and application of lead-free solder bumps [1, 2]. Package level reliability and failure analysis has become an area of more concern and challenge. Effectively detecting failure mechanisms has become very critical. Conventional mechanical cross-section technique is the most common methodology to determine failure modes in the semiconductor industry. However, the typical problem of mechanical cross-sections is the smearing of the soft material into the cracks and delamination, as well as easily inducing artifacts. Thus, it is difficult to determine failure mechanisms.

2. Dual Beam FIB-SEM milling and imaging system Focused ion beam milling can provide detailed and specific information about structures without inducing artifacts by precisely monitoring the beam etch patterning and the area of exposure. FIB systems generally use a Gallium Liquid Metal Ion Source (Ga-LMIS) as the source of the ions, providing a typical beam current range of 1 pA to 20-60 nA [7]. In this study two systems are used; one is a FEI Strada400 with a maximum beam current of 21nA and another is the upgraded Strada400 with a maximum beam current of 65nA. The effect of beam current was studied.

Focused ion beam milling technology is widely used in the semiconductor industry for the purposes of circuit edit, fault isolation, Si- level cross-sectioning, Transmission Electron Microscope (TEM) analysis preparation, and material ablation [3, 4, 5]. By precisely monitoring the beam etch patterning and the area of exposure, very detailed characteristics of the failing structure, such as manufacturing defects, can be detected without inducing any artifacts. Instead of using FIB for Si-level analysis, this paper presents the DB FIB technique to perform package level cross-sections on flip chip packages to determine the failure mechanisms. The detailed process with high precision and artifact free access to the defective buried interconnection and microstructure is also discussed in this paper.

3. Sample preparation The samples in this study are flip chip Organic Pin Grid Array (OPGA) packages and the Si device is Silicon On Insulator (SOI). The Si die with a thickness of 750um is attached to an organic substrate with a thickness of 1.4mm through lead free solder bumps. In order to find the root cause of package failure, an extensive sample preparation is needed to expose

the region of interest buried within the substrate, solder joints, or Si die. Using mechanical processes to section and polish the sample can introduce stresses and smearing of materials. In this work, DB FIB is employed to perform cross sections for package related failures. It is well known that the ablation rate of a FIB on silicon is typically as low as 2.7um3/s for a beam current of 10nA[8].The time required for the FIB preparation is the limiting factor and it will take a very long time to perform a cross section through a Si die with the full thickness of 750um. Two sample preparation methods for DB FIB X-section were developed in this study. One started from the die backside and another was from the bottom of the organic substrate side.

Fig.1 Schematic strucure of sample preparation from Si die backside

(1) Sample preparation from Si die backside The mechanical milling from Si backside to remove excess Si material was employed. A local milling technique using the ASAP-1S from Ultra Tec was performed on the failed samples. In order to reduce the milling time, a selective area milling was applied only over the Area Of Interest (AOI). In this study, the ASAP1-S was used to mill a 7mm x 7mm opening in the silicon over the AOI to be cross sectioned. A 1mm diameter bit was used for milling with a rotational speed setting of 4. Silicon thickness was monitored manually throughout the milling process and milling was stopped when the remaining silicon thickness was approximately 50 – 60um’s. The total process time was less than 30 minutes. Fig.1 shows the schematic picture of local milling from Si backside to remove excess Si material. In order to further reduce DB FIB X-section time from Si die into the C4 solder joint, a chemical etchant was subsequently applied on the samples that had been mechanically thinned down to 60um. Tetramethylammonium Hydroxide (TMAH) with 24.9% aqueous solution at 83°C was used to completely etch away the remaining Si and stop at the SOI layer as TMAH only reacted with Si and didn’t etch SiO2. By then the sample was ready for DB FIB X-section from the Si die backside.

Fig.2 Schematic structure of sample preparation from bottom of organic pacakge

Results and Discussion 1.

DB FIB X-section from Si die backside

The open (I/O pins) failure was reported by automated test equipment (ATE). A Parametric analyzer was used on the failed I/O pins to confirm the open failure. CSAM was performed on the failed unit and Fig. 3 shows a small area of delamination. The CSAM waveform, suggested that the delamination is at Die/C4 bump interface. In order to determine the failure mechanism, a cross section on the delamination area was requested. DB FIB was considered to perform the cross section on the delamination area to prevent further propagation of the delamination and additional artifacts induced by using conventional cross section techniques. In this case, DB FIB X-section from Si die backside was performed to avoid mechanical stress induced on the C4 bump by sample preparation from the organic substrate side.

(2) Sample preparation from bottom of organic substrate side A mechanical parallel polish to remove the organic substrate material was performed using 320 grit SiC paper until complete removal of the substrate and exposure of the C4 bump was attained. Fig.2 shows the schematic of the parallel polish to remove the substrate until the C4 solder bump was exposed. The sample was ready for DB FIB X-section from substrate side into the Si die. The choice of sample preparation methods will be selected based on the failure signature. The cases by using the two sample preparation methods were studied.

Fig.3 CSAM image of delam for I/O open failure 82

Fig. 4 shows the optical image after ASAP local milling over the delamination area. Fig. 5 shows the optical image after TMAH removing Si over the AOI. The trench for the DB Xsection was set to 135um x 240um x 120um (XYZ dimension). A beam with 21nA current was used at 30kV. To mill such large area, the multi-pass pattern was selected to reduce the milling time. It was proven that the multi-pass pattern was about 2.2 times faster than the regular single pattern. Meanwhile, an automated milling operation was set up for such large area, including dynamitic drift control. It took about 12 to 14 hrs to complete the bulk trench. A final cross section cleaning was performed at 30kV and 9nA. The final FIB X-section on the delamination area is shown in Fig.6. It shows the polyimide crack underneath the C4 bump.

completely remove excess Si, it can reduce DB FIB X-section time significantly. DB FIB X-section from the Si backside to detect Polyimide (PI) cracking at the C4 bump was successful and it only took about 11hrs by using 21nA beam current in this particular case study.

Fig.6 SEM image of C4 bump PI crack after DB FIB Xsection 2.

DB FIB X-section from organic substrate side

CSAM on the open failing sample showed die corner delamination (see Fig.7), which suggested that the delamination was inside the die. DB FIB was employed to find the root cause. In order to avoid the mechanical stress induced on the die, FIB X-section was performed from organic substrate side. After parallel polishing to remove substrate material until the C4 bumps were exposed, DB FIB with 21nA current at 30kV was performed on the AOI. Fig.8 shows the SEM images after the organic substrate was removed and the C4 bump was exposed. The trench opening was 160um x 160um x 80um and the same multi-pass patterning with automated milling was selected. After 17 to 19hrs of milling, the trench was completed. A SEM image after the trench was completed is shown in Fig. 8. The final DB FIB X-section after cleaning is shown in Fig. 9. It clearly shows the ILD delamination as the root cause of the failure.

Fig.4 Optical image after ASAP local milling

Fig.5 Optical image after TMAH removing Si above AOI DB FIB X-section on Si backside without any mechanical / chemical thinning requires removing massive amounts of Si material. By using a Gallium Liquid Metal Ion Source (GaLMIS), it provides a typical beam current range of 20-60 nA. This corresponds to a maximum material removal rate by sputtering of ~ 103Îźm3/min for silicon at 60nA [7]. Trenching a 135um x 240um x 120um Si cavity will take about 128hrs for 21nA beam current and 64 hr for 60nA. It is very time consuming. Therefore, by using the combination of Si backside local milling and the chemical etching process to

Fig.7 CSAM on die corner Delamination

DB FIB X-section inside the organic substrate.

A sample with JTAG voltage spec failures was analyzed. Curve trace on the failing pin confirmed a resistive I-V curve. Comparative TDR was performed on the failing unit to determine at what point the impedance profile of the failing unit differed from the known good unit. Fig.10 shows the TDR curve for the failing device compared to the good device and bare substrate (without die). There was a slight difference in the impedance profile of the good device and fail device before the C4 bump interface, suggesting a failure in the package. Further physical analysis was requested to find the failure location and determine the failure mechanism.

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Fig10: TDR curve on JTAG voltage spec failure

(b) Fig.8 SEM images (a) after removing organic package & C4 bump exposed; (b) DB FIB X-section trench

Fig.11 Optical image after parallel delayering above AOI Fig.9 SEM image of die ILD delamination

The exact location of failure can be calculated using material constants and layout information. It suggested that the failure location was in the I/O Cu interconnector layer of the substrate. Based on the isolation, top-down polishing of the substrate was performed and stopped just above the AOI layer. Fig.11 shows the optical image after parallel de-layering above the AOI. To avoid artifacts induced by mechanical polishing on the Cu interconnector, DB FIB was used to perform a X-section on the AOI buried by the organic insulator layer. The substrate trench opening was 450um x 200um x 60um and the beam current used was 21nA. The Xsection took about 4hrs. Fig.12 shows that the failing signal had a very thin copper trace as compared to the neighboring good traces. No mechanical smearing was observed on the Cu trace. The

By increasing the beam current, the X-section time will be reduced significantly. High beam current (65nA) from the upgraded system was used on the failed sample. The trench opening and DB FIB X-section parameter setting was the same as under 21nA beam current. Compared to 21nA, the milling time for 65nA only took about 7hrs. It was about 2x faster and the cross section time was significantly reduced. Compared to DB FIB X-section from Si backside, X-section from organic substrate had reduced the sample preparation steps. It is very useful for die level delamination analysis as it can avoid any external stress applied on the die. 84

thinner area of the failing trace leads to higher resistive drop thus causing the JTAG voltage spec failure. Corrective action was taken based on this root cause analysis.

References [1] Tesch, P., Smith, N., Martin, N., Kinion, D., “High current focused ion beam instrument for destructive physical analysis applications,” Proceedings from the 34th International Symposium for Testing and Failure Analysis 2008, pp. 7-13. [2] Frank Altmann, Matthias Petzold, Christian Schmidt, Roland Salzer, “Characterization and failure analysis of 3D integrated semiconductor devices novel tools for fault isolation, target preparation and high resolution material analysis” Proceedings from the 36th International Symposium for Testing and Failure Analysis 2010 [3] RK Jain, T. Malik “Effects of backside circuit edit on transistors characteristics” Proceedings from the 33rd International Symposium for Testing and Failure Analysis 2007, pp. 29-32 [4] C.R Chen, “Re-thin a TEM lamella by using a novel TEM sample preparation” Proceedings from the 33rd International Symposium for Testing and Failure Analysis 2007, pp. 67-70. [5] B. W. Kempshall, et al., “Ion channeling effects on the focused ion beam milling of Cu.” J. Vac. Sci. Technol. B, Vol. 19, No. 3 (2001), pp. 749-754. [6] Weijinag Yuan, Wenhui Zhu etc “ Pacakging failure isolation with Time-Domain Reflectometry ( TDR) for advance BGA package” 8th International Conference on Electronic Packaging Technology INCEPT, 2007 [7] Shin Ting Liu, Tao Chiliu, “Innovative methodologies of circuit edit of wafer level chip scal package ( WLCSP) devices” Proceedings from the 36th International Symposium for Testing and Failure Analysis 2010, pp. 359-363. [8] Frank Altmann, Matthias Petzold etc, “Characterization and failure analysis of 3D integrated semiconductor device snovel tools for fault isolation, target preparation and high resolution material”, Proceedings from the 36th International Symposium for Testing and Failure Analysis 2010, pp. 163-170

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(b) Fig.12. SEM images (a) DBFIB X-section. (b) Failed copper trace with thinner thickness Conclusions The work presented here showed the successful application of DB FIB X-section in detecting failure mechanisms related to die delamination, C4 bump PI crack, as well Cu trace defects inside the organic substrate with no mechanical smearing or artifacts. Based on the failure signatures, two sample preparation methods for DB FIB X-section were developed. For C4 bump related delamination failures, it is recommended to perform the DB FIB X-section from Si die backside. By combining local mechanical milling and chemical etching to completely remove Si on SOI flip chip packages, it can reduce DB FIB X-section time significantly. For Si die delamination related failures, it is recommended to perform the DB FIB Xsection from the bottom of the organic substrate side to avoid external stress induced on the die during sample preparation. By increasing the beam current from 21nA to 65nA, the Xsection milling rate increased up to 2 times. DB FIB X-section also can be applied to organic substrate defect analysis. This work presented the Cu trace defect inside the organic substrate determined by DB FIB X-section.