How to test USB4 designs

Jit Lim • Keysight Technologies

Designers must look at and characterize the entire Type-C ecosystem when testing USB4 designs.

The USB Type-C connector has received significant adoption with ubiquitous standards like USB, DP, and Thunderbolt. The next-generation variant of USB is USB4. USB4 will transmit and receive on all four lanes of the Type-C connector in parallel, with bonded rates of 40 Gbps in each direction for an 80-Gbps link.

As these signals get sent through even longer passive cables, specialized transmitter and receiver techniques are necessary to preserve signal integrity. They involve new equalization requirements, signaling technologies, and measurement methodologies. Here, equalization at the transmitter and/or receiver serves to mitigate the effect of intersymbol interference and hence, to minimize the bit error rate (BER). In equalization, the signal passes through a filter having its frequency response equal to the inverse of the channel frequency response. A high gain is applied at higher frequency to counter the signal attenuation at the high frequencies. In simple words, equalization is an adaptive filter with coefficients determined at runtime depending upon the physical channel. It takes ultra-lownoise test instruments to properly characterize these highspeed signals.

The USB4 standard was announced in Q1 of 2019 and the specification published in August 2019. Typically, there is often a more lengthy time-lag between the standards announcement and the specification release. But there was only a short period between the USB4 announcement and spec release because USB4 is based on the Thunderbolt 3 protocol.

Earlier generations of USB like USB3.2 could be implemented on the Std A or B connectors, but USB4 must be implemented using the Type-C connector. The USB4 physical data rate is 20 Gbps on one lane with a requirement to run in x2 mode for a 40-Gbps bonded effective bit rate. There are numerous high-speed standards that run much faster. The challenge with USB4 is that the link must work with a lowcost cable that is running as a 20bGbps x4 pipe or 80 Gbps.

THE USB4 ARCHITECTURE

What adds complexity is that a USB4 product must also implement the lower-rate USB4 at 10 Gbps, USB 3.2 at 10 Gbps and 5 Gbps, USB 2.0, and potentially also DisplayPort and PCIe. It might be natural to assume that if the link runs correctly at 20 Gbps, then for sure it would run at 10 Gbps and the slower rates. So why bother testing the lower rates if testing at 20 Gbps passed?

The reason is each of these speed rates takes place under a different set of conditions and experience a different channel loss. So, though a bit rate may be slower, the cable used will be much longer and lossier. There are numerous instances where a link will test fine at 20 Gbps and yet fail at 10 Gbps when tested with a longer cable model.

An understanding of the entire link’s loss budget is critical to designing, testing, and implementing a low-BER system. Comparing USB4 IL to the USB 3.2 IL spec, the loss budget for the link partners has shrunk from 8.5 dB to 5.5 dB at the 10-G rate. So the USB3.2 link implementations may not work with the much tighter USB4 IL budget.

The good news is the cable loss increases from 6 to 12 dB at 10 Gbps. The negative to this relaxed cable loss is that although USB4 10 G runs at the same rate as USB3.2 10 G, it must work with a 12-dB cable and not a 6-dB cable. Thus it’s important to have a thorough understanding of the insertion loss budget.

The next step is understanding where and how the compliance test points are defined. There are no specific rules for naming test-points, so TP0, TP1, TP3’, TP3EQ will mean different things in different specifications.

For USB4 Tx testing, TP2 is the near-end or short channel test point at the Type-C connector. TP3 is the far-end or long channel use case test point - note the definition of TP3 includes the receiver equalization.

For Rx testing, TP3’ would be the short channel test point. TP2 would be the long channel use case. It’s important to know the test points precisely to accurately set up the tests and perform the compliance measurements.

There are significant channel losses with the passive cable use case, so both Tx and Rx equalization are required in the implementation and when testing. When performing Tx testing, it is critical to find the optimal continuous time linear equalization (CTLE) and decision feedback equalization (DFE) setting that provides the largest eye opening. CTLE is a linear filter applied at the receiver that attenuates low-frequency signal components, amplifies components around the Nyquist frequency, and filters out higher frequencies. DFE is a filter that feeds back a sum of detected symbols to the symbol decoder for the purpose of reducing intersymbol interference. Because there is little signal margin, the Rx equalization used during the Tx compliance testing must accurately reflect the specification and should also reflect how the silicon Rx is implemented.

The Tx specification has the common test parameters like voltage, eye diagram, SSC, and rise/fall times. There are also the familiar jitter parameters like UI, TJ, and DDJ. However, there are also requirements for UJ or uncorrelated jitter. In the traditional jitter decomposition model, TJ was split into RJ and DJ. In this case, TJ is split into correlated jitter (DDJ) and uncorrelated jitter. UJ can further be decomposed into RJ and UDJ.

One reason for this finer distinction is a large cross-talk element when 20-Gbps lines run on four differential pairs in parallel over tiny structures and cables. If the jitter decomposition is not implemented precisely per the spec, incorrect jitter analysis results.

A new requirement that did not exist in the USB 3.2 compliance test specification is the return loss test. If the impedances don’t match, the signal from the Tx silicon will never make it to the Type-C connector; nor will the Rx signal going into the Type-C connector make it to the Rx silicon. This test should always take place before Tx or Rx testing. If it fails, there is no point proceeding with the Tx and Rx testing.

Protocol Decode of USB4 Signaling. In parallel, it's necessary to view, trigger, and decode the high-speed 10G and 20G lanes.

TRANSMITTER EQUALIZATION

There has always been the need to characterize the transmitter equalization (Tx Eq). However, in the USB 3.2 spec, there was just one Pre-shoot at 2.2 dB and 1 de-emphasis at -3.1 dB. (As a quick review, pre-shoot and de-emphasis refer to boosts to the signal just before and just after a signal polarity inversion respectively.) For USB4, there are now 16 presets with different combinations of preshoot and de-emphasis.

In addition to testing each of the 16 presets, USB4 requires optimization of the Tx Eq for the optimal eye opening. It is common to over-look the optimization of the Tx Eq or set it incorrectly in the Tx silicon. At 20 Gbps, it is common to fail signal integrity because there are only one or two Tx Eq settings that will work for each specific loss channel implementation.

The various Tx tests discussed so far were at TP2 where the use case is a cable with an embedded retimer, redriver, or an optical cable. But USB4 has the notion of a 0.8-m lossy, passive cable. This is a much more demanding use case. The measurements are essentially like TP2, but must allow for the 0.8-m-cable loss model. This is probably the most difficult test to pass for Tx testing at 20 Gbps.

Like the Tx test cases, Rx testing also has the short-channel use-case and long-channel test cases. Case one is the shortchannel test case where the PG stressed cocktail is applied directly to the Type-C connector. Case two is the significantly more complex use and test case where the BERT-stressed cocktail now must go through the 0.8-m 20-G or 2-m 10-G use case. Improper set-up of the calibration channel or calibration of the stress cocktail will cause either understressing or over-stressing the Rx.

During product turn-on, it is critical to view, trigger, and decode on the SBTx and SBRx low-speed lines for negotiation and debug. In parallel, it would be necessary to view, trigger, and decode the high-speed 10-G and 20-G lanes also. Not having the ability to view all the low-speed and high-speed lanes in parallel curbs the ability to debug the power-on sequence.

In a nutshell, one must view testing of a USB4 design not as an independent entity but in conjunction with the other technologies that must also be implemented simultaneously. Hence one must also consider design simulation, protocol, USB power delivery, channel characterization, side-band testing, Thunderbolt, and DisplayPort. Important as well are the specific instrumentation, software, and fixtures for testing the entire Type-C ecosystem.

References: Keysight Technologies, USB4, https://about.keysight.com/ en/newsroom/pr/2019/12dec-nr19156.shtml