Power & Energy Efficiency Handbook November 2017

Efficient cooling for EV battery packs thanks to CFD Page 10

Early warning for EMC problems Page 15

November 2017

POWER & ENERGY EFFICIENCY HAND BOOK

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POWER & ENERGY EFFICIENCY

The down side of free samples If

HANDBOOK

you’ve had hassles trying to get component samples for a project, you can thank the efforts of a few enterprising students for making your life more complicated.

Here’s a microcosm of what has happened with sample parts: The folks at Texas Instruments used to have a liberal policy about giving out free samples of the firm’s ICs, even those that are relatively expensive.

You could pretty much get a sample through the mail of even pricey chips from TI with few questions asked. According to TI internet marketing V.P. Dave Youngblood, a lot of students took advantage of TI’s largess, but perhaps not in the way the firm expected.

TI began to notice some of the ICs it gave out as samples showed up for sale on sites like eBay. The fact that a given chip is a sample is obvious, at least at TI, from markings on the package. So TI did some digging, Youngblood says. It turned out that a few individuals had what amounted to side businesses devoted to reselling sample chips. The practice was particularly widespread among students, Youngblood says.

The scam was helped along by websites dedicated to giving tips on how to cajole sample chips out of suppliers.

Comments on these sites are still around and are illuminating.

Despite numerous entreaties from posters not to abuse supplier free sample policies, it's clear that a lot of site users do just that. “They shipped everything fast, without questions and absolutely free,” said one student in Germany. “I didn't get any calls and they don't seem to have any hard limit for request frequency, either,” said another. “If you are not a company ... then use Independent Designer or Independent Consultant in the company name field,” was another tip.

TI wasn't the only supplier labeled an easy mark. One poster commented about getting parts from Fairchild (now part of ON Semiconductor): “Their ‘Corporate Address’ checking system is fairly weak. You can successfully sneak past it using a disposable e-mail address ...”

However, those days of easy access to freebie chips are pretty much gone. As Youngblood related at a recent meeting of the Electronic Components Industry Association, these sorts of shenanigans forced TI to tighten its policy on handing out samples. Indications are that other chip suppliers have gotten wise to bogus sample part requests and have become more cautious as well.

Of course, there may be a fine line between being played and accommodating customers. That becomes evident when talking to suppliers of passive components. Those we've asked don't have the same black-market problems experienced by chip suppliers. They say the closest thing to abuse arises among customers needing to build prototypes. The typical scenario is where the usual limit is six samples and prototypes might need 12. “In this case, they may order six pieces from two different distributors or six pieces directly and the rest through a distributor,” says one.

The usual policy is to just send out the parts. “What we came to realize is that the cost of the samples is insignificant. The benefits of providing customers what they need is far more beneficial. But we still don't have an anything-you-want policy. We still qualify each sample request,” says one distributor.

So the next time you call a supplier and get the third degree about a free sample, you can thank unscrupulous individuals trying to run a hustle for your extra trouble.

LEE TESCHLER | EXECUTIVE EDITOR

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INSIDE POWER & ENERGY EFFICIENCY HANDBOOK

22 The fundamentals of supercapacitor balancing

02 The down side of free samples

06 How power suppy efficiency has evolved Manufacturers aren’t done making power supplies more efficient. There are likely to be governmental regulations in the future that dictate even more severe constraints for supply manufacturers.

24 Longer battery life for hearables and wearables

10 Efficient cooling for EV

battery packs thanks to CFD

Advanced 1D and 3D computational fluid dynamics simulation techniques can help analyze the thermal properties of battery cooling packs powering electric vehicles.

Engineers who wait until the end of the design phase to check for unwanted electromagnetic emissions run the risk of incurring big delays.

vehicular LED drivers There are numerous features in the electronics that power vehicular LEDs that you won’t find in other LED applications.

A review of SiC MOSFET performance data shows these devices have improved dramatically in a short time. And improvements are likely to continue.

34 Tougher stress tests for automotive MOSFETs

19 The differences between vehicular and non

Single-inductor, multiple-output circuitry can provide the kind of high conversion efficiency necessary for super-small consumer electronics.

29 Guaging progress in SiC MOSFET technology

15 Early warning for EMC problems

The low voltage available from a single supercapacitor forces most applications to use several supercaps in series. Here are the tricks involved in stringing these components together.

Current automotive quality standards may not be selective enough for power electronic devices that will run next-generation vehicles. Device makers are responding with their own more stringent test regimes.

38 Fuses that blow safely

New fuse technology designed specifically for electric vehicles helps meet stringent automotive reliability standards.

06 19

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HANDBOOK

POWER & ENERGY EFFICIENCY

The short cable and lack of LED indicators on this external supply highlight the initial recommendations for how to boost power supply efficiency to meet more stringent regulations.

How power supply efficiency has evolved INVENTUS POWER

Manufacturers aren’t done making power supplies more efficient. There are likely to be governmental regulations in the future that dictate even more severe constraints for supply manufacturers.

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The

latest DoE energy efficiency requirements won’t be the last. Here are a few of the changes in efficiency regulations the power supply industry can expect.

As early as the 1990s studies showed that smaller external power supplies -- such as those powering cell phone chargers, game boxes, cordless phones, and so forth -- were becoming a major source of energy demand and were growing explosively. It also soon was obvious that the reduction of energy consumption in power supplies sitting idle but connected to power lines was even more important to reducing overall power consumption. Thus began demands that the power supply industry build more efficient power supplies to reduce the waste in energy consumption.

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HOW POWER SUPPLY EFFICIENCY HAS EVOLVED

In 2004, California became the first government organization in the U.S. to declare legal energy efficiency requirements, followed by the U.S. government with the Energy Star program, a voluntary but not mandatory requirement for efficiency.

When the DoE first came out with its proposal for efficiency standards, the reaction from the power supply industry was enormous and severe. The new standard was to be 88% at 50 to 250 W, with a sliding scale of 85 to 88% between 18 and 50 W, and a maximum no-load input draw between 0.1 and 0.21 W. The previous requirements were also a sliding scale to 49 W, with 80% at 18 W, and 86% at <49 to 250 W, and between 0.3 and 0.5 W at no-load. The biggest changes were expected in the lower powered units, nearly a 10% improvement at 18 W, where factors like voltage drop through the output cable is a fixed loss.

On top of the overall efficiency, the no-load power consumption was to drop to nearly onethird the current requirements. All the changes needed to bring power supplies into compliance with the technology available at that time forced the loss of features that consumers wanted, such as removing LEDs and shortening cables from the typical six feet to four feet, or even to just two feet. Even with those changes, power supply engineers were saying they could barely meet the requirements and still maintain a reasonable cost; initial forecasts from the industry were suggesting a two-dollar-per-unit rise in price to the consumer.

Consequently, the DoE delayed issuing the ruling by almost a year. During that time, the LED industry made significant advances in brightness while dissipating considerably less power. The designers of power supply control chips also took that time to devise new control chips able to realize higher efficiencies, particularly by boosting efficiency levels at lighter loads (~25% of full rated power).

When the DoE did release requirements in 2014, the industry had better technology and components to comply with the new regulations. eeworldonline.com | designworldonline.com

Inventus — P&EE Handbook 11-17.indd 7

Still the changes are not without cost. The two-dollar boost was no longer a concern, because the price of power supply controllers has come down as higher volumes and improved efficiencies allowed manufacturers to reduce box size. These improvements offset much of the cost rise, but there were also additional expenses. New control chips forced new design layouts, new production fixtures, new safety certificates, and managing soon-to-be obsolete product stocks.

At Inventus, we also found errors in the first control chips released for higher power levels, i.e.

150 W+, which delayed development programs until improved versions were ready. Many power supply companies came out with new model numbers that forced customers to reopen their safety files at an average cost of $8K to $10K each. Roughly half our OEM customers of information technology equipment (ITE) power supplies had to requalify our products.

We chose to keep the same model numbers so our OEM customers could minimize updates to their safety reports. But we recommended they at least perform a system evaluation and repeat their EMI testing. Even with an external power supply, EMI must be tested with the entire assembly. While our EMI profiles are close to those of our previous power supplies, they are not exact. If one of our frequency peaks happened to shift slightly closer to that of the main system, the combined EMI at that frequency could exceed allowed limits, forcing additional design work.

Additionally, all power supply manufacturers had to finish their design and agency approvals within two years. The reason was OEM customers needed time to complete their evaluation and clear out their inventory before the February 2016 deadline.

There continues to be confusion in the market as to whom the new standards apply. The standard is ~80 pages long, with only a few pages specifying the requirement, the rest explaining the reasoning behind the final version. There are lots of suggested inputs from people in the industry which, if you don’t realize you are reading a suggested input, can be misunderstood to be part of the requirement.

Additionally, the power supplies the commission tested are all from electronics found in the home such as cable boxes, game boxes, and toys. The commission only found one multi-output power supply in everything they tested, in a game box. But 11 • 2017

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we know that multi-output power supplies, although declining, still find use in the industrial world. One might infer that the standard aims at home-based applications, though this is never explicitly stated. The obvious ambiguity has led many industries to require the standard in their non-consumer products to safeguard against future problems, while also being able to advertise their use of the latest technology.

As efficiency requirements are becoming ever stricter. The European Union’s Code of Conduct (CoC) Tier 1 came out as a voluntary requirement in January 2014, mostly harmonizing the EU with US DoE Level VI. The main difference between the two is a slightly less severe noload consumption requirement.

Its adoption as an EU Ecodesign rule is currently under review with a targeted implementation date sometime this year.

The EU’s more stringent CoC Tier 2 requirement became effective on a voluntary basis in January 2016 and is also under review

to become law as an Ecodesign rule, potentially in 2018. The key difference between the CoC Tier 2 and Level VI is a new 10% load efficiency measurement, which imposes efficiency requirements roughly 10% lower than the overall requirement when the power supply is running at 10% load. The control chips designed to meet Level VI efficiency should allow most supplies to meet the new requirements, but all designs will need to be rechecked for compliance. Historically most power supplies have been terribly inefficient at light loads, considered to be anything under 25% of full load.

Efficiency requirements are not the only changes in power supply regulations. Sometime this year the EU is expected to release its approval of a new agency standard 623681. This new standard combines the Information Technology and the Audio-Visual standard into one document. The US has decided to grandfather-in any device which already has 60950-1 approval but will require testing to 62368-1 for

new submissions as of June 20, 2019.

The EU is expected to declare that to maintain a CE mark, products must be recertified to 62368-1. No design changes should be needed, but it’s another cycle of testing and reports to be borne by the power supply manufacturers and their customers.

As consumers of electric power, we appreciate the savings efficiency regulations bring both in our own electric bills and in avoiding the need for additional power plant capacity.

However, the stricter efficiency needs have brought a high turnover in products over the last three years, and the trend is expected to continue. Gone are the days of a design having a graceful retirement after ten years. Companies that want to stay relevant in the market now need to plan on continuing updates and engineering costs to support their products.

References Inventus Power, www.inventuspower.com

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POWER & ENERGY EFFICIENCY

Efficient cooling for EV battery packs thanks to CFD DOUG KOL AK, BORIS MAROVIC, STEVE STREATER | MENTOR, A SIEMENS BUSINESS

Advanced 1D and 3D computational fluid dynamics simulation techniques can help analyze the thermal properties of battery cooling packs powering electric vehicles.

The

cooling system for an electrical vehicle’s battery pack is slightly less complex than that for a hybrid. It is generally a liquid-cooled system that includes the battery pack, preheater, pump, and coolant reservoir. The battery pack of an EV looks, electrically, like rows of cells. A medium-sized EV battery might consist of large cells divided into six rows with eight cells in each row.

The coolant flow can be either directly around the cells, with cold plates between them, or even around the other end of some heat pipes arranged between two battery cells. A thermal analysis with CFD can look at various design possibilities; there’s a need for flexibility because the design must be optimized for pressure loss and thermal management.

Here’s how an EV battery pack might appear when modeled with a 3D CFD program.

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EFFICIENT COOLING

BATTERY COOLING IN 1D

Battery cooling packs modeled in 1D CFD. A 1D-CFD simulation, also called system level CFD, is a type of CFD simulation that focuses on the entire system rather than on the details of a specific component.

For an analysis down to the component level, 3D CFD allows a study of detailed flow and thermal behavior. Any unacceptable operation such as misguided flow patterns or extreme thermal gradients can be identified early in the design. Later in the process when the performance of the entire battery cooling system is the main concern, 3D CFD helps create a more accurate 1D system simulation, ensuring proper system performance.

Characterizing battery cells with 3D CFD The main consideration in the design of a cooling pack is ensuring all cells in the battery remain at the same temperature.

It is important to manage temperature in individual cells because high gradients within

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a battery cell can cause fast degradation and early failure.

A 3D CFD program can analyze flow paths through the pack as well as the pressure drop, velocity, heat transfer, and local temperatures to evaluate pack performance. In the past, highly trained specialists handled this type of CFD analysis; however, a CAD-embedded, 3D CFD thermal simulation tool such as FloEFD allows designers and engineers to analyze pressure drop and thermal performance without the need to call in a CFD guru.

The tool runs natively from the same MCAD software used to design the battery cooling pack. Consequently, there’s no need to create a separate CFD model, and any redesigns can take place immediately. This strong CAD linkage is especially interesting when the design is at an early stage and a lot of changes are still necessary. The tight CAD linkage allows faster iterations of the overall thermal design while providing a good characterization of the battery cell.

In comparison, a 1D CFD tool called FloMaster is good for focusing the analysis on the overall performance of the system and for identifying how the components of the system interact. Overall performance data is difficult to capture and takes much longer using 3D CFD. One of the important design considerations is how to model the battery cooling pack. It would be easy, and can be acceptable, to A surface map of cooling model it as a pack temperature versus single lumped coolant flow rate and cell component load from the results of a using an overall parametric study of the heat transfer example cooling pack. coefficient and combined thermal duty.

However, accuracy is important, so the pack is modeled as individual cells to ensure the capture of any temperature gradients across the pack. This

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POWER & ENERGY EFFICIENCY

T I M E ( M I N . ) T O R E A C H M I D - P A C K T E M P . O F 2 0O C 2kV

3kV

4kV

5kV

6kV

7kV

8kV

9kV

10kV

500 rpm

36.5

24.2

18.1

14.5

12.1

10.3

9.1

8.1

7.3

1,000 rpm

37.0

24.5

18.3

14.6

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HANDBOOK

information can be handy in the event of redesigns.

Also, the pressure loss and heat transfer associated with the piping in the system is considered negligible.

Thus, the model excludes these parts of the system.

One of the biggest benefits of using 1D CFD is that analysis can take place quickly, especially for transient events. However, 1D CFD requires significant amounts of data to describe the physical phenomenon going on inside each component.

But FlowMaster has a substantial built-in database of empirical data for a wide range of geometric components such as valves, bends, and junctions.

In the example battery pack, temperature statistics reveal pump speed has little influence on warm up time.

This built-in information minimizes the need for finding performance data via testing or from the manufacturer.

The characterization data obtained from 3D CFD can be used inside the 1D model. For example, the battery cooling pack components in FlowMaster can use the characterization of the pressure loss as well as of the heat transfer from the FloEFD analysis. Once both the 1D and 3D CFD models are constructed, data such as the maximum heat rejection rate of 30 W/cell can be used for analysis in both software programs.

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EFFICIENT COOLING

Example of a trendline for sustained battery cell load with coolant flow rate. This could be used as a starting point for any tuning of pump control algorithms.

Analysis for peak condition cooling Suppose we want to find an appropriate volumetric flow rate to keep the system under the 40 ºC critical temperature for a lithium-ion battery. The industry has used a 30–40ºC temperature band as the general guideline for preserving the lifetime of these costly battery packs. We’ll use a worstcase scenario to ensure the system can meet the heat rejection requirements without the use of the cabin A/C circuit often pressed into use for highdemand cooling applications.

We keep the heat rejection into the cooling system at 30 W/cell and vary the pump flow rate from 2 to 15 L/min when conducting a parametric study using the FloEFD simulation software. This heat rejection rate will determine the minimum pump volumetric flow rate needed to keep the battery pack under 40ºC using a 50/50 glycol/ water coolant and 20ºC ambient temperature.

The minimum flow rate that ensures all sections of the battery pack stay below 40ºC is about 9.5 L/min or 2.5 gal/min. A simple crosscheck with the pump supplier can ensure that the pump selected for the system meets this requirement.

With the minimum volumetric flow rate determined, we’ll want to understand how the cooling pack performs under a range of operating conditions, particularly during changes in coolant flow rates and cell loads. Again, a parametric study of the cooling pack in FloEFD can produce data for a surface map of cooling pack temperature versus coolant flow rate and cell load. This map provides a quick reference showing the ideal conditions the cooling pack should see and gives an opportunity for redesign if necessary.

The surface map can be used to deduce a trend line that shows battery cell load versus pump performance. This data can serve as a starting point for tuning the pump control algorithms.

For example, an intended battery cell load of 20 W requires a coolant flow rate of 5.5 L/min, which would allow the battery to stay below the critical temperature of 40ºC. Besides helping to create a pump control algorithm, the surface map aids in characterizing the cooling pack’s thermal performance. This thermal data, along with the pressure drop data, is all that is required to model the cooling pack in FloMaster.

Warm-Up from cold start After the initial component-level design has been vetted with 3D CFD analysis, it is important to investigate how it will perform within a system. A critical real-life challenge for EV battery systems is a cold start because there is no internal combustion engine to provide heat. Imagine a winter day in Chicago at -10ºC. The vehicle battery pack must reach an acceptable operation temperature (AOT) within a reasonable time. With no ICE to provide heat for cold startup, there’s a need for a positive temperature coefficient (PTC) heater.

In this example, the battery pack needs a 3-kW heater to reach an operating temperature of 20ºC in less than 30 minutes.

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Two quantities can be varied in this simulation, pump speed and PTC heater size.

The acceptance criterion is the cooling pack reaching 20°C in less than 30 minutes.

In this example, we’ll analyze high and low pump speed with heat power ranging from 2 to 10 kW. Apparently, the pump speed has little influence over the total warming time. Running at half speed will reduce the load on the auxiliary battery while not affecting warm-up time.

This insensitivity to pump speed means we need only vary the size of the heater in the design parameters. The smallest PTC heater that would work for the system is 3 kW which brings an AOT of 20°C in less than 30 minutes.

Now consider the time at which the front of the pack and the rear of the pack get to the AOT during battery warm-up. In this example, the rear cells in the pack reach the temperature of the front cells after five minutes. The front cells sit closest to the heater.

Another interesting point in the warm-up study is that a snapshot shows a difference of 5ºC between the front and rear of the pack. If that difference didn’t meet design objectives, you could re-run the analysis with, say, a higher flow rate, an extra heater added for the rear cells, or the flow geometries reconfigured to create better flow around the pack.

References FloEFD products, www.mentor.com/products/ mechanical/floefd/

Proven integrity AND industry know-how Electrocube is one of the most respected design manufacturers of passive electrical component products for a wide range of standard and custom applications – from aerospace and audio to elevators and heavy equipment – as a capacitor supplier, resistor-capacitor distributor, and more.

ELECTROCUBE.COM | 800.515.1112 | INFO@ELECTROCUBE.COM

Electrocube -- P&EE 11-17.indd 101 11-17 V4.indd 14 Mentor Graphics — P&EE Handbook

11:41 AM 11/6/17 11:42

EARLY WARNING FOR EMC PROBLEMS

Early warning for EMC problems BRUCE ROSE | CUI INC.

Engineers who wait until the end of the design phase to check for unwanted electromagnetic emissions run the risk of incurring big delays.

One

design activity often left to the end of a project is the verification a product meets electromagnetic compatibility (EMC) emissions requirements. Considering EMC compliance earlier in the design process helps avoid unexpected costs and project delays.

At low frequencies (less than about 30 MHz) the conductors and cables of most electronic devices are ineffective as antennas so radiated emissions are not an issue. At these low frequencies the conductors and cables can conduct RF energy through shared power sources or loads and cause issues with other electronic products. At high frequencies (above about 30 MHz) the impedances of the conductors and cables attenuate conducted energy enough to keep it from being an issue. However, conductors and cables can act as antennas at these higher frequencies and radiate RF energy, potentially interfering with nearby electronics.

Most industrial and consumer electronic products sold in the U.S. must meet conducted and radiated emissions standards as described in FCC regulations Title 47 Part 15, often referred to as FCC Part 15. Similar standards for products sold in Europe are governed by European regulations CISPR 22/EN 55022. Both sets of these regulations describe limits for conducted and radiated emissions and apply to the final system, including the internal or external power supply.

These two sets of regulations are created and administered by separate organizations but they have been constructed to be similar or “harmonized.” One benefit of harmonizing these regulations is that a product designed to meet one set of regulations typically will also satisfy the requirements set forth in the other.

Conducted radiation specifications cover emissions in the frequency range of 150 kHz through 30 MHz. A separate set of radiated emissions specifications covers the eeworldonline.com | designworldonline.com

CUI — P&EE Handbook 11-17 V4.indd 15

spectrum of 30 MHz and greater. Test procedures and tools are slightly different for conducted versus radiated emissions, and the filter components used to mitigate the EMC issues are similar but differ in electrical values. Because the conducted emissions frequency band is lower than the radiated emissions frequency band the filter components used to address conducted emissions will be electrically and physically larger than those for radiated emissions.

EMC for power supplies Most internally mounted power supplies are designed and tested to meet EMC regulations. The testing takes place with the supply configured as a stand-alone product. Once the power supply has been installed into a system the completed assembly must also be tested to ensure it meets EMC regulations.

Incorporating compliant power supplies minimizes the potential for EMC-related issues during system testing, but

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HANDBOOK

it does not guarantee the completed system will pass emissions testing. Many vendors of internally mounted power supplies will provide recommended circuits to address EMC issues encountered during system integration. Because the requirements vary with each application, these recommendations are left to the discretion of designers; this way each design incorporates only the components needed for the specific application.

Similarly, most wall plug and desktop versions of external power supplies are also designed and tested to meet EMC regulations as stand-alone units. OEMs combining the power supply with a load must test to ensure the complete system meets EMC regulations. As the circuitry on wall plug and desktop versions sits in an enclosed case, it will be more challenging to add external components for EMC issues.

TYPICAL INPUT-FILTERING COMPONENTS

Safety Ground

A typical front-end filter to prevent conducted emissions in a power supply. Here X capacitors are connected between the line phases and are effective against symmetrical interference (differential mode). Y capacitors are the EMI capacitors that connect from the input power feeds to chassis ground and are effective against asymmetrical interference (common mode). Sometimes they connect from each converter’s power output terminal to chassis ground as well.

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Part 15 of FCC rules specifies that any spurious signal exceeding 10 kHz is subject to regulation. It also says radiated emissions must be controlled between 30 MHz and 1 GHz, and conducted emissions must be controlled in the frequency band between 0.45 MHz and 30 MHz. The FCC classifies electronic equipment using SMPS power supplies as either Class A or B. Class A signifies use in the commercial, business, and industrial environments, and Class B is for the residential space.

EMC regulatory testing of power supplies is performed with static resistive loads, but almost all power supplies are based upon switching regulator topologies. A switching regulator inherently produces conducted and radiated emissions which need to be mitigated in the design of the supply. The load applied to the power supply may create additional emissions. The uncertainty of the conducted and radiated emissions from the combined power supply and load is addressed by allowing a margin in the stand-alone power supply test results to take into account variations when a load is applied to the power supply.

The case for early testing Reasons for putting off EMC testing until the end of a project often include time, cost and workload constraints. Engineers unfamiliar with compliance tests also tend to think the necessary test regimes are difficult. In reality, it does take special equipment and facilities for EMC compliance testing, but many test labs have the experience and means to handle the job.

The costs associated with compliance testing often become a case of “pay me now or pay me more later.” It can cost a lot to run tests for full certification at the end of the design process. But for preliminary screening eeworldonline.com | designworldonline.com

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EARLY WARNING FOR EMC PROBLEMS

LISN IN USE

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Conducted emissions test set-ups use a line impedance stabilization network (LISN) as specified in various EMC/EMI test standards as from CISPR, the IEC, CENELEC, FCC, and in MIL-STD tests. A LISN is a low-pass filter used to create a known impedance and to provide an RF noise measurement port. It also isolates the unwanted RF signals from the power source.

Industrial

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the cost is minimal. And getting test time can be an issue as many labs are booked up several weeks out. However, they can often find small blocks of time for preliminary testing outside of peak hours. The small amount of resources spent performing preliminary EMC testing early in the design cycle may prevent considerable and expensive redesign efforts late in the development effort.

Another common reason for delaying EMC testing is the misconception that the power supply causes the EMC issues.

The thinking then goes that the system will be EMC-compliant if the supply has already passed stand-alone regulatory testing. In many instances, the power supply gets the blame for EMC issues within the system when in reality it is “only the messenger.”

Rather than wait for the project’s final phase, it’s often a good idea to run preliminary EMC compliance tests once system assembly has begun. Early in a project, schedules are more flexible and design teams are more receptive to modifications.

By the end of a project much effort has been put into design work. So the power supply is often perceived as an easy target for EMC compliance efforts that won’t degrade system performance. It is sometimes possible to add simple chokes and capacitors to address EMC issues, but these 11 • 2017

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measures mitigate the effects of the problem and don’t address its source.

One issue with adding EMC suppression to the power supply is that it may void the supply’s safety certificates. Changes to the safety certificates may also force the power supply vendor to get involved.

The system circuitry may need modifications to minimize emissions if the addition of a few passive suppression components won’t do the job.

The typical way of adding noise suppression on products which use internal power supplies is through components either on the supply input or output conductors, usually bypass capacitors and ferrite cores. Ferrite cores add inductive impedance in series, and bypass capacitors provide a lowimpedance path to ground for noise signals.

There may be fewer options for EMC suppression in systems employing external power supplies. A ferrite core on the cable between the power supply and the system may help with radiated emissions. The frequencies associated with conducted emissions are low, so the ferrite core needed to mitigate them might be too big for many applications. A better way to deal with conducted emissions in external power supplies is to either select a different external supply or have the power supply vendor modify the design.

SIMPLE RADIATED EMISSIONS TEST SETUP

The general approach to measuring radiated emissions is to position the EUT a known distance away from the receiving antenna. This distance must be greater than three wavelengths at the lowest frequency of interest, but 10 ft. is the usual distance. The magnitude of the loss of any cabling between the receiving antenna and the spectrum analyser must be known, as is the antenna gain for the frequencies of interest. Similarly, the sensitivity of the spectrum analyzer attached to the antenna is also known. The path loss over the distance between the EUT and the antenna can be calculated. With this setup, the amplitude of the signal measured at the spectrum analyzer will indicate the amplitude of the EUT radiated emissions.

Pre-compliance testing Final testing of conducted and radiated emissions must take place in a certified laboratory using calibrated test equipment.

But testing labs will also cooperate to perform pre-compliance testing early in the design phase. Additionally, design teams can conduct pre-compliance testing with a minimal amount of test equipment.

The basic equipment needed for conducted emissions testing is an LISN (line impedance stabilization network) and a spectrum analyzer. The LISN is a passive network used to minimize the noise conducted from commercial power lines. It also provides a controlled impedance test port to monitor the conducted emissions from the EUT (equipment under test). The spectrum analyzer can be a basic model that spans 150 kHz through 900 MHz. Many spectrum analysers can perform quasipeak measurements and incorporate conformance parameter limits in the display to simplify EMC compliance testing.

For checking radiated emissions, spectrum analyzers should be able to measure from 30 MHz through at least 900 MHz. The ability to perform quasi-peak measurements and display 18

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conformance parameter limits in the display are both helpful. The antenna should have a bandwidth similar to the spectrum analyser. And antenna gain vs. frequency qualities must be known.

Radiated emissions tests generally take place in RF screen rooms with at least three meters (10 ft) between the antenna and the EUT. An initial measurement in the room with the EUT powered off can characterize the ambient RF noise that will be present during testing.

References CUI Inc., www.cui.com

eeworldonline.com | designworldonline.com

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THE DIFFERENCES

The differences between vehicular and non-vehicular LED drivers J A T I N T H A K E R , DAV E S T R Y C H A R Z | N X P AU T O M O T I V E

The

automotive market is quickly moving away from traditional incandescent lighting towards more intelligent systems that promote reduced energy use, safety, and individualization options that boost brand recognition. Automotive LEDs now extend their light range, automatically adapt beam patterns to changing traffic situations, and last longer than older lighting technology. Automotive lighting systems are also changing to support autonomous driving functions with dynamic front lighting or glare-free high-beams for pedestrians and lane markers.

LED drivers for the automotive market are designed with reliability requirements of the industry in mind. Products must be qualified according to AEC-Q100, which is a failure mechanism-based stress test qualification for integrated circuits. This qualification means automotive LED drivers are reliable and have a long lifetime in high ambient temperatures and in challenging electromagnetic compatibility (EMC) situations.

Automotive LED drivers also sport several facilities not found in drivers aimed at other uses.

For one thing, smart LED drivers can communicate with other vehicle electronics and exchange essential data for lighting control. Also built-in is a means of configurability, as well as diagnostics LED DRIVER PLATFORM to support functional safety requirements at the system level specified by ISO 26262 standards.

There are numerous features in the electronics that power vehicular LEDs that you won’t find in other LED applications.

Here’s one example of what LED drivers targeting vehicular uses can do: The NXP Matrix LED Controller (MLC) can drive LED segments and pixel arrays. A single chip drives 12 LEDs, 32 chips will drive 384 LEDs. This matrix driver chip could let future LED headlight systems put on their own small-scale version of a drive-in theater experience. The idea is to individually control each LED in the headlights to, say, spell out “Ford” or “BMW” on a garage wall when the car starts. Features of the MLC that distinguish it from other kinds of LED applications include a limp-home mode – if the driver loses its connection with the vehicle central controller at start-up or in steady state operation, the LED headlights stay turned on.

The chip can also detect and diagnose open/ short conditions in each LED and implements a bypass feature. eeworldonline.com | designworldonline.com

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LED drivers targeting automotive use include this two-phase boost converter. The two-phase mode reduces the size of the magnetic components for easier packaging. LED drivers in vehicle typically communicate with a remotely located vehicle computer. Consequently, this IC includes an SPI communication interface and a timeout function to detect a break in the SPI communication lines. If a problem arises, the IC can power the LEDs in a limphome mode so the vehicle doesn’t lose its lighting.

POWER & ENERGY EFFICIENCY

ASL2417SHN: 2 CHANNEL BUCK LED DRIVER

HANDBOOK

The ability to monitor LED operation allows for accurate control, promoting light uniformity and protective measures such as on-chip temperature measurement, detection of lamp open, short circuits, and much more.

The extensive requirements and testing involved in vehicular applications generally force vehicle electronics to have a longer design cycle and production cycle than that of other applications. So it is important to capitalize on design re-use wherever possible. Also, industrial applications are often sole-purpose designs. This means the loads, lifetime and environment are all known and easily predictable. But this is rarely the case for automotive applications.

Consider an automotive headlamp module – it could be configured in multiple ways to accommodate different

vehicle platforms, each with a different style and functions. In addition, automotive applications typically have requirements to ensure constant brightness and color, controllable brightness and built-in safety mechanisms. The challenge of dealing with ambient temperature and power dissipation and mechanical stress are also higher in automotive applications. NXP addresses this challenge with modular reference designs complete with inductors, capacitors and other components. These reference designs can then be scaled up or down to optimize feature sets for different platform models.

The LED driver module used for exterior vehicle lighting is driven from the 12-V car battery and is specifically designed to handle high power, around 150 W. The power output requirement is specified by the OEM. But in general, output must remain constant down to 9 V and can have some diminished operation down to 6 V. For consumer or domestic uses, power requirements vary widely. There are low-power dc-dc converters for mobile handhelds, medium-range power requirements for home LED lamps, and applications like solar street lighting may have reasonably high wattage.

Today it is possible for automotive solid-state lighting

NXP Multi-channel N X P MDriver U L T I - CEvaluation H A N N E L D Board R I V E R E VA L U A T I O N B O A R D - Complete system solution from NXP

CAN (e.g. for ASL5xxx – Matrix Drivers)

S32K Evaluation Board

LIN

New Boost Buck Evaluation Board

3 channel buck driver IC

Power FET

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Inductor coil 4 Phase Boost converter

An evaluation board for the MLC chip from NXP and LED array boards. The eval board helps implement LED matrix operations that might find their way into vehicular LED headlights.

Free wheel diode FET

PUBLIC

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THE DIFFERENCES

(ASSL) systems to power multiple groups of loads more efficiently- say LED, OLED and laser diodes in the same lighting module. The light control unit (LCU) usually contains a microcontroller and one or more transceivers to communicate with the body control module (BCM). A boost voltage regulator and an independent constant-current source will drive different LED or laser diode functions.

As it is a two-stage topology, the voltage source is more stable for a wide range of battery conditions, but still able to respond to dynamic loads in each stage. The NXP boost driver IC can provide two independent voltages from one boost IC, controlled individually via an SPI interface, resulting in higher system efficiency and phase interleaving to deliver a higher overall power to the application.

The buck channel uses a hysteretic buck converter with an integrated bootstrap diode. This topology optimizes efficiency while delivering constant (controlled) current within an accuracy of ±5% across the temperature range of -40 to 125°C. A flexible platform for multi-channel automotive LEDs allows an efficient combination of loads driven with a common architecture, so all LED string configurations and matrix, or segment switching, can be driven through one platform.

LED drivers go beyond simple road illumination. They are electronically managed to combine the power and data processing that is essential for ADAS applications. This is seen in dynamic lighting, marker beams, laser and highcurrent LED spots that use dynamic switching of individual LEDs or segment LED control. Such tasks require a large amount of real-time information exchange with the BCM. One key challenge for these types of applications is in delivering the high number of channels, signal processing, and necessary functions. These needs put a strong focus on thermal management and system efficiency.

References

NXP automotive LED lighting, nxp.com/products/automotive-products/energypower-management/lighting-driver-and-controller-ics/ automotive-lighting-led-driver-ics:MC_71502?fsrch=1&sr =1&pageNum=1

you could incorporate the switch functionality of a circuit breaker with the high protection level of a fuse?

New Fused Disconnect Switch UL98 Rated for CC fuses up to 30A & 600V The new Fused Disconnect Switch (FDS) series incorporates the switch functionality of a circuit breaker with the high protection level of a fuse. The FDS allows end-users to shut off and isolate branch circuits in electrical control systems in order to safely perform maintenance on the downstream circuit components.

To view the product data sheet and learn more about the FDS, please visit: www.marathonsp.com/New Products/Fused Disconnect Switch Regal and Marathon are trademarks of Regal Beloit Corporation or one of its affiliated companies. ©2016 Regal Beloit Corporation, All Rights Reserved. MCAD16061E • SB0045E

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POWER & ENERGY EFFICIENCY

The fundamentals of supercapacitor balancing R O B E R T C H AO | A D VA N C E D L I N E A R D E V I C E S I N C .

HANDBOOK

TYPICAL CHARGE/DISCHARGE CYCLE

The low voltage available from a single supercapacitor forces most applications to use several supercaps in series. Here are the tricks involved in stringing these components together.

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For example, in a batch of supercapacitors it is possible to find one cell rated at 2.7 V with a capacitance value of 100 F next to one at 127 F. If these two cells are wired together in a 5-V stack, one could settle at 2.2 V and the second could reach 2.8 V, which is out of spec.

The usual way of dealing with these imbalances is to put a balancing circuit in parallel with the supercapacitor stack.

One such technique places a The charging cycles of a supercapacitor. bypass resistor in parallel with each cell, sized to swamp out average supercapacitor has the cell leakage current. When a maximum charging voltage resistors with the same value are in parallel of between 2.5 and 2.7 V. For many with all cells, the cells with higher voltages applications a voltage this low isn’t will discharge through the external resistor particularly useful, so the common practice at a higher rate than the cells with lower is to place multiple supercapacitor in voltages. This action helps distribute series. Unfortunately, supercapacitors may the total stack voltage evenly across the have a tolerance difference in capacitance, entire series of capacitors. Applications resistance and leakage current. These with a limited energy source or high level differences create an imbalance in the of cycling might use an active voltage cell voltages of supercapacitor wired in balancing circuit instead of a resistor series. It is important to keep the voltage network. The active balancing circuit on any single cell below its maximum typically draws much less current in steady recommended working voltage. Otherwise state and only requires larger currents the supercapacitor could degrade from when the cell voltage is out of balance. electrolyte decomposition, gas generation, But the problem with balancing or a rising effective series resistance (ESR). circuits is that they are ineffective if The factor that initially dominates there is too much variation among the imbalance is the capacitance difference cells. To avoid this, a designers should between cells -- a cell with a lower pre-measure and pair supercapacitor capacitance will charge to a higher together with similar capacitance values. voltage in a series string. Supercapacitor Given the example above, designer capacitance values may differ as much would group all cells together with a as ±20% (total of 40%) from cell to cell. capacitance value between 100 and 110

The

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THE FUNDAMENTALS

F. Similarly, all cells between 120 and 130 F should be sorted and placed in the same supercapacitor stack.

After each cell is tested and matched, the next step is to test each supercapacitor for leakage current. Manufacturers often do not provide or guarantee leakage values, so designers must determine this parameter before placing a cell in a circuit for balancing. A standard method for gauging leakage current is to power up the supercapacitor with a small resistor such as 100 Ω at 2.7 V over 96 hrs. to measure a settled value. The initial current into the cell is the supercapacitor charging current.

Once completely charged, any residual current detected determines the dc leakage current. Notice only a max leakage is mentioned, as a cell could have values that vary widely from those of other cells but can be balanced if leakage is below an allowed value.

Thus, there are four steps that will ensure cells in a series stack will balance.

1. Determine the individual capacitance value of each cell.

2. Group the supercapacitor with similar capacitance values together.

To realize voltage levels that are within limits for each cell in the stack, the capacitance values of each cell must be reasonably close to that of other cells.

3. Once the cells are grouped by capacitance values, determine the leakage currents of each group.

4. Finally, group together cells that have similar capacitance and leakage current.

The next step is to choose a balancing method suitable for the currents involved. For example, if the leakage current spec is 23 µA, a SAB (supercapacitor auto

TYPICAL AUTO BALANCING M O S F E T A R R AY A P P L I C A T I O N

The schematic of a fully-populated SABMB16 with three MOSFET arrays. The design ensures the voltage across each supercapacitor (VA – VB, for example) does not exceed the maximum allowed value.

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ALD — P&EE Handbook 11-17 V2.indd 23

balancing) MOSFET could be used to balance leakage currents up to 230 µA (up to ten times the nominal max leakage current value).

With the balancing method determined, it's time to place two similar leakage-tested supercapacitors in series and power them up. For example, if the voltage rating is 2.7 V for each cell, then the two-cell stack may be operated at 5 V, which leaves a 0.2 V voltage margin. A more conservative operating voltage range may be 4.2 to 4.6 V instead of 5 V. The balancing method should result in little or no change in the voltage over time. A SAB MOSFET, for example, will balance the supercapacitor by preventing leakage current imbalance from causing an excessive voltage to change in either cell so that it protects the supercapacitor from drifting into a dangerous state.

It's important to remember that the balancing of individual supercapacitor cells is a relatively new horizon, as is the use of series stacks. Engineers with relatively little experience in supercapacitor deployments are just now starting to cope with these nuances. When in doubt, allow extra voltage margins for all the possible lot-to-lot capacitance variations to ensure cells don’t see over-voltages.

All in all, engineers need to test cells individually to get a more accurate reading of individual capacitance and leakage current values. Only then can designers begin the process of grouping cells together within a certain range before the balancing begins. Once incorporated into the design process, it will help ensure durability and reliability for the life of the application.

References

Advanced Linear Devices, Inc. www.aldinc.com

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Longer battery life for hearables and wearables CARY DEL ANO, RENO ROSSETTI | MAXIM INTEGRATED

Single-inductor, multiple-output circuitry can provide the kind of high conversion efficiency necessary for super-small consumer electronics.

GENERIC HEARABLE POWER FLOW

When

you’re designing hearables and wearables, user experience dictates that long battery life is a key requirement. Nobody wants to stop and recharge the batteries on their earbuds during a long walk or while working on a home remodeling project. Or consider a medical patch that might sit in a storeroom long before being used. You wouldn’t want the battery to die before the patch gets into a patient’s hands.

The task of extending battery life is even more challenging in ultra-small electronic devices where device size limits battery capacity. One way to manage power use in these types of products is with a specific kind of switching regulator: a single-inductor multiple-output (SIMO) power converter A typical power flow diagram for a hearable design. optimized for low quiescent current. A closer look at the SIMO architecture reveals why it is advantageous in these types of applications. could be serviced by an individual inductor. Inductors are A typical power management system typically large and expensive. Their size is a reflection of the for a hearable device includes a power management IC necessary current-carrying capacity (as measured by Isat, the (PMIC) that uses a battery charger, a buck converter, and a total saturation current). Therefore, designers of ultra-small low-dropout regulator (LDO) to power the sensors. A dual LDO powers the microcontroller, Bluetooth, and audio. There electronic devices want to minimize the number of inductors.

A more compact option could use linear regulators, are also some external passives. Because LDOs are used for but they are lossy. A SIMO architecture, on the other hand, three rails in this architecture, the overall efficiency of such a reduces the number of inductors needed while still providing typical implementation is only 69.5%. the efficiency you’d expect from a switching converter.

Fortunately, the SIMO architecture shines in delivering What’s more, by minimizing the number of inductors, a SIMO efficiency. Let’s illustrate how this architecture works using further reduces the total footprint compared to a circuit using SIMO buck-boost regulators as an example. For context, in multiple inductors. a traditional architecture, using switchers instead of LDOs Consider the nearby diagram of a new buck-boost SIMO to improve efficiency, each switching regulator would need regulator. In this architecture, there are three independently a separate inductor for each output, so each voltage rail

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KNOWLEDGE IS POWER

Massive power density in the smallest packages

Microchip Technology now offers an integrated switching power module designed specifically for height-constrained telecom, industrial and solid-state drive (SSD) applications. These products come in an impressive thermally-enhanced package that incorporates inductors and passive components into a single, molded power converter. The slim packages simplifies board design, saves space and eliminates concern over passive components that may introduce unexpected electromagnetic interference (EMI).

Highlights •

Variety of module package offerings (small to large, fit to application)

•

High power density with integrated magnetic and passive components

•

Performance (efficiency, thermal, transient response)

•

Reliable (power and thermal stress tested)

•

Low EMI (CISPR 22 Class B ratings on modules)

www.microchip.com/powerpromo The Microchip name and logo and the Microchip logo are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. All other trademarks are the property of their registered owners. © 2016 Microchip Technology Inc. All rights reserved. 9/16 DS20005637A

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BASIC SIMO CIRCUIT

HANDBOOK

POWER & ENERGY EFFICIENCY

programmable power rails from a single inductor. This approach reduces component count, maximizes available board space, and delivers high efficiency.

Buck-only SIMO architectures are an option, but when an output voltage approaches the battery voltage, the buck-only SIMO would need the inductor for too much time, impacting other channels. The buck-boost SIMO architecture uses the inductor more efficiently because it requires less time to service each channel. Also, circuits that require at least one boost voltage are almost always better with a buck-boost SIMO. One might wonder how a SIMO uses one inductor and still delivers high efficiency on each output. Fundamentally, a SIMO is still a switching architecture which includes an inductor. It maintains the low loss of a traditional inductive switching converter by turning on switches when there is near-zero volts across them. This practice keeps the dissipation low. The SIMO adds the benefit of time-sharing the inductor to each output (SBB0, SBB1, and SBB2 in the figure) using low-loss switches, maintaining the same high efficiency one would expect from a buck-boost converter.

TRADITIONAL POWER TREE, ONE INDUCTOR

A traditional power tree for a mostly LDO-based consumer electronic design.

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The SIMO architecture adds the benefit of time-sharing the inductor to each output (SBB0, SBB1, and SBB2) using low-loss switches, maintaining the same high-efficiency benefits available from a buck-boost converter.

Design tradeoffs in hearables Hearable devices differ from standard stereo Bluetooth headsets in several ways.

Hearables, for example, integrate one or more optical or inertial MEMS sensors. Through use of photoplethysmography (as employed by FitBit and Apple watches), an integrated optical sensor can measure blood-oxygen saturation, pulse rate, or vital signs.

One problem is that to generate enough light, LEDs must operate at a voltage range (4 to 5 V) higher than that of Li+ batteries. This leaves designers with a tough decision: Add a buck-boost to the system, which means another IC; add another inductor and more capacitors, an option that also takes up space and volume; or accept higher power dissipation, undesirable in small systems.

The SIMO buck-boost architecture provides an answer without the unsavory tradeoffs.

This architecture can use one of its outputs set to the desired voltage, up to 5.2 V, to drive the LED and also optimize sensor performance.

The Isat of an inductor is a function of its core volume. At first glance, this may seem to imply

that a SIMO offers no advantage versus separate bucks. However, compared to using separate dcdc converters, a single inductor in a SIMO architecture provides significant advantages: • •

•

•

Better use of Z-height (when the system allows it).

Lower cost through use of fewer inductors; and less area on the board devoted to inductor spacing.

Time multiplexing. Often, different features aren’t used simultaneously. When one system is off and another is on, the two can share their Isat if they share the inductor. This approach is useful for events that happen sequentially using different rail voltages.

One example is in Bluetooth systems where the data can be downloaded before it activates a function.

RMS (current rating for inductors)—Even when channels aren’t timemultiplexed, often they don’t consume peak power simultaneously, which can lower the total inductor Isat requirements.

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POWER & ENERGY EFFICIENCY

Though there are tradeoffs associated with the SIMO architecture, they can be managed with careful design. Ripple voltage is one concern. With a single inductor providing multiple buckets of energy, ripple voltage will often be high. Larger output caps can help offset this ripple. And compared to traditional architectures, SIMO configurations may exhibit more crosstalk.

An example of a SIMO that addresses these tradeoffs is the Maxim MAX77650 PMIC. It features a micropower SIMO buck-boost dc-dc converter implementing three switching regulators using a single inductor. Its high-frequency operation lets the PMIC use a small inductor, which saves board space. In a single chip (2.75 x 2.15 x 0.8 mm WLP), the MAX77650 integrates the battery charger and regulation for powering the sensor (3.3 V), the microcontroller (1.2 V), the Bluetooth, and audio (1.85 V). In standby mode, the part draws just 300 nA and in active mode, 5.6 uA. Overall system efficiency is 78.4% as described in the accompanying table.

An integrated LDO in the PMIC provides ripple rejection for noise-sensitive applications such as audio.

Optional resistors (24 Ω) in series with the serial data line (SDA) and serial clock line (SCL) minimize crosstalk and undershoot on bus signals, simultaneously protecting device inputs from high-voltage spikes on the bus lines.

To further extend battery life, every block in these regulators has low quiescent current (1 µA per output).

SIMO POWER TREE, ONE INDUCTOR

C O M PA R I N G S I M O A N D CONVENTIONAL APPROACHES Parameter

Traditional

SIMO

SIMO

Li+ Battery Current

49mA

43.4mA

SIMO saves 5.6mA

System Efficiency

69.5%

78.4%

SIMO is 8.9% more efficient

Minimum Li+ Battery Voltage

3.4V due to 3.4 LDO

2.7V

SIMO allows more discharge

The PMIC always operates in discontinuous conduction (DCM) mode, so the inductor current goes to zero at the end of each cycle, further minimizing crosstalk and preventing oscillation.

The converter in this architecture has a SIMO control scheme with a proprietary controller that ensures all the outputs are serviced in a timely way. The state machine rests in a low-power rest state when no regulators need service. When the controller recognizes a regulator needs service, it charges the inductor until the peak current limit is reached. Then the inductor energy discharges into the associated output until the current reaches zero.

When multiple output channels need servicing simultaneously, the controller makes sure no output uses all the switching cycles. Instead, the cycles interleave between all the outputs needing service, skipping those that don’t. A soft-start feature is implemented by limiting the slew rate of the output voltages during startup. Each SIMO buck-boost channel provides an active-discharge feature that automatically enables independently for each SIMO channel based on the SIMO regulator status. This approach provides for complete and timely power-down of system peripherals.

References

MAX77650 evaluation kit, www.maximintegrated.com/en/products/power/battery-management/ MAX77650EVKIT.html

A hybrid power tree for a traditional mostly LDO-based circuit, redone using a SIMO and a less lossy LDO (by using a lower voltage drop across the LDO).

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Nested hysteretic current-mode single-inductor multiple-output (SIMO) boosting buck converter, www.ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6573566&tag=1 Hearables Get Longer Life with SiMO, www.maximintegrated.com/en/design/technical-documents/design-solutions.html

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GAUGING PROGRESS

Gauging progress in SiC MOSFET technology A review of SiC MOSFET performance data shows these devices have improved dramatically in a short time. And improvements are likely to continue.

K E V I N M . S P E E R , P H D | L I T T E L F U S E , I N C ., SUJIT BANERJEE, PHD | MONOLITH SEMICONDUCTOR INC.

Insulated

gate bipolar transistors (IGBTs), first commercialized in the early 1980s, revolutionized the power electronics industry.

Today, silicon carbide (SiC) devices are changing the power electronics world all over again. The IGBT gave us a transistor simultaneously capable of blocking high voltages with low on-state (i.e., conduction) losses and well-controlled switching. The device is limited, however, in how fast it may be switched, which leads to high switching losses, large and expensive thermal

management, and a ceiling on power conversion system efficiency.

The advent of SiC transistors all but eliminates IGBT switching losses for similar on-state losses (lower, actually, at light load) and voltage-blocking capability, bringing high efficiency while reducing the overall weight and size of the system.

Although device-related SiC materials research began in the 1970s, the promise of SiC for use in power devices was most formally suggested in 1989 by prominent

S T R E S S I N G S i C M O S F E Ts A T H I G H T E M P E R A T U R E

High-temperature gate bias (HTGB) stress tests performed at 175°C on 77 devices from three different wafer lots out to 2,300 hours at NIST for Monolith Semiconductor MOS technology. Here, (left) negative, VGS = -10 V, and (right) positive, VGS = 25 V. NIST observed negligible deviation.

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lGBT researcher B. Jayant Baliga.

Baliga’s figure of merit served as additional motivation for scientists to continue advancing SiC crystal growth and device processing techniques. In the late 1980s, intense efforts were underway worldwide to improve the quality of SiC substrates and hexagonal SiC epitaxy. The improvements continued throughout much of the 1990s until the first commercial device was released in 2001 in the form of a SiC Schottky diode by Infineon.

For a few years following their release, SiC Schottky diodes experienced field failures that were traced to material quality and device architecture. There was rapid and drastic progress to improve the quality of substrates and epitaxy; meanwhile, a diode architecture known as the junction barrier Schottky (JBS) was used, which more optimally

distributed the peak electric field.

In 2006, the JBS diode morphed into what is now called the merged p-n Schottky (MPS) structure, which maintains optimal field distribution but also allows for better surge capability by incorporating true minority carrier injection. Today, SiC diodes have proven reliability, demonstrating more favorable FIT rates even than silicon power diodes.

How the SiC MOSFET evolved

The SiC MOSFET has had its share of issues, most related to the gate oxide. The first signs of trouble were observed in 1978 when researchers at Colorado State University measured a messy transition region between the pure SiC and the grown SiO2.

Such a transition region was known to have high densities of interface states and oxide traps that inhibit carrier mobility and lead to instabilities

in threshold voltage; numerous research publications later verified this phenomenon. Many in the SiC research community spent the late 1980s and 1990s further studying the nature of various interface states in the SiC-SiO2 system.

Research in the late 1990s and early 2000s led to remarkable improvements in understanding the sources of interface states (whose density is abbreviated Dit), as well as reducing them and mitigating their negative effects. To mention a few noteworthy discoveries, oxidation in a wet environment – that is, using H2O as an oxidation agent instead of dry O2 – was observed to reduce Dit by two to three orders of magnitude.

Also, the use of off-axis substrates was found to reduce Dit by at least an order of magnitude.

Last but certainly not least, the effects of post-oxidation annealing in

H I G H - T E M P E R A T U R E T E S T S O F S i C M O S F E Ts

High-temperature reverse bias test data taken at NIST on 82 samples after 1,000 h of stress at VDS = 960 V and TJ = 175°C, illustrating no change in (left) drain leakage at VDS = 1,200 V or (right) blocking voltage at ID = 250 μA.

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GAUGING PROGRESS

nitric oxide – a process commonly called nitridation – were first discovered by Hai-feng Li and co-workers at Austrlia’s School of Microelectronics Engineering in 1997 to reduce Dit to extremely low levels. This was subsequently affirmed by six or seven other groups. It would be an egregious omission, of course, not to underscore the seminal contributions made by the bulk-growth and waferresearch community. These individuals have taken us from mere hexagonal SiC crystals called Lely platelets to 150-mm wafers that are virtually free of devicekilling micropipes.

Commercially available 1,200 V SiC MOSFETs have come a long way in terms of quality over the past few years.

Channel mobility has risen to suitable levels, oxide lifetimes have reached an acceptable level for most mainstream industrial designs, and threshold voltages have become increasingly stable. What is equally important from a commercial standpoint is that multiple suppliers have reached these milestones.

That brings us to today’s SiC MOSFET quality, including long-term reliability, parametric stability, and device ruggedness. Using accelerated timedependent dielectric breakdown (TDDB) techniques, the oxide lifetime of Monolith Semiconductor’s MOS technology has been predicted by researchers at NIST to exceed 100 years, even at junction temperatures exceeding 200°C. The NIST work used lifetime acceleration factors of applied electric field across the oxide (greater than 9 MV/cm) and junction temperature (up to 300°C); for reference, oxide electric fields used in practice are around 4 MV/ cm (corresponding to VGS = 20 V), and junction temperatures during operation are typically lower than 175°C. It is also worth noting that while a temperaturedependent acceleration factor is

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Littelfuse — P&EE Handbook 11-17 V2.indd 31

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commonly seen in silicon MOS, it had not been seen by NIST for SiC MOS prior to its work with devices from Monolith Semiconductor.

Threshold voltage stability also has been convincingly demonstrated. High-temperature gate bias (HTGB) took place at a junction temperature of 175°C and under negative (VGS = -10 V) and positive (VGS = 25 V) gate voltages.

As dictated by JEDEC standards, 77 devices from three different wafer lots were tested; observers saw no significant shift. Still another parameter set proven to be stable over the long term is the blocking voltage and off-state leakage of our MOSFETs. In high-temperature reverse bias (HTRB) tests, more than eighty samples were stressed for 1,000 h at VDS = 960 V and TJ = 175°C, after which post-stress measurements revealed no change in drain leakage or blocking voltage.

With respect to device ruggedness, preliminary measurements reveal a short-circuit withstand time of

at least 5 µsec and an avalanche energy of 1 J. Although we cannot speak to the long-term reliability or ruggedness of devices produced by other manufacturers, our evaluation of commercially available SiC MOSFETs shows there are now multiple suppliers capable of supplying production-level quantities of SiC MOSFETs. These devices appear to have acceptable reliability and parametric stability, which will surely encourage mainstream commercial adoption.

Commercial prospects

In addition to quality improvements, the past few years have seen tremendous commercial progress.

Multiple SiC MOSFET suppliers are available to satisfy secondsource concerns while also creating a competitive landscape that is good for both suppliers and users.

Commercially available parts have been released from Wolfspeed, ROHM, ST Microelectronics, and

SiC MOSFET SHORT-CIRCUIT TEST

Microsemi; the community can expect offerings soon from Littelfuse and Infineon.

Multi-chip power modules are also a hot topic in the SiC world.

We believe many opportunities remain for SiC MOSFETs in discrete packages, as best layout practices of both the control and power circuits can easily extend discrete solutions to handle tens of kilowatts. Higher power levels and the motivation to simplify system design will drive SiC module development efforts, but the importance of optimizing parasitic inductance from the package, control circuit, and surrounding power components cannot be overstated.

Price is the eternal question when it comes to the commercial prospects of the SiC MOSFET. Our view on price erosion is favorable, based on two aspects of our approach: First, our devices are manufactured in an automotivegrade silicon CMOS fab. Second, the process runs on 150-mm wafers.

Use of existing silicon CMOS fabs allows us to slash capital expenses and reduce operating expenses to keep costs down.

Furthermore, manufacturing on 150mm wafers produces more than twice as many devices as on 100-mm wafers, which has a major Short-circuit testing of a 1,200 V, 80 mΩ SiC MOSFET at a dc link of 600 V and VGS = 20 V, indicating a withstand time of at least 5 μsec.

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GAUGING PROGRESS

S i C M O S F E T AVA L A N C H E R U G G E D N E S S Avalanche ruggedness test on a 1,200 V, 80 mΩ SiC MOSFET, showing that 1.4 J of energy was safely absorbed in the device with Ipeak = 12.6 A and L = 20 mH.

impact on the per-die cost. Since the first announcement at Digi-Key six years ago, the price of a 1,200-V, 80-mΩ device in a TO-247 has fallen by more than 80%, even if the SiC MOSFET is still 2-3X more expensive than a comparable silicon IGBT. Designers are already viewing substantial system-level price benefits using SiC MOSFETs over Si IGBTs at today’s price levels, and we expect SiC MOSFET pricing will continue to fall as economy of scale takes hold with 150-mm wafers.

In all, the current state of the SiC MOSFET indicates resolution on major commercial impediments including price, reliability, ruggedness, and diversification of suppliers. Despite a price premium over Si IGBTs, the SiC MOSFET has already seen success thanks to cost-offsetting system-level benefits; the market share for this technology will rise sharply over the next few years as materials costs fall.

After more than forty years of development effort, the SiC MOSFET finally appears poised for widespread commercial success and a substantial role in the green energy movement.

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References

B. J. Baliga suggested the promise of SiC here: “Power semiconductor device figure of merit for high frequency applications.” IEEE Electron Device Letters 10 (10), 1989.

The merged p-n Schottky (MPS) structure debuted in: R. Rupp, M. Treu, S. Voss, F. Bjork, and T. Reimann, “2nd Generation SiC Schottky diodes: A new benchmark in SiC device ruggedness.” Proc. of IEEE International Symposium on Power Semiconductor Devices and ICs, 2006.

Documentation of SiC diode failure in time rates: T. Barbieri, “Technical Article: SiC Schottky Diode Device Design: Characterizing Performance & Reliability,” www.wolfspeed.com.

CSU researchers measured the transition region between pure SiC and grown SiO2: R. W. Kee, K. M. Geib, C. W. Wilmsen, and D. K. Ferry, “Interface characteristics of thermal SiO2 on SiC.” Journal of Vacuum Science and Technology 15 (4), 1978.

Several examples of improving knowledge of SiC interface states: S. M. Tang, W. B. Berry, R. Kwor, M. V. Zeller, and L. G. Matus, “High frequency capacitancevoltage characteristics of thermally grown SiO2 films on -SiC.” Journal of the Electrochemical Society 137 (1), 1990.

H. Yano, T. Kimoto, and H. Matsunami, “Interface States of SiO2/SiC on (11-20) and (0001) Si Faces.” Materials Science Forum, vols. 353-356, 2001.

H. Li, S. Dimitrijev, H. B. Harrison, and D. Sweatman, “Interfacial characteristics of N2O and NO nitride SiO2 grown on SiC by rapid thermal processing.” Applied Physics Letters 70 (15), 1997.

S. Pantelides et al., “Si/SiO2 and SiC/SiO2 Interfaces for MOSFETs – Challenges and Advances.” Materials Science Forum, vols. 527-529, 2006.

NIST predictions of MOS oxide lifetime: Z. Chbili, K. P. Cheung, J. P. Campbell, J. Chbili, M. Lahbabi, D. Ioannou, and K. Matocha, “Time Dependent Dielectric Breakdown in high quality SiC MOS capacitors.” Materials Science Forum, vol. 858, 2015.

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Tougher stress tests for automotive MOSFETs ALEKSANDRA KOZYCZAK, LOURDES GARCIA | INFINEON TECHNOLOGIES

Current automotive quality standards may not be selective enough for power electronic devices that will run next-generation vehicles. Device makers are responding with their own more stringent test regimes.

Modern

vehicles rely heavily on electronic systems. Each electronic component in these systems is a source of potential failure. Systemic failure modes in vehicles are extremely expensive for automakers because they can lead to vehicle recalls, service problems, and damage to brand and reputation.

To promote reliability, standards such as AEC-Q101 have been developed. But in the automotive world technology moves quickly, and any failure is unacceptable. So simply meeting these qualification standards is not enough.

Developers of automotive power electronics are particularly concerned with the reliability of MOSFETs and their common failure modes in the harsh automotive world. But there are processes used to ensure that MOSFETs significantly exceed the reliability requirements and mission profiles on which the AEC-Q101 is based.

According to the statistics firm Statista, currently around a third of an average car’s cost is tied up in electronic components. This figure is set to reach half a vehicle’s total cost within the next decade.

The overall electronics content is varied and includes a multitude of sensors, microcontrollers and other devices. However, MOSFETs are crucial devices in their role as electronic actuators, switching loads such as lamps, motors, injectors and more.

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VEHICLE COSTS ATTRIBUTED TO ELECTRONICS

Data from the statistics firm Statista indicates that the average automobile produced in 2030 will be half electronic in terms of its percentage of total cost.

Current estimates are that the average car now uses around 60 power MOSFETs. If we assume a rate of just one defect-per-million (dpm), about sixty cars in every million manufactured (within certain confidence level) would fail solely because of a MOSFET. This defect level is not acceptable in the automotive industry.

To standardize the way in which discrete semiconductors are qualified for automotive applications, the Automotive Electronics Council (AEC) worked with several major semiconductor suppliers, including Infineon, to develop an industry-wide standard. The resulting AEC-Q101 Standard set requirements covering certain

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POWER & ENERGY EFFICIENCY 36

mission profiles and qualification definitions. These included batch sizes, pass/fail criteria, requirements to re-qualify after process changes, and specific test definitions (including applicability to different device/ process types). The goal of this effort was to simulate the conditions found in vehicles and establish a reliability prediction that was accurate.

AEC-Q101 is a valuable standard that is mainly based on typical mission profiles. It is less effective with the untypical and stringent conditions increasingly common in vehicular applications. It is also a 'one-time' qualification that typically takes place at the end of the development cycle.

Thus, it takes no account of long-term production process stability.

One major drawback of the standard is that its testing requirements involve relatively low sample sizes.

For example, the standard requires just 77 devices from each of three lots to go through high-temperature reverse bias tests; ditto for temperature

cycling tests.

Statistically, the required test sample sizes aren’t always large enough to target a dpm Makers of power semiconductors increasingly use component testing criteria that exceeds those of applicable automotive rate below standards. Here are some examples of Infineon’s qualification 10,000 at a 90% testing that extends beyond AEC-Q101 requirements. confidence level - not acceptable in modern harsher mission profiles characterizing automotive electronics. modern automotive applications.

To address the needs of the While the standard allows High automotive market, Infineon began Temperature Gate Bias (HTGB) and developing an enhanced qualification High Temperature Reverse Bias (HTRB) test regime founded on the solid tests to take place on 'virgin' products, principles defined in AEC-Q101. A Infineon uses parts that have been first step is to focus on extending the preconditioned. Taking this approach lifetime of the device until the wearmakes the test more severe and also out failure period. To realize this goal, takes account of customer device Infineon lengthened the time duration processing such as double-sided IR of the qualification tests to ensure reflow that may cause package popproducts will perform in much harsher corning defects. application environments.

In addition, High Humidity High AEC-Q101 stipulates that devices Temperature Reverse Bias (H3TRB) must be preconditioned and thermally can take place at 80% of VDS,max. But cycled (TC) 1,000 times from -50 to Infineon tests at 100% of this value, +150 °C. Infineon doubled this to 2,000 thereby ensuring full coverage of the Areas of focus for the Infineon cycles, making the test relevant for the published datasheet specified values. design process.

Infineon has over 40 years of experience in the automotive AUTOMOTIVE MOSFET DESIGN PRACTICES market and has shipped over five billion MOSFETs since 2010. This experience plus application knowhow and stringent process control leads to minimal levels of random defects. A focus on three key areas (die attach, delamination and gate oxide) during development further boosts reliability. This holistic approach to automotive power MOSFET quality yields a dpm below 0.1 which is a benchmark in the industry.

Like all packaged semiconductor devices, MOSFETs suffer from mismatches of the coefficient of thermal expansion (CTE) of the mold compound, DESIGN WORLD — EE NETWORK

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TOUGHER STRESS TESTS

silicon die, lead frame and die pad during the thermal cycling expected in automotive applications. Simply put, as the MOSFET heats up rapidly and then cools, the different components expand and contract at slightly different rates. This action puts stress on dissimilar-metal interfaces that can eventually lead to device failure through lifted or broken bond wires and delamination.

To address this issue, Infineon developed a proprietary process that improves the adhesion between the molding compounds, silicon die, wirebonds, and the lead frame. This process involves growing hair-like dendrites on the die and lead frame that improve the adhesion by providing a mechanical attachment. Validation includes 1,000 thermal cycles, and devices undergo ultrasonic inspection at each stage to ensure there is no visible delamination.

In power devices, the thermal resistance between the semiconductor junction and the package (Rthjc) is a critical parameter. Designers rely upon it to ensure the package can conduct heat well enough to prevent any thermal build-up.

However, delamination can also affect the attachment of the die to the die pad. Should the die become (partially) detached, then Rthjc will rise because of the impeded thermal path, raising the MOSFET junction temperature (Tj). As Tj rises, so will the on resistance of the MOSFET (Rdson), leading to higher power losses and the generation of more heat. As this thermal runaway continues, the most likely outcome is a device failure with an electrical overstress signature.

There are several ways of measuring Rthjc. Infineon uses the Delta VSD technique as it has proven to be effective and

accurate. This technique relies on the fact that in a MOSFET the voltage across the intrinsic body diode (VSD) is linear with respect to Tj. After preconditioning, VSD is measured at 25°C and then measured again after the device is heated by a known reference current. A VSD reading lower than normal indicates Rthjc has risen, a clear indication of delamination.

Part average testing Good design practices and stringent qualification testing ensures MOSFETs will be reliable. But there will always be variations within production batches. Most of these devices remain well within datasheet specification limits. However, a few may be weaker than others. Reliability studies indicate that semiconductor components having abnormal variations are more likely to have long-term quality and reliability problems. These outliers are more likely to fail in the field.

There is a technique commonly used for ICs called Part Average Testing -- PAT -- but it is used for MOSFETs. Infineon uses it to identify outliers on the production line. PAT identifies outliers before they get shipped to customers. PAT basically modifies the pass/fail test limits based on statistical sampling of multiple devices.

PAT is a dynamic test. It looks at the mean and standard deviation of measurement results as tests proceed. Outlier parts are considered those that passed the test but are not in a range determined by the mean and some multiple of the SD. All in all, ever-more-stringent product qualification processes go beyond standards alone and assure automakers of reliable performance.

A N E X A M P L E O F PA R T AV E R A G E T E S T I N G

References Infineon Technologies AG, MOSFETs, www.infineon.com/cms/en/product/power/mosfet/channel. html?channel=db3a304319c6f18c011a14e5341b25f1

PAT identifies and discards ‘in-spec’ devices that exceed the average test results by a predetermined amount and thus may be more prone to failure,

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POWER & ENERGY EFFICIENCY

Fuses that blow safely New fuse technology designed specifically for electric vehicles helps meet stringent automotive reliability standards.

Electric

HANDBOOK

vehicles (EVs) and hybrid electric vehicles (HEVs) now use high-energy lithium battery systems. These power sources have spurred a need for a reliable means of protecting against catastrophic failures. Resettable devices are suitable for overcurrent conditions caused by transitory fault conditions, and the venerable “one-shot” fuse remains the best circuit option where fault currents can damage other circuits or systems. Moreover, the move toward small, distributed and embedded electronics has elevated the need for high-performance, miniature surfacemount fuses.

Located under the vehicle’s dashboard in the fuse box, bladetype fuses are still a ubiquitous method for providing fault protection.

The monolithic structure of a SolidMatrix ceramic fuse (left) absorbs fault current and shows no external damage. There is visible damage on the conventional printed circuittype chip fuse (right).

However, automotive electronics, with its higher current ratings and shrinking space constraints, has driven the need for advanced surfacemount fuse technology. Now, newgeneration fuse technology has been designed to better meet automotive circuit protection needs.

Solid body, or chip, fuses are used in a wide range of spaceconstrained applications with current ratings typically ranging from as low as 125 mA to several Amperes. These devices come in both slow-blow and fast-acting configurations. The two most common structures for solid body chip fuses are the multi-layer ceramic type and printed circuit style.

The ceramic type offers distinct advantages over the more commonly used printed-circuit style fuse.

Because of its monolithic structure, the ceramic fuse is capable of higher current ratings in a smaller package, has a wider operating temperature, and has stable operating qualities in extreme conditions. Additionally, its structure is less susceptible to

MONOLITHIC FUSE AFTER OVERCURRECT

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mechanical damage.

The ceramic fuse has a co-fired monolithic structure with up to four layers of fusible material embedded within. In the printed circuit structure, the device is mainly comprised of an epoxy substrate and glass fiber (FR4).

The fuse element is bonded to the surface of the pc board and coated with a protective polymer.

A new advance in ceramic fuse technology is called the SolidMatrix ceramic fuse. This solid-body ceramic fuse’s patented, multi-layer construction provides excellent mechanical and thermal stability over a wide temperature range (-55 to +150°C).

It is useful to compare how a SolidMatrix ceramic fuse and a conventional printed-circuit type fuse might behave when subjected to an over-current fault condition. The fuse element of the conventional printedcircuit board type fuse opens, but the high over-current fault condition can lead to surface melting, cracking and compromised mechanical integrity.

CONVENTIONAL FUSE AFTER OVERCURRENT

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FUSES THAT BLOW SAFELY

SAMPLE A 250A/250V PULSE TEST

SAMPLE B 400A/450V PULSE TEST

Two conventional wire-in-air fuses experienced significant damage when subjected to extreme overload conditions that simulated a catastrophic EV battery short circuit.

As a result, arcing and surface damage may arise.

The SolidMatrix ceramic fuse fares significantly better. The proprietary construction of this device allows the metal fusing elements to diffuse into the ceramic; plus, they have a central location within the structure that ensures energy stays within the body. As a result, mechanical integrity is maintained, and there is no external change in the device’s appearance.

Wire-in-air fuses are typically applied in higher operating current applications that need fast-acting and superior arc-suppression. Applications include battery chargers, battery packs and circuits subject to high fault currents and higher voltages. The common construction for this type of fuse has the fusible wire element housed inside a ceramic tube and connected to the endcaps with solder beads.

There are several disadvantages associated with conventional wire-inair fuses. Endcap detachment is a common failure mode in the conventional construction. There is also a lack of uniformity in performance because of variations in where the wire element sits inside the ceramic tube. Additionally, under worst-case, high-current-stress conditions, the solder in the ceramic tube can vaporize and build up pressure to the point where the fuse explodes. If this happens, solder is redeposited across the trace, which can result in AIR MATRIX a secondary conductive path with 450A/450V PULSE TEST potentially serious consequences.

In comparison, the fuse element of advanced AirMatrix wire-in-air fuses use a proprietary, hermeticallysealed wire-in-air structure that assures consistent electrical performance.

The AirMatrix fuse element is uniformly straight across the cavity and externally bonded to the endcap.

Unlike the conventional square nanotype fuse, with its ceramic body and solder connect design, the AirMatrix fuse uses a fiberglass-enforced An AirMatrix fuse sustains no damage body and solderless direct connect after being subjected to extreme construction. overload conditions that simulate a As an illustration, two catastrophic EV battery short circuit. conventional wire-in-air fuses were eeworldonline.com | designworldonline.com

AEM — P&EE Handbook 11-17 V2.indd 39

subjected to a short circuit condition as might arise in an EV. One sample saw 250 V/250 A while another saw 450 V/450 A. Both exhibited significant damage to the fuse and collateral damage to the surrounding circuitry. Each fuse also experienced a secondary current flow that ultimately resulted in pc board damage.

When subjected to the same EV battery short circuit as the square nano-tube fuses, the advanced construction of the AirMatrix fuse let it withstand 450 V/450 A conditions without experiencing any external damage. Current flow through the AirMatrix fuse dropped to zero. And the AirMatrix fuse opened with no secondary conduction.

All in all, new structures being utilized by the SolidMatrix multi-layer ceramic chip fuse and the AirMatrix wire-in-air fuse can offer significant advantages over typical fuse approaches. They are particularly helpful in automotive applications where engineers must qualify their devices for the AEC-Q200 automotive standard. Manufactured in a TS16949-certified facility, the fuses are specifically designed for reliable operation in highstress automotive applications.

References AEM Components Inc., www.aemcomponents.com

EETech Labs worked with AEM Components to produce a video (www.allaboutcircuits.com/industry-articles/how-to-protect-against-catastrophic-shorts-in-evs/) demonstrating what happens to circuit protection devices that see worst-case electric vehicle (EV) battery short circuit conditions. The video clearly shows what short circuits from EV batteries can do to a fuse. Automotive specifications require that circuit protection devices break the circuit without damaging PC boards or other components. AEM wire-in-air fuses comply with this demand by remaining intact. Competitive fuses tested under the same conditions not only caught on fire but also damaged the PCB on which they mounted.

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