Power Electronics Handbook 2022

Protecting fast EV charging stations Page 10

Putting supercapacitors to work Page 14

FEBRUARY 2022

Optimizing power delivery networks Page 40

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POWER ELECTRONICS HANDBOOK

Up in the sky! It’s a bird! It’s a plane!

It’s a flying battery!

A

ccording to a company called Joby Aviation, in a few years you’ll be able to summon up an air taxi on your Uber

phone app for trips of 25 miles or so. And you won’t have to feel guilty about the environmental impact of your trip because the plane will actually be a Joby eVTOL, an electric vertical takeoff and landing, aircraft. Joby envisions a network of “vertiports” first in the U.S. and eventually worldwide, with perhaps 10,000 such six-engined aircraft in service at 20 cities within 10 years.

As you might suspect, these plans have attracted a lot of skepticism. Among the reasons: Joby’s eVTOL, dubbed the S4, has yet to be certified for carrying passengers by the FAA. And though the firm has a big investment from Toyota for factory automation expertise, it has never produced a single flying airplane before the S4, let alone 10,000 of them.

Skeptics also have problems with the technical details of the S4, though these are hard to discern because Joby is secretive about the design. The eVTOL’s battery is said to be comprised of lithium-nickel-cobalt-manganeseoxide cells, the same type used in EVs such as the BMW i8, Chevy Bolt, and Nissan Leaf S Plus. Company officials have said the cells have “almost” 300 W-h/kg of specific energy, high for that type of battery chemistry.

One analysis by Carnegie Mellon University

2

DESIGN WORLD — EE NETWORK

engineering Prof. Venkat Viswanathan used this figure to show what it implies for the plane’s design. Joby says the S4 will have a top cruising speed of 200 mph and a range of 150 miles.

The FAA requires passenger planes to have a reserve of 45 minutes of flight time over and above their advertised range. To do this, Viswanathan calculates the S4 would need a battery pack with 200 kW of energy.

Of course, battery packs need insulation and packaging to ensure a thermal runaway in any one cell won’t propagate, as well as a battery management system and some capacity for cooling. Consequently, Viswanathan estimated that the assembled battery pack would have an energy density of 200 Wh/kg.

That implies an S4 battery pack would weigh 2,200 lb. (In interviews, Joby officials have claimed an even higher energy density, 235 Wh/ kg.) For comparison, the Tesla Model X currently carries a battery pack sporting 186.21 Wh/kg.

Joby has put the S4’s max gross weight— it’s empty weight plus passengers and baggage-at 4,800 lb. Subtracting the weight of the battery, as well as 1,000 lb for the pilot and four passengers, leaves only 1,600 lb for the airframe, avionics and everything else onboard.

This relatively small fraction of gross weight devoted to the airplane’s structure is also noteworthy. For comparison with a conventional plane, consider the Cirrus SR22 which also carries four passengers and a pilot. It’s empty weight is 2,272 lb and gross weight (which in the case of the Cirrus would include fuel) is 3,600 lb.

Recall that Joby foresees 2 • 2022

running these planes seven hours a day, seven days a week. That works out to roughly 12,000 takeoffs and landings annually, more than what airliners rack up. So it’s fair to wonder if the 1,600 lb-worth of light composite airframe in the S4 will be up to that kind of beating.

Nevertheless, the kind of distributed electric propulsion that Joby envisions has advantages such as motors with a low part count and a design conceived with the help of sophisticated computer software.

This approach will probably have a place somewhere in aviation even if the S4 isn’t it.

LELAND TESCHLER EXECUTIVE EDITOR

EE-PwrElecHdbk K-Blog_BCCR_EV_2-22p.indd 1

1/6/22 11:08 AM

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2 • 2022

CONTENTS POWER ELECTRONICS HANDBOOK • FEBRUARY 2022

02 07

UP IN THE SKY! IT’S A BIRD! IT’S A PLANE! IT’S A FLYING BATTERY!

14

18

HOW TRIMMING AFFECTS THICK-FILM RESISTOR PERFORMANCE

ORDINARY THICK-FILM RESISTORS CAN DISPLAY VARYING QUALITIES DEPENDING ON HOW THE MANUFACTURER ELECTED TO TRIM THE DEVICE. IT PAYS TO KNOW WHAT TO LOOK OUT FOR.

27

37

PUTTING SUPERCAPACITORS TO WORK

BETTER THERMAL MANAGEMENT OF eGaN FETS

POUCH-TYPE EDLCs FOR THIN-AND-LIGHT CIRCUIT DESIGNS

SUPERCAPACITORS NOW COME IN A SMALL, THIN FORMAT THAT MAKES THEM CANDIDATES FOR USES CHARACTERIZED BY CRAMPED QUARTERS.

SAVING ENERGY WITH MCU POWER MANAGEMENT

MCU LOW-POWER FEATURES SUCH AS BUILT-IN ENERGY HARVESTING HELP OPTIMIZE APPLICATIONS WHERE LONG BATTERY LIFE IS IMPORTANT.

THERE ARE A VARIETY OF MODERN APPLICATIONS IN WHICH SUPERCAPACITORS ARE BETTER CANDIDATES THAN EITHER BATTERIES OR ORDINARY CAPACITORS.

A FEW SIMPLE THERMAL MANAGEMENT GUIDELINES CAN HELP CONDUCT HEAT AWAY FROM GAN FETS.

24

34

PROTECTING FAST EV CHARGING STATIONS

SEVERAL STANDARDS DICTATE SAFETY MEASURES THAT FAST CHARGING STATIONS MUST EMPLOY.

USING SIMULATION TO OPTIMIZE GAN-POWERED DESIGNS

COMPARISONS OF TRANSISTOR DEVICE MODELS AND SIMULATION TECHNIQUES ILLUSTRATE WHICH APPROACH WORKS BEST FOR SPECIFIC DESIGN SCENARIOS.

CONFIGURABLE SIC DIGITAL GATE DRIVERS ENABLE ELECTRIFICATION REVOLUTION

SILICON-CARBIDE MOSFETS AND DIGITAL GATE DRIVERS WORK TOGETHER TO MAKE ELECTRIFIED METRO, SUBWAY, AND OTHER HEAVY TRANSPORTATION VEHICLES POSSIBLE.

10

31

40

44

OPTIMIZING POWER DELIVERY NETWORKS

A FEW RULES OF THUMB HELP NAVIGATE THE NUANCES AND COMMON PITFALLS OF POWER SYSTEM DESIGN USING POWER MODULES.

POWER SYSTEM DELIVERY FOR 5G NETWORKS

SPECIAL FEATURES SUCH AS FOLD-BACK PROTECTION AND GOOD DYNAMIC RESPONSE COME IN HANDY FOR THE DC-DC CONVERSION STAGES POWERING 5G RANS.

BASIC CURRENT SENSING CONSIDERATIONS IN POWER SYSTEM DESIGN

SIZE CONSTRAINTS AND A NEED FOR HIGH EFFICIENCY ARE FORCING DESIGNERS TO USE MORE SOPHISTICATED CURRENT SENSING TECHNIQUES IN MODERN ELECTRONICS.

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5

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SAVE THE DATE JOIN THE TOP POWER ELECTRONICS ENGINEERS, RESEARCHERS AND SCIENTISTS AT ECCE THE WORLD’S LEADING CONFERENCE ON ELECTRICAL AND ELECTROMECHANICAL ENERGY CONVERSION. For more information check our website: https://www.ieee-ecce.org/2022/

Or contact us at: info@ieee-ecce.org

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S I C G AT E D R I V E R S

Configurable SiC digital gate drivers enable electrification revolution

NITESH SATHEESH, TOMAS KRECEK, PERRY SCHUGART, XUNING ZHANG, KEVIN SPEER, MICROCHIP TECHNOLOGY

SILICON-CARBIDE MOSFETS AND DIGITAL GATE DRIVERS WORK TOGETHER TO MAKE ELECTRIFIED METRO, SUBWAY, AND OTHER HEAVY TRANSPORTATION VEHICLES POSSIBLE.

G

reen initiatives continue to transform power electronic system designs in industrial, aerospace, and defense

applications, and especially the transportation sector. Silicon Carbide (SiC) technology is at the center of this trend, delivering new capabilities for cutting greenhouse gas (GHG) emissions by electrifying a broad and growing range of vehicles and aircraft.

SiC devices enable smaller, lighter, and more efficient electrical alternatives to aircraft pneumatics and hydraulics systems for powering on-board alternators, actuators, and Auxiliary Power Units (APUs). They also reduce the maintenance requirements for these systems.

But the most prominent showcase for SiC technology is the mission to electrify commercial transportation vehicles which are among the

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2 • 2022

world’s biggest sources of GHG emissions.

With the arrival of 1,700-V MOSFETs and configurable digital gate driving technology, today’s SiC devices enable designers to extract the most productivity from these systems while dissipating the least amount of energy.

Moving to 1,700-V MOSFETs has extended SiC technology’s power conversion benefits to electrified commercial and heavy-duty vehicles as well as to light rail traction and auxiliary power. The devices are enabling the automotive powertrain of today and the future and are quickly replacing older silicon MOSFETs and Insulated-Gate Bipolar Transistors (IGBTs). They meet the high power and voltage requirements of big CO2-equivalent GHG emissions emitters including buses, rail, medium- and heavy-duty trucks, and the charging infrastructure. They also deliver much higher system efficiency and reliability than silicon MOSFETs and IGBTs, enabling designers to reduce the size of auxiliary power units (APUs) and other key vehicle systems.

Today’s 1,700-V SiC devices reduce switching losses to a tiny fraction of what

DESIGN WORLD — EE NETWORK

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POWER ELECTRONICS HANDBOOK

silicon IGBTs exhibit. This enables designers to boost switching frequency and shrink the size of the power converter. The devices have no knee voltage, unlike IGBTs, so conduction losses are also lower for systems such as transportation APUs that operate under “light load conditions” – i.e., they open and shut train doors that spend most of their time closed and not drawing power. A vast array of applications operate at light load across the majority of their service lifetimes. Designers can make use of SiC MOSFETs’ low switching and conduction losses to eliminate a variety of thermal management measures such as heat sinking.

The simplified circuit topology and reduced component count of today’s higher-voltage SiC MOSFETs also improve reliability while reducing costs. Their 1,700V blocking voltage reduces power converter size and enables designers to replace three-level circuit architectures with a much less complex two-level circuit—that is, two semiconductor devices between input and output rather than three.

This halves device count – or more while streamlining control.

SIC MOSFET CONSIDERATIONS

When choosing SiC MOSFETS for heavy-duty transportation vehicles and other multimegawatt applications, designers must consider several important factors. Among these is whether to use modular devices based on a basic unit cell (also known as a power electronics building block or sub-module).

Historically, the power semiconductor devices used in the unit cells have been 1,200 to 1,700V silicon IGBTs. Much as in lower power applications, the deployment of 1,700-V SiC MOSFETs at the unit cell level extends power

8

handling capability and electrical performance. Because 1,700-V SiC MOSFETs have much lower switching losses, it becomes possible to boost switching frequency and drastically reduce the size of each unit cell. Moreover, the high 1,700-V blocking voltage reduces the number of unit cells needed for a given dc link voltage, which ultimately heightens system reliability while slashing cost.

Designers should also evaluate the SiC MOSFET intrinsic body diode. Devices should show no perceptible shift in tests of pre- to post-stress ON-state drain–source resistance (RDSon). This point is critical for ensuring the MOSFET will not degrade after many hours of constant forward current stress as it conducts reverse current and commutates any remaining energy after a switching cycle. Designers must carefully review SiC MOSFET test results because devices from different suppliers can exhibit substantial variations. Many show at least some level of degradation while others may even become unstable. Choosing a SiC MOSFET that will not degrade eliminates the need for an external antiparallel diode and associated die cost and power module real estate.

There still may be challenges associated with varying levels

DESIGN WORLD — EE NETWORK

2 • 2022

of potentially inconsistent body diode performance – for some devices more than others. These inconsistencies can be resolved by adjusting the SiC MOSFET turn-on parameters using configurable digital gate drivers. These same drivers also are used to mitigate the secondary effects arising from the faster switching speeds of SiC MOSFETs. These effects can include noise and electromagnetic interference (EMI) as well as limited short-circuit-withstand time and overvoltage caused by parasitic inductance and overheating.

Configurable digital gate driving has become the key to unleashing the full capability of SiC technology.

Configurable digital gate drivers have been designed specifically to mitigate the secondary effects of SiC MOSFETs’ faster switching speeds. Besides cutting drain-source voltage (VDS) overshoots by up to 80% as compared to the traditional analog approach, they halve switching losses and reduce time to market by up to six months. They make it possible to source/sink up to 20 A of peak current and provide an isolated dc/dc converter with a lowcapacitance isolation barrier that can be used for pulse-width modulation signals and fault feedback.

Configurable digital gate

COMPARING A TRADITIONAL ANALOG GATE DRIVER TO TWO GENERATIONS OF CONFIGURABLE DIGITAL GATE DRIVER TECHNOLOGY.

drivers also provide robust fault monitoring and detection while delivering independent short-circuit response. They offer much more precise MOSFET turn-on/turn-off control than traditional analog gate drivers, which only control turn-off slope through gate resistors for normal and short-circuit situations.

Even when standard analog gate drivers are adapted for use with SiC MOSFETs, they cannot deliver these capabilities.

Augmented switching capabilities via configurable digital gate drivers enable designers to significantly reduce development time. Designers can explore configurations and re-use them for different gate driver parameters such as gate switching profiles, systemcritical monitors, and controller interface settings. Thus designers can quickly tailor gate drivers to a variety of applications without any hardware changes. Control parameters can be modified at any point in the design process, and designers also can change switching profiles in the field as application conditions require and/or SiC MOSFETs degrade.

These augmented switching

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S I C G AT E D R I V E R S

capabilities continue to evolve. Digital gate driving now provides up to two turn-on control steps compared to the single step of traditional analog drivers, and up to three turn-off control levels. The multiple steps provide a “soft landing” during turn-off that is much like tapping a foot on an antilock system’s brakes.

The addition of a fourth short-circuit setting level provides the opportunity for even more precise control over the secondary effect of SiC switching speeds. It also helps address overshoot, ringing and turn-off energy, among other variables. These capabilities give designers the combination of faster switching and more granular and dynamic, multi-step turn-on and turn-off control that will enable them to meet the increasing demands of SiC applications.

One example is motor control. A too-high rate-of-change of voltage (dV/dt) shortens motor life expectancy and correspondingly boosts warranty costs. Until higher-frequency motors are available, the only way to solve this problem with analog gate drivers is to slow SiC switching speed at the expense of efficiency. Only with the configurable augmented turn-on capabilities of digital gate drivers can dV/dt be optimized.

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Use of a comprehensive SiC ecosystem offers a direct path from evaluation to production. Key elements include a gate driver core, module adapter boards, an SP6LI lowinductance power module, mounting hardware, and connectors to the thermistor and dc voltage. Programming kits should be provided for the configurable software.

The module adapter boards are particularly important. They enable designers to quickly configure and re-use gate driver turn-on/turn-off voltages. This re-use can take place across many different suppliers’ SiC MOSFETs with a variety of positive or negative voltage ranges, without requiring any redesign, even if the SiC MOSFET previously used an analog gate driver. Simply reconfiguring the digital gate driver enables designers to immediately move into production. Meanwhile they can continue mixing and matching gate driver cores and module adapter boards and follow the same accelerated path to production. They can begin testing immediately with an SP6LI low-inductance power module connected to a laptop computer and a phase leg.

2 • 2022

The combination of 1,700-V SiC MOSFETs with digital gate driving technology has already had an impact on the “electrification of everything” and, more specifically, heavyduty transportation vehicles. It has enabled SiC technology to support vehicle power conversion needs while improving efficiency and reliability. In addition, the augmented switching capabilities provided by configurable digital gate drivers is speeding and simplifying the path from design to production. Use of these drivers also create new capabilities including the ability to change switching profiles in the field as application conditions require and/or as SiC MOSFETs degrade.

One of the most welcome benefits for designers is that the use of configurable digital gate driving with these devices eliminates the laborious process of soldering gate resistors onto a board to change behavioral parameters.

All of this can now take place via keystrokes, accelerating the Electrification of Everything.

REFERENCES

Microchip Technology, www.microchip.com

DESIGN WORLD — EE NETWORK

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POWER ELECTRONICS HANDBOOK

Protecting fast EV charging stations An

SEVERAL STANDARDS DICTATE SAFETY MEASURES THAT FAST CHARGING STATIONS MUST EMPLOY. PHILIPPE DI FULVIO, LITTELFUSE, INC.

estimated 5.5 million electric vehicles (EVs) were on the road in 2020. By

2025, the expectation is that over 24 million EVs will be in use. A significant limitation to wider EV adoption is the public charging infrastructure required to support long-distance travel. In 2019, only 7.3 million chargers existed worldwide with less than a million available for public access. Few of these chargers could recharge an EV in a time frame anywhere near that of filling the gas tank of an internal combustion vehicle.

Today, the latest high-power, dc charging technology can handle battery charging in under 30 minutes. As more fast-charging stations become available, the adoption of EVs will also accelerate.

Clearly, design engineers face multiple challenges in developing EV charging stations.

Most important is that of safety, as users must interface with over 300 kW of charging station power. Other important design parameters include high efficiency to reduce both power consumption and maximum temperature rise.

Outdoor recharging stations must perform reliably despite exposure to a wide range of environmental conditions.

There are three types of commercial charging stations. In North America, charging stations are classified into ìLevelsî while the European Union differentiates charging stations

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using ìModes.î The AC Level 1 charging station, with the in-cable control box (ICCB), is intended for charging at a residential home. The AC level 2 can be either a home or a public installation. The third type is a DC Fast Charging Station used in public and commercial settings. Organizations such as the Society of Automotive Engineers, the European Union automotive standards organization, and Asian counties such as Japan and China are trying to standardize charging stations.

The DC Fast Charger (Mode 4) is designed to charge an EV battery to 80% capacity in under 30 minutes. These chargers have power ratings up to 350 kW and can supply up to 400 A to a battery. Mode 4 chargers present special design challenges in keeping the charger cables cool and preventing ground currents. But they are of high interest today because their charging time is shorter than the alternatives.

Compared to ac charging systems, the dc charging station has the added complexity of ac-dc power conversion. When designing with tens of hundreds of kilowatts of power, it is essential that dc charging station designers particularly emphasize efficient power conversion, reliability, and user safety.

POWER DISTRIBUTION UNIT

At the connection to the ac source, the dc charger requires protection from overload currents and short circuit conditions with a fast-acting, high current fuse. The fuse must have a current interrupting rating large enough to ensure it exceeds the energy available from the ac line. Some fuses can have ratings up to 200 kA. The main protection from current overloads and voltage transients comes from the Input Protection circuit. It should

EV CHARGING STATION TYPES AND THEIR POWER CAPACITY.

2 • 2022

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FAST EV CHARGING

DC CHARGING STATION AND THE RECOMMENDED PROTECTION, CONTROL, AND SENSING COMPONENTS.

incorporate a fast-acting fuse to protect downstream sensitive circuitry.

As with the ac charging station, it should also contain surge-protection measures to withstand high-energy transients. Instead of using a surgeprotection device, consider a power TVS diode for fast response and low voltage clamping. A TVS diode can also serve as a secondary level of protection accompanying a primary surge protector.

One essential requirement for three-phase power sources is a monitoring facility for a fault in the power system ground. The recommended way of monitoring current in the ground line is via a current transformer. The current transformer should be able to detect under 30 mA and should incorporate flux conditioning to avoid saturation. Use a ground-fault protection relay to measure the current

from the current sensor and disconnect the input power in the event a high ground current is detected.

Let us now turn to the rectifier and power factor correction (PFC) function. Bridgeless PFC circuits seek to minimize the number of semiconductor devices in the active current loop at any time to minimize power losses and maximize efficiency. If the ac power source is three-phase for a high-power dc charger, the topology is known as Vienna or a boost-stage topology.

Because the dc charger is a high-power system, even small improvements in efficiency bring significant savings in power consumption. Use of Schottky rectifier diodes or diode modules reduces turn-on voltage requirements. Along with low forward voltage, look for diodes exhibiting low leakage current. Select individual diodes or use diode modules if the component count is a critical concern.

Use of silicon MOSFETs, SiC MOSFETs, or IGBTs can all maximize the efficiency of the rectifier and PFC circuit. Silicon and SiC MOSFETs exhibit fast switching rates and enable higher frequency operation.

Use of higher switching frequencies reduces inductor size which in turn improves efficiency. Of course, transistor temperature should be monitored to prevent excessively high junction temperatures.

Consider using a gate driver chip to control the power transistors.

Standard

Title

General Scope

Region

IEC 61851 Series

Electric Vehicle Conductive Charging System

Various parts of this standard cover general requirements, along with AC chargers and DC chargers specifically.

Global

IEC 62196 Series

Plugs, Socket-Outlets, Vehicle Connectors and Vehicle Inlets - Conductive Charging of Electric Vehicles

Standards for charging plugs, sockets, and connectors.

Global

GB/T 18487 Series

Electric Vehicle Conductive Charging System

Various parts of this standard cover general requirements, along with AC chargers and DC chargers specifically.

China

GB/T 20234 Series

Connection Set for Conductive Charging of Electric Vehicles

Standards of charging plugs in China.

China

SAE J1772*

Electric Vehicle and Plug-in Hybrid Electric Vehicle Conductive Charge Coupler

Physical, electrical, functional and performance standard for charging plugs in North America.

North America

UL 2594

Standard for Electric Vehicle Supply Equipment

Safety standard for supply equipment (charging stations, cord sets, power outlets, etc) in North America. Tri-national standard for U.S., Canada, and Mexico (known as CAN/CSA C22.2 No. 280 in Canada and NMX-J-677-ANCE in Mexico).

North America

UL 2202

Standard for Electric Vehicle (EV) Charging System Equipment

Safety standard for electric vehicle charging equipment.

U.S.

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EV CHARGING STANDARDS

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POWER ELECTRONICS HANDBOOK

Gate drivers can operate the transistors at a high switching frequency and consume little power while providing drive currents as high as 30 A. There are both inverting and non-inverting versions. In a nutshell, gate driver chips simplify the task of controlling power MOSFETs and IGBTs. The full bridge, resonant, and gate driver circuits should use the same protection components suggested for the rectifier and PFC circuitry. These components help to minimize power losses in the whole ac-dc conversion block.

DC OUTPUT

The dc output should use a fastresponding high-current, high-voltagerated fuse to protect the output circuitry from overheating. The CHAdeMO (CHArge de MOve) Association promotes a fastcharging infrastructure for dc charging that calls for a reverse-flow protection diode in the secondary rectifier. This diode serves as redundant protection against a short condition. Finally, control the output to the vehicle with a high-voltage dc contactor.

This should be an IP-67-rated, gas-filled contactor both to mitigate arcing and to prevent moisture and dust ingress.

The DC-Earth-Fault Protection circuit monitors for ground faults on ungrounded systems. Select a dc ground-fault monitor with an adjustable alarm threshold limit and an adjustable trip delay to avoid nuisance activation of the relay. Use a ground reference moduleóbasically, a twoelement resistor network which, with the ground-fault monitor, is designed to detect when either the high or low output lines short to earth ground. The contacts of the high-voltage dc contactor open to prevent damage to the vehicleís battery circuitry and the charger circuitry.

The Charging Plug Position/Temp circuit is another significant safety circuit.

Both dc and ac chargers should use the same temperature and proximity sensors.

In the ac-dc converter for the logic and control circuitry, use of Schottky diode rectifiers and high-power MOSFETs with high-speed switching minimize power loss and maximizing efficiency. The MOSFETs have a low RDS(On) which reduces power consumption when the MOSFET is conducting.

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DC CHARGING STATION BLOCK DIAGRAM WITH COMPONENTS RECOMMENDED FOR CIRCUIT BLOCKS.

Standards bodies require a fuse in the Auxiliary Power Supply. Transient protection can come from either a MOVGDT combination identical to that in the ac charging station Input Protection circuit or a MOV-protection thyristor as recommended for the ac charging station Auxiliary Power Unit.

The Communication, User Interface, and Access Panel Sensors circuits perform the same functions in both dc and ac charging stations. Protect the data lines from ESD using the components recommended for the ac charger. Use the reed proximity sensor recommended for the AC Access Panel Sensors circuit in the dc charger circuit.

Because dc charging stations consume and deliver high power, they must meet several safety certifications. IEC 61851, UL 2594, and GB/T 18487 Series are the three primary standards that charging stations must meet.

2 • 2022

Ensuring that charging circuits are both protected from environmental hazards and safe for user interaction complicates the job of designing EV charging stations.

It is difficult to be an expert in all areas of dc charging station design. Fortunately, manufacturers of protection products can offer design recommendations and help save development time. Application engineers can provide useful advice on the tradeoffs between power/volume, efficiency, and component costs. Some manufacturers will also assist with standards compliance and can offer precompliance testing services.

REFERENCES

Supercharged Solutions for EV Charging Stations Guide, http://www.littelfuse. com/~/media/electrical/brochures/ littelfuse-electric-vehicle-charging-

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POWER ELECTRONICS HANDBOOK

Putting supercapacitors to work GEORGE WUNDSAM, CORNELL DUBILIER

S

upercapacitors are not new. First developed in the 1950s, commercial versions were marketed over 40 years ago. At that time, supercapacitors were certainly not on a fast track to

practical application. They were expensive, had quite low operating voltages, and were outperformed by other, more economical approaches.

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THERE ARE A VARIETY OF MODERN APPLICATIONS IN WHICH SUPERCAPACITORS ARE BETTER CANDIDATES THAN EITHER BATTERIES OR ORDINARY CAPACITORS.

Gradually, things changed. Supercapacitors (a.k.a. ultra-capacitors or EDLC capacitors) have become quite practical. Their capabilities and performance have greatly improved, with higher operating voltages, capacitance, and the ability to retain a charge. In many applications, they are now the approach of choice.

While most engineers have a basic understanding of supercaps, relatively few have put them to use. So it is helpful to discuss the applications that best fit supercaps and the pluses and minuses of the technology vs. batteries or in combination with batteries.

Lithium-ion battery technology continues to dominate global markets and will for the foreseeable future. But alternative energy storage technologies like supercapacitors are becoming more accepted as safe, scalable, efficient, and sustainable options. Instead of relying on chemicals for energy storage, as with batteries, supercapacitors store energy electrostatically and neither age nor wear out the same way batteries do. The dry electrode used in supercapacitors has a long lifespan and can be made from a variety of advanced materials such as carbon nanotubes, graphene, and carbon aerogels.

Supercapacitors have clear advantages over batteries as they have a wide operating temperature range, as well as short charge and SUPERCAPS COME IN A discharge times. The short charge/ VARIETY OF PACKAGE SIZES. discharge times arise because of their

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S U P E R C A PA C I T O R S

Supercapacitor

Hybrid LLC Supercapacitor

Lithium-Ion Battery

Energy density

Low

Medium

Very high

Power density

High

Medium

Medium

Rapid charge/discharge

Seconds

Minutes

Hours (requires charge control)

Internal resistance

Low

Medium

High

Low temperature performance

Good

Limited

Poor

High temperature performance

Good (up to 85°C)

Good (up to 85°C)

Poor (up to 55°C)

Self discharge rate

Medium

Low

Low

Maintenance

Maintenance Free

Maintenance Free

Maintenance/ Replacement

Lifetime (Float/Cycling)

Long

Long

Relatively Short

Safety and Flammability

High Safety (no thermal runaway)

High Safety (no thermal runaway)

Safety Issues (self heating/flammability)

Application

Very High Power (Lower Energy)

High Power (Medium Energy)

Medium Power (High Energy)

HERE ARE HOW THE PROPERTIES OF SUPERCAPACITORS, HYBRID LIC SUPERCAPACITORS, AND LITHIUM-ION BATTERIES STACK UP.

minimal internal resistance. They can be cycled hundreds of thousands, if not a million times. It is also safer to store energy in an electric field instead of chemically, thus diminishing the risk of thermal events.

All in all, supercaps have a service life of between 10-15 years.

COMPARING ENERGY STORAGE TECHNOLOGIES

Hybrid LIC (lithium ion capacitor) supercapacitors can be charged and discharged up to 500,000 cycles; the figure is one million cycles for conventional supercaps. (LICs are called hybrids because the anode is the same as those used in lithium-ion batteries while the cathode is the same as in supercapacitors.) And unlike batteries, the energy storage capability of supercaps does not degrade with each charge/discharge cycle.

Supercapacitors serve as a key technology for preserving the environment: They provide short bursts of high power that are useful in electric vehicles and grid applications.

Supercapacitors can provide main power, backup power, or pulse power. Unlike batteries, supercaps have the same efficiency during charge or discharge. This property enables the supercapacitor to recharge quickly without

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current limiting, provided the current is within the supercap ratings.

Supercapacitors are offered in a full range of capacitance values, in singlecell or modular configurations. Supercap modules allow virtually unlimited working voltages or capacitance. As a result, supercap applications span milliamp or milliwatt levels on up to several hundred amps or several hundred kilowatts.

Electrolytic capacitors have long been critical components in uninterruptible power supplies. The capacitors let the UPS kick in quickly, while lead-acid and lithium-Ion batteries handle the power requirements for sustained backup. But supercapacitors can supply bulk storage with less volume and fewer components. They have become a maintenance-free alternative to lead-acid batteries and lithium-Ion for short-term and bridge power applications. For example: In data centers and cloud computing, supercapacitor-based UPS systems can reliably provide 15-30 seconds of power.

Their wide temperature ranges and safety make such systems candidates for use in hospitals and other critical backup applications. The newer designs also eliminate the high costs associated with battery maintenance and replacement.

2 • 2022

In electronics/semiconductor manufacturing, two seconds of ride-through time is required per SEMI F47. Here too, the benefits of long-term reliability (500K+ power cycles), maintenance-free operation, and design flexibility have been recognized.

Supercapacitors have become a good source of backup power for Internetenabled wireless data terminal products.

In the automotive industry, they support innovative analytics, business intelligence, driver identification, location, and data management. Supercapacitors extend device connectivity by providing highly reliable power to capture and transmit real-time data if the device is unexpectedly disconnected.

In another recent application, CDE worked with a manufacturer of barcode scanners for use in point of sale (POS) systems. These handheld scanners incorporate power-consumption management to prolong overall battery life, provide last-gasp functions and battery ìhot-swapî support. CDE supercapacitors contribute to the scannersí power efficiency by delivering lower power drain, saving an estimated 20% to 30% of the batteryís power.

Depending on the product, backup power is supplied by single-cell sizes ranging from 1.5 to 110 °F and by custom assemblies with pre-

DESIGN WORLD — EE NETWORK

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POWER ELECTRONICS HANDBOOK

attached wire leads and connectors. The same approach taken in these scanners can be applied to various types of portable instrumentation.

Supercaps also play a role in automated warehouse storage and retrieval systems (ASRS). The use of supercapacitors as a power source in shuttles and 3-D shuttles reduces system failures and maintenance requirements caused by power source interruptions.

Supercapacitors can also provide peak power when used in conjunction with traditional power sources to overcome starting inertia, allowing for smaller main power sources.

Here too, we see similar benefits to other applications, including fast charge/discharge, maintenance-free (no scheduled downtime) operation, design flexibility, and wide operating temperature range -40 to 85 °C. In the quest for net carbon zero energy goals, the use of supercapacitors in support of batteries can make hybrid storage systems efficient and flexible, reducing the total cost of ownership and lowering the overall environmental impact. Larger energy storage generally requires supercapacitor modules.

A single supercapacitor cell operates at relatively low voltage, so many applications require multiple cells in series to realize the required voltage. It is necessary to prevent individual cells from exceeding their rated voltage, a task complicated by the fact that each cell has a slight tolerance in capacitance and resistance.

The procedure for keeping supercap cells below their rated voltage is called balancing. Balancing can be active or passive. Passive balancing implies no variation in the voltage regulation as a function of the ultracapacitor condition. The most typical method of passive balancing utilizes resistors in parallel with the capacitors. In contrast, active voltage balancing is preferred for applications with a limited energy source or a high level of cycling. An active circuit typically draws a current much lower than resistive balancing when it is in steady-state. And it only requires larger currents when the cell voltage is out of balance.

In summary, supercapacitors deliver rapid, reliable bursts of power over hundreds of thousands to millions of duty cycles ñ even in demanding conditions.

Supercapacitors are candidates for applications ranging from wind turbines and mass transit to hybrid vehicles, IoT, consumer electronics, smart meters, telematics, and industrial equipment.

WHEN A SUPERCAP CHARGES, THE ELECTRODES START TO ATTRACT THE IONS OF OPPOSITE POLARITY. THE POSITIVE ELECTRODE ATTRACTS THE NEGATIVE IONS OR CHARGES AND THE NEGATIVE ELECTRODE ATTRACTS THE POSITIVE IONS OR CHARGES. AS A RESULT, THE POSITIVE IONS OR CHARGES CREATE A LAYER NEAR THE NEGATIVE ELECTRODE AND THE NEGATIVE IONS CREATE A LAYER NEAR THE POSITIVE ELECTRODE. AS TWO LAYERS ARE FORMED BY THE ELECTRICAL CHARGE CARRIERS, SUPERCAPS ARE SOMETIMES CALLED ELECTRICAL DOUBLE LAYER CAPACITORS(EDLC). WHEN WE CONNECT A LOAD ACROSS THE SUPERCAPACITOR, THE IONS START DISTRIBUTING THROUGH THE ELECTROLYTE SOLUTION AND GO TO THE MIXED STATE.

REFERENCES

Cornell Dubilier, http://www.cde.com/

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POWER ELECTRONICS HANDBOOK

Better thermal Management of eGaN FETs A FEW SIMPLE THERMAL MANAGEMENT GUIDELINES CAN HELP CONDUCT HEAT AWAY FROM GaN FETS. ASSAAD HELOU, EFFICIENT POWER CONVERSION

E

nhancement-mode gallium nitride (eGaN) FETs offer high power-density with ultra-fast switching and low on-resistance, all in a compact form factor. However, the power levels these

high-performance devices provide can be limited by extreme heat-flux densities. If not managed properly, the generated heat can compromise reliability and performance. Fortunately, chip-scale packaging for eGaN FETs can be leveraged at the board-side and the backside (i.e., case) to better dissipate heat.

Packaged electronic devices dissipate the heat they generate through two main paths – to the printed circuit board (PCB) at the board-side and to the case at the backside. Both avenues can benefit from thermal management strategies.

Heat generated within the FET encounters its first thermal resistances from the semiconductor junction to the PCB (RθJB) and from the junction to the transistor case (RθJC). These two thermal resistances, usually given in °C/W or °K/W, differ for each FET because they depend on the device construction and the thermal conductivity of the materials used. For wafer level chip-scale packaged (WLCSP) GaN FETs, the RθJC is lower than for silicon devices. But both RθJC and RθJB can be used to significant advantage.

Semiconductor device makers typically report the maximum

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JUNCTION-TO-CASE AND JUNCTION-TO-BOARD THERMAL RESISTANCE COMPARISON BETWEEN GaN AND SILICON DEVICES.

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THERMAL MANAGEMENT

SIMPLIFIED THERMAL RESISTANCE NETWORK MODEL SHOWING MAIN HEAT CONDUCTION PATHS AND ASSOCIATED TEMPERATURE NODES FOR AN FET LAYOUT. PCB THERMAL PERFORMANCE COMPARISON BETWEEN DIFFERENT CONFIGURATIONS THAT INCLUDE THERMAL VIAS NEAR AND UNDERNEATH THE FET PADS.

temperature rise (in °C or °K), and the resulting overall thermal resistance for the maximum temperature at the device junction with reference to an ambient temperature in still air (RθJA) or in moving air (RθJMA). The thermal resistance to the board is one component in a network of heat conduction paths that determines the overall self-heating in a GaN FET device.

A simplified circuit model representing the main heat conduction paths from the junction to ambient on a standard PCB contains four thermal resistances: In addition to RθJC and RθJB mentioned previously, there are thermal resistances from the case to the ambient, RθCA , and from the PCB to ambient, RθBA. Additionally, when two heat-generating devices sit near each other on the PCB, there may be another thermal resistance between their mounting points on the PCB, RθB12. Because the FET area is much smaller than that of the PCB, the heat dissipated from the FET to ambient through the case is minimal, so thermal resistance RθCA is large.

As a result, without any back-side cooling, the main heat dissipation path from the FET is through the PCB. This explains why good thermal conductance at the board-side must be ensured.

Heat conducts from the FET into the board mainly by the copper traces within the

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conducting layers of the PCB. Thus it is helpful to specify PCB traces that are thicker not only for low electrical resistance but also for better heat conduction at each layer of the PCB. For example, two-ounce copper layers have twice the conductance of one-ounce layers in the lateral directions. Moreover, the in-plane heat conductance depends proportionally on the number of PCB layers because more layers offer more paths to dissipate heat.

In the through-plane direction, the insulating dielectric layers separating the copper layers have a low thermal conductivity and thus obstruct heat dissipation. Heat conduction can be partially improved by placing vias beneath or near the FETs. The vias provide a path with high thermal conductivity

that bridges the dielectric layers and carries generated heat into the inner copper layers of the PCB. The inner layers, in turn, help spread heat, further reducing RθJB and RθJA. Strategically placed thermal vias near or under the FET pads can reduce self-heating (ΔT) by up to 33%.

IMPROVING JUNCTION-TO-CASE DISSIPATION

Heat also dissipates from a wafer level chipscale packaged (WLCSP) GaN FET device die through the case which offers a much lower resistance (RθJC) than the board-side and lower than other types of packaged devices. The exposed die area of the FET is too small for any significant thermal exchange with the

PCBS WITH A), NO BACK-SIDE COOLING; B), WITH A CONNECTED COPPER HEAT SPREADER; C), WITH AN ALUMINUM HEATSINK. NOTE. THE HEAT SPREADER AND HEATSINK CAN BE COMBINED OR BE INDEPENDENT. HEAT FLUX STILL FLOWS INTO THE PCB.

2 • 2022

DESIGN WORLD — EE NETWORK

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POWER ELECTRONICS HANDBOOK

surrounding air, so implementing simple thermal management strategies can improve backside cooling considerably.

The addition of a heat spreader in contact with the die provides a path for conducting heat in the lateral direction. The heat spreader increases effective surface area of the device and reduces its operating temperature. A heat sink can be added to the heat spreader to further enlarge the area of heat exchange area with ambient air. The heat spreader and heatsink typically use high conductivity materials, such as aluminum and copper, to ensure optimal performance.

A simple and assembly-friendly approach to attaching a heatsink to GaN FETs and ICs uses a thermal interface material (TIM) to enhance the thermal conductivity at the interface between the device and the heatsink, as well as to provide electrical insulation.

An SMD spacer between the heat sink and the PCB maintains the right spacing between the heatsink and the GaN device for the TIM and provides sturdy mechanical attachment for the heatsink.

Obviously, components taller than the SMD spacers must be excluded from under the heatsink.

Heat spreader/heatsink attachments added for backside cooling introduce several interfaces that impede heat conduction due to surface roughness and thermal contact imperfections. Moreover, air gaps between the components and attachments don’t conduct heat well. TIMs improve thermal contact and provide good conductance at the interface. TIM can come in several forms, including pads, gels, and liquid gap fillers.

The choice of a TIM involves several selection criteria. Perhaps most obvious, the TIM must have good thermal conductivity (κ) and low thermal resistance to conduct heat . A rule of thumb for κ is >

IA HEATSINK ATTACHMENT WITH A TIM PAD FOR GaN FETS AND ICs.

HEATSINK COOLING THAT INCLUDES A TIM PAD AND THERMAL GAP FILLER.

AN EXAMPLE OF HEATSINK ASSEMBLY USING SCREWS.

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A COMPREHENSIVE THERMAL SYSTEM ASSEMBLY WITH HEATSINK, SMD SPACES, TIM PAD, AND GAP FILLER.

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THERMAL MANAGEMENT THERMAL MODEL

THERMAL SYSTEM CROSS SECTION

THERMAL RESISTANCE CIRCUIT MODEL WITH HEAT SINK ATTACHMENT AND CORRESPONDING CROSS-SECTIONAL IMAGE. NOTE: T S ASSUMED UNIFORM IN LOCATION OF FETS.

3 W/m·K. TIMs with higher performance reaching κ > 15 W/m·K are available but more expensive and can be used at the FET interface.

The electrical resistivity is also important for the GaN FET die because the upper FET case will be at switch (SW) node potential and must be electrically isolated from the thermal components. T-Global A1780 and A6200 TIMs are examples for thermally and electrically compliant TIMs with high and moderate κ = 17.8 W/m·K and 6.2 W/m·K respectively.

Another consideration for selecting TIM is the compression force exerted on the die for a certain compression rate (thickness percentage given in the materials’ datasheets). The compression force must not exceed the stress limit of the GaN FETs. Generally, larger devices can withstand higher force. Land grid array (LGA) devices can withstand higher force than equivalent ball grid array (BGA) devices of the same size. The maximum recommended pressure on eGaN FETs and ICs is 40 psi/ mm2 of the total bump area and 50 psi for GaN devices in general, based on testing results.

Given the small scale of eGaN FETs, the area of their die sides is comparable to that of the top and bottom surfaces. Thus the sides can contribute considerably to heat conductance. For instance, the 0.9x0.9x0.625 mm EPC2038 FET die has a top and bottom surface area of 1.62 mm2 with the four sides measuring 2.25 mm2 in total. As a result, the four sides can also be used to help dissipate heat, usually by adding a gap filler material around the sides of the FET, such as the GF4000 liquid gap filler from Bergquist (κ = 4 W/m·K).

Now consider a resistive circuit model modified to include additional thermal resistances representing the heat conduction from the case to the sink (RθCS) and from the sink to ambient (RθSA). The board also connects to the sink through the metal shim, spacers and gap filler. Also, heat conducts between the board and sink and is represented by RθBS. Though this model contains more thermal resistances than the previous example, the combined thermal resistances of RθCS and RθSA are ideally

RESULTS OF THE THERMAL SIMULATIONS FOR ANALYZED CASES R th,JMA (K/W)

Percent improvement

Percent of heat extracted from PCB

Percent of heat extracted from case

R th,JS (K/W)

No vias

45.0

-28%

96

3

—

Side vias

35.6

-7%

97

2

—

Vias under pads (baseline)

34.5

—

97

2

—

+ Heat spreader

21.6

39%

54.5

45

4.9

Heat spreader + heat sink

14.9

60%

38.5

61

4.9

Case

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POWER ELECTRONICS HANDBOOK

THERMAL SIMULATION RESULTS FOR EPC9097 PCB WITH EPC2204 FETS AND HEAT SPREADING AND HEATSINKING. THE VIAS MODELED IN THE SIMULATIONS HAVE A VIA-IN-PAD PLATED OVER (VIPPO) CONSTRUCTION. MORE DETAILS ON THIS CONSTRUCTION CAN BE FOUND IN CHAPTER FOUR OF THE TEXTBOOK GAN POWER DEVICES AND APPLICATIONS.

much lower than RθCA. Thus, the overall effect is less total thermal resistance.

An example of how attaching a heat spreader and heatsink improves thermal dissipation can be seen in the EPC9097 development board.

It contains two EPC2204 GaN FETs which are considered major heat sources that must be cooled.

There are multiple scenarios for cooling these devices. First, consider the case where a copper heat spreader (κ ≈ 400 W/m·K) is attached to the board using M2 screws and SMD spacers. The high-performance TG-A1780 TIM (κ = 17.8 W/m·K) sits between the FETs and the heat spreaders.

Now consider an alternative approach where an aluminum heatsink is attached to the heat spreader using the same type of TIM. Power losses of 1 W are assigned to each FET. The PCBs are placed in 400 LFM air flow at 20°C for forced convection cooling.

The two above scenarios can be compared with baseline models where only board-side cooling is present and when vias are placed in various locations.

The maximum temperature is extracted from the thermal model and the overall thermal resistance is calculated in reference to ambient temperature for each FET power (1 W). The percentage of heat dissipated from the board-side and from the case-side are also reported to compare the thermal resistance of each path.

The results of the thermal analysis summarized in the nearby table show that even without backside cooling, improvements to the board design can reduce temperature by 30%. Compared to boardside cooling, adding a heat spreader to the FETs reduces the overall thermal resistance from 34 °K/W to 22 °K/W (about 40%), while a heatsink reduced the overall thermal resistance to ambient to around 15 °K/W (a 60% decrease from baseline). By reducing

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2 • 2022

the thermal resistance to back-side cooling, the percentage of heat dissipated through the case rose from 2% (baseline) to 45% with a heat spreader and 61% with an attached heatsink. Given that junctionto-sink thermal resistance is at 4.9 °K/W, improving the heatsink (larger fins, more air flow) can reduce the overall thermal resistance even further.

All in all, when limited to board-side cooling, strategically placement of thermal vias under or near the FETs can improve board conductance significantly. This strategy allows heat to dissipate into the board’s inner copper layers more effectively and reduces peak operating temperatures by around 30%. Moreover, with a low junction-to-case thermal resistance of WLCSP eGaN FETs, the backside offers considerable thermal cooling potential.

Simple thermal management strategies, such as attaching a heat spreader or a heatsink, can increase a device’s effective thermal dissipation area. Use of these measures can reduce FET temperatures by up to 60%, as determined by detailed simulations. With good thermal considerations and simple thermal management strategies, small chip-scale devices can be adequately cooled for reliable performance in high-power applications.

REFERENCES

Efficient Power Conversion, www.epc-co.com GaN Power Devices and Applications, epc-co.com/epc/Products/Publications/ GaNPowerDevicesandApplications.aspx

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The Loss Leaders (lowest)

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Their ultra-low DCR and higher Irms also allow XGL Family inductors to operate

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Download the datasheets and request free samples at www.coilcraft.com. ®

WWW.COILCRAFT.COM

POWER ELECTRONICS HANDBOOK

How trimming affects thick-film resistor performance KORY SCHROEDER, STACKPOLE ELECTRONICS INC.

ORDINARY THICK-FILM RESISTORS CAN DISPLAY VARYING QUALITIES DEPENDING ON HOW THE MANUFACTURER ELECTED TO TRIM THE DEVICE. IT PAYS TO KNOW WHAT TO LOOK OUT FOR.

S

urface-mount thick-film chip resistors are the predominant type of resistor in electronic circuits today. This

technology is inexpensive; thick-film resistors are produced by screen-printing a special paste (a mixture of glass and metal oxides) on to a ceramic substrate. Depending on the size of the chip, hundreds or thousands of parts may be processed simultaneously.

The screen printing process generally yields resistors within 5% to 20% of the required value, so manufacturers calibration-trim the resistors by laser to get the right value without slowing resistor production.

There are different laser trim designs and shapes which present different manufacturing challenges and that yield different strengths and weaknesses.

The process of laser trimming thickfilm resistors involves pulsing a round laser beam into the cured thick-film material.

The laser light vaporizes the material under and around the beam. Removal of resistor material slightly raises the resistance value.

Subsequent pulses remove more material and further raise the value of the resistance.

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DESIGN WORLD — EE NETWORK

The simplest and most obvious trim shape is the single plunge or straight cut.

Of all the trim shapes it can be made the fastest but is also less precise than some other trim designs. The single-plunge trim is challenging for high precision because the further the cut into the element, the greater the effect. This trim type isn’t practical if the initial element value is far below the desired value because it will be difficult to adjust the resistance value without overshoot. However, a singleplunge trim is economical when the initial resistance is close to the final resistance value—trimming doesn’t take long and it is relatively easy to control the resistance value. But the trim speed for single-plunge trim tends to be somewhat slower than for other types though overall trim time is less.

Pulse-handling resistors should have little if any trimming. Current crowding effects—peaks in the current density--arise in the area around the trim, and that is the failure point for thick-film resistors under pulse conditions. So pulse-handling resistors are generally printed to close to their desired resistance. The single plunge is a effective trim shape for these types of resistors, but it is often too imprecise for general purpose and commodity chip resistors.

The double-plunge cut provides much more precision than single-plunge cuts.

2 • 2022

PLUNGE CUT IS THE MOST ECONOMICAL LASER TRIM TYPE THOUGH OVERALL TOLERANCE ACCURACY CAN BE LESS THAN THE OTHER METHODS. THIS METHOD IS OFTEN RECOMMENDED FOR DC APPLICATIONS.

DOUBLE CUT TRIM SPEED CAN BE GREATER THAN FOR A SINGLE CUT BECAUSE PRECISION COMES FROM THE SECOND CUT, WHICH SITS IN A LESS SENSITIVE TRIM AREA THAN THE FIRST. THE SECOND TRIM IS GENERALLY KEPT TO WITHIN 50 TO 80% OF THE FIRST TRIM LENGTH FOR THE BEST ADJUSTMENT RESULTS.

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THICK-FILM RESISTORS A L TRIM TYPICALLY STARTS AT ABOUT 15 TO 20% OF THE TOTAL RESISTOR LENGTH AWAY FROM THE CONDUCTOR-RESISTOR JUNCTION TO AVOID JUNCTION EFFECTS AND PROVIDE THE MAXIMUM ROOM FOR THE SECOND CUT.

SERPENTINE CUTS ARE CHARACTERIZED BY MULTIPLE TRIMS SPACED AN EQUAL DISTANCE APART. THEY MAY BE USED FOR VERY HIGH RESISTANCE VALUES OR LOW RESISTANCE METAL ELEMENTS.

TOP HAT TRIMS ARE EFFECTIVE FOR TRIMMING HIGH RESISTANCE AND HIGH VOLTAGE PRECISION FILM ELEMENTS.

THE SCAN CUT OFFERS BOTH HIGH ACCURACY AND HIGH FREQUENCY COMPATIBILITY. THE RESISTOR MATERIAL IS REMOVED ONLY FROM THE EDGE OF THE RESISTOR BODY. THIS TECHNIQUE TYPICALLY REQUIRES CONSIDERABLY MORE TIME PER RESISTOR THAN THE OTHER TRIM TYPES.

The first cut brings the resistance value close to the desired final value. The second cut is in an area with less current flow, so it changes the resistance much less, allowing for precise resistance control. The second trim length is kept between 50% to 80% of the length of the first cut to ensure stable electrical performance and continuous power handling. The precision for this trim shape depends only on the second cut, so the machine trim speed can be faster than for the single plunge. Many thick-film resistors are trimmed in this manner, especially those with smaller elements.

L trim is another common trim shape. This shape can yield a precision resistance while also providing a greater range of resistance value adjustment. The initial trim into the part stops when the resistance value begins to change rapidly. Then the laser changes direction and proceeds toward the opposite termination.

The second part of the trim allows for precision control because the current crowding arises only along the first part of the trim, so the second part causes much less change in resistance. L trimming can usually take place at the same speed as a double-plunge trim. The L trim is generally regarded as a more stable trim than single or double plunge but requires a somewhat larger resistor area for effective value calibration. Most thick-film resistors currently on the market will have either a plunge or L cut trim.

Serpentine cuts may be used to adjust resistance to a value significantly higher than the printed resistance. Trims are spaced equally apart and continue until the resistance value is reached. This trim type will have higher parasitic noise, lower overall stability, poorer pulse performance.

And the resistance material must be long enough to permit adequate value adjustment. Thus serpentine cuts are most effective for high resistances where power and current handling requirements are irrelevant.

Serpentine cuts are also occasionally used for adjusting metal plate sense resistors. These resistors generally use resistive material comprised of exotic alloys such as manganese-copper or nickel-chromium-aluminum to obtain special properties such as low inductance or low thermal EMF. Even when timed with serpentine patterns, their element mass and pulse capability stays roughly the same despite the length of the trims and the substantial amount of material removed.

Top hat trims—so named because the resistor material topology resembles the outline of a top hat-- provide the best accuracy and stability for high voltages and high resistance values. Top hat trims require a precise serpentine resistance element and are best for larger chip sizes.

The serpentine resistance pattern dramatically increases both the voltage capability and resistance value of the element. The top hat portion of the

MICROCRACKS ARISING BECAUSE OF THE LASER TRIMMING PROCESS MAY EXTEND INTO THE RESISTOR MATERIAL CAUSING POTENTIAL DRIFT PROBLEMS. MICROCRACKS CAN ALSO CAUSE A SHIFT ASSOCIATED WITH THE TEMPERATURE COEFFICIENT OF RESISTANCE (TCR).

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POWER ELECTRONICS HANDBOOK

TYPICAL VCR CURVES BY CASE SIZE

ONE OF THE OUTCOMES OF THE TRIMMING PROCESS CAN BE SHIFTS IN RESISTANCE VALUES DURING THE RESISTOR’S OPERATING LIFE AND A CHANGE IN RESISTANCE WITH VOLTAGE, PARTICULARLY FOR HIGHRESISTANCE THICK-FILM RESISTORS.

element provides a wider area for the laser trim, allowing precision value control without harming the resistor’s voltage capability. Most precision high-voltage resistor series utilize the top hat type of trim.

In scan cut trims, resistor material is typically removed from each edge of the resistor equally. Scan cuts are generally used when the adjustment range is small and high precision is required. This trim process is significantly slower than others and requires overlapping subsequent laser trim scans to ensure all material from each trim is completely removed. The best stability comes from starting and finishing scan trims in the conductors on the ends of the element.

This type of trim requires materials that are compatible with this trim operation. Thus this type of trim is not commonly used because of unique material requirements and of the time and control required.

LASER TRIMMING EFFECTS

It should be noted that the basic rule for trimming is that the trim itself should be minimized. For thick-film resistive elements, the process of laser trimming has detrimental effects which can’t be overcome. As the laser moves through the element, the material adjacent to the laser trim permanently changes. The thick-film material heats up in proportion to the distance from the laser trim.

As this material cools, microcracks develop

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DESIGN WORLD — EE NETWORK

TYPICAL 1000 HOUR LOAD LIFE AT FULL VOLTAGE RATING

because the cured thick-film material conducts heat relatively poorly. These microcracks lead to poorer TCR (temperature coefficient of resistance), poorer lifetime stability, higher parasitic noise, and increased VCR (voltage coefficient of resistance).

Also at the edge of the trim a dielectric glass layer forms. The material at the edge is referred to as laser slag and has a non-uniform appearance. The dielectric glass layer helps to stabilize resistive material at the trim edges and prevents it from falling into or across the trim line.

The effect of trimming becomes evident in graphs of resistance vs. VCR and resistance change vs. operating time. Generally 2 • 2022

speaking, trimming can cause significant degradation of VCR and resistance change over the life of the part.

All in all, each trim shape has its advantages relative to the design goals of specific thick-film resistor series.

Manufacturers minimize the trim length to ensure the best possible TCR, overall stability, and lowest noise.

REFERENCES

Stackpole Electronics Inc., www.seielect.com

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CURRENT SENSING

Basic current sensing considerations in power system design TEOMAN USTUN, ACEINNA SIZE CONSTRAINTS AND A NEED FOR HIGH EFFICIENCY ARE FORCING DESIGNERS TO USE MORE SOPHISTICATED CURRENT SENSING TECHNIQUES IN MODERN ELECTRONICS.

T

he historical mindset of power design being an afterthought in

ADVANCED CURRENT SENSORS SERVE IN A WIDE RANGE OF APPLICATIONS.

the overall system architecture is

changing. Before the focus of electronic design shifted to power efficiency, it was a common practice to simply add a power circuit to a system design once it was finished. This practice would simply not work today as power handling must be intrinsic to circuit control and monitoring.

The issues created by faulty power handling may cause intermittent performance problems which are extremely difficult to reproduce, especially during development. This problem is exacerbated once a system is deployed in the field; initial performance issues can cause cascading problems throughout the system that require expensive troubleshooting.

In recent years wide-bandgap materials have become available with significantly higher levels of performance than silicon in the areas of electron mobility, temperature, and switching speed. These materials are gallium nitride (GaN), a piezoelectric semiconductor that

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is well-suited to low-power and high-speed switching apps, and silicon carbide, whose remnants are sold to the jewelry industry as moissanite “artificial diamond” and can handle power and thermal levels far above those pracitcal for silicon-based circuits. Silicon is still the go-to material for microcontrollers and other logic devices but its days as a power semiconductor are numbered.

The ability to handle higher levels of power

2 • 2022

at a higher efficiency is already a game-changer, but the ability to switch at high speeds also enables the entire circuit to shrink, as you can use smaller passives such as capacitors and inductors, reducing board space used as well as weight. This extends beyond simple space savings, as the higher switching speed of GaN, for example, enables high-frequency systems like LIDAR to be driven in an optimum manner.

DESIGN WORLD — EE NETWORK

27

POWER ELECTRONICS HANDBOOK

MASTERING CONTROL

Another major aspect of modern power electronics is the ability to control the circuit down to the point of load, a capability that emerged in the last decade or so. This movement arose from the initial adoption of distributed power architectures, where a bus converter on the board sent power to individual point-of-load (PoL) converters sitting near devices to be driven. And this divided architecture could be controlled digitally.

This digital control was first standardized under the PMBus protocol, although there are other proprietary control methodologies available. The key is that each power device on the board can be addressed, polled, and controlled remotely. This setup enables a granular, optimized, and efficient way to manage power on the board. And the polling ability provides a way to obtain data on important aspects like a thermal map of the entire circuit.

Digital power management is at the core of the Internet of Things; control of any electronic system also entails control of power. In this context, current sensors are becoming increasingly important in power converter applications. For example, dc/dc switching applications achieve high efficiency via fast switching currents. Numerous control algorithms also depend on real-time current measurements.

The increased performance of widebandgap semiconductors has pushed other components on the board to boost performance to match, and the latest topologies demand the latest in protection and

A TYPICAL TOTEM POLE PFC SCHEMATIC SHOWING THE LOCATION OF A MAGNETIC SENSOR MODULE BASED ON HALL EFFECT OR AMR SENSING.

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DESIGN WORLD — EE NETWORK

control methodologies. For example, smart power techniques require the use of monitoring devices such as advanced current sensors.

These sensors measure current bidirectionally to both protect the circuit and batteries against abuse and to optimize performance.

The high energy densities and accelerated battery charge/discharge times that characterize modern electronics have brought more stringent requirements for current sensing. In the case of high energydensity batteries such as lithium-ironphosphate (LFP) or lithium-titanate-oxide (LTO, sometimes just called lithium-titanate) require coulomb counting to determine battery state-of-charge (SoC), state-of-health (SoH), and state-of-function (SoF).

Increasingly, traditional fuses are inadequate for advanced over-and undercurrent protection of power systems employing wide-bandgap semiconductors.

Use of a fuse for circuit protection also doesn’t provide any feedback on the realtime performance of the power electronics.

To protect from overcurrent conditions and improve safety, IC devices such as those from ACEINNA respond quickly and handle a large current measurement range. The isolated devices can operate in both the high and low sides of the power circuit, and their integrated construction simplifies the protection scheme compared to a shunt-plusamplifier approach. Using ACEINNA current sensors in high side, ground faults of the phase current (possibly due to wrong wiring, aging etc.) can also be detected.

The advantages of isolated current sensors such as those from ACEINNA become evident in the specific example of a totem-pole power factor correction (PFC) circuit. One such design uses a SiC-MOSFET C3M0065090K from Wolfspeed as its highfrequency switches and a IXFH80N65X2 from IXYS as the low-frequency switches. The SiCMOSFET provides the breakdown voltage needed and can dramatically reduce the 2 • 2022

ARM-BASED CURRENT SENSORS VERSUS OTHER COMMON CURRENT SENSOR TECHNOLOGIES.

reverse-recovery loss so the totem pole PFC can work in CCM (continuous conduction mode) to support higher power.

For traditional PFC designs, typically a shunt resistor is connected to the input of an op-amp is placed in the ground line to sense current. But in totem pole PFC designs, there is no ground line, so there’s no way to add a current-sensing shunt resistor as in a traditional PFC. That leaves designers with three other ways to sense current: current transformers (CTs), a shunt resistor with an op-amp and an isolator, and magnetic current sensor modules or ICs. A CT can sample the current through the main inductor. However, a CT can only work in ac. To sense switching current, it would take three CTs to sample and integrate the inductor currents in the positive and negative cycle through the MOSFET and rectifier.

And unfortunately, CTs also suffer from nonlinearities and hysteresis over temperature.

Another way to measure current is to insert a current shunt in series with main inductor. This approach requires an op-amp, an isolator, and a separate isolated power supply with multiple passive components around the isolator and op-amp. The circuit design is complex and adds to the space needed to house the PFC. Additionally, applications using higher currents must use accurate low-value resistors to minimize power dissipation, and these resistors can be costly. Further, output response time is slow because there is an opto-isolator and op-amp in the signal path. The combined output step response time can easily be over 1 µsec.

An isolated magnetic current sensor module or an IC containing Hall Effect or AMR (Anisotropic Magneto-Resistive) magnetic field sensors is another widely used method of current sensing. These magnetic current sensors provide the required isolation and do not need separate isolated power supplies. eeworldonline.com

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CURRENT SENSING

However, there are two major challenges with regard to magnetic current sensors.

First, traditional Hall Effect sensor modules or ICs typically have a bandwidth of about 120 kHz at best. That›s fine for 60-Hz PFC current, but the slow output response (related to bandwidth) can’t support the time frame needed for peak and over-current protection for fast switching currents.

Second, Hall effect magnetic current sensor modules are relatively large because they contain a ferrite core. The size of current sensor modules adds to the space needed and thus reduces the power density of the PFC. Additionally, current sensor modules that have sufficient bandwidth and accuracy for this Totem pole design are relatively costly.

Now consider a Totem pole design employing a high-accuracy, 4.8-kV isolated AMR current sensor IC (MCA1101-50-5) from ACEINNA to sample the inductor

current. This ±50-A sensor IC has a typical accuracy of 0.6%, 1.5 MHz bandwidth, and output response time of 300 nsec. It provides reinforced isolation and meets UL60950 with no additional isolated power supply. It includes an Over Current Detection (OCD) threshold that can be set on the IC and a fault-flag pinout designed to interface with an MCU to trigger an interrupt in the event of an over current.

The MCA1101 provides many advantages for a Totem Pole PFC application. These include high accuracy over temperature, high bandwidth, fast response, use of a single power supply, reinforced isolation, a programmable OCD voltage and a fault pin to provide current information to an MCU.

REFERENCES

ACEINNA Inc., www.aceinna.com

It’s not a web page, it’s an industry information site So much happens between issues of R&D World that even another issue would not be enough to keep up. That’s why it makes sense to visit rdworldonline.com and stay on Twitter, Facebook and Linkedin.

It’s updated regularly with relevant technical information and other significant news for the design engineering community.

rdworldonline.com

ACEINNA’S ±65-A MCX1101 IS THE INDUSTRY’S MOST ACCURATE AND HIGHEST BANDWIDTH CURRENT SENSOR. DESIGNED FOR WIDE BANDGAP APPLICATIONS AND AVAILABLE IN 3.3 AND 5-V VERSIONS, THIS HIGHLY ACCURATE, AMR-BASED CURRENT SENSOR IS A CANDIDATE FOR A WIDE RANGE OF NEXT-GENERATION POWER SYSTEMS AND APPLICATIONS.

A57_DesWrld9x10_875.qxp_Layout 1 1/7/22 1:29 PM Page 1

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S I M U L AT I O N

Using simulation to optimize GaN-powered designs COMPARISONS OF TRANSISTOR DEVICE MODELS AND SIMULATION TECHNIQUES ILLUSTRATE WHICH APPROACH WORKS BEST FOR SPECIFIC DESIGN SCENARIOS. LEI KOU, LUCAS LU, GaN SYSTEMS

W

hen designing a new system based on gallium nitride

(GaN) power transistors, simulation provides engineers with a powerful design optimization tool. Through simulation, designers can estimate system efficiency, choose the appropriate device or topology, find suitable thermal strategies, and optimize the magnetics design. Once the design is complete, simulation also aids in system debugging.

There are three types of GaN transistor modeling in wide use: SPICE (Simulation Program with Integrated Circuit Emphasis), Analytical Loss Modeling, and PLECS (Piecewise Linear Electronic Circuit Simulation). Similarly, there are three widely used systemlevel simulation techniques: PLECS, Python, and Mathcad.

Comparisons of transistor device models and examples of simulations offer a detailed focus on the different approaches.

When designing a GaNpowered product or system, good simulation tools are essential for fast time-to-market. For instance,

DEVICE-LEVEL SIMULATION (LTSpice and PSpice)

a loss breakdown analysis helps the designer verify the system efficiency and make modifications before building hardware. It also enables the selection of the most suitable transistor device characteristics and the best topology. For example, results showing the conduction loss of the system dominates will guide the designers toward using a lower RDS(on) transistor.

By determining the system loss results through simulation, the user can settle on thermal design that realizes the system design targets. Simulation can also help optimize the magnetics and the

CONVERTER/SYSTEM-LEVEL SIMULATION (PLECS)

COMPARED TO SPICE, PLECS MODELING SIMPLIFIES SYSTEM LOSS ANALYSIS. IN THIS EXAMPLE, THE PLECS MODEL PROVIDES A BETTER METHOD TO EVALUATE A GAN-BASED SYSTEM LOSS AND THERMAL PERFORMANCE.

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2 • 2022

choice of the switching frequency.

Similarly, simulation reveals the systemís maximum efficiency point, how high the current can go under certain conditions, as well as the maximum operating rating.

GaN TRANSISTOR DEVICE MODELING

Different GaN device models can be used depending on the design topology and critical design parameters. The commonly used SPICE model allows designers to evaluate and observe GaN switching parameters: rise time (Tr), fall time (Tf), dv/dt, EON/EOFF; gate driving performance: gate waveform and the influence of RG on switching, and thermal performance under different conditions like transient and steady state.

The architecture of the GaN transistor spice model resembles that of a silicon transistor. The GaN Systems SPICE Model, for instance, shows good correlation with actual measurements in static, EON/EOFF , and dynamic testing using the double-pulse test (DPT) technique. Variations of the basic SPICE model, including Cauer four-layer Thermal Modeling, allow the evaluation of GaN performance under different thermal considerations.

Designers use an Analytical Loss model to understand device

DESIGN WORLD — EE NETWORK

31

POWER ELECTRONICS HANDBOOK PYTHON losses under certain conditions without performing a switching period simulation.

Because GaN devices do not have reverse recovery losses, the switching, conduction and dead time loss calculations are more straightforward using this model. Analytical Loss models were developed based on experimental data. Implementing a scaling algorithm provides the simulated GaN switching losses (EON/EOFF) under various conditions, including the desired drain to source voltage (VDS), junction temperature (TJ), and gate resistance (RG).

PLECS uses a modeling methodology similar to that of the Analytical Loss model while also providing a user-friendly visual interface that makes it easy to determines switching, conduction, dead time, and thermal modeling. By inserting the PLECS model into the simulation circuit, designers verify the GaN transistor characteristics by analyzing the resulting waveforms.

It is interesting to compare the SPICE and PLECS models. Device-level simulation of SPICE models allows the user to check the GaN device characteristicsñsuch as rise time and fall timeñduring switching transients. This simulation allows users to see parasitic effects on the switching performance. In contrast, PLECS converter/ system-level simulation simplifies the switching transient. And for complicated device-based system-level simulation, the PLECS model also simplifies the analysis.

MATHCAD

PLECS

A COMPARISON OF PYTHON, MATHCAD, AND PLECS FOR SYSTEM LOSS ANALYSIS. AN INSULATED METAL SUBSTRATE (IMS) BOARD WAS USED WITH FORCED AIR COOLING. A GS66516B GAN DEVICE IS THE TRANSISTOR CANDIDATE WITH R?JA OF 5.4 °C/W PER GAN DEVICE.

GaN Systems provides PLECS models for all devices and an online simulation tool for eight system topologies such as common power factor correction (PFC) and inverter/converter designs. For each system topology, designers can choose different transistors and change system parameters that include voltage, current, switching frequency, and more. This online tool provides results such as device loss, converter operating waveforms, and thermal analysis.

An excellent system loss model provides accurate modeling for each switching cycle, including the real-time waveform, conduction loss, dead time analysis, and switching loss analysis.

Also essential are accurate thermal modeling and thermal-loss iterations and magnetic and other applicable passive loss analysis ñ as applied to electromagnetic interference (EMI) filters, transformers, bus capacitors, and more. Moreover,

the model should correlate well with experiments for key parameters, such as Tj, efficiency, and others. Moreover, models should run under various conditions to confirm the GaN transistors are being well utilized and that the design is being optimized.

Python, Mathcad, and PLECS all have builtin temperature iteration capability. Depending on designer preferences, each tool offers different features and options. Python and Mathcad simulations have been verified with hardware designs such as, for example, the Python 48-12-V buck converter and Mathcad 3-kW full-bridge LLC. All three simulation tools have high accuracy. Python is an open-source, free tool and both Mathcad and PLECS require licenses. PLECS models on the GaN Systems website are free.

In terms of the user interface, PLECS is

GS6651GB IMS BOARD

SYSTEM PARAMETERS

Input Voltage

110/230 Vrms

Output Voltage

400 V

Switching Frequency

65 kHz

Load Current

7.5 A

Inductor

360 uH

Dead Time

100 ns

R ΘJA GaN

5.4 °C/W

TA

25 °C

Heatsink with forced air cooling

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2 • 2022

KEY SYSTEM AND TEST PARAMETERS IN THE 3-KW TOTEM-POLE PFC ANALYSIS.

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S I M U L AT I O N

EFFICIENCY COMPARISON BETWEEN TEST RESULTS AND LOSS MODEL

MEASURED TEMPERATURE OF GaN AND HEATSINK

RTH(J-A) per GaN

GaN Junction Temperature

Conduction Loss from GaN

Switching Loss

Conduction Loss from Si

Inductor Loss*

5.4 °C/W

57 °C

5.89W

6.68W

6.45W

10.99W

LOSS MODEL DETAILS AND ACTUAL TEST RESULTS.

LOSS CALCULATION RESULTS FROM LOSS MODEL @ 3kW

the most straightforward and the easiest to use of the three tools because many waveforms can be observed from the summation. The strength of Mathcad is the visualization of mathematical equations. If details are desired, such as loss calculations, Mathcad is preferred.

In contrast, users must write the necessary code for Python to see the waveforms and equations. But Python is the most flexible of the three because it allows users to program any missing considerations into the model.

The totem pole PFC is a fundamental topology widely used in many applications where high efficiency is a goal. As a result, GaN, with its excellent switching performance, works well for this topology. Consider an example of a PLECS system simulation of a 3-kW totempole PFC reference design. Here, the example employs an insulated metal substrate (IMS) board with forced air cooling. A GS66516B GaN device is the candidate GaN transistor with RΘJA of 5.4 °C/W. PLECS provides the simulated loss model and simulated efficiency to compare modeled operation at different power levels with experimental results.

the efficiency curve at different power levels for both simulation and test results have the same trend and compare favorably.

To meet performance goals and speed time-tomarket, design engineers need the most effective device modeling and system simulation tools available. For these purposes, GaN Systems provides analytical and numerical PLECS and SPICE models as well as different levels of simulation tools including Python and Mathcad.

Experiments by GaN Systems provide excellent, and verified, correlation between these simulation tools and test results.

REFERENCES

GaN Systems, http://gansystems.com/

Steps to set up the PLECS architecture include: • Building circuit and import device models for GaN and silicon switches • Defining the system parameters • Designing closed-loop control for PFC and loss analysis code for both GaN and silicon devices • Observe simulation results With the set-up complete, modelers can obtain information such as current and voltage waveforms, as well as junction temperatures during both transient and steady-state and system losses. If one examines the results of the example simulation, one sees that eeworldonline.com

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33

POWER ELECTRONICS HANDBOOK

Pouch-type EDLCs for thin-and-light circuit designs

SHINJI HIGUMA, TDK CORP.

SUPERCAPACITORS NOW COME IN A SMALL, THIN FORMAT THAT MAKES THEM CANDIDATES FOR USES CHARACTERIZED

BY CRAMPED QUARTERS.

In

the next several years, the internet of things (IoT) will include tens of billions of connected devices. Consumer, industrial, medical, and automotive applications will

feature connected devices, but not all connected devices will be phones, machinery, healthcare equipment or vehicles. A large percentage of what is connected to the IoT will be small, remote endpoints with relatively simple features. Many will have narrowly defined uses such as monitoring the temperature of food in a catering operation.

Despite the many different types of smart endpoints, their basic architecture is broadly similar. It includes a processing capability, a form of communication (typically wireless), and a source of power with associated power management.

Some IoT endpoints may not have access to reliable offline power.

And adding offline rectification and regulation could be too expensive for many smart endpoints. A primary or secondary (rechargeable) cell might be an option. The CR2032 coin cell battery is a favorite and can deliver many years of service in a lot of applications.

Battery lifetime depends on the endpoint operating conditions. If the endpoint provides critical data, the manufacturer

Structures and shape

Capacitance

Main applications

Chip type

Ultra-low capacitance, 0.1F and less

Clock and memory backup in various electronic devices

Coin type, molded type Pouch type, laminated type Cylindrical type, rectangular type

Low capacitance, 0.1 to 1F Medium capacitance, 1 to 100F

Modules (large number of interconnected cylindrical High capacitance, or rectangular cells) 100F and above

Standby power for home appliances and A/V equipment Battery load leveling in mobile devices, high-brightness LED flash assist current, momentary power loss protection for SSDs, energy harvesting Road marking studs, LED signs, drive power for compact motors in toys Energy regeneration in industrial equipment and automobiles, UPS (Uninterruptable Power Supply) equipment, emergency power supply for wind power generation control

EDLC TYPES, CATEGORIZED BY SHAPE, STRUCTURE AND CAPACITY. FOR SMART ENDPOINTS AND SIMILAR APPLICATIONS, THE POUCH OR LAMINATED TYPE BALANCES CAPACITANCE, SIZE, DESIGN FLEXIBILITY AND AVAILABILITY.

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DESIGN WORLD — EE NETWORK

2 • 2022

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S U P E R C A PA C I T O R S

POWER SUPPLY STABILIZATION TO REDUCE NOISE

ADDITION OF HIGH OUTPUT FUNCTION

POUCH-TYPE EDLCS CAN PROVIDE INSTANTANEOUS ENERGY AND VOLTAGE STABILITY DURING PEAK DEMANDS.

might add a supplementary power source that steps in if the main source is depleted.

Energy harvesting involves converting ambient energy from heat, vibration, solar and other sources into electricity. There are many microcontrollers (MCUs) and processing modules having power requirements low enough to operate just from harvested energy. But while itís feasible to operate a smart endpoint from harvested energy, the means of storing the energy most efficiently remains an issue.

Electrolytic capacitors can store energy short-term with a relatively high power density. In applications requiring a short energy burst, such as driving an electromechanical actuator, a large capacitor is a good option.

However, conventional capacitors are large and subject to aging. As a longer-term form of backup power, they are not an ideal technology.

are manufactured in various forms, including chip, coin cell and pouch. Cell type devices are also packaged in modules or stacked.

The pouch-type EDLC is supplied in a soft, flexible foil-based pouch that can easily conform to irregular shapes. This makes the pouchtype EDLC suitable for thin and light circuit designs.

Like capacitors EDLCs store energy as charges (the charge carriers are ions in EDLCs) that adhere to an activated carbon electrode. Electrically, EDLCs behave like conventional secondary battery cells. But EDLCs can recharge in seconds rather than the minutes needed to recharge secondary cells which are based on chemical reactions.

Thus EDLCs have a higher power density than that of batteries.

Power density refers to the amount of time needed to charge and discharge energy. EDLCs have faster charge and discharge rates than batteries because the chemical reactions within batteries take longer to release DATA BACK UP FOR SOLID STATE DRIVE (SSD)

POWER STORAGE DEVICE FOR PHOTOVOLTAIC POWER GENERATION

INSIDE EDLC TECHNOLOGY An alternative growing in popularity is the Electric Double Layer Capacitor (EDLC). EDLCs

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AN EDLC CAN ENSURE A CONTROLLED SHUTDOWN IN THE EVENT OF SUDDEN TOTAL POWER LOSS. BELOW, POUCH TYPE EDLCS PROVIDE AN EFFICIENT WAY OF STORING HARVESTED ENERGY.

electrons than the electrical discharge in EDLCs. EDLC electrodes typically have a make-up that includes 70 to 95 wt% carbon-based material, binder, and other conductive additives (often carbon black) to enhance electrochemical properties. The structure of the activated carbon capacitance largely defines an EDLC, including its specific surface area, volume and pore diameter. The electric double layer capacitance is roughly proportional to the accessible surface area of the electrolyte ions, hence the use of activated carbons as electrode materials. The high capacitance of the activated carbon arises from the high specific surface area (>1,000 m2/g) provided by the presence of many micropores. But this structure also gives EDLCs a significant internal resistance.

For applications that require a large current, itís best to select an EDLC with the lowest possible internal resistance.

Manufacturers such as TDK can construct EDLCs with capacitances exceeding that possible with other types including aluminum electrolytic, film, ceramic and tantalum.

However, most other capacitors feature a higher operating voltage. Consequently, EDLCs are candidates for power sources if the supply voltage is relatively low, as with smart endpoints which routinely operate at voltages of 3.3 V or less.

EDLCs can store energy for long periods, but they exhibit a leakage current. There are three main contributors to leakage current: charge redistribution, faradaic reactions, and ohmic leakage. Charge redistribution arises from the movement or loss of charged ions adsorbed on the electrode. Faradaic reactions are

2 • 2022

oxidation or reduction reactions on the electrode surface caused by overcharging or the presence of impurities. Ohmic leakage comes from internal ohmic leakage pathways between the positive and negative electrodes.

The structure of an EDLC, in conjunction with its operating environment, will determine the magnitude of the leakage current.

Engineers should factor leakage current-even when the EDLC is fully charged-in to power calculations. Energy harvesting applications may be able to compensate for leakage current losses if the average energy available exceeds the level of leakage current.

With its small size and capacitance of up to 1 farad (F), pouch-type EDLCs are suitable for three main applications: power assist, power backup and micro energy storage.

In a power assist scenario, the pouch type EDLC can provide power under heavy or peak loads. The pouch type EDLC can also provide emergency power to, for example, ensure a controlled shut-down when a battery is being removed or is temporarily dislodged. Similarly, a pouchtype EDLC can let a solid-state drive store critical data before its power fails.

In smart endpoints that use harvested power, EDLCs can be a handy way of compensating for the inconsistent and intermittent nature of harvested energy.

Its construction gives EDLCs a greater energy density than any other type of capacitor, in the range of 3~5 Wh/kg (though this is two orders of magnitude lower than that of the commercial lithium-ion batteries).

The technology also performs well in applications

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35

POWER ELECTRONICS HANDBOOK

COMPARISON CHART FOR POWER & ENERGY DENSITIES

EDLCS PROVIDE BETTER ENERGY DENSITY THAN OTHER TYPES OF CAPACITORS.

PROVEN SHOCK, VIBRATION & NOISE REDUCING SOLUTIONS

MATE

RIAL

where physical space is limited. Basically, EDLCs donít heat up much in normal use.

Thereís no need for cooling technologies such as forced air or a heatsink. An EDLC can continue to operate when operating temperatures fall below 0 °C. However, continuous charging and discharging can cause a slight temperature rise.

EDLCs need no special charging circuitry; charging takes place by applying a voltage equal to the EDLC rated voltage.

Unlike a conventional battery, EDLCs do not exhibit any degradation because of deep discharging. They are also durable enough to survive a short-circuit on the output, which also helps simplify the power management circuitry. But as with any energy storage technology, they should not be over-charged.

EDLCs can be paralleled or connected serially to increase capacity or voltage.

Treat each EDLC as a separate device and incorporate load balancing in the design so all EDLCs see the same charging voltage. This measure helps ensure each device delivers a typical 1,000 hours of operation at the maximum rated temperature and voltage.

At the end of the day, pouch EDLCs offer a small outline and good energy density in a flexible, light format. This option gives engineering teams greater design freedom without introducing design complexity.

REFERENCES

TDK Corp., http://product.tdk.com/en/ products/capacitor/edlc/edlc/index.html

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TRACKER TYPICAL IOT APPLICATIONS.

T

he spectacular growth of the Internet of Things (IoT) is driving the need for devices that are smarter, faster, and can last for long periods on small and inexpensive batteries. To meet such requirements, Renesas has developed a new, ultra-efficient microcontroller (MCU) power management architecture. This architecture is based on Silicon on Thin Buried oxide (SOTB)

process technology with the widely used Cortex M series CPU cores at its heart.

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POWER ELECTRONICS HANDBOOK

ESTIMATING POWER CONSUMPTION

HOW POWER CONSUMPTION TYPICALLY BREAKS DOWN IN A CONVENTIONAL IOT APPLICATION CHARACTERIZED BY SENSING, DATA COLLECTION, AND TRANSMITTING DATA.

The Silicon on Thin Buried Oxide (SOTB) process is proprietary transistor technology from Renesas based on SOI (Silicon on Insulator) wafers. The benefit of SOTB is it can greatly reduce both active and standby current, which are normally traded off against each other. SOTB has the lowleakage benefits of larger geometries, with the high-performance and low active current benefits of smaller silicon geometries.

In SOTB chips, a thin insulating oxide film (BOX, buried oxide) is deposited on top of the base silicon substrate. Next, a thin silicon layer with no impurities is deposited on top of the BOX insulator layer to form a dopantless channel transistor under the

gate, a structure that reduces threshold voltage variance, and thus enables a low operating voltage.

The net effect of the BOX insulating layer and the dopantless channel is high performance, low-voltage operation with both low leakage current and low operational current. To further optimize performance while reducing leakage during standby, a bias voltage may be applied to the base silicon substrate beneath the BOX insulator layer. (As an aside, SOC designers can mix the use of SOTB and standard CMOS bulk transistors as needed to optimize performance, efficiency, and adapt to existing IP designs. Examples of bulk transistor use can be found in I/O ports, charge pumps, and specific analog functions.)

A TYPICAL RE MCU SYSTEM CONFIGURATION WITH EXTERNAL DC/DC CONVERTERS SUCH AS THE HIGHLY EFFICIENT ISL91XX SERIES.

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The typical way of computing the power consumption of a system is to first decompose the operation of the system for each task and model the operation time and electrical current each task requires.

Additionally, the power assessment process requires defining the cycle time of each task, that is the standby time paired with the operation time.

For IoT devices, three tasks typically define most operations: sensing, data processing, and communication processing. The power consumption of the entire system can be thought of as the sum of the power consumption of these tasks.

ELECTRIC CURRENT PROFILE OF TASK A ELECTRIC CURRENT USE IN A TYPICAL IOT APPLICATION.

It’s evident that the ratio of the active and standby mode times is an important parameter. Important, too, is the magnitude of the electric current in the active and standby modes: The total power consumption of a task is expressed by the area of its current profile. Dividing the total profile area by time yields the average current. A design that reduces the area of the electric current profile is also a design that minimizes power consumption.

The SOTB process technology greatly reduces both active and static power consumption. The digital functions of the device--such as the SRAM, CPU, and peripheral functions--are supplied with a regulated internal voltage and are implemented by transistors based on SOTB technology.

The RE MCU family, based on SOTB process technology, draws low current in both active and standby modes. RE devices having 256 KB flash draw 25 µA/ MHz when in active mode (12 µA/MHz with an external dc/dc converter) and a eeworldonline.com

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POWER MANAGEMENT COMPARING CURRENT CONSUMPTION

HOW CURRENT CONSUMPTION OF RE MCUS, FABBED USING THE SOTB PROCESS, COMPARES WITH THAT OF CHIPS FABRICATED USING CONVENTIONAL IC PROCESS DIMENSIONS. THE RENESAS RE MCU FAMILY IS ALSO CERTIFIED BY EEMBC (EMBEDDED MICROPROCESSOR BENCHMARK CONSORTIUM) TO HAVE A SCORE OF 705 FOR THE ULPMARK-CP ULPMARK BENCHMARK, WHICH QUANTIFIES MANY ASPECTS OF ULTRA-LOW POWER MCUS.

standby current of 0.4 µA (with SRAM retention), 380 nA with a real-time clock only. The RE family can also operate at high speed at a low voltage. Use of multiple power modes lets the MCUs optimize their power consumption for any specific operating condition, making it possible to suppress dynamic current while operating at up to 64 MHz and to reduce leakage current during 32.768- kHz operation and in the standby modes. Developers can design the operating mode transition to suit the application. The key factor should be the duration of the CPU in active mode and active time compared to the standby time.

In addition to using power from the builtin power management unit, the RE family has a mechanism to supply power directly to the MCU. This mechanism makes it possible to efficiently convert the main power supply to the required voltage for powering the MCU. The result is better power efficiency for the entire system.

Typical applications combine several devices such as sensors, MCUs and communication modules, each requiring an appropriate power supply voltage.

The conversion efficiency involved in generating each voltage factors into the power consumption for the total system.

In the interest of IoT battery life, the RE family supports energy harvesting power supplies. This power supply system temporarily stores harvested energy in a capacitor to maintain the MCU operation. Moreover, use of a supercapacitor or a secondary battery in addition to the capacitor can help maintain the system when the supply current from the capacitor alone is eeworldonline.com

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insufficient. With a starting current of only 5 µA, the MCU system can operate from an energy harvesting supply having a small current capacity.

REFERENCES

Renesas RE Cortex-M Ultra-low Power SOTB MCUs, https://www.renesas.com/products/microcontrollersmicroprocessors/re-cortex-m-ultra-low-power-sotb-mcus

A BLOCK DIAGRAM OF A TYPICAL ENERGY HARVESTING CONTROLLER SETUP EMPLOYING AN EXTERNAL CAPACITOR WHICH POWERS THE MCU DURING ITS STARTUP PHASE.

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Optimizing power delivery networks JEFF HAM, VICOR CORP.

W

ith industry emphasis on minimizing and eliminating waste wherever possible, it

is the responsibility of the system designer to optimize the overall power architecture. Every piece of electronic equipment has a power delivery network (PDN) typically comprised of, but not limited to, cables, bus bars, connectors, circuit board copper power planes, ac-dc and dc-dc converters and regulators.

A FEW RULES OF THUMB HELP NAVIGATE THE NUANCES AND COMMON PITFALLS OF POWER SYSTEM DESIGN USING POWER MODULES.

load. High power dissipation requires more complex and extensive cooling methods which all add cost and size, especially for applications in harsh environments.

Dissipated power is the difference between input power and output power. One determines the power converter’s dissipated power by dividing the power rating of the converter by its decimal equivalent efficiency: A 100-W-rated converter with an efficiency of 80% will have in input power of 125 W and a dissipated power of 25 W. It is critical to consider each element in the system this way to determine total system losses.

Boosting efficiency by even a small amount can significantly reduce losses. For example,

a 10-point rise in efficiency--to 90% in this example--may not seem like much, but it reduces the power dissipated by more than half: 11.1 W down from 25 W. What does this efficiency increase do for the power delivery network? Apart from reducing the thermal impact of a converter, it also reduces the demand on the input source which needs to deliver less power.

This lower power use also means that for a given input voltage, the source current is also lower. From Ohm’s law, power can be viewed as the product of voltage and current and as the product of resistance and the square of the current (P = VI = I2R). In analysis of power delivery networks it is the resistance term that

Everything within this network influences how well the design functions as it sees line, load and environmental variations.

Historically, power architectures have been defined in the late stages of product development, when space and options are already limited. A more proactive approach that places architecture design early in the process lends itself to producing more robust systems able to accommodate changing design specifications during development.

Power designers often focus on the conversion stages to maximize conversion efficiency and minimize power loss. The primary driver has been thermal management because the conversion stages are typically among the largest contributors to the thermal

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A 12-V LOW-VOLTAGE PDN SUPPLYING FIVE INDEPENDENT LOADS. IN THIS EXAMPLE THE LOADS ARE LOW VOLTAGE (< 5 VDC) AND HAVE HIGHER CURRENT FLOWING BETWEEN THEM AND THE CONVERTERS (SHOWN BY THE THICK TRACE).

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POWER DELIVERY

AN IMPROVED PDN WITH THE SOURCE VOLTAGE RAISED FROM 12 TO 48 VDC. THE FIVE INDEPENDENT LOADS HAVE THE SAME CURRENT REQUIREMENTS AS THOSE SHOWN IN THE FIRST EXAMPLE. AS A RESULT OF THE HIGHER SOURCE VOLTAGE, THE CURRENT FLOWING FROM THE BATTERY TO THE CONVERSION STAGE IS LOWER (INDICATED BY THE THIN TRACE).

is frequently overlooked. All paths from the source to the load have a fixed resistance. All of them bear on the power loss in the aggregate system. There are also safety and stability components that contribute to overall power loss that must be accounted for: fuses, circuit breakers and filters for electromagnetic interference reduction and voltage smoothing.

In each of these elements, there is a voltage drop penalty that can degrade the stability of switching regulators and create other issues within the system.

End-use equipment (that the power delivery network supplies) that has large power swings like a CPU, pulsed load, or motor will cause significant voltage variation at the converter input and output.

As a general rule of thumb, the source impedance the converter sees should be a factor of ten less than the lowest impedance the converter presents.

Going back to the 90% efficient 100-W converter example, let’s say the operational input range for this device is 18 – 36 V. At an input of 18 V the converter draws about 6.2 A. The converter input impedance (R) is therefore V/I or 18/6.2 = 2.9 Ω. At 36 V the input

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current is half, so the impedance is 11.7 Ω. At the converter’s lowest input impedance, the rule of thumb dictates that the source impedance to assure stable operation should be no more than 0.29 Ω.

A point to note is that system stability is important when designing a power system. This simplistic resistance discussion does not account for the reactive elements, e.g., capacitance and inductance, both real and apparent in place which can cause resonances and other problems if

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not well understood. These topics are beyond the scope of this article.

What can be done to optimize the PDN as it relates to system power loss?

Whether it is analyzing an existing design or creating a new architecture from scratch, the approach is the same.

First: Though it may sound obvious, use the most efficient available converters. Consider the PDN in two parts: the outputs from the actual application load(s) to the first conversion stage including any

intermediate conversion stages, and the input from the source to the first conversion stage.

The application load will have a predetermined minimum voltage requirement. The current demands for modern electronic systems can be high, in some cases exceeding 1,000 A at sub1-V levels. To minimize losses in these applications, point-of-load (PoL) converters are placed near the load consuming the power.

PoL avoids long wiring distances between the converter and load characterizing conventional power supplies and provides a precise voltage supply that meets low-voltage/ high-current needs. The PoL stage should be located as close as physically possible to the load it powers to minimize the interconnect resistance.

Moving toward the input, the PoL input voltage should be as high as practical. Consider a 12-V low-voltage PDN supplying five independent loads. In this example the loads are low voltage (< 5 Vdc) and have higher current flowing between them and the converters.

Such a setup could be a legacy computer supply, vehicle

COMPARISON OF CURRENT, VOLTAGE DROP AND POWER LOSS REDUCTION FOR DIFFERENT SOURCE VOLTAGES IN EACH TETHER CONDUCTOR FOR THE AIRBORNE VEHICLE REQUIRING 500 W. THIS CLEARLY ILLUSTRATES THE ADVANTAGE HIGHER VOLTAGES YIELD.

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POWER ELECTRONICS HANDBOOK

power system or drone payload. There is a fixed trace resistance to the input to the PoLs that will have a given power dissipation for any given operating power level. If we can increase the voltage by a factor of four (i.e., to 48 V) at the same power, the current flowing in this leg is now one-quarter of the previous level. Thanks to the squared current term in the power equation, the new power dissipation is significantly less, and there is a reduction in voltage deviation too.

Additionally, 48 V is a good distribution voltage because it is also within Safety Extra Low Voltage (SELV) limits, defined by the IEC as having a low risk of electrical shock. For an existing application, raising the voltage will require different PoLs. Here, a modular approach using a device having the same package size will be an easy conversion because the converters will be drop-in replacements.

EXAMPLE: TETHERED-UAV POWER DELIVERY NETWORK

Consider the more extreme example of a tethered UAV or drone and specifically, the effects of the source-to-first conversion stage.

The tether represents the interface between the ground supply.

Assume the UAV tether is 100 ft long and contains 24-AWG conductors, each of them having approximately 2.5 Ω of resistance per 100 ft.At a 48-V distribution, the current in this tether is about 10 A; the resistance is 5 Ω for the 100-foot round trip, so the power lost in the tether is 500 W! Clearly this UAV can’t fly because the tether dissipates all the power, leaving nothing for the vehicle.

Now consider use of a higher input voltage. Assume a 400-V system with the same conditions as above.

At a 400-V distribution, tether current drops to about 1.25 A and the tether only dissipates about 8 W. Doubling the input to 800 V drops the tether current to about 0.6 A, reducing power dissipation in the tether to about 2 W. The lower current draw potentially makes possible the use of smaller-gauge tether conductors, potentially reducing drag and windage and possibly the power needs of the UAV as well.

Power dissipation is one thing, but regulation at the end of the tether is also important. The regulators onboard the UAV will have a defined input voltage range. There

is a voltage drop across the tether resistance.

Given the 24-AWG 100-foot tether and its 5-Ω round trip resistance, there is a 5-V drop for every amp of current. Reducing the voltage dropped across the tether also reduces the ratio of the voltage drop over applied voltage, further improving regulation: If the voltage doubles and the current is halved, the the drop across the tether halves and the ratio of tether drop to load voltage is quartered.

It should be apparent moving to an 800-V source for the ground supply is the way to optimize power transmission up the tether. But the UAV must convert that 800 V down to low voltages to power its motors and electronics. For this part of the PDN, 48 V for the onboard electronics makes the most sense for reasons described earlier.

All in all, the path to optimize a PDN can be summarized into six steps: •

• •

•

•

•

Think power first. Once you have the initial power requirements, carve out space for a modular power design.

A modular approach is flexible and scales easily.

Pay attention to each element in the current path.

Use the highest voltages allowable to reduce the amount of current needed.

Use the most efficient conversion elements possible to reduce conversion losses.

Use the highest power density devices to allow for close placement to loads.

Minimize interconnect resistance as much as practical to reduce both voltage drop and power loss.

REFERENCES

Vicor Corp., www.vicorpower.com

OPTIMIZED TETHERED DRONE PDN FROM THE GROUND SUPPLY TO THE AIRBORNE VEHICLE. THE 800 V USED WITHIN THE TETHER MINIMIZES THE CRITICAL TRANSMISSION LOSSES AND VOLTAGE VARIATIONS DUE TO THE OPERATION OF THE UAV. BECAUSE THE CURRENT IS SIGNIFICANTLY LOWER THAN WITH LOWER SUPPLY VOLTAGES, THE MOVE TO 800 V HAS THE ADDED BENEFIT OF POTENTIALLY REDUCING THE TETHER WINDAGE AND WEIGHT BY ALLOWING FOR THE USE OF SMALLER-GAUGE CONDUCTORS.

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Less interference.

Smaller EMI designs.

Simpler designs.

As electronic systems become increasingly dense and interconnected, reducing the effects of electromagnetic interference (EMI) becomes an increasingly critical system design consideration. Designing for low EMI can save you significant development cycle times while also reducing board area and solution cost. With TI, you can leverage multiple features and technologies to mitigate EMI in all of the frequency bands of interest.

Your partner in solving EMI challenges.

Learn more > TI.com/lowemi

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POWER ELECTRONICS HANDBOOK

Power system delivery for 5G networks SPECIAL FEATURES SUCH AS FOLD-BACK PROTECTION AND GOOD DYNAMIC RESPONSE COME IN HANDY FOR THE DC-DC CONVERSION STAGES POWERING 5G RANs. ANDY BROWN, ADVANCED ENERGY INDUSTRIES, INC.

W

ith its high speeds, low latency, reliability and potential for rapid scalability, 5G is set to

change the way we use and share data and to move concepts such as the connected vehicle and the smart city from the drawing board to reality. Based on a proliferation of small cells, 5G radio access networks (RANs) have demanding power requirements in terms

lamps, for example, may need to operate from ac mains, while those on top of or inside buildings could use ac or -48-V PoE (Power over Ethernet). Many converters will need to operate with a conventional 12-V power supply, while newer applications could use HVAC or HVDC power. Irrespective of the input power source, reliability, thermal management, efficiency, EMI, noise and protection-attributes will all be among the key criteria in selecting power conversion solutions for 5G RAN infrastructures.

Critical to the success of 5G networks is the ability of the communication cell to operate

with maximum uptime. 5G base stations and their active antennae must always operate reliably and, in the case of applications such as connected vehicles and smart cities, ensure safety. In many cases redundancy or even self-diagnosis and self-repair is necessary. And if an engineer does need to be called out, it is essential that fixes take place without any break in service.

This need for reliability means that the power supplies for the base station must have Mean Time Between Failures (MTBF) calculated in the millions rather than a few hundred

of reliability, efficiency, EMI and the ability to operate in often harsh conditions.

According to the research firm ResearchAndMarkets, the market for 5G infrastructure will see a compound annual growth rate (CAGR) of 55% from 2021 to reach $115.4 billion by 2026. Much of that growth will come from the proliferation of small cells that will need to be added for the line-of-sight coverage over short distances that the higher spectrum frequencies used by 5G demand.

These cells are being added to light poles, traffic lights, buildings and other tall structures and are being complemented by pico- and femto-cells for enterprise and residential deployments so as to to create dense 5G heterogeneous networks or HetNets.

DC-DC converters are fundamental elements of every small cell and, depending on the specific application, they will work from a variety of potential input power sources.

Communication cells mounted on street

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CROSS SECTION OF POWER SUPPLY BASEPLATE, WHICH IS THERMALLY BONDED TO THE HEATSINK. IN THIS CASE THE BASEPLATE OF AN ADVANCED ENERGY ARTESYN AGF DC-DC CONVERTER IS THERMALLY BONDED TO A HEATSINK. WHEN DEPLOYED IN IP-SEALED CASES, THESE SUPPLIES CAN HANDLE AMBIENT TEMPERATURES EXCEEDING 85ºC INSIDE THE CASE (WHERE THERE IS NO AIRFLOW AVAILABLE) AT FULL LOAD, AND THE FULL POWER RATING OF THE UNIT (UP TO 800 W DEPENDING ON THE MODEL CHOSEN) REMAINS AVAILABLE AS LONG AS BASEPLATE TEMPERATURE REMAINS BELOW 100ºC.

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5G POWER

ADVANCED ENERGY’S ARTESYN ADH700, 700 W DC-DC CONVERTERS, WHICH CAN POWER GAN RF POWER AMPLIFIERS IN A 5G RAN BASE STATION, COMBINE HIGH EFFICIENCY WITH ADJUSTABLE OUTPUT VOLTAGE.

thousand hours, irrespective of the harsh outdoor environment in which they operate. Heat is a key contributor to power supply failures. (The rule of thumb for MTBF is that every10°C rise in component temperature halves the MTBF.) So designers must concentrate on optimizing thermal management.

Deployed close to (or in) the antennas located on cell towers or roof tops, the RF circuitry of the remote radio head (RRH) provides signals via fiber optic cable to a base band unit (BBU) sitting inside a shelter or cabinet at the base of the tower. The RRH is usually powered by a low-voltage power line (typically 48 and 52 Vdc) at the top of the tower next to the antenna. Some newer applications use ac or higher voltage dc to lessen the cable size and hence reduce the weight and cost of the cables the cell tower must support.

Unfortunately, RRHs are notoriously inefficient and typically range between 35 to 45% powerin to power-out - with most of that residing in the transmitter amplifier. This inefficiency contributes to overall expense, and operators are constantly seeking to improve it.

Fortunately, power amplifier (PA) efficiency has improved significantly in recent years.

This is due in large part to more sophisticated linearization techniques and newer design and

TWO-STAGE FILTER FOR HIGHER POWER DC-DC CONVERSION APPLICATIONS.

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for cooling. In this case designers can optimize performance and efficiency by configuring the PA voltage to follow changes in the PA envelope by using the voltage output trim pin on the power supply. component technology that enables higher output power capabilities. In terms of power requirements, where the amplifier is 300 to 400 W, an LDMOS (RF laterally diffused MOS) power amplifier may need that power at 28 Vdc whereas an amplifier built around gallium nitride (GaN), could need approximately 50 Vdc. In addition, there is usually a 12-V rail that may be required to provide 60 to 100 W to power the data processing functions.

The problem is that next-generation “massive MIMO” active antenna unit (AAU) radios need a large number of lower-power amplifiers for each AAU radio. Linearizing each of these small amplifiers is costly and marginally effective because the additional circuitry itself consumes much of the power that it is designed to save.

Use of the latest high-efficiency dc-dc converters for the PA power supply can boost overall system efficiency and reduce operation costs. The Artesyn ADH700 series of half-brick isolated dc-dc converters, for example, offers an ultra-high conversion efficiency exceeding 95% at half load. And of course, the more efficient the power conversion, the lower the dissipated heat and the easier the thermal management.

Many of these newer converters offer a wide range of output voltage adjustment (from 50 to 118% for the ADH700) which improves PA efficiency and reduces the need

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When implementing a PA power supply design it is important to: 1.

2.

3.

Ensure there are safeguards to the protect the overall system.

Ensure that EMI and regulatory requirements are met Match the dynamic load response of the power converter to what the system requires. We’ll discuss each of these points in turn.

Safeguards: An input circuit at the front end of the dc-dc converter must include a fuse and Metal Oxide Varistor (MOV) for surge suppression, as well as a Negative Temperature Coefficient (NTC) inrush limiting power thermistor for powering and protecting the RF architecture. For higher power dc-dc conversion applications a two-stage filter will typically be deployed.

EMI and regulations: A good input filter and layout design will minimize the EMI signature. Fast-switching currents in associated circuitry can generate magnetic fields and fastchanging voltages create electric fields that may result in undesired coupling. Electromagnetic

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POWER ELECTRONICS HANDBOOK FOLD-BACK MODE OVERCURRENT PROTECTION IN A 48-V INPUT/28-V OUTPUT POWER SUPPLY.

coupling can be minimized by the use of solid grounds and shielded cases.

Use of multiple vias for bypass capacitors can reduce resistance and inductance. Also, designers should ensure that ground-voltage potential remains stable and never floats.

Traces that carry high-frequency signals generate a time-varying electromagnetic wave that can propagate and cause interference. Two traces at a 90° angle will cause the least interference between the two signals they carry. A good case ground also helps prevent outside signals from entering the system as well as providing shielding. The ground loop for the RF should also be kept separate from the ground loop of the noisier digital components.

Dynamic load response: Power converter load response demands selection of the appropriate output capacitors that match with the power converter control characteristics to meet the system demands.

Dynamic load changes can quickly discharge output capacitance, causing the output voltage to drop out of its static regulation specification.

Even if the load step draws current that is within the rated current of the power supply, there may be some “droop” in the output voltage. A voltage feedback circuit senses the droop, which in turn causes the supply to boost the output voltage to bring the unit back within static voltage regulation specification. This correction doesn’t happen instantly. Typically a 10% to 90% voltage

recovery time is specified, along with a percentage of maximum rated voltage overshoot allowable.

A further consideration when it comes to protection is a characteristic known as fold-back mode overcurrent protection. With normal (high side) current limiting the current is limited to a fixed value as the load resistance approaches zero and the supply voltage begins to drop. With foldback protection, the current limit also drops fairly linearly as the output voltage drops. This provides more protection because extreme short circuits won’t cause a large current draw.

Fold-back mode protection is especially useful when powering a ‘peaky’ RF power amplifier, which has the potential to affect the power supply. In general, the designer does not want the dc-dc power supply to see a fast peak. The power supply could interpret this peak as a fault, go into a shut-down mode, and switch off the output voltage while it attempts to reset and restart. Fold-back mode prevents this scenario by allowing for some level of voltage output without automatically turning off the output voltage completely.

Furthermore, to manage the fast-spiking load nature of the PA, some applications may have a large output capacitance on the order of tens of thousands of microfarads.

Starting up a power supply in such a load is usually difficult because these capacitors will initially look like a short circuit. Use of a

dc-dc converter with a fold-back characteristic eliminates the problem.

Size is the final consideration when selecting dc-dc converters for 5G RAN applications. While they are not as spacelimited as many consumer applications, converters for 5G cells must still be as small and as light as possible. Manufacturers try to minimize the overall cell size so the demand for low-profile, small-footprint supplies will grow.

REFERENCES

Advanced Energy Industries Inc., advancedenergy.com 5G infrastructure market statistics, https://www.businesswire.com/ news/home/20210910005400/en/ Global-5G-Infrastructure-MarketReport-2021-Market-Is-Expected-toGrow-From-12.9-Billion-in-2021-to-115.4Billion-by-2026---ResearchAndMarkets.com

5G Small Cell Types

Deployment

Number of Concurrent Users

Power Range

Distance Coverage

Femto cell

It is primarily used in residences and enterprises

4 to 8 users (residence) 16 to 32 users (enterprise)

10 to 100 mW (indoor) 0.2 to 1 W (outdoor)

10s of meters

Pico cell

Public areas such as indoors, outdoors, airports, malls, train stations

64 to 128 users

100 to 250 mW (indoor) 1 to 5 W (outdoor)

10s of meters

Micro cell

Urban areas to fill macro coverage gaps

128 to 256 users

5 to 10 W (outdoor)

Few 100s of meters

Metro cell

Urban areas to provide additional capacity

> 250 users

10 to 20 W (outdoor)

100s of meters

Wifi

Residences, offices, enterprises

< 50 users

20 to 100 mW (indoor) 0.2 to 1 W (outdoor)

Few 10s of meters

A SUMMARY OF 5G SMALL CELL TYPES INCLUDING THEIR TYPICAL POWER REQUIREMENTS.

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EE Classroom on Silicon Carbide

Silicon Carbide (SiC) has made its mark in bringing faster, a smaller, and more reliable components than its fellow semiconductors to market. While SiC components have been around for a couple of decades, there is still a lot to learn and a lot to consider when choosing the most suitable WBG semiconductor for your device. LET US HELP with tutorials, from looking at how WBG semis stack up in power conversion efficiency to an overview of SiC FETs and MOSFETs.

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1/6/22 3:09 PM

1887

Emile Berliner receives the patent for the gramophone.

James Blyth builds the first electricity generating wind turbine.

Herman Hollerith receives a U.S. patent for his punch-card calculator.

Sager opens its first location in Boston, Massachusetts.

All great things begin with a single step – or in Sager’s case a single storefront.

Recognized as the first distributor in the industry, Sager opened for business one hundred thirty-five years ago in downtown Boston, Massachusetts, servicing the growing interest in radio technology.

Under the vision and leadership of Joe Sager, the company established a thriving business that put the needs of its customers first. Since then Sager has grown into a North American distributor of interconnect, power, thermal and electromechanical products and a provider of custom design and manufacturing solutions.

And after 135 years, Sager still operates just as Joe envisioned – based on a commitment to exceeding expectations and keeping the customer at the center of its business philosophy.

Sager Electronics, a TTI Inc., Berkshire Hathaway Company

www.sager.com | 1.800.724.8370