YILDIRIM BEYAZIT UNIVERSITY EE 205 – DIGITAL DESIGN LABORATORY MANUAL – 2 – Modular Implementation of Complex Logic Circuits Laboratory Exercise: 1. Find the truth table of the logic diagram shown in Figure1.
Figure 1
Can this logic diagram be achieved with reduced number gates (less components)? If so, draw the reduced diagram. Write Structural modeling codes for the diagram in Figure1. Write Behavioral modeling codes for the diagram in Figure1.
2. Run testbench simulation of the code in part1 for the input values given values below. Show your code and the output F waveform.
A 0 0 1 1 1 1
B 0 1 0 1 0 0
C 0 0 0 1 1 0
D 0 1 0 1 0 0
Time(ns) 0-10 10-40 40-100 100-130 130-135 135-150
3. Generate the “.ucf” file and send it to the BASYS2 FPGA card. Assign inputs A, B, C, D to switches and output F to a led on the card.