Controller scalability methods for digital point of load by ZMDI

Controller Scalability Methods for Digital Point Of Load Converters Marco Meola, Alessandro Cinti, Smart Power Management Dept., ZMDI Munich, GERMANY {marco.meola, alessandro.cinti}@zmdi.com Abstractâ&#x20AC;&#x201D; Unmodeled dynamics cause DC-DC controller design to be an iterative procedure where controller parameters are tuned and re-tuned to achieve the desired transient performance. Once the controller is designed any change of the output filter requires a new compensator design to guarantee stable operation. In this paper programmability of controller parameters in digital Point Of Load (POL) converters is exploited to investigate methods to scale an existing controller to accommodate variation of the resonant frequency of the LC filter, with the aim to eliminate the need for such iterative tuning. A new method to scale a compensator is then proposed to maintain bandwidth and phase margin of the original controller design. Experimental results are provided for 12-to-1.2V, 20A, 500kHz 0.18Âľm CMOS digital POL converter to show the effectiveness of the proposed method. Keywordsâ&#x20AC;&#x201D;scalability, controller scaling, auto-tuning, digital control, Point Of Load, DC-DC converter

INTRODUCTION

In the design of a POL converter, once the elements characterizing the power stage are dimensioned, a controller that meets both stability and closed-loop dynamic requirements has to be designed. While stability criteria are well understood ([1]-[2]), controller design to optimize transient performance in the presence of unmodeled dynamics requires an iterative procedure where controller parameters are tuned, measured and re-tuned in order to achieve the desired performance. Appropriate tuning methods can eliminate the need for such iteration by observing that the characteristics of a particular DC-DC converter change in a known way. This is useful in case the resonant frequency of the LC filter changes, especially when the bulk capacitance value is uncertain. Solutions to allow compensator tuning have been investigated and proposed in both the analog [3] and digital domains [4][13]. Auto-tuning methods seek to address the issue of parameter variation. In general, the compensator auto-tuning process of a digital PWM controller is a two step procedure: firstly, in the system identification phase, characteristics of the plant to

Anthony Kelly Smart Power Management Dept., ZMDI Limerick, IRELAND anthony.kelly@zmdi.com

compensate are extracted by injecting a perturbation signal on the duty cycle and measuring its effect on the output voltage. Secondly, when at least the resonant frequency of the plant is identified, the controller enters a tuning phase in which it is tuned to meet the specified design targets. The need for a system identification phase in the auto-tuning process leads to one or more of the following issues that make auto-tuning problematic: 1) perturbations are injected in the system in steady state, thus causing jitter on the PWM signal and unwanted noise on the output voltage; 2) computational complexity of the system identification process is high; 3) the identification phase requires a long learning phase. Significant effort has been made to reduce the impact of these issues as well as to eliminate the system identification phase ([12][13]). In [12], for example, one of the controller variables, e.g. the gain, is tuned by observing the amplitude and the frequency of the error signal in steady state. In [13], instead, LMS adaptive filters are used to identify the plant to be compensated and a PD controller is tuned to obtain desired location of system closed-loop poles. Although the proposed auto-tuning processes do not require any perturbation of the plant they still suffer from having a tuning process that brings the closed-loop system at the limit of stability ([12]) and of having a very long learning phase. Additionally, in all the proposed tuning methods ([4]-[13]) controller parameters are tuned independently thus lengthening the tuning phase. Depending on the tuning algorithm used, the resulting controller may not be optimal and may not achieve the desired close loop performance. In this paper it is proposed that the controller parameters of a digital POL converter may be tuned by defining relations between compensator parameters and a single common tuning variable, where compensator parameters are tuned as a function of converter resonant frequency. In this way when a reference controller is designed for a specific power stage scenario its closed-loop characteristics can be transformed in a known way to fit different power stages by varying the single common tuning variable. Some work has been done so far on the scalability of controllers applied to DC-DC converters ([14]), but the importance of this area to the application of digital DC-DC converters motivates more attention. Consequently the aim of this paper is to investigate compensator scaling methods to scale a digital controller from an existing design, focusing on

|Gc(j )|dB

Ki/ Kd* Kp

B esr

Fig. 1 Schematic of a Buck converter. Gvd(s) is the control to output transfer function showing how the duty cycle d acts on the regulation of the output voltage Vout.

the case where controller tuning is used to accommodate a change of one of the power stage parameters (i.e. bulk capacitance or output inductor). In this paper three compensator scaling methods based on a single tuning variable are presented and analyzed. In particular, a new controller scaling method is proposed which is shown to maintain both bandwidth and phase margin of the original design as well as closed-loop characteristics. The proposed scaling methods address practical and simple solutions for compensator scaling, leading to simple scaling formulas and therefore resulting in low computational complexity. Moreover, all proposed tuning methods are suitable to be implemented as auto-tuning algorithms, if desired, once the resonant frequency of the LC filter is known. II.

PROBLEM FORMULATION

Without loss of generality, let us consider a buck converter as in Fig. 1, having an LC output filter made up of one inductor L and the parallel of n equal capacitors C. The control to output transfer function is given by: G vd (s) =

( s ωesr + 1) ⎛ s ⎜⎜ ⎝ ωo

⎞ s ⎟⎟ + +1 ⎠ Q ⋅ ωo

Vin

(1)

where ω o = 1 n ⋅ L ⋅ C is the resonance frequency of the plant Gvd(s), ωesr =1/(Rc·C) is the zero caused by the ESR of the output capacitor (Rc) and Q·ωo = L(Rl+Rc/n), Rl being the DCR of the inductor L. Assume the compensator Gc(s) is designed according to some desired criteria for the case n=1 and stabilizes the plant Gvd(s) with bandwidth ωc and phase margin PM. Gc(s) has the structure:

( s ω z1 + 1)(s ω z 2 + 1) (2) s( s ω p + 1) Typically, compensating a converter to meet regulation objectives implies placing the zeros of the compensator Gc(s) in the vicinity of ωo to compensate the phase variation due to the LC output filter while the pole ωp is placed close to ωesr to guarantee sufficient attenuation of the frequencies above the bandwidth ωc. Furthermore consider the scenario where the number of output capacitors n increases. In this situation ωo moves to lower frequencies while the zero in ωesr does not Gc ( s) = K

log( )

Fig. 2 Frequency response of Gc(s). Ki, Kp, Kd must be intended in dB. The zeros ωz1 and ωz2 are the projections of the points A and B on the log(ω) axis.

change its location. Therefore the controller Gc(s), designed for the case n=1, may still stabilize the plant but loop bandwidth and phase margin are adversely affected, reducing the benefit of the additional output capacitors. For example, it will be shown that doubling the output capacitance results in significantly less improvement in the output voltage deviation under load step conditions than it would be expected if this reduction in loop bandwidth and phase margin had not been considered. The purpose of this paper is to investigate methods to scale the compensator Gc(s) in a way that stability and closed-loop dynamics are preserved, thus resulting in optimum transient response as designed, yielding the full benefit of additional capacitors. III.

COMPENSATOR SCALING METHODS

Compensator scaling methods can be better understood when the controller Gc(s) is expressed in its proportional, integral, derivative (PID) form. The controller transfer function in (2) can then be rewritten as:

Ki Kd s (3) + s ( s ω p + 1) where Kp, Ki, Kd are respectively the proportional, integral and derivative coefficients of Gc(s); ωp is the high frequency pole. An equivalent controller to (3) in the digital domain can be derived applying scaling factors to Kp, Ki, Kd once the sampling frequency of the controller is chosen. For ease of explanation controller scaling methods will be analyzed in the analog (S-)domain and the same results can be transferred to the digital (Z-)domain. Fig. 2 shows a bode plot of Gc(s) highlighting its proportional, integral and derivative asymptotes as from (3). The term Ki/ ω (integral asymptote) models the integrator behavior of Gc(s) at low frequencies, while the derivative asymptote Kd· ω is responsible for its behaviour at high frequency. The proportional asymptote Kp, parallel to the log(ω) axis, intersects the integral and derivative asymptotes (points A and B) which gives rise to the controller zeros ωz1 and ωz2, i.e. projections of the points A and B on the log(ω) axis. Typically, the desired control bandwidth ωc, is constrained to lie between ωo and ωesr of Gvd(s) and this assumption holds throughout the paper. Control bandwidths lower than ωo lead to very slow controllers. Bandwidth values higher than ωesr do Gc ( s) = K p +

this condition the following methods to scale controller parameters are proposed.

Fig. 3 Graphical representation of the asymptote shifting principle used in Method 1 to scale the original controller Gc(s) (blue curve) designed to stabilize the plant Gvd(s) (green curve) to accommodate a variation of ωo (light green curve) due to an increase of n times of the bulk capacitance. The scaled compensator is represented by the cyan curve. ω’c=ωc·Δωo is the bandwidth of the scaled controller.

Method 1 Controller Gc(s) can be scaled by means of the controller scaling theorem as in [14]: given Gc(s) that stabilizes the plant Gvd(s) with bandwidth ωc and phase margin PM the controller Gc(s/Δ ωo) stabilizes the plant Gvd(s/Δ ωo) holding the same phase margin and reducing the bandwidth to ωc·Δ ωo. With the increase of output capacitance the new plant Gvd(s/Δ ωo) will results in a frequency scaled version of the original plant Gvd(s) only if the ESR zero ωesr is cancelled out by the controller high frequency pole ωp. Under this assumption a controller Gc(s) with zeros ωz1 and ωz2 placed near ωo so that (5) is satisfied

ω z1 ωz 2 = a1 , = a2 , ωo ωo

(5)

can be scaled using the controller scaling theorem in [14]. The scaled controller Gc(s/Δωo) will have zeros that still satisfy (5) for the new value of ωo but bandwidth ωc·Δ ωo (Fig. 3). This results in the new controller parameters being: Kp_tuned = Kp, Ki_tuned = Ki Δ ωo= K i / n ,

Fig. 4 Graphical representation of the asymptote shifting principle used in Method 2 to scale the original controller Gc(s) (blue curve) designed to stabilize the plant Gvd(s) (green curve) to accommodate a variation of ωo (light green curve) due to an increase of n times of the bulk capacitance. The scaled compensator is represented by the cyan curve.

not improve converter dynamics with respect to load transient since the minimum achievable undershoot is set by the capacitor ESR, together with load step amplitude. The aim of the controller scaling methods is to shift controller asymptotes to accommodate variations of the plant Gvd(s) to preserve controller stability as well as closed-loop dynamics. Once the location of ωp is fixed, by comparing (3) with (2) the following relations can be derived

Kd_tuned = Kd/Δ ωo= K d n where Δω o = 1 / n . Although the phase margin is preserved the bandwidth of the loop obtained with the scaled controller is reduced, thus reducing the benefit of adding additional output capacitance. As such Method 1 fails to meet the requirements as a suitable scaling method. Method 2 Assuming that ωc is far from ωo, which is usually the case in POL applications, relation (5) ensures closed-loop stability because the contribution of the phase lag of the plant at the bandwidth ωc is lower as n increases.

Ki = K K p'= Kd ' =

Kp Ki

ω z1

ωz2

−

(4)

ωp

Kp' Kd 1 = − K i (ω z1 ⋅ ω z 2 ) ω p

Starting the design of Gc(s) for the case n=1 and placing the high frequency pole ωp at frequency ωesr to have a zero-pole cancellation, as n increases the plant Gvd(s) scales in frequency by a factor of Δωo corresponding to the variation of ωo. Under

Fig. 5 Graphical representation of the asymptote shifting principle used in Method 3 to scale the original controller Gc(s) (blue curve) designed to stabilize the plant Gvd(s) (green curve) to accommodate a variation of ωo (light green curve) due to an increase of n times of the bulk capacitance. The scaled compensator is represented by the cyan curve.

Fig. 6 Bode plot of plant Gvd(s) and compensator Gc(s) for n = 1,2,3,4 using Method 3. As n increases ωo moves at lower frequencies and the zeros ωz1 , ωz2 of Gc(s) moves to lower frequencies leading to a boost of the gain of the open loop at frequency greater of ωo . Low frequency gain is scaled to accommodate the change of ωo thus maintaining the original phase margin PM.

Fig. 7 Bode plot of the Open Loop for n=1,2,3,4. The controller Gc(s) scaled as described in Method 3 preserves both phase margin and bandwidth of the original compensator.

This suggests that the open-loop gain may be adjusted to achieve the desired bandwidth while the location of controller zeros with respect to the new ωo is maintained. From (4) the location of the zeros ωz1 and ωz2 is related to the parameters Kp’ and Kd’. The bandwidth of the original controller is maintained when Ki of the scaled controller equals Ki of the original one and Kp, Kd are scaled to achieve bandwidth and zeros location constrains (5). Considering n=1 and assuming that the bandwidth ωc is such that ωo < ωc < ωesr, at ω >> ωo the plant Gvd(s) can be approximated as: 2

⎛ jω ⎞ ⎛ω ⎞ ⎟⎟ ⎯ ⎯→ Gvd (ωc ) ≅ 1 / ⎜⎜ c ⎟⎟ (6) Gvd ( jω ) ω >>ω ≅ 1 / ⎜⎜ o ω ⎝ o⎠ ⎝ ωo ⎠ For n>1 the resonance frequency of the plant is ω ' o = ω o / n and the gain of the plant at ωc is Gvd (ωc ) ≅ ωc (ωc n ) = Gω / n . As shown in Fig. 4 the scaled compensator should boost the gain of the loop by a factor n at frequencies above ωo, i.e. Kd should increases of n, while the location of PD zero ωz2 should be scaled of n to accommodate ω’o. This results in the new c

Fig. 8 Application schematic of the ZMDI ZSPM1363 Dual Phase digital controller used to evaluate the proposed scaling methods. Resistor value at the RTUNE™ pin can be trimmed to select different values of n to scale a preconfigured compensator upon a variation of the bulk capacitance.

controller parameters being Kp_scaled = Kp · n , Ki_scaled = Ki, Kd_scaled = Kd · n. The phase margin of the resulting controller increases due to a weaker influence of the LC output filter on the phase behavior at ωc, as ωo moves to lower frequencies. As a consequence the closed-loop output impedance of the scaled controller will exhibit a smaller peak at ωc with respect to the original design resulting in an improvement of the voltage undershoot [15]. Conversely, because the integral parameter of the scaled controller is not affected by the scaling process the attenuation of the closed-loop impedance at low frequencies is the same as for the original design. This results in an increase of the settling time upon a load step transient. Although this may be acceptable in applications Method 2 does not meet the target of this paper, i.e. derive a controller that scales the closed-loop dynamics of the original design at every frequency. Method 3: Proposed Method As stated in [10] with two-parameters compensators, the bandwidth/phase margin constrains uniquely define the compensator frequency response and, hence, the desired system loop gain at every frequency. It is clear then that once Kd_scaled is fixed to achieve the bandwidth constraint both Kp and Ki of the original PI controller need to be scaled to preserve the original phase margin. As Kd increases by a factor n to maintain the bandwidth, Kp has to be increased by the same factor to maintain the location of ωz2 and therefore its phase contribution at ωc. Differently from Method 2, here, Ki is increased by a factor n to shift the zero in ωz1 to follow ωo, thus guaranteeing enough phase boost around ω'o. Fig. 5 illustrates the compensator scaling principle. In summary, to achieve enough phase boost at ω'o, the PI zero ωz1 has to shift together with ωo while the zero in ωz2 maintains its original location to compensate for the phase variation at ωc given by ωo that has moved to lower frequencies. This results in a scaled compensator having parameters Kp_scaled =Kp · n, Ki_scaled = Ki · n , Kd_scaled= Kd · n

Fig. 9 Comparison between the transient responses of the reference design compensator for the case n=3 (black) and the case n=6 (blue) without compensator scaling. The increase of output capacitance penalizes the close loop dynamic.

Fig. 11 Comparison between the transient responses of the reference design compensator for the case n=3 (black) and the compensator scaled with Method 2 for the case n=6 (blue). The increase of phase margin significantly slows down the settling time.

Fig. 10 Comparison between the transient responses of the reference design compensator for the case n=3 (black) and the compensator scaled with Method 1 for the case n=6 (blue).

Fig. 12 Comparison between the transient responses of the reference design compensator for the case n=3 (black) and the compensator scaled with Method 3 for the case n=6 (blue). Bandwidth, phase margin and control loop dynamics are preserved compared to the reference design.

Fig. 6 and Fig. 7 show the frequency response of the plant, the controller and the open-loop obtained by scaling the compensator as proposed in Method 3. TABLE I: Summary of the scaling factors to be applied to controller proportional, integral and derivative parameters for the proposed compensator scaling methods.

Kp Ki Kd

Method 1 1

Method 2 n

Method 3 n

1/ n

1 n

IV.

EXPERIMENTAL PLATFORM

Method 3 has been incorporated into a commercial POL controller, the ZSPM1363 from ZDMI. The controller could be set for various values of capacitance selecting an RTUNE™ trim resistor (accordingly to the scaling factor n) to evaluate the proposed compensator scaling method. Fig. 8 shows the application schematic of the ZSPM1363. For comparison, Methods 1 and 2 were also evaluated on the same platform.

EXPERIMENTAL RESULTS

Experimental results have been collected for a single phase POL converter, as described in Section IV, having the following parameters: Vin=12V, Vout=1.2V, Fsw=500kHz, L=470nH, output capacitor C=100µF, ESR of output capacitor Rc=2.6mΩ. A controller was designed for: bandwidth fc=52.54kHz, phase margin PM=45.25°, scaling factor n=3. A reference transient response for a load step from 5A to 10A was taken. The controller was then scaled for the case n=6 using the three proposed methods. For comparison, the undershoot for a 5A load step was approximated as ΔVout _ pp = ΔI out ( 2πf c ⋅ n ⋅ C ) [11], yielding ΔVout _ pp = 53mV and ΔVout _ pp = 26.5mV for n=3 and n=6 respectively. Fig. 9 to Fig. 12 show comparisons between the transient performance of the original compensator (n=3) and the scaled compensators (n=6) using the three proposed methods. Starting from the case where additional capacitance is added without tuning the controller (Fig. 9), i.e. closed-loop dynamics deteriorates both in bandwidth and phase margin, Method 1 shows that closed-loop dynamic can be scaled in time, as explained, by scaling the bandwidth as well (Fig. 10). Method 2 leads to a slightly higher bandwidth compared to the reference design but also increases the phase margin. As

Fig. 13 Gain-Phase measurements of reference compensator design (blue), original compensator (green) and compensator scaled using Method 3 (red) upon increase of the output capacitance of 3 times. Bandwidth and phase margin are preserved.

explained in Section III the settling time of the scaled controller increases because the lack of attenuation of the scaled closed-loop output impedance in the low frequency range (Fig. 11). Method 3 (proposed method) preserves both bandwidth and phase margin, thus maintaining the dynamic performance of the closed-loop as capacitance varies (Fig. 12). TABLE II summarizes the results in terms of bandwidth fc, phase margin PM, position ωn of the closed-loop poles and the associated Q factor Qn. It is interesting to notice that for the case of Method 3 closed-loop pole location is maintained with respect to the original design thus showing that frequency response of the original controller is scaled at every frequency, resulting in a load transient response that is actually a scaled version of the load transient response obtained for the original design. Finally, Fig. 13 shows the effectiveness of the proposed method (Method 3) in the frequency domain. TABLE II: Comparison between obtained bandwidth fc, phase margin PM and position of closed-loop zeros ωn, as well as their associated Q factor Qn with respect to the reference design. Reference design n

Method 1 6

Method 2 6

Method 3 (proposed) 6

52.54

37.28

58.87

52.5

45.25

42.31

52.27

56.76

40.48

2.06*105

8.28*104

1.45*105

1.66*105

2.05*105

0.702

0.555

0.69

0.54

0.67

[kHz] PM [deg]

ωn [rad/s] Qn

as well. Differently from most of the auto-tuning methods proposed so far controller parameters are tuned by acting on a controller proportional, integral and derivative asymptotes rather than controllers zeros directly. As Method 3 clearly shows, the zeros of the scaled controlled are not forced to be of the same type as the zeros of the original controller so that the required phase boost to maintain phase margin constraint is always achieved, resulting advantageous for our purposes. Finally, the proposed scaling methods are defined by simple scaling formulas leading to low computational cost tuning solutions that can also be applied to auto-tuning controllers, if desired, with the aim of shortening the controller tuning phase while enabling the tuned controller to match closed-loop dynamics requirements. REFERENCES [1] [2]

[3]

[4]

[5]

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[10]

[11]

VI.

CONCLUSIONS

In this paper three methods to scale a controller from an original design to accommodate variation of the power stage resonant frequency are presented and compared. In particular a new scaling method is proposed which is proven to maintain closed-loop dynamics of the original controller. It is shown that only one single tuning variable is required to preserve both bandwidth and phase margin of the original design which results in maintaining the original closed-loop poles location

[12]

[13]

[14]

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