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Cadence’s Cerebrus Offers a Revolution in Chip Design Productivity To enable the semiconductor industry to continue growing, the chip design process must become more efficient. With the availability of massive, cloudenabled, distributed computing and advancements in ML computer science, the next chip design automation revolution is now possible states Venkat Thanvantri | VP, R&D, AI/ML Digital and Signoff | Cadence while talking in an exclusive Interview with Niloy. In this most-awaited interview, the veteran underlines what’s changing design processes for the semiconductor industry and also the need for advanced technologies like AI/ML in their respective design strategies. Edited excerpts below.
Q
Let’s talk about how Cadence is extending Digital-Design leadership with stated revolutionary ML-Based Cerebrus? Cadence’s Cerebrus Intelligent Chip Explorer utilizes massively distributed compute power and a unique machine learning (ML)-based reinforcement learning engine, combined with the Cadence digital full flow solution, to deliver better PPA more quickly. Cerebrus automation capabilities enable engineering teams to scale more efficiently and boost productivity so more designs can be implemented concurrently. In addition to automated implementation flow optimization, Cerebrus has the capability to explore high-level design optimizations, such as dynamically resizing and shaping a floorplan to improve PPA much more efficiently than a manual approach. All design learnings are stored in a reinforcement learning model that can easily be used in future design projects to optimize the flow even more quickly. Cerebrus offers a revolution in chip design productivity, which will allow the semiconductor industry to continue growing and delivering the new SoC product features and capabilities we all expect in our increasingly connected world.
Q
What is driving the need for automating digital chip design integrating advance technologies such as (AI/ML)? To enable the semiconductor industry to continue growing, the chip design process must become more efficient. With the availability of massive, cloudenabled, distributed computing and advancements in ML computer science, the next chip design automation revolution is now possible. The Cadence Cerebrus Intelligent Chip Explorer utilizes both of these technologies, based on the industry-leading Cadence digital full flow, to deliver better power, performance, and area (PPA) more quickly. Engineering teams now are able to scale and become more productive using the Cerebrus reinforcement learning engine to meet the challenges of increasingly large and more complex system-on-chip (SoC) designs.
Venkat Thanvantri
VP, R&D, AI/ML Digital and Signoff, Cadence
Q
According to you the key reason behind global chip shortage and how AI/ML can rev-up the semiconductor industry? When Cadence talks about AI and ML in its software, we are talking about helping chip designers automate certain parts of the design process to speed time to market. The chip shortage has to do with manufacturing and
16 09 | 2021 BISinfotech
