Design of Request Completion Handler for PCI Express

IDL - International Digital Library Of Technology & Research Volume 1, Issue 2, Mar 2017

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International e-Journal For Technology And Research-2017

Design of Request Completion Handler for PCI Express Niranjan Mamadapur1, Shriram P Hegde2 Department of Electronics and Communication Engineering 1 SDM Institute Of Technology 2 SDM Institute Of Technology Ujire, India

Abstract: PCI Express is the third generation high performance I/O bus used to interconnect peripheral devices in applications such as computing and communication platforms. The first generation buses include the ISA, EISA, VESA, and Micro Channel buses, while the second generation buses include PCI, AGP, and PCI-X. PCI Express is an all-encompassing I/O device interconnect bus that has applications in the mobile, desktop, workstation, server, embedded computing and communication platforms. Request completion handler is the interface operates in between the PCIe master and the PCIe client. It performs the data transactions between the PCIe master and PCIe client. Requests are sent to the client through request completion handler and completions are sent back to the master through the request completion handler. Request completion handler performs the completions for non-posted requests as well as posted requests. The scope of this work involves designing the request completion handler for PCIe, develop coding for simulation and test it.

Keywords: PCI Express, ISA, EISA, VESA 1.

INTRODUCTION

receives the requests from the master. Perform the completions [3] for non-posted requests and send them back to the master.

PCI Express PCI Express [1] is the third generation high performance I/O bus used to interconnect peripheral devices in applications such as computing and communication platforms. The first generation buses include the ISA, EISA, VESA, and Micro Channel buses, while the second generation buses include PCI, AGP, and PCI-X. PCI Express [4] is an allencompassing I/O device interconnect bus that has applications in the mobile, desktop, workstation, server, embedded computing and communication platforms. The PCI Express specification defines a layered architecture for device design as shown in figure. The layers [8] consist of a Transaction Layer [6], a Data Link Layer [2] and a Physical layer [9].

The layers can be further divided vertically into two, a transmit portion that processes outbound traffic [13] and a receive portion that processes inbound traffic.

However, a device design does not have to implement a layered architecture as long as the functionality required by the speciation [12] is supported.

The PCIe slave interface [11] is the communication interface which operates in between the PCIe master and the slave or client. It provides the necessary interface to perform the following operations. Sends the requests from the master, both posted and nonposted requests are sent to the client or slave. Performs the completions of non-posted requests sent by the master.

PCIe Master: PCIe master or the host is the one which initiates the transaction. PCIe Slave: PCIe slave IDL - International Digital Library

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Byte Ordering At Endpoints

PCIe System

The header [15] contains 3 or 4 Data Words. Important fields are part of the first Data Word. The Fmt field gives information about how long is the header and whether data payload is present. The Type field defines the TLP operation. R fields are the reserved fields. The TD field gives information about whether there is an extra CRC on the TLP data. The Length field defines the length of the data. The Requestor ID gives information about the sender of the packet[14].The First Word BE field (1st DoubleWord Byte Enable) allows to choose which of the four bytes in the first Data Word are valid and should be written. The Last Word BE field must be zero when Length is unity, since the first Data Word and the last is the same one. Address field is the address to which the first Data Word is written. It is shown in the Figure below.

PCIe system [17] is shown in the figure below.

Request completion handler is the interface which operates in between the PCIe master and the PCIe client. It provides the necessary interface to perform the data transactions between the PCIe master [5] and PCIe client. Requests are sent to the client through request completion handler and completions [16] are sent back to the master through the request completion handler.

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International e-Journal For Technology And Research-2017 PCIe Controller PCIe controller is located at the endpoints [10] of PCI express system. PCI hard macro implements the three layers of the PCI Express namely transaction layer [6], data link layer and physical layer. PCI Tx (Transmitter) Rx (Receiver) processor initiates the transactions [11]. PCIe request handler provides the necessary interface [7] for the transaction between the master and the slave. PCIe request completion handler sends the requests from the master to the client and send the completions from the client to the master.

Requests are two types posted requests and non-posted requests. Posted requests are the one which does not need an acknowledgement where as non-posted requests are the one which need an acknowledgement.

Example of the posted request is the memory write operation. In this case the master sends the address as well as the data along with the write request. There is no need of acknowledgement or the completion from the client. Example of non-posted request is the memory read operation. In this case the master sends read request along with the address from which it has to be read. The client has to send an acknowledgement or the completion which is nothing but the read data.

These request and completion operations are performed by the PCIe request completion handler.

PCIe controller is shown in the Figure below

completion handler performs the completions for the non-posted requests. The attribute FIFO holds the attributes, data FIFO holds the data, header FIFO holds the header information and completion FIFO holds the completion data.

2.

OBJECTIVES

  

To design the slave request handler.

To design the slave completion handler.

To design the attribute FIFO, data FIFO, header FIFO and completion FIFO. To design the client (slave) which in this case is memory.

Develop the code for all the blocks using Verilog HDL. Integrate all the blocks.

Perform the synthesis using ISE simulator.

Simulate the design.

Test all the operations of the request completion handler.

    



Request Completion Handler Request completion handler operates in between the PCIe [5] Tx-Rx processor and the client. The block diagram of the request completion handler is shown in the Figure below. The requests are sent to the client through the request completion handler and IDL - International Digital Library

3.

OPERATION OF REQUEST COMPLETION HANDLER

The operation of request completion handler is to send both posted and non-posted requests to the client and 3|P a g e

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International e-Journal For Technology And Research-2017 send back the completions or the acknowledgements to the master depending upon whether the request made is posted or non-posted request. The request completion handler gets the inputs from the byte ordering of the PCIe endpoint. The inputs given to the PCIe slave are the 1) Attributes 2) Header Information 3) Data Attribute information consists of the following.

1) Address.

2) Length in bytes.

3) Base address registers being hit.

4) Whether the request being made is to the memory space or IO. 5) Whether the request being made is a read request or the write request.

Header information consists of the following.

1) Tag. 2) Traffic class which assigns the speed priority to the packet to travel through the PCIe fabric.

3) Length of the transaction.

4) Byte count.

5) Requestor ID. 6) First Word Byte Enable FWBE. 7) Lower Address LWADDR. Data information consists of the following.

1) Data to be written.

2) Byte enable.

3) Information about the end of data EOD. 4) Forwarded error.

- Get the data which is read from the client for nonposted requests and shift it according to the FWBE signal.

- Get the header information from the header FIFO, -Form the quad words. Quad word 1 which is nothing but the header, quad word 2 holds the header plus the shifted data and quad word 3 holds the data.

- Slave completion handler selects the quad words according to the status of header FIFO, completion FIFO, the error signals and sends them to the slave completion FIFO - It also performs the EOD operation.

4.

SIMULATION RESULTS

The simulation result of the request handler is shown in the Figures below.

A. Operation of Slave Request Handler Operations of slave request handler is as following.

-To receive the attribute, header and data information from the end point block byte ordering.

-Shift the data according to the FWBE and LWBE by using data shifting logic so that only valid bytes are sent to the client.

-Checks the end of data.

-Performs the error check logic.

-Sends the appropriate information to the appropriate FIFO so as to store them for further processing.

Attributes are sent to the attribute FIFO, data is sent to the data FIFO and header information is sent to the header FIFO. B. Operation of Slave Completion Handler Operation of the slave completion handler is as following.

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International e-Journal For Technology And Research-2017

The simulation result of the completion handler is shown in the Figures below.

The simulation results of the top module is shown in the Figures below

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5.

OUTCOMES

The work is done in designing the Request Completion Handler for PCI Express, which performs the completions for requests sent from the master to the client. The Request Completion Handler is interfaced with the memory which is used as a client in this work. Both posted and non-posted transactions are performed. Simulation and synthesis of PCI Express Slave interface is done by writing the test bench with all the requirements specified in the user guides.

Further work can be extended in simulating and testing the design using End Point Block Plus for PCI Express present in the core generator tool of Xilinx 12.2 version.

CONCLUSION Request handler for PCI Express has been designed using Verilog HDL and simulated using Xilinx ISE simulator. Implementation of the design in Virtex 5 FPGA can be performed.

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