FPGA Implementation of High Speed 8bit Vedic Multiplier using Barrel Shifter

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FPGA Implementation of High Speed 8bit Vedic Multiplier using Barrel Shifter Punith Kumar M B Dept. of ECE, PESCE Mandya, India. punithpes@gmail.com

Sahana Raj B S Dept. of ECE, PESCE Mandya, India. sahanagandhi@gmail.com

Abstract— In today’s world Vedic mathematics has proved to be the most robust technique for arithmetic operations. In contrast, conventional techniques for multiplication provide significant amount of delay in hardware implementation of n-bit multiplier. Moreover, the combinational delay of the design degrades the performance of the multiplier. Hardware-based multiplication mainly depends upon architecture selection in FPGA or ASIC. A barrel shifter is a digital circuit that can shift a data word by a specified number of bits in one clock cycle. It can be implemented as a sequence of multiplexers (mux.), and in such an implementation the output of one mux is connected to the input of the next mux in a way that depends on the shift distance.

Keywords- Vedic Mathematics, Barrel Shifter, FPGA, Xilinx.

I.

INTRUDUCTION

Arithmetic operations such as addition, subtraction and multiplication are deployed in various digital circuits to speed up the process of computation. Arithmetic logic unit is also implemented in various processor architectures like RISC, CISC etc. Arithmetic operations unit is a fundamental building block of the central processing unit CPU) of a computer, and even the simplest microprocessors contain one for purposes such as maintaining timers. The processors found inside modern CPUs and graphics processing units (GPUs) accommodate very powerful and very complex Arithmetic operations unit; a single component may contain a number of Arithmetic operations unit. In general, arithmetic operations are performed using the packed-decimal format. This means that the fields are first converted to packed-decimal format prior to performing the arithmetic operation, and then converted back to their specified format (if necessary) prior to placing the result in the result field.

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Multiplication is an important fundamental function in arithmetic operations. Multiplication-based operations such as Multiply and Accumulate(MAC) and inner product are among some of the frequently used Computation- Intensive Arithmetic Functions(CIAF) currently implemented in many Digital Signal Processing (DSP) applications such as convolution, Fast Fourier Transform(FFT), filtering and in microprocessors in its arithmetic and logic unit. Since multiplication dominates the execution time of most DSP algorithms, so there is a need of high speed multiplier.

Currently, multiplication time is still the dominant factor in determining the instruction cycle time of a DSP chip. The demand for high speed processing has been increasing as a result of expanding computer and signal processing applications. Higher throughput arithmetic operations are important to achieve the desired performance in many realtime signal and image processing applications. One of the key arithmetic operations in such applications is multiplication and the development of fast multiplier circuit has been a subject of interest over decades. Reducing the time delay and power consumption are very essential requirements for many applications.

Vedic mathematics covers explanation of several modern mathematical terms including arithmetic, geometry (plane, coordinate), trigonometry, quadratic equations, factorization and even calculus.

Vedic Mathematics is the name given to the ancient system of Indian Mathematics which was rediscovered from the Vedas between 1911 and 1918 by Sri Bharati KrsnaTirthaji (1884-1960). According to his research all of mathematics is based on sixteen Sutras, or word-formulae. For example, 'Vertically and crosswise` is one of these Sutras.

The objectives of this work are listed below:

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IDL - International Digital Library Of Technology & Research Volume 1, Issue 2, Mar 2017

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i.

Design a method to put into effect a high speed Vedic multiplier using barrel shifter.

ii.

Develop an algorithm to implement sutra by modified design of “Nikhilam Sutra”due to its feature of reducing the number of partial products.

iii. The barrel shifter used at different levels of design, drastically reduces the delay when compared to conventional multipliers. iv. The hardware implementation of Vedic multiplier using barrel shifter contributes to adequate improvement of the speed in order to achieve high outturn.

II.

LITERATURE SURVEY

Multiplication is one of the basic arithmetic operations and it requires substantially more hardware resources and processing time than addition and subtraction. In fact, 8.72% of all the instruction in typical processing units is multiplication.

Comparative study of different multipliers is done for low power requirement and high speed. “UrdhvaTiryakbhyam” algorithm of Ancient Indian Vedic Mathematics which is utilized for multiplication to improve the speed, area parameters of multipliers. Vedic Mathematics suggests one more formula for multiplication of large number i.e.

“Nikhilam Sutra” which can increase the speed of multiplier by reducing the number of iterations .

Vedic mathematic is an ancient technique with unique approach and it has got different sutras. Here, “Nikhilam Navatascaramam Dasatah”Sutra is used , which is efficient in speed of the multiplier. The implementation of an 8-bit Vedic multiplier enhanced in terms of propagation delay when compared with conventional multipliers. In our design we have utilized 8-bit barrel shifter which requires only one clock cycle for “n” number of shifts.

Vedic mathematics is an ancient technique which was used in the time of Vedas. It has got as many as 16 Sutras that can be used for different Arithmetic calculation. Vedic Sutras apply to and cover almost every branch of Mathematics. They apply even to complex problems involving a large number of mathematical operations. Vedic mathematics has proved to be the most robust technique for arithmetic operations. In contrast, conventional techniques for multiplication provide significant amount of delay in hardware implementation of nbit multiplier. Moreover, the combinational delay of the IDL - International Digital Library

design degrades the performance of the multiplier. Application of the Sutras saves a lot of time and effort in solving the problems, compared to the formal methods presently in vogue.

Though the solutions appear like magic, the application of the Sutras is perfectly logical and rational III.

PROPOSED WORK

The high speed implementation of such a multiplier has wide range of applications in image processing, arithmetic logic unit and VLSI signal processing. The propagation delay of array multiplier and conventional Vedic multiplier implementation on FPGA is very high. Since propogation delay is high it reduces the speed of the device. In our design we reduce the propagation delay by implementing the vedic multiplier on FPGA using barrel shifter.

We assume that the multiplier is ‘X’ and multiplicand is ‘Y’. Though the designation of the numbers is different but the architecture implemented is same to some extent for evaluating both the numbers. Mathematical we solve using nikhilam sutra.

The hardware deployment is partitioned into three blocks. i. Base Selection Module ii. Power index Determinant Module iii. Multiplier.

The base selection module (BSM) is used to select the maximum base with respect to the input numbers. The second sub-module power index determinant(PID) is used to extract the power index of k1 and k2. The multiplier comprises of base selection module (BSM), power index determinant (PID), subtractor, barrel shifter, adder/subtractor as sub-modules in the architecture.

IV.

VEDIC MATHEMATICS

History of Vedic Mathematics:Vedic mathematics is part of four Vedas (books of wisdom). It is part of Sthapatya- Veda (book on civil engineering and architecture), which is an upaveda (supplement) of Atharva Veda. It covers explanation of several modern mathematical terms including arithmetic, geometry (plane, co-ordinate), trigonometry, quadratic equations, factorization and even calculus. His Holiness Jagadguru Shankaracharya Bharati Krishna Teerthaji Maharaja (1884-1960) comprised all this work together and gave its mathematical explanation while discussing it for various applications.

Algorithms of Vedic Mathematics: Arithmetic operations such as addition, subtraction and multiplication are deployed 2|P a g e

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in various digital circuits to speed up the process of computation. Arithmetic logic unit is also implemented in various processor architectures like RISC, CISC etc.,Vedic mathematics has proved to be the most robust technique for arithmetic operations. In contrast, conventional techniques for multiplication provide significant amount of delay in hardware implementation of n-bit multiplier. Vedic Sutras apply to and cover almost every branch of Mathematics.

Vedic Multiplication: The proposed Vedic multiplier is based on the Vedic multiplication formulae (Sutras). These Sutras have been traditionally used for the multiplication of two numbers in the decimal number system. The multiplier is based on an algorithm UrdhvaTiryakbhyam (Vertical & Crosswise) of ancient Indian Vedic Mathematics.

UrdhvaTiryakbhyam Sutra is a general multiplication formula applicable to all cases of multiplication. It literally means “Vertically and crosswise”. It is based on a novel concept through which the generation of all partial products can be done with the concurrent addition of these partial products.

V.

Figure 1: Base Selection Module 

Power Index Determinant

METHODOLOGY

Assume that the multiplier is ‘X’ and multiplicand is ‘Y’. Though the designation of the numbers is different but the architecture implemented is same to some extent for evaluating both the numbers.

The mathematical expression for modified nikhilam sutra is given below.

P=X*Y= 2k2 * (X+Z2*2k1-k2) + Z1*Z2…………....(1) Where k1, k2 are the maximum power index of input numbers X and Y respectively. Z1 and Z2 are the residues in the numbers X and Y respectively. 

Base Selection Module The base selection module has power index determinant (PID) as the sub-module along with barrel shifter, adder, average determinant, comparator and multiplexer.

Operation: An input 8-bit number is fed to power index determinant (PID) to interpret maximum power of number which is fed to barrel shifter and adder. The output of the barrel shifter is ‘n’ number of shifts with respect to the adder output and the input based to the shifter. Now, the outputs of the barrel shifter are given to the multiplexer with comparator input as a selection line. The outputs of the average determinant and the barrel shifter are fed to the comparator.

The required base is obtained in accordance with the multiplexer inputs and its corresponding selection line.

The input number is fed to the shifter which will shift the input bits by one clock cycle. The shifter pin is assigned to shifter to check whether the number is to be shifted or not. In this power index determinant (PID) the sequential searching has been employed to search for first ‘1’ in the input number

Figure 2: Power Index Determinant IDL - International Digital Library

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starting from MSB. If the search bit is ‘0’ then the counter value will decrement up to the detection of input search bit is ‘1’. Now the output of the decrementer is the required power index of the input number.



Multiplier Architecture

The base selection module and the power index determinant form integral part of multiplier architecture. The architecture computes the mathematical expression in equation1.Barrel shifter used in this architecture.

The two input numbers are fed to the base selection module from which the base is obtained. The outputs of base selection module (BSM) and the input numbers ‘X’ and ‘Y’ are fed to the subtractors. The subtractor blocks are required to extract the residual parts z1 and z2. The inputs to the power

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index determinant are from base selection module of respective input numbers. The sub-section of power index determinant (PID) is used to extract the power of the base and followed by subtractor to calculate the value. The outputs of subtractor are fed to the multiplier that feeds the input to the second adder or subtractor. Likewise the outputs of power index determinant are fed to the third subtractor that feeds the input to the barrel shifter. The input number ‘X’ and the output of barrel shifter are rendered to first adder/subtractor and the output of it is applied to the second barrel shifter which will provide the intermediate value. The last sub-section of this multiplier architecture is the second adder/subtractor which will provide the required result.

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Figure 3: Multiplier Architecture

VI.

SIMULATION RESULTS AND DISCUSSION

Here we deals with results obtained by simulation, synthesis and implementation of Vedic Multiplier module and their sub modules. Simulation is done in Xilinx ISim simulator. Synthesis results are obtained using ISE tool.

Implementation is done on Xilinx Spartan-6 CSG324 evolution kit and using ChipScope Pro. Simulation results of Vedic Multiplier Top module, are discussed below. Simulation Results of Vedic Multiplier is shown Figure 4. Inputs “a and b” are forced to module each of 8-bit. The output “op” is obtained which is of 16-bit after simulation. The inputs values are forced to the module and simulation is performed to obtain the output. In the above figure the simulation result of input “a=125” and “b=75” is shown. After simulation output “op=9375” is obtained. For different values of inputs, output is obtained after simulation.

Figure 5: RTL Schematic of Vedic Multiplier

The total power utilization is shown in Figure 6.

After simulation and implementation, the power report is obtained from Xilinx XPower Analyzer. The total power utilization of the module obtained after simulation is 0.032W. Figure 4: Simulation results of Vedic Multiplier module

Synthesis Report of Vedic Multiplier module are synthesized using Xilinx XST synthesis tool for Xilinx Spartan-6 CSG324 device. The RTL schematics of module shown in Figure 5

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Figure 6: Power Analysis Report

Figure 7: ChipScope Pro Result

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The ChipScope Pro tool also interfaces with your Agilent Technologies bench test equipment through the ATC2 software core. This core synchronizes the ChipScope Pro tool to Agilent’s FPGA Dynamic Probe add-on option.

This unique partnership between Xilinx and Agilent gives you deeper trace memory, faster clock speeds, more trigger options, and system-level measurement capability all while using fewer pins on the FPGA device.

The ChipScope Pro Result of the Vedic Multiplier Module is shown Figure 7.

VII. CONCLUSIONS We achieve a high percentage of reduction in the propagation delay when compared to array multiplier and conventional Vedic multiplier implementation on FPGA. The wide ranges of applications of multiplier unit can be witnessed in VLSI and signal processing applications. The project can be extended to the power analysis of the multiplier.

We conclude that the proposed technique of multiplication using Urdhva Tiragbyam algorithm and Nikhilam Sutra algorithm causes less latency when compared to available techniques in literature. The proposed technique when implemented for 8x8 bit multiplication, the delay is found to be reduced on SPARTAN 6. The adoption of this algorithm for higher bit size multipliers will further show improvement in speed. Further, higher speeds can be achieved by making use of pipelining and parallel processing techniques. This work will increase awareness of Vedic mathematics techniques in the field of engineering and delivers high performance in DSP Processors.

The proposed Vedic multiplier architecture exhibits speed improvements. The 8x8 Vedic multiplier employing Nikhilam Sutra found to be better than 8x8 conventional multiplier in terms of speed when magnitude of both operands are more than half of their maximum values. This approach may be well suited for multiplication of numbers with more than 16bit size.

[2] Shamsiahsuhaili and Othmansidek, “Design and implementation of reconfigurable alu on FPGA”, 3rd International Conference on Electrical & Computer Engineering ICECE 2004, 28-30 December 2004, Dhaka, Bangladesh, pp.56-59.

[3]Sumit Vaidya and Deepak Dandekar, “Delay-Power Performance Comparison of Multipliers in VLSI Circuit Design”, International Journal of Computer Networks & Communications (IJCNC), vol.2, no.4, july 2010, pp.47-56.

[4] P. Mehta, and D. Gawali, "Conventional versus Vedic mathematical method for Hardware implementation of a multiplier," in Proceedings IEEE International Conference on Advances in Computing, Control, and Telecommunication Technologies, Trivandrum, Kerala, Dec. 28-29, 2009, pp. 640-642.

[5] Prabirsaha, Arindam Banerjee, Partha Bhattacharyya, Anupdandapat, “High speed ASIC design of complex multiplier using vedic mathematics” , Proceeding of the 2011 IEEE Students' Technology Symposium 14-16 January, 2011, litkharagpur, pp. 237-241 [6] Arnav Gupta, Harshit Gupta, “Design and Simulation of High Speed 8-bit Vedic Multiplier Using Barrel Shifter on FPGA”,International Journal of Engineering Research Technology (IJERT), Vol. 2 Issue 10, October – 2013.

[7] P. Sreenivasa Rao, C.Md. Aslam. “Design of Complex Multiplier WITH High Speed ASIC Using Vedic Mathematics”,International Journal of Engineering Research & Technology (IJERT)Vol. 1 Issue 6, August – 2012.

[8] Jagadguru Swami Sri Bharatikrisnatirthaji Maharaja, “Vedic Mathematics: Sixteen Simple Mathematical formulae from the Veda”,Delhi.

[9] Devika, K. Sethi and R.Panda, “Vedic Mathematics Based Multiply Accumulate Unit,” 2011 Internationalconference on Computational Intelligence and communication Systems, CICN 2011, pp.754-757, Nov.2011.

REFERENCES [10] J. S. S. B. K. T. Maharaja, Vedic mathematics, Delhi:motilalbanarsidass Publishers Pvt Ltd, 2001.

[1] Sudeep M C, SharathBimba M, MahendraVucha.

“Design and FPGA Implementation of High Speed Vedic Multiplier”,International Journal of Computer Applications (0975 – 8887) Volume 90 – No 16, March 2014.

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[11] Ramchandran.S and Kruthi.S.Pande. May-June 2012.

“Design, Implementation and Performance Analysis of an Integrated Vedic Multiplier Architecture.” Amrita college of Engineering, Bangalore.

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[12] Samir Palnitkar.“Verilog HDL, A guide to Digital Design and Synthesis” 2nd edition. Dorling Kindersley and Pearson Education, Inc. 2008.

[13] Poornima M., Shivaraj Kumar Patil, Shivukumar, Shridhar K P and Sanjay H. May, 2013. “Implementation of Multiplier using Vedic Algorithm”. MVJCE, Bangalore.

[14]Pushpalataverma and K.K.Mehta.

June 2012.“Implementation of an efficient Multiplier Based on Vedic Mathematics using EDA tool.”

[15]Charles. Roth Jr. “Digital Systems Design using VHDL” Thomson Brooks/Cole,2005.

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