Chapter 5 - Arithmetic Circuit

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Half-Adder • Recall the basic rules for binary addition are:0+0=0 0+1=1 1+0=1 1 + 1 = 10 • The operations are performed by a logic circuit called halfadder. • The half-adder accepts two binary digits on its inputs and produces two binary digits on its outputs, a sum bit (S) and a carry bit (Cout). Logic symbol

A

B 10/9/2012

Half Adder

Sum Carry 1


Chapter 5 Arithmetic Circuits Half Adder & Full Adder Signed Number System Subtractor Circuit Adder-Subtractor Circuit


Half-Adder Truth table

A B Sum Cout 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1

Boolean Expression

S  A.B  A.B  A  B C  A.B

Logic Circuit A B

S

out

Cout

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Full-Adder • The full-adder accepts two input bits and an input carry and generate a sum output and an output carry. Truth table

Logic symbol

A B Cin Sum Cout A

B Cin

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Full Adder

Sum Cout

0 0 0 0 0 1

0 1 0

0 1 1

0 0 0

0 1 1 0 1 0

1 0 1

0 1 0

1 0 1

1

1

0

0

1

1

1

1

1

1 4


Full-Adder Boolean Expression

Logic Circuit

S  A.B.C  A.B.C  A.B.C  A.B.C in

in

 A( B.C B.C in 

in ) 

in

in

A( B.C  B.C in

in )

 A( B  C )  A( B  C )  A B C in

A B

in

Cout

in

Co  A.B.C  A.B.C  A.B.C  A.B.C in

in

in

Cin

S

in

 C ( A.B  A.B)  A.B.(C  C ) in

in

in

 C ( A  B)  A.B in

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Signed Numbers

• The left most bit is the sign bit which can be either positive or negative. • 0 represents positive number while 1 represents negative number. • Three common representation of signed numbers are: Sign-Magnitude

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1’s Complement

2’s Complement

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Sign-Magnitude Number • In sign-magnitude system, a number consists of two parts: Sign bit

Magnitude

• The magnitude is the true binary number. +25 = 0 00110012 Example Sign bit

Magnitude

-25 = 1 00110012 • Range : -(2n – 1-1) to +(2n-1 -1) where n is the number of bits. For n = 4, the range is: Example

= -(24 – 1-1) to +(24-1 -1) = -7 to +7 10/9/2012

Signed Decimal +7 +6 +5 +4 +3 +2 +1 +0 -0 -1 -2 -3 -4 -5 -6 -7

Sign-magnitude 0111 0110 0101 0100 0011 0010 0001 0000 1000 1001 1010 1011 1100 1101 1110 1111 7


1’s Complement Number • The 1’s complement of a binary number is derived by changing 1s to 0s and 0s to 1s. Example

+25 = 000110012 -25 = 111001102

• Range : -(2n – 1-1) to +(2n-1 -1) For n = 4, the range is: Example

= -(24 – 1-1) to +(24-1 -1) = -7 to +7

• If an operation produces a result that falls outside the available range, then an overflow occurs. 10/9/2012

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2’s Complement Number • The 2’s complement of a binary number can be derived by adding 1 to the 1’s complement. Signed Decimal 2's complement n – 1 n-1 +7 0111 • Range : -(2 ) to +(2 -1) Example

For n = 4, the range is: = -(24 – 1) to +(24-1 -1) = -8 to +7

• If an operation produces a result that falls outside the available range, then an overflow occurs.

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+6 +5 +4 +3 +2 +1 +0 -8 -7 -6 -5 -4 -3 -2 -1

0110 0101 0100 0011 0010 0001 0000 1000 1001 1010 1011 1100 1101 1110 1111

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2’s Complement Number Example:

Convert -2510 using 8 bit two’s complement number system. Steps:

1

Convert 2510 to binary using 8-bit

+2510 = 000110012

2

Then, complement each bit, 0 to 1 and 1 to 0 (1’s complement)

111001102

3

Add 1 to the complemented number

111001102 + 1 -2510 = 111001112 10/9/2012

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2’s Complement Arithmetic Example:

Perform 2510 - 1510 using 8 bit two’s complement number system. Steps:

1

Convert 2510 and 1510 to binary using 8-bit.

+2510 = 000110012

2

+1510 = 000011112

Then, calculate -1510 (1’s complement + 1).

11110000 + 1 = 111100012

3

Add both numbers. Discard the carry.

000110012 + 111100012 1 000010102 10/9/2012

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2’s Complement Arithmetic Example:

Determine the decimal value for the following 2’s complement numbers. a) 010101112 Based on the sign bit, 010101112 is a positive number. Therefore, = 1*26 + 1*24 + 1*22 + 1*21 + 1*20 = 64 + 16 + 4 + 2 + 1 = 8710 b) 110110102 Based on the sign bit, 110110102 is a negative number. Therefore, = -1*27 + 1*26 + 1*24 + 1*23 + 1*21 = -128 +64 + 16 + 8 + 2 = -3810 10/9/2012

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Subtractor Circuit • Subtraction A-B in the 2’s complement number system is performed as A  B  1 . • The 2’s complement is formed by the A1 B1 inverters on the B input and adding Cin = 1 to the LSB. The MSB (A4, B4 and S4) A2 is used for the sign bit and the B2 C4 output is not used. Cin= 1

Full Adder

Co

Cin

Full Adder

A4 A3 A2 A1 B4 B3 B2 B1  1 S4 S3 S2 S1

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Full Adder

Cin

A4 B4

Full Adder

S2

Co

Cin

A3 B3

S1

S3 Co

S4

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Adder-Subtractor Circuit • Adder-Subtractor circuit can perform either A1 addition or subtraction processes. B1 • It has one control input. • If the control input is 0, the circuit A2 B2 performs addition. A  B  0 where Cin=0. • If the control input is 1, it performs A3 subtraction. A  B  1 where Cin = 1. B3

Cin Full Adder

Co

Cin

Full Adder

S2 Co

Cin

Full Adder

Cin

A4 B4

S1

Full Adder

S3 Co

S4

Control

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