Chapter 7 Latches and FlipFlops Sequential Circuit Set-Reset Latch and Flip-Flop Data Latch and Flip-Flop JK Flip-Flop
Objectives • At the end of this chapter, students should be able to:– Differentiate between combinational and sequential circuit. – Distinguish between latch and flip-flop. – Describe the operation of Set-Reset Latch/Flip-flop, Data Latch/Flip-flop and JK Flip-Flop. – Draw the timing diagram for each flip-flop. – Explain the usage of D flip-flop in a simple calculator application.
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Logic Circuit • Two categories of logic circuits: Combinational Logic Circuit Sequential Logic Circuit
• Combinational logic circuit is a type of digital logic which is implemented by Boolean circuits, where the output is a pure function of the present input only. Input
Combinational Logic Gates
Ouput
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Logic Circuit • In sequential logic circuit, the output depends not only on the present input but also on the history of the input. Input
Combinational Logic Gates
Ouput
Memory
• In other words, sequential logic has memory while combinational logic does not.
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Data Storage • Two memory elements that have been used as data storage are latch and flip-flops. • Two types of latch are: SR Latch
D Latch
• Three types of flip-flops are:
SR Flip-flop
D Flip-flop
JK Flip-flop
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Set-Reset Latch Block Diagram S R
SR Latch
Truth table Q
Q
• Based on the following figure, draw the Q waveform for the SR latch. Assume that Q starts LOW.
Input
Output
S
R
Q
Mode
0
0
Q
Hold
0 1 1
1 0 1
0 1 -
Reset Set Invalid
TimingDiagram
Reset
Reset
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Set-Reset Flip-flop Block Diagram
Input
Truth table
CLOCK S
R
SET
CLR
Q
Q
Based on the following figure, draw the Q waveform for the SR flip-flop. Assume that Q starts LOW. CLK
TimingDiagram
1
2
3
Output
S
R
Q
Mode
0 0 1 1
0 1 0 1
Q 0 1 -
Hold
4
Reset Set
Invalid
5
6
7
8
Set
Set
Hold
Reset
S R Q Hold Set
Hold Reset
Output Q changes states (reacts) when the CLK changes from 0 to 1
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Data Latch Block Diagram
D E
Truth table
Input
Output
E
D
Q
Mode
Q
0
0
Q
Hold
1 0 1
Q 0 1
Hold
Q
0 1 1
Copy the value of D Copy the value of D
Based on the following figure, draw the Q waveform for the D latch. Assume that Q starts LOW. 1 2 3 4 TimingDiagram
E D Q
Output Q changes states immediately when D changes
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Data Flip-flop Block Diagram
D
SET
CLR
Truth table Input
Q
CLOCK
Q
Output
D
Q
Mode
0 1
0 1
Hold Reset
Based on the following figure, draw the Q waveform for the D flip-flop. Assume that Q starts LOW. TimingDiagram
CLK
1
2
3
4
D Q
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Application of D Flip-flop: Simple Calculator
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Application of D flip-flop: Simple Calculator
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JK Flip-flop Block Diagram
J
SET
Input
Truth table
CLOCK
Q
K CLR Q
Output
J
K
Q
Mode
0 0
0 1
Q 0
Hold
1 1
0 1
1 Q
Reset Set Toggle
Based on the following figure, draw the Q waveform for the JK flip-flop. Assume that Q starts LOW. TimingDiagram
CLK
1
2
3
4
Hold
Set
Hold
Reset Toggle Toggle Hold
5
6
7
8
J K Q Toggle 12