Hughes SRS IC Design by Sony

IEEE Transactions on Consumer Electronics, Vol. 37, No. 4, NOVEMBER 1991

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A NEW ANALOG SIGNAL PROCESSOR FOR A STEREO ENHANCEMENT SYSTEM Masaaki lshihara Sony Corporation Atsugi, Japan Kenji Komori, Atsushi Hirabayashi, Yoshimichi Maejima, Kyoichi Murakami Sony Corporation Tokyo, Japan Abstract A new single-chip analog signal processor IC for a stereo enhancement system has been developed, allowing the number of extemal components to be reduced.

Introduction Home TV sets, VCRs and Video Disc Players equipped with MTS (Multi-channel Television Sound) decoders are proving popular because their picture quality has recently been greatly improved. Under these circumstances, the application of a sound field system is desirable. SRS (Sound Retrieval System), developed by Hughes Aircraft Company, is most suitable for this purpose. This paper describes the development of a new SRS analog signal processing IC.

Principle of SRS The block diagram of SRS is shown in Fig. 1.

The input signal of the left and right channel is fed to the splitter block. The difference component (L-R) and the sum component (L+R) of the input signal are formed by the splitter. The L-R servo control block then processes the signal level of L R and R-L, with the appropriate filtering and the gain control. The processed signals are called (L-R)PL and (R-L)PR. The level of the signal (L-R)PL is

controlled by the L+R signal and the left channel input signal. In like manner, the level of the (R-L)PR signal is controlled by the L+R signal and the right channel input signal. So the signal level of (L-R)PL and (R-L)PR are independently controlled in response to the left channel and the right channel input signal, respectively. Next, the L+R servo control block processes the signal level of the L+R signal, in reference to the L-R servo control. The processed signal is called (L+R)PD. The (L+R)PD signal level increases simultaneously with the increase of the L-R and R-L signal. The level of the (L-R)PL and (R-L)PR signal is controlled in the space control block. Also, the level of the (L+R)PD signal is controlled in the center control block.

Finally, the left channel output signal is obtained by the mixer block, through summing the original left channel signal, the processed L-R signal and the processed L+R signal. h the same way, the right channel output signal is obtained by the mixer block, through summing the original right channel signal, the processed R-L signal and the prFessed L+R signal.

The processed L-R and R-L signal is used to extract the ambience and spatial characteristics of the sound source.

The processed L+R signal is used for the extraction of dialog and the voice of soloists, which should be localized in the center.

It is well known that the human hearing spectral response varies with the location of the sound source, and

Fig. 1 Block Diagram of SRS

Manuscript received September 1 1 , 1991

0098 3063/91 $01.00

1991 IEEE

Ishihara et al.: A New Analog Signal Processor for a Stereo Enhancement System the perception of direction depends on the hearing spectral response. In the SRS circuit, the frequency response of the (L-R)PL and (R-L)PR signal is determined so that the transfer function of human hearing described below is effectively exploited. There is a frequency band that makes a harsh sound on the ear, and a band that causes a shift of the sound image when the listener moves his head.

The (L-R)PL and (R-L)PR signal in the vicinity of such frequency bands are attenuated in the SRS circuit. Good localization can be obtained, therefore, in the wide listening area.

AdvantaEes of SRS In comparison with conventional stereo enhancement systems, SRS has the following advantages :

The servo circuit operates in the following way. As the amplitude ratio of input 2 / input 1 increases, the input current of the integrator changes, which changes the control voltage of the VCA (the output voltage of the limiter), which results in the increase of the VCA's gain. During this operation, the absolute value of the input current of the integrator decreases. Finally, the input current of the integrator converges to zero, the output voltage of the integrator keeps the same value, and the gain of the VCA is determined. In this manner, the servo circuit controls the amplitude ratio (output / input 2) so that the ratio becomes equal to the a1 / a2 ratio.

A typical relationship between the gain and the signal amplitude ratio (input 2 / input 1) in the servo circuit is shown in Fig.3.

1. Stereo sound with a three-dimensional ambience can be obtained with only two speakers.

GALN

2. A wide optimum listening area is created.

3. A realistic sound image (including the sound localized in the center) is maintained regardless of the apparent position of the sound source.

I

mal-

-

/--

- - - -

4. Specific encoding is not required.

5. Digituanalog delay, artificial phase correction, or harmonics regeneration is not required.

INPUT2 INPUT 1

Servo Control Circuit The block diagram of the new IC's servo circuit is shown in Fig.2.

Peak detector 1 and peak detector 2 detects the amplitude of the signal at the output and input 2 terminal, respectively.

These two peak detectors have the opposite polarity. "al" and "a2" are the coefficients which transform the output voltage of peak detector 1 and peak detector 2 into the input current of the integrator. The output voltage of the integrator is held between a minimum and maximum value by the limiter. The gain of the VCA is controlled by the output voltage of the limiter.

Fig. 3 Gain Control Characteristic of Servo Circuit

The frequency response of (L-R)PL, (R-L)PR and (L+R)PD is formed by filters positioned in the input section of servo circuits. The actual level of the input signal changes as the signal frequency changes. Therefore, an e m r in the servo circuit operation results in an error of gain and frequency response as well --- the accuracy of the SRS circuit operation mainly depends on the accuracy of the servo circuit.

INPUT1 0

I

ONIOFF CONTROL

INTEGRATOR

INPUT2

I

DETECTOR 1

DETECTOR 2 I

I

Fig. 2 Block Diagram of Servo Circuit

n

IEEE Transactions on Consumer Electronics, Vol. 37, No. 4, NOVEMBER 1991

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We introduced the following new approaches to the design of this IC, in order to maintain error-less operation : 1. We used an analog switch circuit which achieves high

precision without an FET.

2. We used a combination of peak detectors and an operational ampUier.

3. We used a simplified method for canceling the temperature coefficient of the VCA's gain-control sensitivity.

4. We used a VCA circuit which achieves less DC offset and an equal pedormance in the inverting and noninverting operation.

The bias current I, and I, is switched by the current switches composed of (Q,,Q,) and (a3,%) pair. When Q1 and Q3 are turned off and Q2 and Q4 are turned on, the circuit operates as a buffer amplifer. When Q1 and Q3 arc turned on and Q2 and Q4 are turned off, no bias current is supplied to the amplifier section and the output terminal of the circuit becomes open (the high impedance state).

Pgand R3 are added to avoid the offset voltage caused by the diffmnce of Q i s Vce and Qs's Vce. As a result, the accuracy of the integrator input current is maintained without an E T . vsc

Analog Switches

As noted above, the VCA's gain is determined by the output voltage of the integrator, and the output voltage of the integrator changes with the change of its input current.

In the SRS. there is a condition that the VCA's gain must keep the same value, and the operation is realized by cutting off the input current of the integrator. Conventionally, the cut off has been realized by utilizing a CMOS analog switch as a discrete component. If we use a bipolar process to make the circuit, however, we can keep the cost low. In this IC, the switching function is realized by replacing the analog switch with the on / off buffer ampwier.

In order to utilize these buffer amplifiers, we have modified the block diagram of the servo circuit. The modified block diagram of the circuit is shown in Fig.4.

While buffer amplifiers are in the "on" state, two buffer amplifiers operate as unity gain buffers. In this state, the output voltage of the two peak detectors are converted into the current I, and I, respectively, and these currents flow into the integrator. When the buffer amplifiers are in the "off' state. I1 and I, become zero, and the output terminals of the buffer amplifiers are altered to a high impedance state, with the result that no current flows into the integrator.

The circuit of the buffer is shown in FigS.

---O

lNPUl

OFF

ON

Fig. 5 Buffer Circuit with Switch Function

I I

I

I

1

1 1

DETECTOR 1 ON I OFF CONTROL 0

t

I

I1

-1

POSITIVE PEAK DETECTOR 2

I

Fig. 4 Modified Block Diagram of Servo Circuit

OUTPUT

Ishihara et al.: A New Analog Signal Processor for a Stereo Enhancement System

Peak Detector The SRS circuit employs positive peak detectors and negative peak detectors. In an integrated circuit, a pair of peak detectors which makes a complementary circuit has a disadvantage. Generally, device parameters such as hfe, Vbe, Early voltage and parasitic capacitance are different in NPN and PNP transistors in the integrated circuit.

Furthermore, these parameters change independently in NPN and PNP transistors. Therefore, composing positive peak detectors and the negative peak detectors by utilizing the complementary circuits is not a good idea, because the error of the positive peak detector and the negative peak detector change independently, so it is not easy to cancel the error.

We adopted two positive peak detectors and an unitygain inverting amplifier as shown in Fig.4, instead of the Complementary peak detector circuit. If the error of peak detector 1 change concurrently with the change of device parameters, temperature, and/or supply voltage, the error of peak detector 2 change at the same rate. In addition to that, R I is set equal to R 2 in this IC. Therefore, the error of I, and I, is equal. As a result, the input-to-output relationship of the servo circuit is not influenced by the error of peak detectors. The coefficient a l , a2 was replaced with the attenuators inserted in front of each peak detector.

The peak detector and the inverting amplifier were designed with the assistance of circuit simulator CAD so that the offset voltage between input and output becomes insignificant.

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The peak detector circuit is shown in Fig.6. The output voltage of the output buffer stage is fed to the reference input (the base terminal of Q2) of the comparator stage in order to eliminate output buffer's offset voltage.

Servo Gain Limiter Generally, a VCA requires a temperature-dependent control voltage in order to obtain constant gain regardless of the temperature, because the VCAs gain-control is realized using the ratio of the two output current of a differential amplifer. In consequence the gain-control sensitivity changes in inverse proportion to the absolute temperature.

In the SRS circuit, the minimum and maximum value of the VCA's gain is used to regulate the servo-control range.

Therefore, an appropriate measure should be taken to cancel the temperature coefficient of the VCA's gain-control sensitivity. A simple method is to cancel the temperature coefficient itself by employing a compensation circuit in the VCA. Another approach is to change the limit voltage in proportion to the absolute temperature, as described below.

If the limit voltage of the limiter changes in proportion to the absolute temperature, the temperature coefficient of the VCAs gain-control sensitivity and the limit voltage is essentially canceled, and in consequence the minimum and maximum gain of the VCA does not change.

We applied the simple method to change the limit voltage by the absolute temperature in the following way. The principle of the limit voltage generator is shown in Fig.7.

vcc

OUTPUT

INPUT

Fig. 6 Peak Detector Circuit

IEEE Transactions on Consumer Electronics, Vol. 37, No. 4, NOVEMBER 1991

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0

VGC

T

111

&-

VCA Circuit

1

In the servo circuit, the gain of the VCA changes every moment with the change of the amplitude of the input signal. The dynamic offset of the VCA affects both the sound quality and dynamic range of the circuit. The quiescent offset also has an influence on the dynamic range.

Figure 9 shows the outline of the VCA circuit which is used in this IC. An example of the conventional VCA circuit is shown in Fig.10. The major advantages of the Fig.9 circuit compared with the Fig.10 circuit are as follows :

REFER ENC E OUTPUT

1. Dynamic and quiescent offset is reduced by adding

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2. Equal performance can be obtained in both the inverting and non-inverting operations.

Fig. 7 Limit VoItage Generator The current I, is given by 2 (l/R1) (kT/q) (In N)

. 12

changes in proportion to the absolute temperature, because I2 is derived from Il. For this reason, assuming that the temperature coefficients of R, and R, are equal, V, changes in proportion to the absolute temperature.

The entire circuit of the limit voltage generator is shown in Fig.8. The advantage of this circuit is that an increase in the circuit scale and the power consumption, which results from applying the limit voltage regulator, is small because a band gap reference circuit already exists in the circuit.

This method enables us to maintain the minimum and maximum value of the VCA gain regardless of the temperature, with high stability, simple circuit and small power consumption.

BAND GRP REFERENCE

OUTPUT

OB2 02

2v

: 2

Fig. 8 Limit Voltage Generator Circuit

The first advantage of this circuit is explained below.

The offset voltage is mainly caused by the difference between Ql's Vce and Q ~ Vce, s except the difference between Ql's Vbe and Q i s Vbe. However, in the Fig.9 circuit, an addition of transistor Q3 and the diode D3 makes the Vce of Q, and Q, equal, and an increase of the offset voltage is avoided.

The second advantage of this VCA circuit is described as follows. In the SRS circuit, a phase-inverting operation is required in the L-R Servo Control block, because the polarity of (R-L)PR is opposite to the L-R signal. Equal performance is needed to obtain left and right channel signals of equal quality. There are two approaches to the realization of the phase-inverting operation. The first approach is to combine a non-inverting VCA and an inverting amplifier, and the second approach is using an inverting VCA. The combination of the non-inverting VCA and the inverting amplifier has been used in the conventional design. However, the additional amplifier causes a gain error and an increase of power consumption.

The conventional circuit can be used in the inverting operation by modifying the circuit as shown in Fig.11.

However, the inverting operation in Fig.11 is not suitable for our purpose, because the quiescent and dynamic offset becomes large compared with the non-inverting operation.

We selected the second approach with applying the Fig.9 circuit. Equal gain and offset performance can be obtained in the inverting and non-inverting operation, because it is the balanced circuit. The inverting amplifier is not required, which results in a better gain match between left and right channels.

Consequently, the reduction of offset voltage, the equal signal quality and improved gain matching between left and right channel, and the simplification of the circuit are achieved in the VCA section.

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Ishihara et al.: A New Analog Signal Processor for a Stereo Enhancement System VSS

NON-INVERTING INPUT INVERTING

OUTPUT

INPUT

CONT

Fig. 9 VC.4 Circuit

VCC

*OUTPUT NON-INVERTING INPUT

Fig. 10 Example of Unbalanced VCA Circuit (Non-Inverting Operation)

OUTPUT

Fig. 11 Example of Unbalanced VCA Circuit (Inverting Operation)

IEEE Transactions on Consumer Electronics, Vol. 37, No. 4, NOVEMBER 1991

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Synthetic Stereo Circuit The SRS demonstrates its ability when the input signal is stereophonic. However, when the input signal is completely monaural, the difference signal L-R disappears, and stereo-enhanced sound is not derived, To maintain an illusion of stereo sound in such a case, SST (Stereo Synthesis Techniques) has been developed concurrently with SRS. Figure 12 shows the block diagram of SST. The system is basically composed of two phase shifters, a filter, and mixers. The phase difference between output signal of the phase shifter 1 and the phase shifter 2 is set at 90 degrees. The output signal of phase shifter 2 is fed to the filter in order to form the frequency response which is most effective on the transfer function of human hearing. Finally,

the synthesized left and right signals are brought by mixers through summing the output signal of phase shifter 1 and the filter. The SST circuits are also integrated in the IC.

The Configuration of the IC Figure 13 shows the block diagram of the IC. The splitter, the L-R servo control, the L+R servo control, the phase shifter 1 and 2, and the filter block are integrated in a single chip. Mixers for SRS and SST are placed outside the IC, in order to obtain a high maximum signal handling level. The IC is packed in the @pin SDIP (Shrink DIP)and QFP (Quad Flat Package). The mask pattem of the chip is shown in Fig.14. 2500 elements are integrated in a space .

3.96" x 4.97"

PHASE SHIFTER 1

-

OEUT

+

PHASE SHIFTER 2

Fig. 12 Block Diagram of SST

LEFT

m RIGHT INPUT

Fig. 13 Block Diagram of the IC

RIGHT

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Ishihara et al.: A New Analog Signal Processor for a Stereo Enhancement System

Biographies

Masaaki Ishihara received his B.E. in Electrical Engineering from Waseda University, Tokyo, in 1982. In 1982, he joined Sony Corporation,. where he has been engaged in the Bipolar Div.

Fig. 14 Mask Pattem of the IC

Kenji Komori received his B.E. in Electronic Engineering from Doshisha Universitv. Kvoto, in 1987. In 1987, he joined Soiy C&poration,where he has been engaged in the TV Display Development Div.

Conclusion A single-chip stereo enhancement system IC has been developed. The IC achieves good performance, as is shown in Table I. Also, we've managed to reduce the number of external components by 46%, as well as the area and cost.

Atsushi Hirabayashi received his B.E. in Electrical Engineering from Scienceuniversity of Tokyo, in 1981.

In 1981, he joined Sony Corporation, where he has been engaged in the TV Display Development Div.

Performance of the IC 8 to13 V 34 mA (typ.)

Table I Supply Voltage Supply Cumnt SRS overall gain error

within k2.0 dB

SRS max. input level (lkHz,THD=3%)

13.5 dB (typ.) above ref. level*

SRS THD+N ( lldlz)

0.05 % (typ.)

SRS S/N ratio ( IHF-A weighted)

Yoshimichi Maejima received his B.E. in Electronic Engineering from Tokyo Denki University, Tokyo, in 1969. In 1973, he joined Sony Corporation, where he has been engaged in designing audio amplifiers.

84 dB (typ.)

*ref.leveI = 500 mVrms

Acknowledgement The authors wish to express appreciation to A. Klayman, S. Gates, J. Olshefski for their technical suggestions, M. Nagami for his support and estimates, M. Katakura for his technical suggestion, and K. Abe and I. Hata for their support through the project.

References Len Feldman "Beyond Stereo" Radio Electronics Magazine, September 1989

Kyoichi Murakami received his M.E. in Nuclear Physics from Tokyo Institute of Technology, in 1970.

In 1970, he joined Sony Corporation, where he has been engaged in television research and development. He is a member of the B E .