LPC2148 Instruction Set by Dr.R.Theagarajan

ARM â&#x20AC;&#x201C; LPC2148 Instructions

R. Theagarajan. ME., MSc., PhD Rtd. Professor in Engineering email: rtheagarajan@yahoo.com rtrajan59@gmail.com

Instruction Set 6 groups      

Data processing instructions Arithmetic & Logic instructions Branching instructions Load & Store instructions Software interrupt instructions Other instructions

Instruction Format ARM instructions commonly take two or three operands

Instruction Syntax

Destination Register

Source Register2

Source Register1

ADD r3, r2, r1

ADD{cond} r5, r4, r3

Condition codes {cond} Suffix EQ NE

Tested Status Flags Z set Z clear

Description equal not equal

CS/HS

C set

unsigned higher or same

CC/LO MI PL VS VC HI

C clear N set N clear V set V clear C set and Z clear

unsigned lower negative positive or zero overflow no overflow unsigned higher

C clear or Z set

unsigned lower or same

N equals V

signed greater or equal

N not equal to V

signed less than

Z clear AND (N equals V)

signed greater than

Z set OR (N not equal to V)

signed less than or equal

(ignored)

always (usually omitted)

Operating modes Mode 10000 10001 10010 10011 10111 11011 11111

Description User mode Fast Interrupt mode Interrupt mode Supervisor mode Abort mode Undefined mode System mode

Registers

Processor Status Register

Shift types Logical Shift Right (LSR)

shift right the content of specified register by 1 time and load it in destination register. D0 is shifted into C flag. D1 is shifted into D0 bit position. Similarly other bits occupies the previous bit position. Zero occupies the D31 bit position as MSB.

Shift types Logical Shift Left (LSL)

shift left the content of specified register by 1 time and load it in destination register. D31 is shifted into C flag. D30 is shifted into D31 bit position. Similarly other bits occupies the next bit position. Zero occupies the D0 bit position as LSB.

Shift types Arithmetic Shift Right (ASR)

Arithmetic shift right the content of specified register by 1 time and load it in destination register. D0 is shifted into C flag. D1 is shifted into D0 bit position. Similarly other bits occupies the previous bit position. D31 bit value copies into D31 bit position as MSB.

Shift types Rotate Right (ROR)

Rotate right the content of specified register by 1 time and load it in destination register. D0 is shifted into C flag and D31 bit position. D1 is shifted into D0 bit position. D2 is shifted into D1 position. Similarly other bits occupies the previous bit position.

Shift types Rotate Right Extended (RRX)

Rotate right the content of specified register by 1 time through C flag and load it in destination register. D0 is shifted into C flag. D1 is shifted into D0 bit position. Similarly other bits occupies the previous bit position. C flag content occupies the D31 bit position as MSB.

MOVE Move the source operand to destination MOV Rd, <operand> MOV r2, r3 ; move or copy r3 content into r2 MOV r5, #0x20 ; load r5 with the given constant 0x20 MOV r4, r5, SHL #4 ; shift left the content of r5 by 4 times and load it in r4

Flags : N, Z, C

MOVE Move the source operand to destination MVN Rd, <operand> MVN r3, r6

; performs a bitwise logical NOT on the value of r6 ; and then the result is moved into r3.

MOV r3, ~r6

; Tilt symbol does the logical NOT operation on the ; value of r6 and then moved into r3

Flags : N, Z, C

MOVE Move the source operand to destination MRS Rd, CPSR ; Current PSR to register MRS r4, cpsr

; Move the content of the CPSR to a ; general-purpose register r4

MRS r5, spsr

; Move the content of the SPSR to a ; general-purpose register r5

Flags : N, Z, C SPSR cannot be accessed when the ARM processor is in user or system mode.

MOVE Move the source operand to destination MSR CPSR_<fields>, Rm ; selected bytes only MSR CPSR_<fields>, #<imed_8> ; immediate

Load fields of the Program Status Register with an immediate constant or register content

Flags : N, Z, C

MOVE Move the source operand to destination

MSR SPSR_<fields>, Rm ; selected bytes only MSR SPSR_<fields>, #<imed_8> ; immediate Load fields of the Program Status Register with an immediate constant or register content

Flags : N, Z, C

ARITHMETIC ADDITION ADD Rd, Rn, <operand> Rd = Rn + operand ADD r0, r2, r4 ADDS r5, r4, #0xFE

Flags : N, Z, C, V

; add r2 & r4 and store to register r0 ; add value of 0xFF00 & r4 and store in r5

ARITHMETIC ADDITION ADC Rd, Rn, <operand> Rd = Rn + operand + C ADDS r0, r2, r4 ADC r1, r3, r5

Flags : N, Z, C, V

; add R2 & R4, store result to r0, set flags ; add R3 &R5 with carry , store into r1

ARITHMETIC SUBTRACTION subtracts the value of Op from the value in Rn.

SUB Rd, Rn, <operand>

;

Rd = Rn – operand

SUB r8, r6, #135

; r8 = r6 – 135

SUBS r7, r5, #246

; r7 = r5 – 246

Flags : N, Z, C, V

ARITHMETIC SUBTRACTION subtracts the value of Op and Carry from the value in Rn.

SBC Rd, Rn, <operand> SBC r7, r5, r4

Flags : N, Z, C, V

;

Rd = Rn – operand – C

; r7 = r5 – r4 – C

ARITHMETIC SUBTRACTION

RSB Rd, Rn, <operand>

;

Rd = operand â&#x20AC;&#x201C; Rn

subtracts the content of Rn from the value of Operand RSB r5, r4, #1280

Flags : N, Z, C, V

; subtracts contents of r4 from 1280 ; and the result is transferred into r5

ARITHMETIC SUBTRACTION

RSC Rd, Rn, <operand>

;

Rd = operand – Rn – C

subtracts the value of Rn and Carry flag from the content of Operand. RSC r5, r4, #1234

Flags : N, Z, C, V

; r5 = 1234 – r4 – C

ARITHMETIC MULTIPLY

MUL Rd, Rm, Rs

;

Rd = (Rm * Rs)

Multiplies the values of Rm and Rs, and places the least significant 32 bits of the result in Rd.

MUL r10, r2, r5 MUL r9, r5, #0x56

Flags : N, Z, C, V

; r10 = r2 * r5 ; r9 = r5 * 0x56

ARITHMETIC MULTIPLY Multiply-accumulate

MLA Rd, Rm, Rs, Rn

;

Rd = (Rm * Rs) + Rn

Multiplies the values of Rm and Rs, adds the value of Rn, and places the least significant 32 bits of the result in Rd. MLA r7, r1, r3, r5 MLA r9, r4, r6, #0x59

Flags : N, Z, C, V

; r7 = (r1 * r3) + r5 ; r9 = (r4 * r6) + 0x59

ARITHMETIC COUNT LEADING ZEROS

CLZ Rd, Rm

;

number of leading zeros

Rd = number of leading zeroes in Rm ; If r4 contains 29 leading zero, then CLZ r1, r4 ; the register r1 is loaded with 29

Flags :

not modified

LOGICAL AND Rd, Rn, <operand>

;

Bit by bit and operation

Rd = Rn .AND. operand AND r9, r2, #0xF0 r2 = 0011 0011 Immediate value = 1111 0000 Result = 0011 0000

Flags : N, Z, C

; Content of r2 anded with value FF00h

; Result is transferred into register r9

LOGICAL ORR Rd, Rn, <operand>

;

Bit by bit OR operation

Rd = Rn .OR. Operand ORR r2, r0, r5 Content of r5 Content of r0 Result

= 0011 0011 = 1010 0101 = 1011 0111

Flags : N, Z, C

; content of r0 is ored with content of r5

; Result is transferred into register r2

LOGICAL EOR Rd, Rn, <operand>

;

Bit by bit EXOR operation

Rd = Rn .EOR. Operand EOR r5, r0, r3, ROR r6

Flags : N, Z, C

; content of r3 is rotate right by r6 times ; and exored with content of register r0 ; and then result is transferred into register r5

LOGICAL BIC Rd, Rn, <operand>

;

Bit clear

Rd = Rn .AND-NOT. Operand

Performs an AND operation on the bits of Rn with the complements of the corresponding bits available in operand.

BIC r0, r 0, #0x1F MOV CPSR, R0

Flags : N, Z, C

; it clears the mode bits available in CPSR

LOGICAL NOP no operation Registers content remain same Flags not affected.

;

LOGICAL TST Rn, <operand>

;

Test

updates CPSR flags on Rn .AND. Operand Performs a bitwise AND operation on the value of Rn and the value of Op.

This is similar to the ANDS instruction, except that the result is discarded.

Flags : N, Z, C

LOGICAL TEQ Rn, <operand>

;

Test equivalence

update CPSR flags on Rn .EOR. Operand2 Bitwise Exclusive OR operation, result is discarded. Used for conditional operations afterwards. TEQS r4, #3

Flags : N, Z, C

; Test R4 for equality with data 3

COMPARE CMP Rn, <operand>

;

Compare

update CPSR flags on Rn - operand Subtracts the value of Operand from the value of Rn (equals to the SUBS instruction with a discarded result). This instruction updates the condition flags, but do not place the result in register

Flags : N, Z, C, V

COMPARE CMN Rn, <operand>

;

Compare negated register

update CPSR flags on Rn + operand Add the value of Op to the value in Rn.

This instruction updates the condition flags, but do not place the result in register

Flags : N, Z, C, V

BRANCH B Label

;

R15 = Label

The jump distance must be within -252 to +258 bytes for conditional and ±2 KBytes for unconditional branch

Top2: Top1:

CMP r1, #10 BEQ Top1 B Top2 ……………… ………………

; compare r1 with #10 ; jump to label Top1 ; jump to itself

BRANCH BL Label

;

Branch with Link

R15 = Label, R14 = R15-4 Copy address of next instruction to R14 and jump to label.

The jump distance must be within Âą4Mb of the current instruction. Note that this mnemonic is generated as two 16-bit Thumb instructions

BRANCH BX Rm

;

Branch and exchange

R15 = Rm, change to Thumb if Rm(0) is 1 Branch indirect and switch CPU mode (Thumb / ARM) as required

Branch to address in Rm. Change to ARM mode if bit 0 of Rm is clear. BX r5

; branch indirect to address function

BRANCH BLX Label R15 = Label, R14 = R15-4 Cannot be conditional

;

Branch with Link & exchange

LOAD Load 32 bit word from memory LDR{cond} Rd, [Rn] Rn is used to hold memory address like a pointer.

LOAD Load 32 bit word from memory LDR{cond} Rd, [Rn] Rn is used to hold memory address like a pointer. LDR{cond} Rd, [Rn, offset] (Pre-indexed offset) Rn and offset are added and used as address value. LDR{cond} Rd, [Rn, offset]! (Pre-indexed offset with update) Rn and offset are added and used as address value. The new address value is written to Rn. LDR{cond} Rd, label (Program-relative) The assembler calculates the PC offset and generates

LOAD Load register byte value from memory LDR{cond}B Rd, [Rn] Rn is used as address value. LDR{cond}B Rd, [Rn, offset] (Pre-indexed offset) Rn and offset are added and used as address value. LDR{cond}B Rd, [Rn, offset]! (Pre-indexed offset with update) Rn and offset are added and used as address value. The new address value is written to Rn. LDR{cond}B Rd, label (Program-relative) The assembler calculates the PC offset and generates LDR{cond}B Rd, [Rn], offset (Post-indexed offset) Rn is used as address value. After memory transfer, the offset is added to Rn.

LOAD Load register 16 bit half-word value from memory LDR{cond}H Rd, [Rn] Rn is used as address value. LDR{cond}H Rd, [Rn, offset] (Pre-indexed offset) Rn and offset are added and used as address value. LDR{cond}H Rd, [Rn, offset]! (Pre-indexed offset with update) Rn and offset are added and used as address value. The new address value is written to Rn. LDR{cond}H Rd, label (Program-relative) The assembler calculates the PC offset and generates LDR{cond}H Rd, [Rn], offset (Post-indexed offset) Rn is used as address value. After memory transfer, the offset is added to Rn.

LOAD Load register signed byte value from memory LDR{cond}SB Rd, [Rn] Rn is used as address value. LDR{cond}SB Rd, [Rn, offset] (Pre-indexed offset) Rn and offset are added and used as address value. LDR{cond}SB Rd, [Rn, offset]! (Pre-indexed offset with update) Rn and offset are added and used as address value. The new address value is written to Rn. LDR{cond}SB Rd, label (Program-relative) The assembler calculates the PC offset and generates LDR{cond}SB Rd, [Rn], offset (Post-indexed offset) Rn is used as address value. After memory transfer, the offset is added to Rn.

LOAD Load register signed 16 bit half-word from memory LDR{cond}SH Rd, [Rn] Rn is used as address value. LDR{cond}SH Rd, [Rn, offset] (Pre-indexed offset) Rn and offset are added and used as address value. LDR{cond}SH Rd, [Rn, offset]! (Pre-indexed offset with update) Rn and offset are added and used as address value. The new address value is written to Rn. LDR{cond}SH Rd, label (Program-relative) The assembler calculates the PC offset and generates LDR{cond}SH Rd, [Rn], offset (Post-indexed offset) Rn is used as address value. After memory transfer, the offset is added to Rn.

LOAD multiple registers from memory LDM{cond}mode Rn{!}, reglist{^} Load list of registers from [Rn] Loads any subset of the currently visible registers. This instruction supports all possible stacking modes, maintaining full or empty stacks which can grow up or down memory,. They are very efficient instructions for saving or restoring context, or for moving large blocks of data around main memory.

STORE Store 32 bit word to memory STR{cond} Rd, [Rn] Rn is used to hold the memory address.

STORE Store 32 bit word to memory STR{cond} Rd, [Rn] Rn is used to hold the memory address. STR{cond} Rd, [Rn, offset] (Pre-indexed offset) Rn and offset are added and used as memory address.

STORE Store 32 bit word to memory STR{cond} Rd, [Rn] Rn is used to hold the memory address. STR{cond} Rd, [Rn, offset] (Pre-indexed offset) Rn and offset are added and used as memory address. STR{cond} Rd, [Rn, offset]! (Pre-indexed offset with update) Rn and offset are added and used as memory address. The new address value is written to Rn. STR{cond} Rd, label (Program-relative) The assembler calculates the offset address for label with current address

STORE Store register byte value to memory STR{cond}B Rd, [Rn] Rn is used as address value. STR{cond}B Rd, [Rn, offset] (Pre-indexed offset) Rn and offset are added and used as address value. STR{cond}B Rd, [Rn, offset]! (Pre-indexed offset with update) Rn and offset are added and used as address value. The new address value is written to Rn. STR{cond}B Rd, label (Program-relative) The assembler calculates the PC offset and generates STR{cond}B Rd, [Rn], offset (Post-indexed offset) Rn is used as address value. After memory transfer, the offset is added to Rn.

STORE Store register 16 bit half-word value to memory STR{cond}H Rd, [Rn] Rn is used as address value. STR{cond}H Rd, [Rn, offset] (Pre-indexed offset) Rn and offset are added and used as address value. STR{cond}H Rd, [Rn, offset]! (Pre-indexed offset with update) Rn and offset are added and used as address value. The new address value is written to Rn. STR{cond}H Rd, label (Program-relative) The assembler calculates the PC offset and generates STR{cond}H Rd, [Rn], offset (Post-indexed offset) Rn is used as address value. After memory transfer, the offset is added to Rn.

STORE multiple registers to memory STM{cond}mode Rn{!}, reglist{^} Store list of registers to [Rn] Stores any subset of the currently visible registers. This instruction supports all possible stacking modes, maintaining full or empty stacks which can grow up or down memory,. They are very efficient instructions for saving or restoring context, or for moving large blocks of data around main memory.

SWAP Swap 32 bit word between register and memory

SWP{cond}

Rd, Rm, [Rn]

temp = [Rn],

SWP R2, R3, [R4] CMP R0, #55H SWPEQ R0, R0, [R1]

[Rn] = Rm,

Rd = temp

; Load R2 with 32-bit word at address in R4 and ; store R3 to this memory location ; Compare R0 with 0x55, if equal ; exchange memory content at address R1 with R0

SWAP Swap a byte between register and memory

SWP{cond}B temp = [Rn],

SWPB R2, R3, [R4] CMP R0, #55H SWPEQ R0, R0, [R1]

Rd, Rm, [Rn] [Rn] = Rm,

Rd = temp

; Load R2 with 32-bit word at address in R4 and ; store R3 to this memory location ; Compare R0 with 0x55, if equal ; exchange memory content at address R1 with R0

Software Interrupt SWI <imed_24> Software interrupt processor exception

Change to supervisor mode, the CPSR is saved to the supervisor mode SPSR, branches to the SWI vector. The imm24 value can be in the range 0 - 255 and may be used to invoke different operating system functions. Condition Flags are not modified.

SWI 0x15

; execute software interrupt #0x12

Software Interrupt Breakpoint BKPT <imed_16> Pre-fetch abort or enter debug state

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