MSP432P401R-Architecture by Dr.R.Theagarajan

MSP432P401R Architecture

Compiled by R. Theagarajan. ME., MSc., PhD Rtd. Professor in Engineering email: rtheagarajan@yahoo.com

Texas Instruments naming -

Applications • Industrial automation – – – – – – –

Glass breakage detectors Smart thermostats Access panels Gas monitors Field transmitters Process automation Home automation

Applications • – – –

Metering Flow meters Electric meters Communication modules

• – – –

Test and measurement Digital multi-meters Wireless digital multi-meters Contactless and hand-held digital meters

Applications • – – – –

Health and fitness Watches Activity monitors Fitness accessories Blood glucose meters

• Consumer electronics – Mobile devices – Sensor hubs

Features • Core – ARM 32-bit Cortex-M4F CPU with floating-point unit and memory protection unit – Frequency up to 48 MHz – ULPBench™ benchmark : 192.3 ULPMark-CP – Performance benchmark : 3.41 CoreMark / MHz 1.22 DMIPS / MHz

Features • Advanced low-power analog features – SAR analog-to-digital converter (ADC) with 16-bit precision and up to 1 Msps – Differential and single-ended inputs – Two analog comparators – Two window comparators – Up to 24 input channels – Internal voltage reference with 10-ppm/°C

Features • Memories – Up to 256KB of flash main memory (organized into two banks enabling simultaneous read/execute during erase) – 16KB of flash information memory (used for BSL, TLV, and flash mailbox) – Up to 64KB of SRAM (including 6KB of backup memory) – 32KB of ROM with peripheral driver libraries • Ultra-low-power operating modes – Active: 80 μA/MHz – Low-frequency active: 83 μA at 128 kHz

Features • Flexible clocking features – – – – – – –

Tunable internal DCO (up to 48 MHz) 32.768-kHz low-frequency crystal support (LFXT) High-frequency crystal support (HFXT) up to 48 MHz Low-frequency internal reference oscillator (REFO) Very low-power low-frequency internal oscillator (VLO) Module oscillator (MODOSC) System oscillator (SYSOSC)

Features • Code security features – JTAG and SWD lock – IP protection (up to four secure flash zones, each with configurable start address and size) • Enhanced system features – Programmable supervision and monitoring of supply voltage – Multiple-class resets for better control of application and debug – 8-channel DMA – RTC with calendar and alarm functions

Features • Timing and control – Up to four 16-bit timers, each with up to five capture, compare, PWM capability – Two 32-bit timers, each with interrupt generation capability • – – – – – – –

Serial communication Up to four eUSCI_A modules UART with automatic baud-rate detection IrDA encode and decode SPI (up to 16 Mbps) Up to four eUSCI_B modules I2C (with multiple-slave addressing) SPI (up to 16 Mbps)

Features • Flexible I/O features – – – – –

Ultra-low-leakage I/Os (±20 nA maximum) All I/Os with capacitive-touch capability Up to 48 I/Os with interrupt and wake-up capability Up to 24 I/Os with port mapping capability Eight I/Os with glitch filtering capability

Features • Development kits and software – MSP-EXP432P401R LaunchPad™ Development Kit – MSP-TS432PZ100 100-Pin Target Board – SimpleLink™ MSP432 Software Development Kit (SDK)

• Operating characteristics – Wide supply voltage range: 1.62 V to 3.7 V – Temperature range (ambient): –40°C to 85°C

Features • Encryption and data integrity accelerators – 128-, 192-, or 256-bit AES encryption and decryption accelerator – 32-bit hardware CRC engine

100 Pin diagram - PZ package

MSP432P401R

64 Pin diagram - RGC package

MSP432P401R

Functional block Diagram -

CPU

CPU -

Functional block Diagram -

Bus Control Logic

Functional block Diagram -

Address Bus

Functional block Diagram -

Data Bus

Functional block Diagram -

Flash

128, 256 KB

Functional block Diagram -

SRAM

32, 64 KB

Functional block Diagram -

ROM

32, 64 KB

Functional block Diagram -

8 channels

DMA

Memory map -

Supports 4 GB It is divided into eight 512MB zones

Code Memory map -

It is accessible through the ICODE and DCODE buses of the processor and through the system DMA. This region maps the flash 4MB, the ROM and SRAM 1MB each

Signal descriptions -

Port 1 - 8 pins, General purpose digital I/O with port interrupt, wake-up capability, filtering

Signal descriptions -

Port 2 - 8 pins, General purpose digital I/O with port interrupt, wake-up capability, Re-configurable high drive upto 20mA

Signal descriptions -

Port 3 - 8 pins, General purpose digital I/O with port interrupt, wake-up capability, Re-configurable for secondary functions

Signal descriptions -

Port 4 - 8 pins, General purpose digital I/O with port interrupt, wake-up capability

Signal descriptions -

Port 5 - 8 pins, General purpose digital I/O with port interrupt, wake-up capability

Signal descriptions -

Port 6 - 8 pins, General purpose digital I/O with port interrupt, wake-up capability

Signal descriptions -

Port 7 - 8 pins, General purpose digital I/O Re-configurable for secondary functions

Signal descriptions -

Port 8 - 8 pins, General purpose digital I/O Port 9 - 8 pins, Re-configurable for secondary functions

Signal descriptions -

Port 10 - 6 pins, General purpose digital I/O Port J - 6 pins, General purpose digital I/O

Signal descriptions -

Port I2C - Itâ&#x20AC;&#x2122;s for I2C mode of operation These pins meant for clock and data transfer.

Signal descriptions -

Power supply pins : 5 Pins for analog power, 4 Pins for digital power, 1 for core power supply, 1 for switching output.

Signal descriptions -

Reference pins : 2 Pins for internal reference voltage, 2 Pins for external reference voltage, 1 Pin for RTC clock calibration output.

Signal descriptions -

SPI - Serial Peripheral Interface Works in master / slave mode, Signals may be In / Out, After setting the mode, In/out, then enable it.

Signal descriptions -

Timer0, Timer1, Timer2 and Timer3 Each timer have 6 control & 6 counter registers Each timer have interrupt vector address.

Signal descriptions -

Debug / Trace peripherals This zone maps the internal and external PPB regions of the Cortex-M4.

The following peripherals are mapped to this zone : • Core and System debug control registers (internal PPB) • NVIC and other registers in the System Control space of the Cortex-M4 (internal PPB) • FPB, DWT, ITM (internal PPB) • TPIU, Debug ROM table (external PPB) • Reset Controller (external PPB) • System Controller (external PPB)

Interrupts The Cortex-M4 processor on MSP432P401x MCUs implements an NVIC with 64 external interrupt lines and 8 levels of priority. From an application perspective, the interrupt sources at the device level are divided into two classes, NMI and the User Interrupts. Internally, the CPU exception model handles the various exceptions (internal and external events including CPU instruction, memory, and bus fault conditions) in a Fixed and configurable order of priority.

Power on / off Reset The POR initiates a complete initialization of the application settings and device configuration information. This class of reset may be initiated either by the Power Supply System (PSS), Power Control Manager (PCM), Reset (RSTn) pin, Clock System on Digitally Controlled Oscillator (DCO) Device emulation logic (through the debugger). From an application perspective, all sources of POR return the device to the same state of initialization.