Temperature Controller

Page 1


Temperature Controller

R. Theagarajan. ME., MSc., PhD Rtd. Professor in Engineering email: rtheagarajan@yahoo.com rtrajan59@gmail.com


Temperature Controller – Basic requirements


Temperature Controller – Basic requirements Display devices to show temperature Seven segment display - Six I/O lines LCD display - Ten I/O lines


Temperature Controller – Basic requirements Display devices to show temperature Seven segment display - Six I/O lines LCD display - Ten I/O lines Input devices to set temperature limits Key pad, TWS - Four I/O lines


Temperature Controller – Basic requirements Display devices to show temperature Seven segment display - Six I/O lines LCD display - Ten I/O lines Input devices to set temperature limits Key pad, TWS - Four I/O lines Output indicators - Three I/O lines High, Red color LED Normal, Green color LED Low, Yellow color LED


Temperature Controller – Basic requirements Display devices to show temperature Seven segment display - Six I/O lines LCD display - Ten I/O lines Input devices to set temperature limits Key pad, TWS - Four I/O lines Output indicators - Three I/O lines High, Red color LED Normal, Green color LED Low, Yellow color LED Output Alarm, Buzzer One I/O line


Temperature Controller – Basic requirements Input from the sensor unit Thermistor - One I/O line Thermocouple - One I/O line


Temperature Controller – Basic requirements Input from the sensor unit Thermistor - One I/O line Thermocouple - One I/O line ADC to read analog input, Convert to digital to feed it to microcontroller Eight I/O lines


Temperature Controller – Basic requirements Input from the sensor unit Thermistor - One I/O line Thermocouple - One I/O line ADC to read analog input, Convert to digital to feed it to microcontroller Eight I/O lines If ADC is multi-channel, then other lines are required Three I/O lines to select the channel One I/O line for start of conversion One I/O line for End of conversion One I/O line to enable the output


Temperature Controller – Basic requirements Number of Input pins required Thumb wheel switch - Four input lines Analog input to ADC - One I/O line Number of output pins required Seven segment display - 6 lines Output indicators - 3 lines Alarm - one line ADC output - eight lines Start and Output enables lines - 2 Total number of lines required are 24


Vdc

ADC


Vdc

Osc

ADC


R1

Vdc

Clock

C1

ADC


R1

Vdc

Clock

C1

ADC


R1

Vdc

Clock

ADC

C1 V.ref

VR


R1

Vdc

Clock

ADC

C1 V.ref

+12

VR R2

R3


R1

Vdc

Clock

ADC

C1 V.ref

+12

A2 A1 A0

VR R2

R3


R1

Vdc

D-bus

Clock

ADC

C1 V.ref

+12

A2 A1 A0

VR R2

R3


R1

Vdc

D-bus

Clock

ADC

C1 V.ref

+12

A2 A1 A0

VR R2

R3

ALE


R1

Vdc

D-bus

Clock

ADC

C1 V.ref

+12

SOC

A2 A1 A0

VR R2

R3

ALE


+5 V

R1

Vdc

D-bus

Clock

ADC

C1 V.ref

+12

SOC

A2 A1 A0

VR R2

R3

ALE


OE +5 V

R1

Vdc

D-bus

Clock

ADC

C1 V.ref

+12

SOC

A2 A1 A0

VR R2

R3

ALE


OE +5 V

R1

Vdc

D-bus

Clock

ADC

C1 V.ref

+12

SOC

A2 A1 A0

VR R2

R3

ALE

C


OE +5 V

R1

Vdc

D-bus

Clock

ADC

C1 V.ref

+12

SOC

A2 A1 A0

VR R2

R3

ALE

PA

C


OE +5 V

R1

Vdc

D-bus

Clock

ADC

C1 V.ref

+12

SOC

A2 A1 A0

VR

PA

C

ALE Latch

R2

R3


OE +5 V

R1

Vdc

D-bus

Clock

ADC

C1 V.ref

+12

SOC

A2 A1 A0

VR

PA

C

ALE Latch

R2

R3

7447


OE +5 V

R1

Vdc

D-bus

Clock

ADC

C1 V.ref

+12

SOC

A2 A1 A0

VR

PA

C

ALE Latch

R2

R3

7447

R.pad


OE +5 V

R1

Vdc

D-bus

Clock

ADC

C1 V.ref

+12

SOC

A2 A1 A0

VR

PA

C

ALE

PB

R2

R3

Latch

7447

R.pad


OE +5 V

R1

Vdc

D-bus

Clock

ADC

C1 V.ref

+12

SOC

A2 A1 A0

VR

PA

C

ALE

PB

Latch

7447

R.pad

Latch

7447

R.pad

R2

R3


OE +5 V

R1

Vdc

D-bus

Clock

ADC

C1 V.ref

+12

SOC

A2 A1 A0

VR

PA

C

ALE

PB

Latch

7447

R.pad

Latch

7447

R.pad

R2

R3


OE +5 V

R1

Vdc

D-bus

Clock

ADC

C1 V.ref

+12

SOC

A2 A1 A0

VR

PA

C

ALE

PB

Latch

7447

R.pad

Latch

7447

R.pad

R2

R3


OE +5 V

R1

Vdc

D-bus

Clock

ADC

C1 V.ref

+12

SOC

A2 A1 A0

VR

PA

C

ALE

PB

Latch

7447

R.pad

Latch

7447

R.pad

R2

R3 +5


OE +5 V

R1

Vdc

D-bus

Clock

ADC

C1 V.ref

+12

SOC

A2 A1 A0

VR

PA

C

TWS

ALE

PB

Latch

7447

R.pad

Latch

7447

R.pad

R2

R3 +5


OE +5 V

R1

Vdc

Buffer

D-bus

Clock

ADC

C1 V.ref

+12

SOC

A2 A1 A0

VR

PA

PC

C

TWS

ALE

PB

Latch

7447

R.pad

Latch

7447

R.pad

R2

R3 +5


OE +5 V

R1

Vdc

D-bus

Clock

ADC

C1 V.ref

+12

SOC

A2 A1 A0

VR

PA

Buffer

Buffer

TWS

TWS

Latch

7447

R.pad

Latch

7447

R.pad

PC

C

ALE

PB

R2

R3 +5


OE +5 V

R1

Vdc

D-bus

Clock

ADC

C1 V.ref

+12

SOC

A2 A1 A0

VR

PA

Buffer

Buffer

Buffer

Buffer

TWS

TWS

TWS

TWS

Latch

7447

R.pad

Latch

7447

R.pad

PC

C

ALE

PB

R2

R3 +5


OE +5 V

R1

Vdc

D-bus

Clock

ADC

C1 V.ref

+12

SOC

A2 A1 A0

VR

PA

Buffer

Buffer

Buffer

Buffer

5

1

6

2

PC

ď ­C

Low Limit

High Limit

ALE

PB

Latch

7447

R.pad

Latch

7447

R.pad

R2

R3 +5


74138

OE +5 V

R1

Vdc

SOC

D-bus

Clock

ADC

C1 V.ref

+12

PC

A2 A1 A0

VR

PA

Buffer

Buffer

Buffer

Buffer

5

1

6

2

PC

ď ­C

Low Limit

High Limit

ALE

PB

Latch

7447

R.pad

Latch

7447

R.pad

R2

R3 +5


74138

Enable OE +5 V

R1

Vdc

SOC

D-bus

Clock

ADC

C1 V.ref

+12

PC

A2 A1 A0

VR

PA

Buffer

Buffer

Buffer

Buffer

5

1

6

2

PC

ď ­C

Low Limit

High Limit

ALE

PB

Latch

7447

R.pad

Latch

7447

R.pad

R2

R3 +5


74138

Enable OE +5 V

R1

Vdc

SOC

D-bus

Clock

ADC

C1 V.ref

+12

PC

A2 A1 A0

VR

PA

Buffer

Buffer

Buffer

Buffer

5

1

6

2

PC

ď ­C

Low Limit

High Limit

ALE

PB

Latch

7447

R.pad

Latch

7447

R.pad

R2

R3 +5


74138 Enable Enable OE +5 V

R1

Vdc

SOC

D-bus

Clock

ADC

C1 V.ref

+12

PC

A2 A1 A0

VR

PA

Buffer

Buffer

Buffer

Buffer

5

1

6

2

PC

ď ­C

Low Limit

High Limit

ALE

PB

Latch

7447

R.pad

Latch

7447

R.pad

R2

R3 +5


74138 Enable Enable OE +5 V

R1

Vdc

SOC

D-bus

Clock

ADC

C1 V.ref

+12

PC

A2 A1 A0

VR

PA

Buffer

Buffer

Buffer

Buffer

5

1

6

2

PC

ď ­C

Low Limit

High Limit

ALE

PB

Latch

7447

R.pad

Latch

7447

R.pad

R2

R3 +5


74138 Enable Enable OE +5 V Vdc

R1

SOC

D-bus

Clock

ADC

C1 V.ref

+12

PC

A2 A1 A0

VR

PA

Buffer

Buffer

Buffer

Buffer

5

1

6

2

PC

ď ­C

Low Limit

High Limit

ALE

PB

Latch

7447

R.pad

Latch

7447

R.pad

R2

R3 +5


74138 Enable Enable OE +5 V Vdc

R1

SOC

D-bus

Clock

ADC

C1 V.ref

+12

PC

A2 A1 A0

7805

PA

Buffer

Buffer

Buffer

Buffer

5

1

6

2

PC

ď ­C

Low Limit

High Limit

ALE

PB

Latch

7447

R.pad

Latch

7447

R.pad

R2

R3 +5


+5

-

74138

+

Enable Enable

K OE +5 V Vdc

R1

SOC

D-bus

Clock

ADC

C1 V.ref

+12

PC

A2 A1 A0

7805

PA

Buffer

Buffer

Buffer

Buffer

5

1

6

2

PC

ď ­C

Low Limit

High Limit

ALE

PB

Latch

7447

R.pad

7475

7447

R.pad

R2

R3 +5


+5

-

-

74138

+

+

Enable LM335

K

Enable

OE +5 V Vdc

R1

SOC

D-bus

Clock

ADC

C1 V.ref

+12

PC

A2 A1 A0

7805

PA

Buffer

Buffer

Buffer

Buffer

5

1

6

2

PC

ď ­C

Low Limit

High Limit

ALE

PB

Latch

7447

R.pad

7475

7447

R.pad

R2

R3 +5



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