Advanced Packaging extracts from LAYERS 2016

EDITION 2

ADVANCED PACKAGING Solving challenges in the Advanced Packaging industry EXTRACTS FROM LAYERS 2016

LAYERS2016

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ADVANCED PACKAGING

Advanced Packaging

Andreas Erhart, Senior Manager Product Marketing

The past five decades in Advanced Packaging have been driven by the increase of performance and integration but also by a reduction of form factor and costs. Evatec has been a strong partner supporting this evolution of Semiconductor packaging and is very well prepared to pursue this path in the coming decades whether it is for Cu pillar, Interposer, TSV or the more recent requirements for embedded chips in a mold on 300mm wafer. With industryleading recent results of 30’000 wafers sputter etch shield kit life, we look forward to continuing to provide customers with outstanding process solutions and the lowest cost of ownership.

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Advanced Packaging

The Rising Wave of the Semiconductor Industry

The introduction of new functionality, miniaturization and cost down- Advanced Packaging has the potential to offer it all. Thibault Buisson from Yole DĂŠveloppement reviews the prospects for the technologies within the Advanced Packaging market over the next 5 years.

COMPETENCES IN ADVANCED PACKAGING

05

WHERE ARE WE TODAY ?

AN OPPORTUNITY FOR ADVANCED PACKAGING

For more than five decades the semiconductor industry has followed Moore’s law, driving miniaturization of transistors and scaling of the CMOS technology to smaller and more advanced technology nodes while at the same time reducing the cost significantly. This miniaturization process has resulted in higher performance devices, increased I/O density and a more efficient utilization of the silicon space.

To overcome these limitations, the industry has turned its attention to the alternative approach of Advanced Packaging that can address both current and future market demands with more flexible manufacturing and integration approaches, bringing new technologies faster to market at a lower cost, and still addressing further performance increases and miniaturization.

The semiconductor industry is expected to start another cycle that will be driven largely by consumer products and the Internet of Things (IoT). Although performance and cost were the 2 main drivers historically, todays’s growing portfolio of applications and a higher diversity of products means that the ability to incorporate various new functions within a system and product, while continuing the miniaturization,and cost down trends, is becoming even more challenging. Building various functionalities within the chip was traditionally done using a system-on-chip (SoC) type architecture, but its becoming more and more difficult and costly to use the same structure for more complex systems where integration of various disparate technologies is required. While the scaling process continues and more advanced technology nodes are being developed, the investment and developmental time required are increasing significamtly.

Its no surprise that a significant level of activities are currently taking place in this segment. Advanced Packaging brings a broad range of platform and interconnect technologies that can address requirements across various markets, from low to mid and high end applications for consumer, computing, industrial, automotive, renewable energy, military and aerospace, etc.

Packaging of devices was done traditionally with lead-frames and wirebonding, but newer advanced packaging technologies have been developed and commercialized addressing both single and multiple die integration. There are several platforms available today in the market: platforms using encapsulation based technologies (especially applied for MEMS and sensors, wafer level optics), packages with electrical redistribution layers (either within the die, as would be the case of fan-in, or extending outside the die in case of fan-out), embedding dies within organic substrates, flip chip bumped packages using intermediary substrates and stacked devices using through-silicon-via interconnect technologies. The suitability of each of these platforms and market adoption will depend on the final product and application needs.

LAYERS2016

THE EVOLUTION OF SEMICONDUCTOR PACKAGING

(Source: Advanced packaging & Semiconductor Manufacturing Workshops, Yole Développement, July 2016)

ADVANCED PACKAGING PLATFORMS

Source: Advanced Packaging and Manufacturing Business Unit at Yole Développement, July 2016)

FUTURE GROWTH OF ADVANCED PACKAGING

(Source: Status of the Advanced Packaging Industry report 2015, November 2015, Yole Développement)

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COMPETENCES IN ADVANCED PACKAGING

WHAT ARE THE FASTEST GROWING ADVANCED PACKAGING PLATFORMS TODAY? Although the Advanced Packaging market today enjoys only a small share (around 20% in wafers) within the total packaging market of the semiconductor industry, it has potential to grow and is expected to reach by 32% market share by around 2020 as more and more applications transition from traditional packaging platforms like wirebonding and lead-frames to more advanced ones. In terms of revenue, by 2020, Yole Développement estimates that Advanced Packaging will reach approximately 44% of the total revenue for the semiconductor packaging.

Increased performance and functionality, miniaturization and low cost will continue to be the key drivers for Advanced Packaging. However, fab space to accomodate this increased capacity is also at a premium so individual tool throughput and footprint will also be key factors going forwards. Which packaging platform will have the fastest growth in the coming years, will be highly impacted by market demands, high volume applications, and ability to meet market requirements, availability and readiness of the infrastructure and supply chain necessary to support its manufacturing but there are some trends.

faster speeds, higher bandwidth needs, lower form factor and reduced power consumption, its adoption is expected to expand and further grow (25% CAGR until 2020).

Fan-out: A very promising platform that embeds dies in a molding compound. It brings several advantages over other platforms, such as reduced package thickness, better thermal and electrical performance, and enabler of 3D and System-inPackage integration of multiple dies as well as lower cost. As a result, this platform is expected to have the highest growth in the coming years (55% growth). The major OSATs have also been very actively involved in developing their own solutions in addition to the already well established eWLB technology.

REVENUE FORECAST BY ADVANCED PACKAGING PLATFORM FROM 2014 TO 2020 – IN US$ BILLION

Yole Développement continues to see strong interest in high throughput platforms offering low cost of ownership addressing single die needs (such as fan-in) as well as platforms enabling multi-die and System in Package (SiP) integration, such as fan-out, flip-chip and 3DIC: Flip-chip: Still the dominant platform in Advanced Packaging (representing over 70% of the total Advanced Packaging revenue) this could be impacted significantly by the application processors (APU) market in high-end smartphones if fan-out will replace the typical flip-chip package known as package-on-package (PoP), limiting its growth to 5% over the next 5 years> Fan-in: Expected to have a stable growth of 8%, mainly driven by low cost and form factor packaging needs (continues to represent a large share, approximately 30%, as type of package in the high end smartphones) 3D IC: 3D integration using through-siliconvia (TSVs) can be applied directly for stacking devices or using an intermediary interposer (2.5D integration). Applied to CMOS IS initially, its adoption has broaden to other devices as well, such as MEMS, FPGAs, most recently GPUs and activities are ongoing for the first processor using TSVs to commercialize. Due to its ability to address

(Source: Status of the Advanced Packaging Industry report 2015, November 2015, Yole Développement)

ITS AN EXCITING TIME FOR ADVANCED PACKAGING !

Advanced Packaging is a very dynamic offering a wide variety of platforms for the future. Driven especially by consumer and IoT applications, it brings great flexibility in integrating and packaging devices, from single to multiple dies and addresses a wide range of requirements.

“Advanced Packaging is expected to reach more than a 40% market share by revenue of the total packaging market in 2020”

This article has been written in collaboration with Rozalia Beica, former CTO & Business Unit Director of Yole Développement.

LAYERS2016

Solving challenges in processing FOWLP substrates Senior Scientist Mohamed Elghazzali explains how challenges of achieving low contact resistance of the UBM or RDL metallization to the contact pads in FOWLP technology can now be overcome using the latest degas and etch technologies.

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COMPETENCES IN ADVANCED PACKAGING

The use of polymer materials has been a standard for many years already in the field of wafer level packaging.

Sputter etching by argon ions is used for the removal of metal oxide from the contact pads. This process is non-selective and has the disadvantage that the etched polymer forms a thick “not dense” deposit on the chamber shielding during the use of the tool, which would ultimately lead to particle generation.

Since the etch process is required to remove the oxide and organic residue at relatively high rate, it induces heating of the wafers, and an increasing amount of VC outgassing – mainly water vapour and organic residuals - occurs over the process time. Fig. 1 shows an RGA tracing during the ICP etch process.

Excessive VC presence will make the plasma process unstable and contaminate the contact pads resulting in a bad contact resistance.

While processing silicon wafers coated with PI (polyimide) or PBO (polybenzobisoxazole) in vacuum deposition tools already poses challenges due to heavy outgassing and critical temperature limitations, FOWLP technology (Fan-out wafer level package) creates a significantly bigger challenge as the wafers are constituted out of silicon dies embedded in epoxy mold compound and polymers where low cure temperatures need to be used Achieving low contact resistance of the UBM or RDL metallization to the contact pads of such wafers in a conventionally equipped PVD tool is virtually impossible due the challenges mentioned above.

The following key criteria must be addressed at temperature levels of 120 to 150°C: 1.

2.

3.

The two major requirements of the etch process are: a) To guarantee a low contact resistance and b) To keep particle generation low An essential measure to combat particle generation is the use of pasting wafers where Al is backsputtered intermittently to enhance the adhesion of the material deposited on the shields.

Sufficient degas at compliant temperature Removal of the native metal oxide from the contact pads by sputter etch Deposition of the metal contact, typically by sputtering Ti followed by Cu

The degas step is critical; on one hand a certain degas temperature should not be exceeded to avoid over curing of the polymer, while on the other hand outgassing needs time according to the thickness of the polymer material. However, long outgassing times reduce the throughput of a tool and should be avoided, thus alternatives with stack degassing capability had to be developed.

Figure 1: RGA of VC during sputter etch process

After the etch process, the wafer is transferred to the sputter chamber without delay so any contamination is minimized. Once the wafer is covered by the first metal, the contact pad as well as the polymer is sealed and no further impact on the contact resistance can occur.

SINGLE WAFER DEGAS SOLUTION Simple hot plate degassers with substrate clamping and backside-gas coupling have been successfully used for single wafer degassing over many years.

Our new concept heats up the wafer embedded in a shallow pocket as shown in Fig. 2. Very effective dual sided heat transfer is achieved. After heating up the wafer to typically 150°C in less than 20s, the pocket is opened wide to enable effective pump-out of the VCs. The faster heat up rate compared to the hot plate concept provides a much shorter degas time at any given temperature to enable the best possible throughput.

Figure 2: Principle of single wafer degasser

LAYERS2016

The same design can also be used as a cooling station which may be required prior to the etch step.

The degassing output from PBO coated silicon wafers has been analyzed by RGA. VC emission starts much earlier compared with the previous hot-plate design due to the higher heating rate which is ideal as organic volatile compounds are desorbing with a delay compared to water vapor.

Figure 3: Degas spectra of a PBO wafer during degassing at 150°C in new single wafer degas module.

high if a laminar flow of inert gas is applied, while in vacuum the degassing of the volatile components has to take place via less efficient molecular diffusion.

Atmospheric Batch Degassers with laminar flow concept do not show any change in process pressure if new wafers are loaded into the same environment as already outgassed wafers. Vacuum Batch Degassers on the other hand with molecular flow show a much higher risk of contamination of outgassed wafers by new incoming wafers resulting in possible unstable Rc. Eliminating this potential risk would require new wafers only to be added once all outgassed wafers have left the degas chamber resulting in very low throughput.

On completion of degas, the load lock is pumped and the wafers are cooled down ready for the next low temperature process steps.

Mold wafer outgassing on Atm. Batch Degasser (ABD)

Figure 5: H2O partial pressure comparison of mold wafers in etch chamber, not-degassed and degassed in atmospheric batch degasser.

BATCH DEGAS SOLUTION Fan-out wafers with the much thicker polymer/ epoxy mold compound need a much longer degas time than the cycle time of a single wafer. In this case a batch type degasser is used where several heated slots are available and the wafers are degassed in parallel. Two different concepts of batch degassers are used, for either atmospheric or vacuum operation.

The advantage of the batch degasser in atmosphere is a much faster and better controllable heat-up of the wafers along with a simpler design. Diffusion of volatile components from the bulk material to the surface is only driven by temperature. Desorption is driven by the concentration gradient which is the same whether desorption takes place in vacuum or in atmosphere. However, the advantage in atmosphere is that the concentration gradient can always be kept

THE NEW ICP ETCH SOLUTION The ICP sputter etch module covers one of the most important steps in WLP - the removal of oxide from the final metal pads to allow contact formation. To efficiently handle the polymer materials and adhere

011

COMPETENCES IN ADVANCED PACKAGING

Fig. 8, the particle level after 30’000 processed wafers, based on 300Å (SiO2 eq.) removal and PBO passivation, is extremely low.

Figure 8: Particle performance during 30’000 wafer Marathon

40 1.5-10µm

>10µm

30 20 10 0

The design of the RF application on the chuck has also been improved significantly resulting in a higher etch rate, a better uniformity and a reduction of RF noise.

0

5’000

10’000 15’000 20’000 Wafer count #

25’000

30’000

PRODUCTIVITY FOR FOWLP

Figure 7: ICP etch rate (SiO2 equivalent) over 30’000 wafers

Figure 10: Wafer Temperature profile of Fan-out wafer

Evatec’s single wafer sputter tools CLUSTERLIN® and HEXAGON provide highest throughput in the industry for Fan-Out wafers when taking advantage of the new features of the atmospheric batch degas and the new ICP etch.modules Critical aspect like thermal budget in the ICP etch module and optimized process flow ensure that high productivity is achieved.

As shown in Fig. 9 the thermal budget depends on the incoming wafer temperature as well as the wafer mass/thickness. For standard thickness wafers, a throughput of 50 wafers/hr was achieved,based on 30nm removal of SiO2 equivalent in a 2-step etch process.

Airlock

ABD

Artic Cool

Etch 1

Etch 2

PVD Ti

PVD Cu

160 140 120 Temperature [ºC]

The module has been tested during full production with the ICP Etch process, showing that all cooled surfaces stayed stable at a temperature of -30°C. An etch rate 50% higher than previously could be achieved. As Fig. 7 shows the etch rate is stable over the entire marathon test of 30’000 wafers.

Production data - Etch rate stability

Production data - Particle adders over a single kit life 50

Particle adders

to the low processing temperature requirements, a number of new design ideas had to be implemented, especially the improved cooling of the ICP dome, shielding and the substrate pedestal. An optimized shield set combines the highest possible pumping conductivity with full protection of the chamber walls and ,any possible particle generation is kept at an absolute minimum. These combined measures provide significantly shortened maintenance times, i.e. faster cool down/heat from room temperature to -30°C, an easier shield change, and an optimized conditioning.

100 80 60 40 20 0

0 10 20 30 Time [sec]

0

100

200

300

400

500

Time [sec]

CONCLUSIONS New improved solutions for processing of highly outgassing Fan-out wafers have been developed and tested. A batch degas module for Fan-out wafers and an improved ICP etch chamber capable of running higher throughput with reduced maintenance frequency were designed resulting in excellent process results including low contact resistance. The new solutions provide significant savings in terms of maintenance and cost of ownership and extend tool capability for the next generation wafer level packaging requirements.

Even with this high etch rate the new ICP Etch solution achieves extremely low contact resistance (Rc). The Rc shows a high stability over the whole lifetime of the chamber shield kit. As illustrated in

LAYERS2016

Pushing the boundaries in Ionized PVD Evatec’s Senior Scientist Dr. Juergen Weichart and Fraunhofer’s Kay Viehweger* explain how Highly Ionized Sputter (HIS) source technology now enables TSV processing for Aspect Ratios of up to 20:1

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COMPETENCES IN ADVANCED PACKAGING

Kay Viehweger Fraunhofer

Fig.1: Cross section of liner plated TSVs AR 20:1 center position

Highly Ionized Sputtering (HIS) has been developed for the deposition of metal barrier and copper seed layers in Through Silicon Vias (TSV) with very high aspect ratios, where PVD continues to be the preferred method for metal barrier and seed layers before subsequent electroplating. The process flow consisting of deep silicon etch, oxide liner deposition, seed deposition and electroplating on TSVs with aspect ratio 10:1 has been developed in a joint development project between Evatec and Fraunhofer IZM ASSID. and results have been published elsewhere.

In recent experiments however, we investigated the limits of HIS in even higher aspect ratios up to 20:1. Vias with 10µm diameter and 200µm depth were etched in 300mm wafers and a seed layer of ~300nm Ti and ~2.2µm Cu was deposited using the Evatec CLUSTERLINE®300 cluster tool with HIS. The 20:1 vias were cut and analyzed by cross-section SEM showing that the minimal seed thickness for a successful electroplating process of >20nm could be achieved in every location of the via. From experience we know that the region between 50% and 75% of the via depth is most critical here. Subsequently a liner was deposited by electroplating and the result is shown in Figure 1. As this cross-section shows, the seeding is free of defects, however the plating chemistry has reached its limits. A complete filling could by achieved at ASSID for aspect ratios up to 15:1, but they are still under investigation for 20:1. Nevertheless the plated liner could be used to verify the completeness of the liner over the entire 300mm wafer by using X-ray tomography, which is currently the best non-destructive method showing that all vias on the entire wafer received a flawless liner. Figure 2 shows X-ray tomography pictures of the dense pattern of vias in the center and at the edge of the wafer. This tilted view allowed confirmation that the electroplating is complete in every individual via by measuring its length.

*Kay Viehweger, Fraunhofer IZM ASSID, Ringstraße 12, 01468 Moritzburg, Germany

Fig. 2: X-ray tomography of liner plated TSVs with AR 20:1, left: center of the 300mm wafer, right: edge of the wafer

COST EFFECTIVE PROCESSING OF TSVS WITH AR 20:1 IS A GO! Liner plating on TSVs with AR 20:1 has been demonstrated successfully, suggesting that PVD seed deposition can still be used with all its advantages of equipment, process costs, and integration issues. What’s more, the comparatively close target-to-wafer spacing results in high specific deposition rates, and high target utilization provides very good cost-of-ownership compared to other directional sputtering techniques. In addition the same PVD module also allows deposition of UBM and/or RDL metal layers at even lower target-to-wafer spacing without the need of a re-configuration or venting of the tool.

LAYERS2016

A leap forward in EMI shielding EMI shielding of Chips on a package level makes PCB substrate design simpler and more compact as package densities increase and shielding demands get tougher. Senior Product Manager Markus Frei explains why multilayer PVD coating by sputter on SOLARIS S380 is the perfect cost effective solution for high performance applications.

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COMPETENCES IN ADVANCED PACKAGING

GETTING EMI SHIELDING RIGHT

FINDING THE RIGHT MANUFACTURING SOLUTION

Shielding uses multilayer stacks to reduce EMI by reflection and/ or absorption of electromagnetic waves. The primary mechanism of EMI shielding is usually reflection where conductive materials with mobile charge carriers are needed – typically metals like aluminum, silver, gold or copper. The secondary mechanism is absorption where the shield material should have electric and or magnetic dipoles which can interact with the electromagnetic fields in the radiation. Materials like stainless steel and nickel with high values of magnetic permeability are typical. At high frequencies, most of the wave energy is reflected from a shield’s surface, while a smaller portion is absorbed. At lower frequencies, absorption generally predominates. Shielding performance is a function of the properties of the shielding materials and the quality of the coating, the frequency, and the distance from the source to the shield. Step coverage and good adhesion are essential, and packages must be protected from high temperatures during coating to avoid damage.

Low cost solutions like painting or plating may have been good enough in the past, but as portable electronics like smartphones become smaller and lighter, work at multiple frequencies, increasing data transfer rates and higher chip densities, older RF shielding techniques simply are not up to the job. Sputtering however, is an inherently flexible process. Changes in layer materials or thicknesses as shielding process needs change can be implemented quickly and cheaply. The challenge however is to achieve the demanding cost targets in volume production.

LARGE AREA COATING ON SOLARIS S380 FITS THE BILL The new SOLARIS S380 with its dedicated sputter cathode and cooling technologies delivers reduced cost of ownership at typical throughputs of 20,000,000 chips per month.* Integrated precleaning process module for removal of any organic residues ensures good layer adhesion and higher process yields.

Deposition of metals stacks using “Penta Plus 380” cathode technology brings enhanced side wall coverage at a larger radius allowing more substrates to be coated on a single carrier.

Simple 150mm diameter monoblock targets with lower manufacturing costs combined with high target utilisation reduce overall materials costs.

Integrated cooling station keeps backside temperature under control for prevention of package damage Tool architecture ideal for automated fab integration reducing cost of ownership in high volume manufacturing.

SST 0.3µm1) Cu 3 - 5µm1)

SST 0.1µm1) x

Wi-Fi or RF amp etc.

Substrate mounting plate

Requirement of side wall deposition thickness ,x’ of copper: ≥ 2µm1)

Design of typical shield structure on an RF Amplifier

TYPICAL PROCESS FLOW IN THE SOLARIS S380 Plasma Clean

Degas

Adhesion Layer

TAKE A LOOK AT THE RESULTS

Conductive Layer

1.

Passivation Layer 2.

Fig 1: 430mm carrier with coating area 380mm diameter holding 940 chips with 1mm separation* Fig 2: Side Wall Coverage measured at 50% Fig 3: SOLARIS flexibility allows simple management of process temperatures with its cooling station combined with its multi-turn facility

3.

Typical monthly throughputs according to process conditions for a standard shielding stack.

PROCESS

NO. OF MULTI-TURNS

MAX. BACK SIDE TEMP [°C]

TURN TIME PER CARRIER [S]

EFFECTIVE CYCLE TIME PER CARRIER [S]

SUBSTRATES / CARRIER (BASED ON CHIP SIZE 8 X 8 MM)

SUBSTRATES / HOUR

SUBSTRATES / MONTH

0.2µm-3µm–0.2µm 2)

8

154

14.95

120

940

28300

20’300’000

0.2µm-3µm–0.2µm 2)

9

141

14.75

133

940

25500

18’300’000

0.2µm-3µm–0.2µm 2)

10

130

14.60

146

940

23200

16’600’000

* Based on chip dimensions 8 x 8 mm

LAYERS2016

ContactUs GLOBAL HEADQUARTERS

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AMERICAN HUB

Evatec AG Hauptstrasse 1a, CH-9477 Trübbach, SWITZERLAND T: +41 81 403 80 00 E: info@evatecnet.com www.evatecnet.com

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