Power Devices extracts from LAYERS 2016

EDITION 2

POWER DEVICES From Silicon to SiC and GaN whats coming up in Power Devices EXTRACTS FROM LAYERS 2016

LAYERS2016

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POWER DEVICES

Power Devices

Hans Auer, Senior Manager Product Marketing

Power electronics, or more specifically “solid state electrical devices” are used to control electric power.

Silicon semiconductors have been employed in power circuits since the invention of the solid state diode by William Shockley in 1960. Today the discrete power device market has achieved nearly 20 billion USD of market size with a predicted CAGR of ~7%. This continuous growth is driven by the ever increasing needs for energy management and control in domestic and industrial markets, mobile communication/ computing and most recently by greenhouse gas reduction initiatives. Electric vehicles like cars and trains as well as renewable energy generation looks set to spur the major part of power device development and growth in the near future.

Evatec has a strong footprint in the power electronics sector – both as the industry leader in metallization of traditional power devices and also now for latest generation MOSFET and IGBT devices with very thin wafers for 8“ and 12“. Current state of the art technology includes fully automated handling and processing platforms for wafers down to 50µm with high equipment uptimes and device yields. Delivering solutions to deposit stress sensitive 4- layer backside metal stacks with integrated “in situ” clean-etch for oxide removal and annealing capability for the ohmic contact formation is just part of our daily work.

A large part of the innovation for next generation power transistors takes place in wide bandgap GaN and SiC technology. Evatec’s existing experience in silicon power devices and in related technologies such as GaAs III-V devices or GaN technology from the LED industry means we are ideally positioned to contribute to the development and industrialization of these new innovative power device types.

LAYERS2016

Power Semiconductor Devices Senior Scientist Dr. Oliver Rattunde shows how sputtering combined with the right choice of wafer handling and process control achieves successful metallization processes on thin 8 and 12 inch wafers.

Solid state semiconductor power devices, e.g. IGBTs (insulated-gate bipolar transistors) or MOSFETs (metal oxide semiconductor field-effect transistors) have gained large technological importance in efficient processing of electrical energy through means of electronic switching devices on different power levels.

The sketch of an IGBT device (Fig. 1) shows that currents in power devices flow vertically through the silicon substrate. Reducing wafer thickness brings opportunities for optimized device performance including a) reduced electrical on-state resistance and thermal resistivity of the remaining substrate thickness, and b) decreased forward saturation voltage and turn-off losses. In current state of the art power device manufacturing the wafers are first processed on the frontside and then ground down to wafer thicknesses below 100μm prior to backside metallization (BSM). Semiconductor roadmaps are even targeting wafer thicknesses below 50μm in the near future. A variety of wafer support systems to handle these ultra-thin wafers already exist, the most prominent being the so called “Taiko”-wafer where only the inner area of the wafer is thinned, leaving an edge support ring.

Fig 1: Structure of a typical IGBT device

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COMPETENCES IN POWER DEVICES

Although evaporation is a long established metallization method for power devices especially on wafer sizes up to 6”, sputtering has become more common over the last 10 to 15 years. Batch sputtering tools with manual handling were the initial solution of choice for thin wafers due to the lack of automated thin wafer handling solutions, but nowadays with 8” and even 12” in production, reliable thin wafer handling has become a must. Applying the backside metallization on these wafers poses several challenges for semiconductor manufacturing tools, both handling and process wise – all of which have been successfully addressed by the EVATEC CLUSTERLINE® and RADIANCE cassette-to-cassette cluster tools.

Fig 2: Cassette design handles large wafer bows

THIN WAFER HANDLING The EVATEC CLUSTERLINE® and RADIANCE apply a variety of dedicated end effectors and dedicated metal cassette geometries with different slot pitch for reliable handling of thin wafers with less than 100µm wafer thickness tolerating wafer bow of up to 4mm (Figs. 2 & 3).

PROCESS CHALLENGES Fig 3: End effector for thin wafer handling

Sputter source Plasma Wafer Chuck Fig 4: Pyrometer set-up with light pipe and optical fiber integrated in the chuck body looking at the backside of the wafer during processing

Light Pipe Fiber Optics Pyrometer

BSM process optimization requires superior stress control (low wafer bow + warp required for subsequent process steps) as well as advanced temperature management. Wafer temperature is both a major parameter for stress control as well as the activator of good ohmic contact of the backside metal to the semiconductor device, which relies on inter-diffusion or alloying of the BSM with the silicon at elevated temperatures.

EVATEC CLUSTERLINE® manufacturing equipment offers dedicated chuck-top hardware for enhanced temperature control including “black” chucks for enhanced IR radiative heat absorption, and electrostatic chucking for superior thermal contact to the chuck. In addition an optional in situ pyrometer for IR temperature measurement can be installed for monitoring and documenting wafer temperature and process stability (See Fig. 4). Fig 5. shows in situ pyrometer data during NiV deposition proving excellent repeatability and thus process stability in the EVATEC CLUSTERLINE®.

Final bow of thin wafers with complete layer stack Etch / Al / Ti / NiV / Ag has been reduced to values below 10µm with optimized Evatec process settings e.g. by optimizing the NiV process step (Fig. 6).

LAYERS2016

Fig. 5: Pyrometer signal during 200nm NiV deposition for 15 Taiko wafers (130µm) processed during several days

Fig.6: Measured wafer bow for 130µm 8’’ Taiko wafers with complete layer stack Etch / Al / Ti / NiV / Ag for different NiV process settings (NiV film thickness 1100nm).

TEMPERATURE SIMULATIONS

Fig.7: Temperature simulation for BSM layer stack ICP etch / 200nm Al (hot chuck) / 200nm Ti / 600nm NiV / 200nm Ag for different wafer thickness.

Wafer temperature simulations enable modeling and understanding of the effects of different parameter changes on wafer temperature during BSM processing. Fig 7. shows simulated wafer temperatures for different wafer thickness clearly indicating the effect of lower thermal mass for very thin Si substrates. The observed saturation temperature for thin wafer processing depends on both heat input from etch and film deposition as well as on heat loss mechanisms, mainly by radiation. Thus the nature of the wafer (e.g. bare Taiko wafer vs. processed device wafer with reduced frontside emissivity) has a large influence on the final temperature as can be seen in Fig 8. where reduced emissivity of the device wafer (devices facing towards the chuck) leads to far less heat exchange with the chuck underneath.

IN SITU ANNEALING Additional heat sources for in situ annealing enable contact formation at elevated temperatures independent of individual layer thicknesses of the deposited layer stack. This is mandatory for layer stacks that do not provide sufficient thermal budget during the deposition. Also, the combination of depositing thin films at lower temperatures and annealing afterwards reduces thermal stress and thus bow and warp of the ultra-thin substrates.

Fig.8: Temperature simulation for BSM layer stack ICP etch / 200nm Al (hot chuck) / 200nm Ti / 600nm NiV / 200nm Ag for different wafer types. A device wafer usually has reduced heat exchange with the underlying chuck and thus requires process adaptions (in this case for NiV) in order to not exceed 400°C wafer temperature.

For EVATEC CLUSTERLINE® and RADIANCE systems customers can choose from two options for in situ annealing: 1) a lamp anneal module for top side heating by halogen lamps, and 2) bottom side IR radiative heating by resistive heating elements integrated into the chuck.

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COMPETENCES IN POWER DEVICES

Pyrometer Crystal lens assembly IR lamp

Wafer

Fig. 9a: Schematic of the lamp anneal module

LAMP ANNEAL MODULE ANL200

Fig. 10: Heater power and temperature signals during a two-step lamp anneal process for a 725µm thick SensArray wafer.

Infrared Heating

Fig. 11: Microscopy image of Al spiking into the Si for chuck annealing after 200nm Al deposition. Note: Al film has been chemically etched away in order to visually inspect the wafer surface.

Sitting in a highly reflective (mirror-like) chamber the wafer can be heated by an arrangement of six halogen lamps upto a heating rate of 6°C/sec for standard thick wafers and 30°C/sec for 100µm thin wafers respectively. Since heat radiation hits the wafer on the top side first absorption is mainly governed by the emissivity of the (already deposited) backside metals and thus rather independent of the device structure on the front side of the wafer. In situ pyrometer data gives additional information on the stability of the annealing process.

Wafer processing in the anneal module usually involves a ramp-up step at high heater power followed by a second step at reduced heater power in order to maintain the desired equilibrium temperature. This process sequence is displayed in figure 10 where heater power of 100% and 20% respectively are used to reach an equilibrium temperature of 430°C for a 725µm thick Si-wafer equipped with thermo-couples (SensArray). Also displayed is the pyrometer signal which shows good correlation to the thermocouple temperature.

IR CHUCK HEATER Another in situ annealing option which has been applied successfully on EVATEC CLUSTERLINE® and RADIANCE systems consists of a resistive heating element which is completely integrated into the chuck body and thus emits IR heat radiation onto the bottom (device) side of the wafer. Specific designs of the resistive heating elements allow tailored temperature uniformities on the wafer. In principle the IR chuck heater can be mounted in any PVD module; for standard BSM applications it may be installed in the Al module e.g. for in situ anneal after the Al deposition.

Experiments have shown reproducible spiking patterns for Al on Si for in situ post-anneal after low temperature deposition of 200nm Al on thin Taiko device wafers (Fig.11).

LAYERS2016

Driving deployment of Wide Band Gap Power Devices on 200mm Hans Auer and Scientist, Dr. Dominik Jaeger introduce the advantages of Wide Band Gap (WBG) power devices and some of the development challenges ahead.

Today silicon power device technology has evolved to a very mature state.

However, with limited options for major future innovation steps that’s where wide bandgap (WBG) semiconductors now have the opportunity to step in. Their capabilities to operate at higher voltages and temperatures along with significantly lower switching losses enable power circuits to run at much higher frequencies resulting in reduced size. For example, the heat sink size for variable speed drives of industrial electric motors could be reduced by more than 50%. Battery operated vehicles, mobile computing or wearable electronics could all benefit from longer battery lives. Electric drives like fans, pumps, compressors, conveyer systems could all use less power, achieving overall energy savings of more than 20% once wide adoption is achieved.

Pw 1MW

RAIL TRACTION SMART POWER GRID WINDMILLS

GaN SiC DC AC Inverter

DC DC Converter

350kW Hybrid Automotive

100kW

HEV / EV PHOTOVOLTAIC INDUSTRIAL DRIVES

HEV / EV PHOTOVOLTAIC

50kW 30kW 5kW 1kW

POWER SUPPLY HOME APPLIANCE NETCOM, SERVER, NOTEBOOK

Rated voltage 600V

1000V

1200V

Figure 1: application fields for SiC & GaN power devices

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COMPETENCES IN POWER DEVICES

The two most interesting materials to build WBG power devices are silicon carbide (SiC) and Gallium Nitride (GaN). Although their use is still small today, the projected sales growth for these devices is between 50 and 80% for the next 5 to 10 years. SiC is the preferred material for device ratings in excess of 600 volts with applications in hybrid/ electric vehicles, solar inverters and industrial power supplies, while GaN is expected to dominate low voltage applications due to it’s low switching loss with a focus on DC/DC converters/ commodity power supplies and motor drives.

Figure 2: (right) HEMT structure as overgrown by Fraunhofer Institute for Applied Solid State Physics (IAF)

GaN cap layer

25nm

GaN:nid

Figure 3: (below) AFM image by Fraunhofer (IAF)

400nm

GaN:C

1050nm

AlN interlayer

25nm

GaN:C

710nm

AlN interlayer

AN ALTERNATIVE PRODUCTION APPROACH While the SiC power devices are manufactured from bulk SiC wafers, GaN devices are made on Si wafers with epitaxial grown GaN, a lower cost method than building the devices from bulk GaN. The main challenge in manufacture of GaN on Si substrates is the high lattice strain at the GaN / Si interface which necessitates an AlN buffer layer for subsequent GaN crystal growth. While this layer is traditionally made by MOCVD , sputtered AlN has recently made inroads due to the significantly lower cost over MOCVD. Compared to MOCVD deposition, sputtering of AlN enables higher deposition rates and the amount of cleaning cycles in the MOCVD reactor can be reduced dramatically. Furthermore the pit density in the GaN MOCVD is reduced by the AlN PVD buffer layer and hence results in a higher yield.

3nm

AlGaN barrier 25%

25nm

GaN:C

550nm

Al0.25Ga0.75N

550nm

Al0.65Ga0.35N

300nm

Al0.83Ga0.17N

250nm

AlN

100nm Si (111)

FILM DATA OF SPUTTERED ALN OVERGROWN WITH ALGAN: XRD FWHM 00.2 (tilt) of 0.127º Surface roughness comparable to reference (RMS<0.2nm) 2DEG depth 35.0nm Nmin ≈ 1013/cm3 Vth ≈ -3.3V Ns ≈ 5·1012 /cm2

HARDWARE INFORMATION Standard soft etch-module Heated chuck in the process module at T>800ºC with good uniformity (<40ºC) Standard AlN deposition hardware (cathode) for full face deposition Temperature-characterization in Transfer-Module

Figure 4: CLUSTERLINE® 200 II

THE PVD SOLUTION IS READY TO IMPLEMENT A manufacturing solution already used in the LED market for GaN on Si is also now ready to be deployed to the power device market. Process integration work with focus on 8” Si wafers is ongoing with multiple partners. The sputtered AlN buffer layers represent savings in MOCVD capacity of > 20%.

Data of sputtered AlN buffer layer: FILM PROPERTIES (100NM ALN ON SI) Deposition Rate (nm/s)

0.2

Thickness Uniformity

± 3.5%

Film Stress (GPa)

0.6 (tensile)

XRD Rocking Curve AlN (002)

< 2500arcsec

XRD Rocking Curve GaN (102)

Comparable to MOCVD AlN buffer

Roughness (AFM, rms)

< 1nm

“SiC and GaN look set to grow rapidly”

LAYERS2016

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