FRAUNHOFER INSTITUTE FOR PHOTONIC MICROSYSTEMS CENTER NANOELECTRONIC TECHNOLOGIES
ANNUAL REPORT 2012/2013 1
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FRAUNHOFER IPMS-CNT ANNUAL REPORT 2012/2013
Fraunhofer Institute for Photonic Microsystems Center Nanoelectronic Technologies IPMS-CNT Königsbrücker Str. 180 01099 Dresden Germany Phone: +49 351 2607-3001 Fax: +49 351 2607-3005 contact@cnt.fraunhofer.de www.cnt.fraunhofer.de
Fraunhofer Center Nanoelectronic Technologies is a business unit of:
Fraunhofer Institute for Photonic Microsystems IPMS Maria-Reiche-Strasse 2 01109 Dresden Germany Phone: +49 351 8823 - 0 Fax: +49 351 8823 - 266 info@ipms.fraunhofer.de www.ipms.fraunhofer.de
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PREFACE
Director: Prof. Dr. Hubert Lakner
Dear Readers, Friends and Partners of the Fraunhofer Institute for Photonic Microsystems, The Center for Nanoelectronic Technologies (Fraunhofer CNT) was founded as R&D facility in 2005 with an initial equipment invest of over 80 Mio €. The focus of Fraunhofer CNT was on manufacturing and process innovations based on 300 mm silicon wafers for two key players in the Silicon Saxony region. With its fab-like process and analytical equipment placed in an industrial clean room environment Fraunhofer CNT heavily contributed to innovations in nanoelectronics such as the introduction of high-k materials into high performance transistors and the optimization of copper metallization processes. New analytical methods such as atom probe tomography were first evaluated for semiconductor applications on industrial level at Fraunhofer CNT. With the changes in the Saxon microelectronic landscape in 2009, Fraunhofer CNT had to re-adjust its R&D portfolio and broaden its industrial customer base. In recent years the income from industrial revenue was continuously growing and has reached a volume of almost 4 million € in 2012. With the integration of the Fraunhofer CNT as business unit in the Fraunhofer IPMS from January 1st, 2013 this transition period has been finished. Today IPMS-CNT experts work in three focus areas: Nanopatterning, High-K Devices and Interconnects - all related to silicon processing on 300/200 mm wafers. Additional services provided to our customers are structuring of glass substrates, testing of consumables and evaluation of semiconductor processing equipment supported by nanoanalytic methods. One of the research topics are hafnium-based ferroelectrics, enabling CMOS compatible, highlyscaled, ultra-low power non-volatile memory. We are proud that this development work was accepted for highest impact scientific journals and presented at VLSI and IEDM conferences. Have a closer look on our latest research results on the following pages. Our team is always ready to share our ideas and thoughts with you. Contact us – we are ready to bring your R&D ideas to life.
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Executive Board
Center Nanoelectronic Technologies (IPMS-CNT)
Administration
Business Development & Strategy
Active Microoptical Components & Systems
Spatial Light Modulators
Quality Management
Wireless Microsystems
Facility Management & Infrastructure
Sensor & Actuator Systems
Interconnects Engineering Nanopatterning High-k Devices
Test & Reliability
Analytics Fabrication
STAFF
Scientists
FUNDING
25
PhD Students
5
Engineers
9
Management & Administration
Industrial Projects
42%
Public Projects (national)
20%
10
Fraunhofer Basic Funding 19%
49
Public Projects (EU)
1%
Other Research Projects
18%
Total Budget
8.8 Mio. â‚Ź
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BUSINESS MODEL & INFRASTRUCTURE
Competence Areas
History and Mission Fraunhofer Center Nanoelectronic Technologies was founded in 2005 as public private partnership with AMD and Infineon Technologies and has been integrated as business unit of Fraunhofer IPMS in 2013. The business areas of Fraunhofer IPMS-CNT include
INTERCONNECTS
NANOPATTERNING
ANALYTICS
HIGH-K DEVICES
the development of processes and materials as well as the physical and electrical characterization of highperformance logics, derivates (e. g. embedded DRAM) and memory technologies for volatile and non-volatile devices. In close cooperation with industrial partners and other R&D organizations, the objective of our institute is the development of innovative unit process solutions for nanoelectronic systems on 300 mm silicon wafers. ÂťDocking research into ManufacturingÂŤ The results are directly transferable into the production
Fraunhofer IPMS-CNT, the most advanced
processes of the semiconductor industry due to the
Fraunhofer semiconductor research facility
professional environment with industry standards. Apart from the longstanding cooperation with the semiconductor
manufacturer
GLOBALFOUNDRIES,
the institute is open for collaboration with research organizations, industrial partners, universities as well as semiconductor suppliers such as material and tool manufacturers. Fraunhofer IPMS-CNT is located in vicinity to the semiconductor
manufacturers
GLOBALFOUNDRIES,
Infineon and X-Fab. In addition, Dresden as a traditional location for microelectronics offers excellent site conditions and a vast reseach network.
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working on 300 mm silicon substrates.
Infrastructure
Fraunhofer IPMS-CNT
Fraunhofer IPMS-CNT
Products
Services
Fraunhofer IPMS-CNT uses 800 m² industrial-grade clean room space of ISO 6 (class 1000) standard which is equiped with 40 state-of-the-art clean room tools for silicon wafer processing, metrology and analytics. More than 30 experienced scientists and experts
Integrated MIM Capacitors
Development
develop novel materials, processes and nanoelectronic components
to
find
optimal
solutions
for
Technology
our
customers. Process tools and environment are designed to operate
Ferroelectric Memory
under the conditions of semiconductor manufacturing.
Equipment
The results are directly transferable into production processes of the semiconductor industry to reduce time-to-market and costs for our partners.
Evaluation Customized Nanopatterns
Workflow example: Pre-processed wafers provided by our industrial partner enter the clean room. Defined module processing takes place at IPMS-CNT. The wafers return to the customer for further processing.
Copper / low-k interconnects
Electrical Characterization
Reliability and Test
Nanoanalytics
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FRAUNHOFER INNOVATION THROUGH COOPERATION
FRAUNHOFER-GESELLSCHAFT
FRAUNHOFER GROUP MICROELECTRONICS
The Fraunhofer-Gesellschaft is the leading organization for
The Fraunhofer Group for Microelectronics (German
applied research in Europe. Its research activities are conducted
abbreviation: VÂľE), founded in 1996, combines the expertise
by 66 institutes and independent research units at locations
in the field of micro and nanoelectronics of 12 Fraunhofer
throughout Germany. The Fraunhofer-Gesellschaft employs a
institutes (plus three guest institutes) with a total of more than
staff of more than 22,000, who work with an annual research
3,000 employees.
budget of 1.9 billion euros. Roughly two thirds of this sum is
Its main focus is the preparation and coordination of
acquired through contract research with industry and publicly
interdisciplinary research projects, conducting studies and to
funded research projects. Branches in the USA and Asia serve to
assist in the process of identifying strategies.
promote international cooperation. There are four application-oriented business areas (AAL & non-profit
Health, Energy Efficiency, Mobility, Smart Living) and three
organization that takes its name from Joseph von Fraunhofer
cross-sectional business areas (Technology - from CMOS to
(1787–1826), the illustrious Munich researcher, inventor and
Smart System Integration, Communication Technologies and
entrepreneur.
Safety & Security).
The
Fraunhofer-Gesellschaft
is
a
recognized
Member institutes of Fraunhofer Group for Microelectronics:
1 2 1 3 2 4 3 5 4 6 5 7 6 8 7 9 8 10 9 11 10 12 11 13 12 13 a b a c b a c b 8
c
Applied Solid State Physics IAF Electronic Nano Systems ENAS High Frequency Physics and Radar Techniques FHR Integrated Circuits IIS Integrated Systems and Device Technology IISB Microelectronic Circuits and Systems IMS Modular Solid State Technologies EMFT Telecommunications, Heinrich-Hertz-Institut HHI Photonic Microsystems IPMS Nanoelectronic Technologies IPMS-CNT Silicon Technology ISIT Embedded Systems and Communication Technologies ESK Reliability and Microintegration IZM Associated members Digital Media Technology IDMT Open Communication Systems FOKUS Non-Destructive Testing IZFP
CLUSTERED RESEARCH IN DRESDEN, GERMANY
FRAUNHOFER IPMS-CNT ALLIANCES AND NETWORKS
Located within the leading microelectronics cluster in Europe - Silicon Saxony - Fraunhofer IPMS-CNT has a wide network of research and industry partners for advanced material and process development. More than 2,100 companies with more than 51,000 employees develop, manufacture, and promote integrated circuits, or serve as materials and equipment suppliers to the chip industry, produce and distribute electronic products and systems based on integrated circuits, or develop and promote software. In addition, Dresden is the biggest cluster of Fraunhofer facilites worldwide (12).
WHY R&D WITH FRAUNHOFER?
Fraunhofer Applied Research
• Contract research is the Fraunhofer institutes’ main field of business. • The cornerstones of our approach are guaranteed
Innovation
confidentiality, continuity in key positions, top-class facilities, reliable project management and professional
Industry
Universities
R&D for Products
Basic Research
and Services
handling of usage rights. • Professional approach towards cooperation, longstanding ties to industry and high levels of customer satisfaction.
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COMPETENCE AREA NANOPATTERNING
Team Manager NanoPatterning Dr. Christoph Hohle Phone: +49 351 2607-3013
INTRODUCTION
christoph.hohle@cnt.fraunhofer.de I n th e c o mpetenc e area N anoPatter ni ng, proc es s c apabi l i ti es we re f ur t her e n h a n c e d f or 28 nm node manufac turi ng s upport. The e-beam d irect w r it e l i th o cl u s te r c ompri s i ng a V i s tec SB3050D W VSB wri ter as well as resist tra ck , re a cti v e i on etc h and metrol ogy tool s was us ed for fl ex i bl e pat t er ning o f mu l ti p l e c us tomer s pec ifi c des i gns and l ay outs . T h ro u g h c ol l aborati ons wi th mul ti pl e partners and materi al s upplier s, novel c l e a n i n g p roc edures for wafers , adv anc ed hardmas k and res i s t concept s we re e v a l uated us i ng F raunhofer I PM S-C N T’s mos t adv anc ed 300 m m CMOS c l e a n ro o m and manufac turi ng env i ronment.Si gnifi c ant efforts we re spent in e xte n d i n g proc es s es for patter ni ng of l arge area nanoi mpri nt (N I L) m ast er s. D u ri n g th e SA B funded proj ec t “EM ERA L D ” one pos s i bl e bl oc ki ng point f or i n d u s tri a l u s age of e-Beam di rec t wri te i n C M O S manufac turi ng could be s o l ve d . D u r i ng i ntegrati on of e-beam di rec t wri te i nto the 28 nm node BEoL ma n u fa c tu ri ng fl ow of G L O BA L F O U N D RI ES, a pos s i bl e trans i s tor dam age or ma te ri a l d egradati on of underl y i ng hi gh-k materi al s by the ex pos i ng elect ron b e a m c o u l d be ex c l uded by s howi ng c ons i s tent el ec tri c al data.
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APPLICATIONS & MARKETS
DEVICE ENGINEERING & PROTOTYPING
TEST & CALIBRATION PATTERN
NANO IMPRINT MASTERS
• Device engineering • Rapid prototyping • Cell concept learning for 28 nm and beyond using maskless and flexible e-beam direct write lithography • Most advanced data prep solutions
• Customer specific manufacturing of test and calibration patterns in silicon e.g. for metrology and exposure tools
• Manufacturing of 1X nm masters for nanoimprint lithography
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NANOPATTERNING INFLUENCE OF HIGH-ENERGY ELECTRON IRRADIATION ON TRANSISTOR PERFORMANCE
Multi electron beam direct write lithography potentially offers great advantages of flexibility and process time without the need of costly masks. However, there are concerns with respect to fully integrating the technology in the development or production process at advanced nodes. Up to now, state-of-the-art variable shaped beam (VSB) tools with a single beam and lower throughput are used for the CMOS integration of e-beam lithography, mainly for the preparation of calibration or test structures and rapid prototyping applications. Since the physical phenomena of both technologies do not differ, the single beam technology can be used to simulate possible
(a) Layout
multi beam exposures in the future. The present study examined the possible change in transistor performance due to high energy e-beam exposure. Pre-processed 300 mm wafers with a product-like 28 nm BEOL stack from GLOBALFOUNDRIES, Dresden were used for the experiments. Wafers at varying process steps
(b) Exposure area
were exposed to electrons using a 50 kV VISTEC SB3050DW variable shaped electron beam direct writer at Fraunhofer IPMS-CNT in a production-like environment. Since only the energy deposition and scattering behavior of the high-energy electrons is relevant, no resist was applied before the exposure and no bake steps were performed. The layout (Figure 1a) of the test structures of interest was provided by GLOBALFOUNDRIES. Subsequently, a special data preparation step was necessary to selectively place the large exposure areas covering the test structures (Figure 1b) inside the chip (Figure 1c). These sites were set up in a checkerboard arrangement (Figure 1d) to allow comparison to non-exposed chip areas. The BEOL wafer processing was continued at
(c) Inside the chip (schematic)
GLOBALFOUNDRIES and completed with electrical testing of the wafers. The electrical performance of high-k metal gate transistors was characterized by the threshold voltage Vt, the shift of Vt under stress, the gate oxide breakdown voltage and the degradation of the drain current related to hot carrier injection. No effects have been observed for NFET devices in dependency on electron beam exposure. The following figures show some selected results for the PFET devices. The threshold voltage
(d) Wafer
(Vt) shift after stressing the device with increased operating voltage conditions is an important
1 Special dataprep for
measure of transistor degradation. The parameter measured here is the operating voltage that
dry exposure.
has to be applied to cause a shift in Vt by 5 %. In figure 2 the exposure checkerboard is visible. The cumulative probability plot for the PFET in figure 2 shows a median, which is shifted from -2.95 V to -3.15 V. This means the sensitivity to Vt shift is actually reduced. However, the spread of data is also increased. This result could be an indication of a change in trapped charges or less interface states. The breakdown voltage describes the integrity of the gate oxide. Figure 3 shows the map of the measured gate oxide breakdown voltages of an PFET gate oxide. Between the four checkerboard12
exposed wafers and the reference wafer no difference is visible. Furthermore, the cumulative probability that leakage through the oxide will occur is the same for exposed and unexposed transistors. This result is very important since it demonstrates high-energy electrons at 50 keV do not have an influence on gate oxide integrity.
2 Vt shift: measurement map (top left) PFET (bottom left)
3 Gate oxide breakdown voltage: measurement map (top right) PFET (bottom right)
Generally, no degradation of the NFET devices was observed. PFET devices showed a widening or shifting of the measurement data for some critical reliability electrical parameters. While the shift in these specific PFET parameters does not lead to device degradation, it still shows that such effects need to be considered. It may be required to incorporate countermeasures in the transistor design or manufacturing process. Furthermore, it needs to be explored if charge–reducing measures like protective diodes and more sensitive or even conductive resists can reduce the impact of the electron beam exposure. One important fact is the large area exposure applied in the present study which may not be fully representative for a true e-beam patterning. In future experiments, it is planned to pattern the transistors directly by e-beam. In general it seems unlikely that the observed effects will be an obstacle to implementing multi e-beam direct write in future technology nodes. Steidel, K.; Choi, K.-H.; Freitag, M.; Gutsch, M.; Hohle, C.; Seidel, R.; Thrun, X.; Werner, T. “Influence of high-energy electron irradiation on ultra-low-k characteristics and transistor performance”, Proc. SPIE 8680, 86801A, 2013
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NANOPATTERNING INNOVATIVE WATER BASED STRIPPING METHOD FOR THICK PHOTORESISTS
The usage of phase fluid based stripping agents to remove thick photoresists from silicon substrates was studied. Thick photoresists are required for many silicon based technologies such as MEMS patterning, 3D-Integration or backend of line (BEOL) semiconductor applications. Typical fields of application are sacrificial layers during surface MEMS patterning, masking layers during plasma etch processes or as a protection layer during electroplating of solder bumps. Although the use of thick resists is very common, their successful integration often depends on the ability to remove the resist after certain processing steps. On the one hand the resist is changing during subsequent process steps that can cause a thermally activated cross-linking which increases the stripping complexity. 1 Freeze fracture of phase fluid with globular plasmicells
2 & 3 Already applied in commercial cleaning and printing industry
1
2
3
Resist removal is also challenging after the formation of a hard polymer surface layer during plasma processes which is called skin or crust. On the other hand the choice of stripping chemistry is often limited due to the presence of functional materials such as metals which can be damaged by aggressive stripping chemistries. Finally the increasing complexity of MEMS structures requires chemistries which are able to remove resists out of groove or bridge patterns which are not directly accessible from the top of the structure. State-of-the-art resist removal uses solvents like NMP, DMSO, acetone or more aggressive mixtures based on NH4OH + H2O2 (SC1) or H2SO4 + H2O2 (piranha clean). Plasma ash processes are also industry standard, working with O2, H2 and CF4 as single gases or with mixtures of these. WORKING PRINCIPLE OF PHASE FLUIDS • Application of intelligent fluid in bath or spin on processes • Temperature, time according to cleaning task • Distribution and penetration through smallest openings due to dynamic plasmicells • Lift off of resist material • Inactivation of process by addition of DI water or isopropanol • Addition of subsequent process 4 The working principle of lisoPUR®. The layer (orange) is pentetrated, fragmented and finally lifted off from the substrate (red).
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steps possible
Silicon sample with phase fluid
Silicon sample with phase fluid + DIW clean
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Silicon reference
7 5 The graphs show the surface recovery after processing. The top graph shows the silicon sample prepared with phase fluid (without rinse), middle shows surface recovery after rinse off with DI water and below is the bare Si reference.
6 & 7 Particle measurement before and after phase fluid application (including DI water rinse and SC1 short cleaning). The research was carried out on KLA Tencor SP2 (detection between 0.12 and 1 µm) on 300 mm Si wafers with single spin process.
A D VA N TA G E S & F E AT U R E S O F P H A S E F L U I D B A S E D C L E A N I N G • Proof of concept confirmed for phase fluid based cleaning in semiconductor processing applications • Excellent resist removal efficiency leads to processing times < 5 min even for thick photoresists • Phase fluid based cleaning offers a new working principle for cleaning applications • Compatibility to semiconductor environment achieved by application of DI water rinse processes and additional SC1 cleaning if necessary • Tailoring of intelligent fluids possible for customized cleaning tasks • Physical mode of action instead of dissolving • Biodegradable, no aggressive ingredients
in cooperation with:
• Environmental friendly • Neutral pH range, NMP free • Demo runs possible at Fraunhofer IPMS-CNT, Dresden Rudolph, M.; Schumann, D.; Thrun X.; Höhne, A.; Esche, S.; Hohle, C.; "Introduction of an innovative water based stripping method for thick photoresists”, HARMNST 2013
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NANOPATTERNING MANUFACTURING OF LARGE AREA SILICON BASED NANO IMPRINT LITHOGRAPHY MASTER
N a no im pr int l i th o g ra p h y (NI L) i s k n o wn to be a patter ni ng proc es s wi th hi gh res ol uti on, hi gh t hroughput a nd low c ost s . I t b e co me s m o re a n d mo re a c ompl ementary approac h to opti c al l i thography as w ell as f or e le c t ron be a m l i th o g ra p h y (E B L). The ITRS roadmap includes imprint lithography as a "potential successor to optical lithography" (22 nm node: DRAM; 16 nm node: NAND Flash). In addition to the semiconductor industry, niche markets for NIL are growing. Roll-2-Roll NIL (R2RNIL) and rolling mask lithography (RML) enable low cost large area applications. Plasmonic nanostructures for energy enhancement for photovoltaics and wire grid polarizers for increasing energy efficiency for displays are two examples. Several applications of above mentioned technologies require large silicon masters with stitching error free patterns. NIL methods will be used to transfer the pattern from the silicon master into a polymer template (e.g. PDMS) which can be either used as flexible mold for R2RNIL or as an UV light transparent mask for RML. In general, NIL masters are fabricated using electron beam
1 300 mm wafer with exposed layout: 20 x 26 chips, 150 nm contact holes (blue = exposed) lithography. This maskless patterning technology is known to be challenging and expensive especially for smaller feature sizes (< 50 nm). Electron beam direct write can be seen as the method of choice due to the fact that only one unique and defect free master is needed. The feasibility of a large area exposure of contact holes for the manufacturing of a NIL master dealing
2 SEM images of contact holes
with a long writing time was demonstrated at Fraunhofer IPMS-CNT. For the first time, a 300 mm
at different times of writing.
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bare silicon wafer was exposed for 355 h (approx. 15 days) using a 50 kV VISTEC SB3050DW VSB e-beam direct writer in a CMOS cleanroom environment. The used wafer size is the current maximum and state-of-the-art substrate size in the semiconductor business which could be used for Si master fabrication. Figure 1 is showing the exposed area and the contact hole layout. The challenges arising from such an exposure are to guarantee a stable beam and an excellent pattern placement over the complete writing time. Additionally, a stable resist process in terms of a negligible post exposure delay in vacuum is also required to meet the specification for the CD uniformity. E-beam tool and resist parameters were evaluated. Minor linear resist degradation was observed resulting in a CD variation of 6.8 nm (3Ď&#x192;). After 325 h of exposure, the shape size correction of e-beam was not working properly. Additionally to the resist degradation, the CD variation increases slightly and the contact holes are rounding (Figure 2). A minor chip stitching in x (~70 nm) and y (~50 nm) direction was also observed which needs to be corrected with an optimized writing strategy. A flood light image of exposed wafer is shown in Figure 3. 3 Stiching error measured by CD SEM between 2 chips in x (a) and y direction (b).
It is remarkable, that the e-beam tool is stable within 325 h. Also the linear degradation of the positive tone chemically resist of 1 nm/d is respectable. In future, the multi-beam technology (ML2) will be the solution for unique large area exposures for (Roll2-Roll) NIL or rolling mask lithography applications.
Thrun, X.; Choi, K.-H.; Freitag, M.; Gutsch, M.; Hohle, C.; Paul, J.; Rudolph, M.; Steidel, K. "15 days electron beam exposure for manufacturing of large area silicon based NIL master", Mircoelectronic Engineering 110 (pp.119-122), 2013
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COMPETENCE AREA ANALYTICS
Analytics Dr. Lutz Wilde Phone: +49 351 2607-3020
Fraunhofer IPMS-CNT has established a versatile analytical facility. Our expertise ranges from
lutz.wilde@cnt.fraunhofer.de
wafer-level characterization with inline X-ray scattering methods and three-dimensional Atomic Force Microscopy to two- and three-dimensional device characterization with analytical transmission electron microscopy and atom probe tomography. Our in-line metrology enables us to determine physical and chemical properties of structures on 300 mm wafers with x-ray diffraction, angle-resolved x-ray photoelectron spectroscopy, three-dimensional atomic force microscopy, spectral ellipsometry and energy dispersive x-ray spectroscopy. Furthermore, we have facilities that allow for automatic particle inspection, classification and characterization on wafer level. All our tools for wafer level analysis are stationed in a class 1000 cleanroom environment that meets industrial standards. In our dedicated analytical laboratories we can investigate crystallographic parameters and layer structures with x-ray diffraction and transmission electron microscopy, layer composition and contaminations in one-, two- and three-dimensions with total reflection x-ray fluorescence spectroscopy, time-of-flight secondary ion mass spectrometry, energy-filtered transmission electron microscopy and atom probe tomography, two-dimensional stress and temperature distributions with Raman spectroscopy as well as pore sizes with ellipsometric porosimetry. Our expertise in a wide range of analysis methods makes us a competent partner to solve novel challenges in the field of material analysis. For example in cooperation with our industrial partners we have been investigating the temperature-dependent crystallization behavior of thin-films, the stress in MEMS structures and the atomic structure of single nano-devices on a nanometer scale.
1 Automatic particle detection and characterization at Fraunhofer CNT: Particles are mapped on a 300 mm wafer SP2 tool (insert) and subsequently imaged (left) and characterized (right) in a ReviewSEM with EDX capability.
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ANALYTICAL SERVICES
Electrode (Transducers) Piezoelectric Substrate
Surface Accoustic Wave generated and moving either directions of wafer.
10µm
Analysis of the atomic structure of a nano-device with atom probe tomography: In order to carry out an analysis like this we lift the nano-structure
Crystallization of 10 nm ferro-
out of the wafer and form it into a
electric doped HfO2 films for
nano-scale tip using our focused ion
Raman peak shift map of a
FeRAM applications:
beam. Applying a voltage of a few
powered surface acoustic wave
The
kilovolts and a laser pulse to the tip
device:
be observed by means of high-
allows for removing single ions from
Lateral resolved stress distribution
temperature x-ray diffraction at
the tip´s surface by the combined
of a surface acoustic wave device
grazing incidence.
action of the polarization induced
in operation is of high interest to
The Si-doped 10 nm thin film
by the electric field and the thermal
better understand the phenomenon
crystallizes at about 550 °C in the
movement induced by the laser.
of acoustic migration.
high symmetric cubic or tetragonal
These ions can then be projected
Because of the small dimensions of
phase transformation to the polar
onto a position sensitive detector.
the devices stress measurements with
orthorhombic
Measuring the time-of-flight of the
high lateral resolution as provided by
preserved during cooling down to
ions as well as their arrival positions
Raman spectroscopy are essential. In
room temperature. Based on these
enables us to reconstruct the atomic
addition Raman spectroscopy allows
analysis results we are able to better
structure of the analyzed volume
for a contactless measurement and
understand the ferroelectric behavior
with near atomic precision.
hence does not interfere with the
of Si doped HfO2 thin films deposited
operation of the device.
by atomic layer deposition.
crystallization
process
can
phase. Further heating leads to a phase,
which
is
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COMPETENCE AREA HIGH-K DEVICES
Team Manager High-k Devices Dr. Jonas Sundqvist Phone: +49 351 2607-3050
INTRODUCTION
jonas.sundqvist@ cnt.fraunhofer.de I n th e Hi g h-k D ev i c es group we hav e s een growth i n hi gh-k ALD being i n tro d u ce d for appl i c ati on on runni ng 150 and 200 mm bas ed I C applicat ions. T h e re fo re we are now ac ti v el y offeri ng our 300 mm l eadi ng edge high- k te c h n o l o g i es for the I C i ndus try runni ng s mal l er wafer s i z es . T h i s tre n d i s not onl y s een for hi gh-k, i t i s ac tual l y a general tren d f or ALD m a rk e t, whi c h i s forec as ted to grow at a C A G R of 35.4 % ov er t he per iod 2 0 1 2 -2 0 1 6 . O ne of the key fac tors c ontri buti ng to thi s market grow t h is t he g ro wi n g a dopti on of c omponent mi ni aturi z ati on. The G l obal A LD
m ar ket
h a s a l s o been wi tnes s i ng the growi ng us e of A L D i n I C and non- IC a p p l i c a ti o ns . (G l obal A tomi c L ay er D epos i ti on M arket 2012-2016â&#x20AC;&#x153; Inf init i R e s e a rc h , A pri l 2013). We a d d re ss al s o the non-I C market through our partners hi p w it h ot her re s e a rc h o rgani z ati ons i n Sax ony under the umbrel l a of A L D L ab Dresden, wh e re th e parti c i pati ng i ns ti tutes hav e brought together thei r ex p er t ise and i n fra s tru cture i n A L D and bey ond. We offer a uni que c ompetenc e cent re in AL D - b ri d gi ng the need for i ni ti al hi gh i nv es tment for enteri ng the f ield of AL D fo r s m al l to l arge s i z ed c ompani es . Ad d re s s i n g the needs of fas t and ac c urate el ec tri c al res ul ts for process d e v e l o p ment or fai l ure anal y s i s , the hi gh-k team at F raunhofer IPMS- CNT o ffe rs cu s tomi z ed tes t and c harac teri z ati on s erv i c es on wafer l ev el.
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APPLICATIONS & MARKETS
INTEGRATED MIM CAPACITORS
FERROELECTRIC MEMORY
ADVANCED CMOS
• Integrated capacitors from pF to µF • 3D and planar capacitor integration • High temperature and voltage stability
• Ultra-low power memory • CMOS compatible ferroelectrics • Scalability proven on 28 nm technology
• High-k / metal replacement gate • High performance transistors • Low power applications
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HIGH-K DEVICES NICKEL SILICIDE
Nickel silicide is currently implemented in state-of-the-art CMOS
The depositions were performed on a 300 mm warm-wall single
technologies to create ohmic contacts to semiconducting source,
wafer reactor (FHR ALD 300) equipped with an ICP remote
drain and gate electrodes in a so called salicide (self-aligned
plasma source operating at 13.56 MHz at a wafer temperature
silicide) process. Currently these layers are formed by depositing
of 200 °C.
metallic nickel on the cleaned silicon surface by PVD methods. Afterwards, the wafer is subjected to a thermal treatment which
Bis(N,N'-di-tert-butyl-acetamidinate)nickel(II)
induces the formation of nickel silicide faces due to a solid state
the organic metal precursor. While no growth was observed
was
used
as
reaction between metallic nickel and silicon.
with ammonia gas under the given experimental conditions, a deposition could be achieved by utilizing an ammonia plasma.
With decreasing feature size and the increasing trend for 3D-
This is attributed to the high reactivity of radicals (e.g. NH2)
integration of transistors (fin-FETs) there is an increasing need
created in the plasma which lowers the activation energy for
to conduct silicidation within contact holes with aspect ratios
the deposition reaction. Figure 1 shows an SEM cross-section
as high as 10:1, which cannot be conformally coated with PVD
of the as deposited films. The layers are relatively smooth for
techniques easily. Therefore Fraunhofer IPMS-CNT developed
metallic ALD films and closed at a thickness of roughly 15 nm,
an ALD (atomic layer deposition) process for Ni-based thin films
which is another prerequisite for a successful silicidation.
on state- of-the-art 300 mm wafer equipment. While exhibiting drawbacks in throughput, the inherent high conformality of
The deposited films show a resistivity of 90 µΩcm which is
atomic layer deposited films is a major benefit of this methods
roughly one order of magnitude higher than the bulk resistivity
allowing coating of complex substrates with high aspect ratio
value of nickel. This is attributed to the remaining impurities
features.
(e.g. nitrogen) which are also observable by the formation of a Ni3N interstitial phase after deposition, as shown by the x-ray
The main challenges in developing such an ALD process are the
diffractograms in Figure 2. These impurities can be reduced by
limited thermal budget for the deposition, which needs to be
a forming gas anneal at 300 °C, which forms a fcc nickel phase.
significantly below the onset for the silicidation reaction, and
This anneal temperature is well within the temperature range
achieving films with low impurity levels which might inhibit the
for typical silicidations and can therefore be conducted within a
silicidation. Especially oxygen is known to prevent the silicidation
standard silicidation flow which enables an easy transfer into a
due to the formation of SiO2.
semiconductor production environment. NiN3N Ni after deposition forming gas annealing
2 X-ray diffractograms of
1 SEM cross-section of
as deposited and
NiNx film.
annealed films.
S. Bönhardt "Plasma-enhanced Atomic Layer Deposition of Thin Nickel Films for Transistor Contact Applications" 13th Conf. ALD 2013
22
FERROELECTRIC HAFNIUM OXIDE
field effect transistor (FeFET) based on traditional perovskitebased ferroelectrics like PZT or SBT still has fundamental
drain current
Even though researched for several decades, the ferroelectric
P (µm/cm²)
A CMOS-COMPATIBLE AND HIGHLY SCALABLE APPROACH TO FUTURE FERROELECTRIC MEMORIES
shortcomings. Its potential, however, remains unchallenged. Unlike the current-based STT-MRAM, RRAM, PCRAM and Flash technologies the ferroelectric approach is based on a field effect and consumes the lowest power during switching. Scalability and manufacturability on the other hand still remain a major
gate voltage (V)
issue when utilizing perovskite-based ferroelectrics. Recently however, a method to engineer ferroelectricity in the well-known and fully CMOS-compatible HfO2 based dielectrics was discovered. With this ability at hand a consortium of researchers from GLOBALFOUNDRIES, NaMLab gGmbH, and Fraunhofer IPMS-CNT were able to demonstrate that the two order of magnitude scaling gap, prevailing ever since the introduction of FeFETs, is finally closed at the 28 nm technology node. As indicated in Figure 1 the world´s most aggressively
1 (a) Atomic layer deposited FE-HfO2 shows a distinct counterclockwise
scaled FeFETs were successfully fabricated using ferroelectric
Id-Vg hysteresis when implemented into a MFIS-FET stack (inset: PV-
Si:HfO2 in a 28 nm HKMG stack (TiN/Si:HfO2/SiO2/Si).
Hysteresis of MFM capacitor). (b) Gate length scaling trend of FeFETs compared to state of the art logic extracted from literature. The
Excellent 300 mm yield, switching in the nanosecond range,
device reported closes the scaling gap. (c) TEM micrographs of the
and 10-year retention were achieved with first silicon. The
TiN/Si:HfO2/SiO2/Si gate stack and the complete FeFET device showing
consortium further demonstrated endurance characteristics
steep sidewall angles as a result of extensive RIE development.
matching demands of current NVMs utilizing wear leveling.
in cooperation with:
Schroeder, U.; Mueller, S.; Müller, J.; Yurchuk, E.; Martin, D.; Adelmann, C. "Hafnium Oxide Based CMOS Compatible Ferroelectric Materials" Symposium on VLSI Technology, (pp. 25-26), 2012
23
HIGH-K DEVICES ALD LAB DRESDEN
T he pa st y e a r wa s a y e a r o f e xp a n s i o n fo r A L D L ab D res den. F our addi ti onal partners hav e dec i ded t o join A L D L a b D re s d e n : Fra u n h o fe r I P M S , Fra u nhofer EN A S,
N anex a A B and C ol natec . I n addi ti on, num erous
ne w c ust om e rs we re g a i n e d , ra n g i n g from 150 ov er 200 to 300 mm bas ed l eadi ng edge I D M s . ALD Lab Dresden also plays an active role in workshops, trade shows and conferences, especially here in Dresden at Semicon Europa and the AVS topical conference ALD 2012 (June 17-20) organized by ALD Lab member NaMLab. Fraunhofer IPMSCNT and Partners presented recent progress made in the fields of atomic layer deposition (ALD) and materials integration for novel ferroelectric for FeFET, improved reliability for 28 nm HKMG, low cost of ownership large batch furnace replacement gate technology, in depth understanding of ZrO2 DRAM capacitor dielectrics and a superior new ALD titanium precursor for TiO2. In addition, Fraunhofer IPMS-CNT has developed a number of ALD processes that have been qualified at customers around the world. Especially for high-k we have had an increasing strong interest for products on 150 and 200 mm wafers for capacitor applications (see table). Furthermore we started up PEALD process development and can now offer 3 new processes – AlN, Al2O3 and Ni (see bottom table).
Qualified High-k ALD Processes at Customer
Material
Precursors
Qualified Product
Chamber
Application
Wafer Sizes Ta2O5 HfO2
300mm
ASM Pulsar 3000
MIM Cap
HfCl4/H2O
150, 200, 300 mm
ASM Pulsar 3000
HKMG, MIM Cap, FeFET,
Jusung Eureka
FRAM
10 years’ Experience with
ASM Pulsar 3000
HKMG, MIM Cap,
Jusung Eureka
ALD.
FeFET, FRAM,Hardmask
300 mm
Jusung Eureka
MIMCap
150, 200, 300 mm
ASM Pulsar 3000
MIMCap, FRAM
ZrCl4/H2O
150, 200, 300 mm
TEMAZr/O3 TiO2 Al2O3
TMA/H2O
Jusung Eureka
TMA/O3 SiO2
by using micro and nano
TaCl5/H2O TEMAHf/O3
ZrO2
Smart systems integration
SiCl4/H2O
150, 200, 300 mm
3DMASi/O3
HKMG, MIM Cap, FeFET,
technologies & more than
Nanotechnology provider
FHR ALD300
FRAM, liner , spacer,
and system integrator for
FHR ALD300
Hardmask
high-performance surfaces
AlN PEALD
TMA/NH3
150, 200 mm
Qualification ongoing
Al2O3 PEALD
TMA/O2
150, 200 mm
Qualification ongoing
and advanced products.
4DMASi/O3
Qualified Metal and Metal Nitride ALD Processes at Customer
Research in electronic, Material
Chamber
Application
Precursors
Qualified Product
TiN
TiCl4/NH3
Wafer Sizes 150, 200, 300 mm
ASM A412 Large Batch HKMG, MIM Cap, Contact, Barrier
TaCN
TaF5/TMDS
150, 200, 300 mm
ASM A412 Large Batch HKMG, MIM Cap, Contact, Barrier
PEALD Ni
In development 150, 300 mm Ru(EtCp)2 150, 200, 300 mm
Ru
24
mechanical and optical components and their integration into miniature
FHR ALD300
Qualification ongoing
»intelligent« devices and
Jusung Eureka
On request
systems.
THE COMPETENCE CENTER FOR ATOMIC LAYER DEPOSITION (ALD) Yo ur p a r t ne r f or a pp l i e d i n d u s tri a l re s e a rc h , d ev el opment and produc ti on
A L D A P P L I C AT I O N L A B F O R • Rapid ALD precursor screening • Fundamental research on nucleation and film growth • Modeling and simulation for the optimization of equipment and processes BASIC AND APPLIED RESEARCH OF AT O M I C L AY E R D E P O S I T I O N F O R
• Materials research and development - High-k dielectrics and ferroelectrics - Metals and metal nitrides
• Head to head evaluation with conventional deposition techniques (Sol gel, PVD, CVD) • Consultation and Evaluation for Industry R&D projects
- Cu BEoL barrier/seed - Hardmasks for high aspect ratio etching - Backside passivation and transparent conductive oxides (TCO) for next generation photovoltaic devices
• Technology transfer to industry partners • Novel ALD precursors, materials and technologies scaled up from laboratory to pilot production : - Environmental, safety and health (ESH)
Research & Development Production
- Manufacturability - Productivity / low cost of ownership
20k 2k 200
A P P L I C AT I O N • Micro- and Nanoelectronic devices
20 -96
-72
-48
-24
0
24
Volmume [Wafer]
200k
2
Months
• Diffusion barriers for organic electronics (OLED) • Renewable energy sources, Energy storage and harvesting • Industrial coatings for wear and corrosion protection • Spintronic devices
TECHNOLOGIES
• MEMS • Antimicrobial coatings for soft materials • Antifungal coatings
• Thermal ALD, plasma enhanced ALD, thermal flash ALD and molecular layer deposition (MLD)
• Low friction coating for medical applications
• Large batch, shower head and cross flow ALD reactors
• Filters, long experience of anodisation of aluminium to make
• Solid and liquid precursor vaporisation and injection
filters and nano-structures
systems • In-situ metrology (QMS, QCM, Q-MACS, ellipsometry, XPS, AFM, STM) • Analytics
25
HIGH-K DEVICES ENERGY STORAGE ON CHIP INTEGRATED SUPERCAPACITORS
Progressive miniaturization of electronic devices such as of smartphones or sensors for medical, industrial and automotive applications requires smaller substrates. This drives amongst others the integration and scaling of space consuming external passive components for buffering and decoupling purposes on chip (SoC) or package (SiP) level. Simultaneously, extremely high capacitances are needed. The main parameters to increase the capacitance are on the one side the choice of an isolator material with high dielectric constant. Several high-k materials like HfO2, ZrO2 or Ta2O5 based systems are under investigation at the Fraunhofer IPMS-CNT. However, intensive material tuning is necessary to meet the electrical requirements for capacitor applications with respect to capacitance density and linearity, leakage current and reliability. On the other side the capacitor area has to be as large as possible which can be achieved by 3D integration of high aspect ratio (AR) structures. The Fraunhofer IPMS-CNT developed Si-integrated high-density capacitors based on 300 mm wafer technology aiming to buffer capacitor applications. A simplified patterning scheme using e-beam lithography and high technology dry etch processes provides structures with large aspect
2 Electrical characterization of MIM capacitors in a trench array with an AR of 6:1: (a) IV-curve normalized to a capacitor of 1μF, (b) CV-curve and (c) CT-curve.
ratio in a high package density (Figure 1a and 1b). The used capacitor stack is based on a metalinsulator-metal (MIM) structure built from Al-doped ZrO2 as dielectric and TiN electrodes. All materials are deposited by atomic layer deposition to reach highly conformal step coverage in the large aspect ratio structures (Figure 1c). The electrical characteristics show very low leakage current densities normalized for a capacitor of 1 μF (Figure 2a). Thereby, the capacitance is stable over the voltage region with a deviation smaller than 3 % (Figure 2b). The temperature stability is below 5 % (Figure 2c). These values are significantly lower compared to common ceramic capacitors. The good electrical results are complemented by a reliability over 10 years (Figure 3). The maximum capacitance reached for the AR of 6:1 (Gen2) lies around 100 nF/mm2 for the
3 Characteristic life-time to
material system which is adapted to an operation voltage of 3 V. This is a significant increase
failure in dependence of the
compared to planar capacitors (Gen1) shown in Figure 4. By increasing the AR to 13:1 (Gen3) a
electrical field for planar and
capacitance enhancement to 220 nF/mm could be achieved. The Fraunhofer IPMS-CNT forces
three-dimensional trench capaci-
also an up-scaling of the 3D capacitors (Gen4-5) either by an improved etch-process or by using
tor arrays with an AR of 6:1.
2
materials with higher dielectric constant. The outlook predicts integrated capacitors of 1 μF. 1 SEM a) cross section of a trench array with AR 13:1 filled with MIM stack and b) top down micrograph of Si trench array after silicon etch. c) TEM micrograph of a MIM stack
Weinreich, W.; Rudolph, M.; et al. "High-density capacitors for SiP and SoC applications based on threedimensional integrated metal-isolator-metal structures" IC Design & Technology (ICICDT), 2013
26
4 Capacitor Roadmap as capacitance density in dependence of the operation voltage for capacitor integration schemes.
DESIGN, ELECTRICAL CHARACTERIZATION & TEST
Addressing the needs of fast and accurate electrical results for process development or failure analysis, the High-k team at Fraunhofer IPMS-CNT offers customized test and characterization services on wafer-level.
PARAMETER-TEST & RELIABILITY
DEVICE CHARACTERIZATION
• Detailed analysis of active & passive devices • Automated / manual characterization • Study of leakage • PCM testing
mechanisms / short
• Device parameter extraction
channel effects
• Test-setup within 24 h
• Noise analysis (e.g. RTN)
• Fast testing of active/passive
• Trapping studies (e.g.
device parameters
charge-pumping)
MEMORY CHARACTERIZATION & MEMORY TEST • Characterization from
TEST CHIP CONCEPTS & DESIGN
• Design, layout and
single cell to large memory
verification of test
arrays
structures for process
• Memory reliability • Failure detection & el./phys. Characterization • Algorithms & Inhibit
monitoring & development • Pre-Stress methods • Testing w.r.t. coverage, yield and throughput
optimization / Stress pattern • Methods for memory test
• Statistical processing • Wafer-level reliability studies
CHARACTERISTIC
System compliance (ECC,Iddmax...)
PROPERTIES • Short implementation and
Reliability
setup times • Fast availability of first data • Fully automated
Costs Time to market
characterization of wafers • High device statistics and statistical data-processing
Data Rate
Current consumption
• Wide test temperature range from -55 °C up to 200 °C
Test (coverage, yield, Dft)
27
COMPETENCE AREA INTERCONNECTS
Team Manager Interconnects Dr. Romy Liske Phone: +49 351 2607-3040 romy.liske@cnt.fraunhofer.de
INTRODUCTION Advanced metallization remains a challenging R&D topic T h e u s e o f c opper i n the s emi c onduc tor i ndus try as a wi ri ng m at er ial re v o l u ti o n i z ed the metal l i z ati on proc es s and c ontri buted s ubs tant ially t o l a u n c h fa s t er, s mal l er and l ow energy c ons umi ng dev i c es . O n o n e h and, thi s progres s c an be attri buted to new proc es s technologies, wh i ch a l l o w produc i ng c ompl ex mul ti l ay ered i nterc onnec ts ; and on t he ot her h a n d to th e el ec tri c al properti es of the materi al s thems el v es leading t o p e rfo rm a n c e i mprov ement of dev i c es . W i th i n th e s c ope of dev i c e manufac turi ng, i nterc onnec t downscaling is d e e me d a tec hnol ogy dri v er. W hi l e i t i s c l ear that trans i s tor pe r f or m ance i n tri n s i ca l l y i mprov es wi th geometri c al s c al i ng, i nterc onnec t pe r f or m ance d o e s n o t. Therefore, tremendous efforts are bei ng made to de velop new i n te rco n n ec t materi al s and proc es s es . B e s i d e s d o wns c al i ng, new tec hnol ogi es c urrentl y ari s e that c omprise on- chip fu n c ti o n a l iz ati on by i ntegrati ng pas s i v es or anal og dev i c es i n i n t erconnect levels.
28
UNIT PROCESS DEVELOPMENT
PROCESS AND MATERIAL CHARACTERIZATION
PASSIVES IN INTERCONNECTS
SCREENINGS
ELECTRICAL MEASUREMENTS
ANALOG DEVICE INTEGRATION
FEASIBILITY STUDIES
MODELING AND SIMULATION
ON-CHIP FUNCTIONALIZATION
APPLICATIONS & MARKETS
ULTRA-LOW-K INTEGRATION
LINER DEPOSITION
ECD ELECTROCHEMICAL COPPER
• Cleaning • Repair • Characterization
• Material Stacks • Deposition Processes • In-situ Composition Analysis
• High Performance Dual Damascene • Bump Plating • Integration
DEPOSITION
CMP CHEMICALMECHANICAL PLANARIZATION
• Metal and Dielectric Planarization • Process Development • Characterization • Modeling & Simulation
29
INTERCONNECTS INTEGRATION AND CHARACTERIZATION OF ULK MATERIALS
Due to keeping up with miniaturization, increase of performance and reduction of power usage, the traditionally used dielectric to isolate the metal wirings changed from silicon dioxide to materials with lower relative permittivity (commonly called kvalue). Nowadays, ultra-low k (ULK) dielectrics with k-values in the range of 2.5 to 2.0, compared to 3.9 for SiO2, are used. Introduction of these materials came with challenges for their integration and characterization. In the Interconnects group at the Fraunhofer IPMS-CNT we focus on ULK related topics like: • Minimizing ULK damage during the patterning process
2 Left: RC plot of a metal 2 layer from a conventional Fab flow and with ULK repair process introduced at Fraunhofer IPMS-CNT. Right: Corresponding via leakage plot.
• Developing new methods of wet cleaning for integrated ULK materials • Research on ULK repair processes (for restoration of the k-value) • Advanced characterization of ULK dielectrics (TEM techniques, porosimetry, FTIR, …) The degradation of the k-value of ULK materials during the patterning process by dry etching is a well-known challenge in today’s BEOL processing. During the plasma etch step methyl groups are removed in the trench sidewalls leaving behind dangling bonds.
3 TEM image of ULK material integrated in several layers of copper wiring.
properties. New integration schemes (like the use of metallic 1 SEM cross section through a
hard masks) can be introduced to minimize these damages.
copper line embedded in ULK.
However, this leads to aggravated requirements for the
The white margin indicates
subsequent wet clean process. Additionally, novel process steps
the etch damage leading to a
can be introduced to restore the k-value of the ULK dielectric by
degradation of the electrical
means of liquid, gaseous or plasma ULK repair.
properties.
The cleaning and low-k repair process of etched ULK patterns Those are susceptible to the formation of OH groups which in
introduced at the Fraunhofer IPMS-CNT leads to improved
turn leads to a much more hydrophilic nature of the material.
electrical parameters compared to the standard process. The
Adsorption of water is now possible and results in an increased
RC product as well as the leakage current could be considerably
effective k-value of the dielectric, degrading its electrical
lowered.
Uhlig, B.; Gerlich, L.; Liske, R. "The Bigger Picture: Fraunhofer CNT’s BEOL Applied Research" Future Fab Intl. Volume 42, 2012
30
31
INTERCONNECTS ADVANCED COPPER DIFFUSION BARRIERS
Today, a processor die contains more than 3.5 km of copper interconnects on 1 cm² with increasing tendency. Small changes in material properties are influencing the performance and power consumption of processor dies. There are two reasons, why copper and dielectric materials are not in direct contact but separated by a thin barrier/liner film (Figure 1). First, the barrier prevents copper and oxygen diffusion, and second, the liner works as an adhesion layer between these two parts. As the barrier/liner does not improve the electrical performance of the wiring system, it should be as thin as possible. That means it should exhibit highest quality in terms of adhesion,
2 EDX-TEM map of a CVD liner in dense sub-50 nm structures.
resistance and conformity at lowest possible film thickness. In the future, those demands are neither achieved with PVD (physical vapor deposition) processes nor with the conventional materials. One possible solution is CVD (chemical vapor deposition), which provides high quality and very conformal films (Figure 2). The possibility of tuning the chemical structure allows a further variation of the liner properties and therefore optimization potential even for the narrowest structures.
Cu-wiring Liner Barrier Surrounded by ILD
3 SEM images of progress steps for 1 Cross section of a via/trench structure with liner and barrier.
direct on liner Cu plating.
After barrier/liner deposition usually a thin copper seed film has to be deposited by PVD to enable electrochemical copper deposition. An alternative for seed deposition is to use the liner for direct plating or as seed layer enhancement. This technique has the advantage of offering wider via and trench openings for the subsequent copper plating process (Figure 3). Potential liners for seedless plating are cobalt and ruthenium. Those liners also exhibit higher conductivities than the conventional tantalum liner. As a result, the thinner barrier/liners can be fabricated exhibiting a better overall performance. Gerlich, L.; Ohsiek, S.; Klein, C.; Geiß, M.; Friedemann, M.; Kücher, P.; Schmeißer D. "Interface engineering for the TaN/Ta barrier film deposition process to control Ta-crystal growth" Microelectronic Engineering: Volume 106, (pp. 63–68), 2013
32
HIGH PERFORMANCE COPPER ECD
Copper wires can be described as electrons’ highway, where clock signals are distributed and power is provided to the embedded circuits on a chip. In order to support high-bandwidth and low power signaling together with longest endurance, from a material’s point of view the copper simply needs to be perfect. That means the copper itself must be as pure and defect-free as possible. Every impurity, grain boundary or pin hole can lead to inelastic electron scattering, which leads to performance degradation. Therefore, the electrochemical copper deposition is the process of choice, as it provides highly pure and crystalline copper.
1 SEM of Time-resolved structure filling a) without
2 Ion induced (FIB) contrast image of crystalline copper
Superfilling b) supported by Superfilling.
in narrow line.
However, the electrochemical copper deposition poses two challenges. One is to deposit copper in smaller and smaller structures. For the 28 nm technology node, pattern widths of 32 nm provide minimal space for metallization stacks, which consist of barrier and seed layers in addition to the copper itself. The copper deposition process needs to be tuned to bottom-up, high performance copper filling. The other challenge is thick copper deposition, which is required for global wirings, bumps or 3D integration. Pattern sizes are in the tens of micrometer range. Besides the copper quality, the deposition rate is an important process parameter, since a reduced process time directly translates into lower process costs.
Liske, R.; Wehner, S.; Preusse, A.; Kuecher, P.; Bartha, J.W. "Influence of Additive Coadsorption on Copper Superfill" Behavior, Journal of The Electrochemical Society, 156, 12, (H955-H960) 2009 Liske, R.; Preusse, A.; Wehner, S.; Kücher, P.; Bartha, J.W. "Electrochemical Copper Deposition in sub-100-nm Interconnects – Results for a New Model" Advanced Metallization Conference AMC, 2008, San Diego CA, USA, Conference Proceedings, XXIV, IIB.1, 2009
33
INTERCONNECTS PLANARIZATION CHALLENGES
The enhanced global and local planarity of the interconnect structures drive significant yield improvements. Therefore, chemical mechanical planarization (CMP) is one of the key processes in IC fabrication. To meet future process specifications a better understanding of the relevant mechanisms affecting planarization is needed. Fraunhofer IPMS-CNT offers all possibilities for enhancing actual and developing new CMP processes. Depending on the application, the interaction of numerous variables such as applied pressure, relative velocity between pad and wafer, pad (roughness, hardness, elastic modulus, etc.) and slurry characteristics are investigated. Therefore, 300 mm process, metrology and analytic tools for CMP related experiments are available, including an industry standard polisher (Applied Materials Reflexion LK), mobile slurry systems, particle inspection (KLA-Tencor SP2) an ellipsometer (KLA Tencor FX 100), a profiler (KLA Tencor HRP-340), an AFM (Veeco X3D-AFM), a 4-Point-Prober (KLA Tencor RS-100), (FIB-)SEM, TEM and further tools for film and structure characterization. This setup allows us to develop complex CMP processes
1 CMP equipment at the Fraunhofer IPMS-CNT:
step by step. The planarization performance is systematically
Applied Materials Reflexion LK.
2 Structures used for process characterization. (a) density field, (b) pitch field, (c) combined densitypitch field, white: up-regions, black: down-regions.
Bott, S.; Rzehak, R.; Vasilev, B.; K端cher P.; Bartha, J.W. "A CMP Model Including Global Distribution of Pressure" IEEE Transactions on Semiconductor Manufacturing Vol. 24 No.2 (pp. 304-31), 2011
34
examined on dedicated CMP test wafers. Using in house developed analysis routines, the influence of consumables on the planarization behavior is studied. Likewise, novel CMP modeling approaches are a powerful tool for achieving an enhanced process understanding, therefore
enabling
new
integration
paths,
precise
design rules with fill strategies and cost effective process development. The Fraunhofer IPMS-CNT has great know-how in the characterization of planarization processes with the help of patterned CMP test chips. The data collected is used to build up chip and feature scale CMP models, which are capable of simulating the planarization process. Such calibrated models can be used on real production layouts to identify hot spots and support smart fill strategies or suggest design changes before the production of the mask sets. 3 Confocal measurements of a conditioner (top) and a 1mm² conditioned pad sample (down).
Vasilev, B.; Bott, S.; Rzehak, R.; Bartha, J.W. "Pad roughness evolution during break-in and its abrasion due to the pad-wafer contact in oxide CMP" Microelectronic Engineering, Vol. 111, (pp. 21-28), 2013
35
EVENTS & EDUCATION
WoDiM 2012 17th Workshop on Dielectrics in Microelectronics June 25 - 27, 2012 in Dresden, Germany Fraunhofer IPMS-CNT was the organizer of the 17th conference on physics, technology and characterization of dielectric materials for microelectronic application with more than 120 international experts. WoDiM 2012 Audience
www.wodim2012.com
20 Years Fraunhofer in Dresden In 2012, Dresden celebrated its 20th anniversary with 1800 employees, guests of honor and politicians. In 1992, four former GDR research facilities where associated to Fraunhofer, since then Dresden has evolved to the largest research site of Fraunhofer in Germany with 12 institions. www.dresden.fraunhofer.de Dr. Stanislav Tillich (Governor)
Trade Fairs Scientists from Fraunhofer IPMS-CNT presenting their latest research results and connect with existing and new industry partners all year round (e.g. Semicon Europe, Analytica). www.cnt.fraunhofer.de > Events
Fraunhofer CNT at Semicon Europe
Night of Sciences Every year scientists from Fraunhofer IPMS-CNT explain their work to interested children and grown-ups during the Night-ofSciences in Dresden. An Event with 35000 visitors and on more than 130 locations within the city of Dresden. www.wissenschaftsnacht-dresden.de IPMS-CNT scientists at the Night of Sciecnes
36
Industry Partner & Research Day Since 2009, Fraunhofer IPMS-CNT has been organizing its annual event with representatives from leading companies and research institution in nanoelectronics as well as policians to reinforce cooperation and to exchange the latest research results. www.cnt.fraunhofer.de > Events > Research Day Dr. Dina Triyoso (Globalfoundries)
Colloquia Fraunhofer IPMS-CNT has organized 60 colloquia on material and process optimiziation as well as analytics with experts and scientists from all over the world since 2007. www.cnt.fraunhofer.de > Events > Colloquia
Dr. Amal Chabli (CEA Leti)
Promotion of young scientists Fraunhofer IPMS-CNT is engaged in various activities to foster junior scientific staff such as talent school, job fair activities or visitor orientations. Furthermore, we strongly support our scientists in master and doctoral theses. Since 2005 fifteen master theses and nine doctoral theses have been completed in collaboration with Fraunhofer IPMS-CNT. www.cnt.fraunhofer.de > Jobs
Junior scientists in CNT cleanroom
ScientiďŹ c Committees Representatives from Fraunhofer IPMS-CNT are involved in various scientific committees as experts in their respective fields (e.g. IPMS-CNT Nanopatterning at SPIE).
Committee meeting at IPMS-CNT
37
SELECTED PUBLICATIONS
Westwood, G.; Pigliucci, A.; Oszinda, T.; Leppack, S.; Schaller, M. Aqueous fluoride residue removers for 32 nm and beyond copper ultra low-K technologies In: Ultra clean processing of semiconductor surfaces X : Selected, peer reviewed papers from the 10th International Symposium on Ultra Clean Processing of Semiconductor Surfaces, (pp. 249-252), 2012 Oszinda, T. Characterization and chemical recovery of plasma damaged porous low-k SiOCH dielectric for the semiconductor industry Dissertation, TU Chemnitz / Fraunhofer CNT, Fraunhofer Verlag, 2012 Olsen, T.; Schröder, U.; Müller, S.; Krause, A.; Martin, D.; Singh, A.; Müller, J.; Geidel, M.; Mikolajick, T. Co-sputtering yttrium into hafnium oxide thin films to produce ferroelectric properties in: Applied Physics Letters 101, Nr.8, 2012 Thrun, X.; Choi, K-H.; Freitag, M.; Gutsch, M.; Hohle, C.; Grenville, A.; Stowers, J.K.; Bartha, J. W. Demonstration of 22nm SRAM features with patternable hafnium oxide based resist material using electron-beam lithography In: Advances in Resist Materials and Processing Technology XXIX : San Jose, California, USA, 2012 Martin, D.; Yurchuk, E.; Muller, S.; Muller, J.; Paul, J.; Sundquist, J. Downscaling ferroelectric field effect transistors by using ferroelectric Si-doped HfO2 In: 13th International Conference on Ultimate Integration on Silicon, ULIS 2012, IEEE (pp. 195-198), 2012 Wojcik, H.; Kaltofen, R.; Merkel, U.; Krien, C.; Strehle, S.; Gluch, J.; Knaut, M.; Wenzel, C.; Preusse, A.; Bartha, J.W.; Geidel, M.; Adolphi, B.; Neumann, V.; Liske, R.; Munnik, F. Electrical evaluation of Ru-W(-N), Ru-Ta(-N) and Ru-Mn films as Cu diffusion barriers In: Microelectronic engineering 92 (pp. 71-75), 2012 Wojcik, H.; Junige, M.; Bartha, W.; Albert, M.; Neumann, V.; Merkel, U.; Peeva, A.; Gluch, J.; Menzel, S.; Munnik, F.; Liske, R.; Utess, D.; Richter, I.; Klein, C.; Engelmann, H.J.; Ho, P.; Hossbach, C.; Wenzel, C Physical characterization of PECVD and PEALD Ru(-C) films and comparison with PVD ruthenium film properties In: Journal of the Electrochemical Society 159. Nr.2 (pp. H166-H176), 2012 Hohle, C.; Choi, K-H.; Freitag, M.; Gutsch, M.; Rudolph, M.; Thrun, X.; Jaschinsky, P.; Kahlenberg, F.; Klein, C.; Klikovits, J. Feasibility study of optical/e-beam complementary lithography In: Alternative Lithographic Technologies IV : 12.-16.2.2012, San Jose, CA, USA. Bellingham, WA: SPIE (Proceedings of SPIE 8323), Paper 83232C, 2012 38
SELECTED PUBLICATIONS
Vasilev, B.; Bott, S.; Rzehak, R.; Kücher, P.; Bartha, J.W. A feature scale Greenwood-Williamson model predicting pattern-size effects in CMP In: Microelectronic engineering 91 (pp. 159-166), 2012 Müller, J.; Böscke, T.S.; Schröder, U.; Mueller, S.; Bräuhaus, D.; Böttger, U.; Frey, L.; Mikolajick, T. Ferroelectricity in simple binary ZrO2 and HfO2 In: Nano Letters 12, Nr.8 (pp.4318-4323) 2012 Müller, S. Müller, J.; Singh, A.; Riedel, S.; Sundqvist, J.; Schroeder, U.; Mikolajick, T. Incipient ferroelectricity in Al-doped HfO2 thin films In: Advanced Functional Materials 22, Nr.11 (pp. 2412-2417), 2012 Zhou, Dayu; Müller, J.; Xu, Jin; Knebel, S.; Bräuhaus, D.; Schröder, U Insights into electrical characteristics of silicon doped hafnium oxide ferroelectric thin films In: Applied Physics Letters 100, Nr.8, Art. 082905, 2012 Paul, J.; Riedel, S.; Rudolph, M.; Wege, S.; Czernohorsky, M.; Sundqvist, J.; Hohle, C.; Beyer, V. Introduction of zirconium oxide in a hardmask concept for highly selective patterning of scaled high aspect ratio trenches in silicon In: Thin solid films 520, Nr.14, (pp. 4527-4531), 2012 Müller, J.; Böscke, T.S.; Schröder, U.; Hoffmann, R.; Mikolajick, T.; Frey, L. Nanosecond polarization switching and long retention in a novel MFIS-FET based on ferroelectric HfO2 In: IEEE Electron Device Letters 33, Nr.2 (pp. 185-187) 2012 Tauchnitz, T. Optimierung der Grenzfläche von ZrO2/TiN in Metall-Isolator-Metall-Kondensatoren Bachelor Thesis, Hochschule Zwickau / Fraunhofer CNT, 2012 Schunemann, C.; Wynands, D.; Wilde, L.; Hein, M.P.; Pfutzner, S.; Elschner, C.; Eichhorn, K.J.; Leo, K.; Riede, M. Phase separation analysis of bulk heterojunctions in small-molecule organic solar cells using zinc-phthalocyanine and C-60 In: Physical Review. B 85, Nr.24, Art.245314, 2012 Thrun, X.; Choi, K.H.; Freitag, M.; Grenville, A.; Gutsch, M.; Hohle, C.; Stowers, J.K.; Bartha, J.W. Evaluation of direct patternable inorganic spin-on hard mask materials using electron beam lithography In: Microelectronic engineering 98, (pp. 226-229) 2012 39
SELECTED PUBLICATIONS
Jegert, G.; Popescu, D.; Lugli, P.; Häufel, M.J.; Weinreich, W.; Kersch, A. Role of defect relaxation for trap-assisted tunneling in high-K thin films In: Physical Review. B 85, Nr.4, Art. 045303, 2012 Mattern, N.; Shariq, A.; Schwarz, B.; Vainio, U.; Eckert, J. Structural and magnetic nanoclusters in Cu50Zr50-xGdx (x = 5 at.%) metallic glasses In: Materialia 60, Nr.5 (pp.1946-1956), 2012 Shariq, A.; Al-Kassab, T.; Kirchheim, R. Studying nearest neighbor correlations by atom probe tomography (APT) in metallic glasses as exemplified for Fe40Ni40B20 glassy ribbons In: Journal of alloys and compounds 512, Nr.1 (pp. 270-277), 2012 Mülller, S.; Summerfelt, S.R.; Müller, J.; Schröder, U.; Mikolajick, T. Ten-nanometer ferroelectric Si:HfO2 films for next-generation FRAM capacitors In: IEEE Electron Device Letters 33, Nr.9 (pp. 1300-1302), 2012 2013 Sah, R.E.; Kirste, L.; Kirmse, H.; Mildner, M.; Wilde, L.; Kopta, S.; Knöbber, F.; Krieg, M.; Cimalla, V.; Lebedev, V.; Ambacher, O. Crystallographic texture of submicron thin aluminum nitride films on molybdenum electrode for suspended micro and nanosystems In: ECS journal of solid state science and technology : jss 2, Nr.4 (pp. P180-P184) 2013 Weinreich, W.; Shariq, A.; Seidel, K.; Sundqvist, J.; Paskaleva, A.; Lemberger, M.; Bauer, A.J. Detailed leakage current analysis of metal-insulator-metal capacitors with ZrO2, ZrO2/SiO2/ZrO2, and ZrO2/Al2O3/ZrO2 as dielectric and TiN electrodes In: Journal of vacuum science and technology B. Microelectronics and nanometer structures 31, Nr.1, Art. 01A109, 2013 Thrun, X.; Choi, K.-H.; Hanisch, N.; Hohle, C.; Steidel, K.; Guerrero, D.; Figueiro, T.; Bartha, J. W. Effects on electron scattering and resist characteristics using assisting underlayers for e-beam direct write lithography In: Advances in Resist Materials and Processing Technology XXX : 24 - 28 February 2013; San Jose Convention Center and San Jose Marriott, California Bellingham, WA: SPIE (Proceedings of SPIE 8682), 2013 Paul, Jan; Rudolph, M.; Riedel, S.; Thrun, X.; Wege, S.; Hohle, C. Evaluation of an advanced dual hard mask stack for high resolution pattern transfer In: Advanced Etch Technology for Nanopatterning II : 23 - 27 February 2013, San Jose, California Bellingham, WA: SPIE, 2013
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SELECTED PUBLICATIONS
Steidel, K.; Choi, K.-H.; Freitag, M.; Gutsch, M.; Hohle, C.; Seidel, R.; Thrun, X.; Werner, T. Influence of high-energy electron irradiation on ultra-low-k characteristics and transistor performance In: Society of Photo-Optical Instrumentation Engineers -SPIE-, Bellingham/Wash.: Alternative Lithographic Technologies V : 24 - 28 February 2013, San Jose, California Bellingham, WA: SPIE, (Proceedings of SPIE 8680), 2013 Weinreich, W.; Wilde, L.; Müller, J.; Sundqvist, J.; Erben, E.; Heitmann, J.; Lemberger, M.; Bauer, A.J. Structural properties of as deposited and annealed ZrO2 influenced by atomic layer deposition, substrate, and doping In: Journal of vacuum science and technology A. Vacuum, surfaces and films 31, Nr.1, Art. 01A119, 2013 Weinreich, W.; Tauchnitz, T.; Polakowski, P.; Drescher, M.; Riedel, S.; Sundqvist, J.; Seidel, K.; Shirazi, M.; Elliott, S.D.; Ohsiek, S.; Erben, E.; Trui, B. TEMAZ/O-3 atomic layer deposition process with doubled growth rate and optimized interface properties in metal-insulator-metal capacitors In: Journal of vacuum science and technology A. Vacuum, surfaces and films 31, Nr.1, 2013 Yurchuk, E.; Müller, J.; Knebel, S.; Sundqvist, J.; Graham, A.P.; Melde, T.; Schröder, U.; Mikolajick, T. Impact of layer thickness on the ferroelectric behaviour of silicon doped hafnium oxide thin films In: E-MRS 2012 Symposium L: Novel Functional Materials and Nanostructures for innovative non-volatile memory devices : 14-17 May 2012, Strasbourg, France - Elsevier, 2013, Thin solid films 533 (pp. 88-92), 2013 Weinreich, W.. Herstellung und Charakterisierung ultradünner ZrO2-basierter Schichten als Isolatoren in Metall-Isolator-Metall Kondensatoren Dissertation, University Erlangen-Nürnberg / Fraunhofer CNT, Fraunhofer Verlag, 2013 Riedl, T.; Kirchner, A.; Eymann, K.; Shariq, A.; Schlesiger, R.; Schmitz, G.; Ruhnow, M.; Kieback, B. Elemental distribution, solute solubility and defect free volume in nanocrystalline restricted-equilibrium Cu-Ag alloys In: Journal of Physics. Condensed Matter 25, Nr.11, 2013
For full list of publications and full text access: www.cnt.fraunhofer.de > Publications www.publica.fraunhofer.de
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CONTACT
Fraunhofer Institute for Photonic Microsystems
How to reach us
Center Nanoelectronic Technologies IPMS-CNT By plane: Phone: +49 351 2607-3001
Bus line 77 from Dresden-Airport - bus stop Infineon.
Fax: +49 351 2607-3005
From here it is a 5-minute-walk to building 48.
contact@cnt.fraunhofer.de By car: Director
Exit freeway A4 at Dresden-Airport towards Dresden-Airport.
Prof. Dr. Hubert Lakner
Follow Flughafen-Straße which leads into Karl-Marx-Straße.
+49 351 2607-3000
Turn right at junction Karl-Marx-Straße/Königsbrücker
hubert.lakner@cnt.fraunhofer.de
Landstraße. Turn left at the second traffic light (access Infineon Süd) and go to building 48.
Head of Administration Antje Spitzer
By tram:
+49 351 2607-3006
Take the tram line 7 or 8 from the central station towards
antje.spitzer@cnt.fraunhofer.de
“Hellerau” or “Weixdorf”. Get off at the stop „Infineon Süd“. From here it is a 3-minute-walk to building 48.
Project Coordination Martin Landgraf +49 351 2607-3004 martin.landgraf@cnt.fraunhofer.de Business Development Dr. Malte Czernohorsky +49 351 2607-3032 malte.czernohorsky@cnt.fraunhofer.de
See our full process catalog: www.cnt.fraunhofer.de
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EDITORIAL NOTES
Published by Fraunhofer Institute for Photonic Microsystems Center Nanoelectronic Technologies IPMS-CNT Königsbrücker Str. 180 01099 Dresden Phone: +49 351 2607-3001 Fax: +49 351 2607-3005 contact@cnt.fraunhofer.de www.cnt.fraunhofer.de
Coordination and Layout Peter Felten Marketing & Public Relations +49 351 2607-3046 peter.felten@cnt.fraunhofer.de Photo Acknowledgement Maximilian Drescher max.drescher@gmx.net www.MaxLD.gmxhome.de For further informationen please visit; www.cnt.fraunhofer.de
© Fraunhofer Institute for Photonic Microsystems Center Nanoelectronic Technologies IPMS-CNT Dresden 2013 All rights reserved. Reproductions only with permission from Fraunhofer IPMS-CNT.
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Fraunhofer Institute for Photonic Microsystems Center Nanoelectronic Technologies IPMS-CNT KĂśnigsbrĂźcker Str. 180 01099 Dresden Germany Phone: +49 351 2607-3001 Fax: +49 351 2607-3005 contact@cnt.fraunhofer.de www.cnt.fraunhofer.de
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