WoDiM 2012 - Abstracts

WoDiM 2012 17th Workshop on Dielectrics in Microelectronics June 25 - 27, 2012 in Dresden, Germany

-Abstracts(oral presentations)

17th Workshop on Dielectrics in Microelectronics (WoDiM) June 25 - 27, 2012 in Dresden, Germany Quality Hotel Plaza Dresden - Königsbrücker Straße 121a, 01099 Dresden

The WoDiM provides an international platform for application-oriented scientists to exchange ideas and the latest experimental results covering the physics, technology and characterization of dielectric materials for microelectronic applications. www.wodim2012.com

Organization/Contact: Fraunhofer Center Nanoelectronic Technologies (CNT) Koenigsbruecker Str. 180 01099 Dresden, Germany www.cnt.fraunhofer.de Volkhard Beyer (Chairman) Peter Felten, Anke Bernhardt, Kerstin Schob Email: wodim2012@cnt.fraunhofer.de

WoDiM 2012 is supported by:

Resistance switching behaviour in Pt/Nb2O5/Ti/Pt cross-point structures with about 10 nm thick Nb2O5 films grown by atomic layer deposition and sputtering N. Aslam1, T. Blanquart2, H. Mähne3, S. Hoffmann-Eifert1, J. Niinistö2, M. Leskelä2, T. Mikolajick3 and R. Waser1 1 – Peter-Grünberg Institute (PGI-7), Forschungszentrum Jülich and JARA-FIT, Jülich, Germany 2 – Department of Chemistry, University of Helsinki, Helsinki, Finland 3–NamLab GmbH and Institute of Nanoelectronic Materials, TU Dresden, Dresden, Germany Corresponding author e-mail: n.aslam@fz-juelich.de Resistive switching random access memory (ReRAM) is considered to be a strong candidate for the next generation non-volatile memory due to low operation voltage, high operation speed, and a simple structure which promises an easy fabrication process and a high scalability. Transition metal oxide (TMO) layers are important candidates for use in ReRAMs. Recently, the focus of the studies shifted from group (IV) oxides, mainly TiO2 and HfO2, to the group (V) oxide, especially Ta2O5. [1, 2] Less research has been dedicated to Nb2O5 based devices so far. [3] In this work we studied of the resistance switching (RS) behavior of different Nb2O5 thin films integrated into micro-sized crossbar structures. For this purpose stacks of Pt / Nb2O5 /Ti (5nm) /Pt were built on Si/SiO2 substrates by means of lithography and ion-beam etching methods.

The lateral pad sizes of the active device areas varied from (1μm ×1μm) to (13µm×13µm). Nb2O5 films of 8 nm and 15 nm in thickness were deposited onto the structured Pt bottom electrodes by means of atomic layer deposition (ALD) and reactive sputtering . The thermal ALD process from 175 to 325°C was performed in an ASM-120 reactor using tBuN=Nb(NMeEt)3 and ozone as the respective precursors. [4] The reactive sputtering process from a metallic Nb target was done at a pressure of 1.1x10-3 mbar, a mass flow ratio of O2 /Ar of 0.67 and a sputter power of 200 W with no additional heating of the substrate. The as deposited films were amorphous. Some of the films were crystallized by post-annealing at 600°C in oxygen and argon atmospheres, respectively.

Fig.1. I(V) and R(V) curves for constant cycling voltage between 0.8 V and (-1.0 V) at constant positive current compliance of 1 m A for an sputtered 15nm thick Nb2O5 thin film crystallized by post-annealing in Ar atmosphere.

The RS characteristics of the Nb2O5 cross-point structures were analyzed with respect to the film deposition method, the films’ thickness, the crystalline structure and the effect of annealing atmosphere. Stable switching with various characteristics was obtained for the different films. In general, the resistance states, low resistance ONstate and high resistance OFF-state, were altered under low voltage of about ±1 V. As exemplary result Figure 1 shows the RS behavior of a (1µm)2 cell, with a 15 nm thick film of Nb2O5 prepared by sputtering and crystallized under Ar atmosphere. Figure 2 shows multilevel switching in a (1µm)2 cell with an 8 nm thick ALD Nb2O5 film which was crystallized under O2 atmosphere.

The different states, ON-state and OFF-state were observed by applying different current compliances.

Further results and details on the obtained relationships will be discussed in the presentation.

Acknowledgment: This work has been supported in parts by the European Community's Seventh Framework Programme (FP7/2007-2013) under grant agreement number ENHANCE-238409.

References [1] [2] [3] [4]

J. J. Yang et al., Appl. Phys. Lett. 97, (2010), 232102.

M.-J. Lee et al., Nature Materials 10, (2011), 625-630.

L. Chen et al., Current Applied Physics 11 (2011) 849-85.

T. Blanquart et al., Chem. Mater (2012).

Fig.2 I (V) measurements for constant cycling voltage and varied positive current compliance between 50µA to 1mA revealing multilevel switching for an ALD grown 8 nm thick Nb2O5 thin film crystallized by O2 annealing.

Voltage and temperature dependences of the BTI probabilistic occupancy model parameters.

N. Ayala, J. Martin-Martinez, R. Rodriguez, M. Nafria and X. Aymerich.

Departament d’Enginyeria Electrònica, Universitat Autònoma de Barcelona (UAB) 08193, Bellaterra, Spain.

Corresponding author e-mail: Nuria.Ayala@uab.cat.

|IDrain| (A)

(a)

References [1] M. Toledano-Luque et. al., J. Vac. Sci. Technol. B 29, 01AA04 (2011) [2] B. Kazcer et. al., IEEE IRPS 2010 pp. 26-32 [3] T. Grasser et al., IEEE IRPS 2009 pp. 33-44.

[4] J. Martin-Martinez et al., IEEE IRPS 2011 XT.4.1 - XT.4.6 [5] T. Grasser et al., IEEE IRPS 2010. pp. 16-25

2

 e@

@ c

75 º D = 10 C 0n A

I

1 0

7

C 5º

=1 I D

00

nA

7,5ºC 50nA I D=

c

0,7

-1

@ 7,5ºC c

I = D 50

0,6

0

 e@

-1 0,8

0,9

1,0

nA

-2

1,1

|VGS| (V)

Fig. 2. <τe> and <τc> as a function of |VGS| for two different measured defects (Fig. 1a.) at 7.5ºC and 75ºC. 0

20

40

60

80

100

120

140

Time (s) 0

(b)

- < c>

-2

-1

-3 -4 -5 -6

Gate Voltage

o

T=7.5 C  ID~50nA 0

5

10

-0.6V -0.9V

15

c (s)

20

-0.7V -1.0V

25

-0.8V -1.1V

30

Fig. 1. a) From the temporal ID evolution charging/discharging of individual defects can be characterized and their τc and τe measured. b) Dots: values of τc obtained for a single defect at different gate voltages. Lines: fittings to eq. 1. <τc> can be obtained from the graph slopes.

Ln(<>)

-1

Ln(1-F)

1

3

ID~50nA

5,6

5,5

ID~100nA

e

This work was partially supported by the Spanish MICINN (TEC2010-16126) and by Generalitat de Catalunya (2009 SGR-783).

Ln(<c>)

o

VGS=-0.9V T=7.5 C

5,7

The dependences of <τ> with voltage and temperature have been studied (Fig. 2 and 3). Fig. 2 shows that <τc> and <τe> exponentially decrease and increase, respectively, with the applied gate voltage. From the <τc> and <τe> temperature dependence (Fig.3), the activation energies (Ea) of the defects can be obtained. In this case similar values of Ea observed for <τc> and <τe>. The dependence laws derived from Fig.2 and 3 can be easily included in degradation models, such as the probabilistic occupancy model [4], providing an efficient technique to evaluate the NBTI damage at device operation conditions, accounting for the inherent variability of NBTI.

Ln(<e>)

In small devices, Negative Bias Temperature Instability (NBTI) produces discrete threshold voltage (VT) shifts which are attributed to the charge and discharge of single defects. This fact has revealed the stochastic nature of NBTI [1], its parallelism with Random Telegraph Noise (RTN) [2] and inspired new accurate NBTI models [3,4].

Additionally new NBTI characterization techniques based in the measurement of the individual defects have been proposed [5]. In this work a characterization of defects, attending to their stochastic behaviour, on pMOS with SiON as gate dielectric (EOT=1.7nm) and area of 0.15x0.13µm2 is presented. The evolution with time of the drain current (ID) was measured when applying -50mV at the drain, for different gate voltages (VG =-0.6V↔-1.1V) and temperatures (5ºC ↔ 125ºC). Fig. 1a shows abrupt changes in ID(t) (which imply abrupt changes in VT) as a consequence of the charge/discharge of defects in the device. Since defects can be identified by the magnitudes of the different ID steps, the behaviour of two defects is clearly distinguished in Fig. 1a (δID ≈50nA and δID≈100nA). For each defect, the time elapsed between abrupt ID changes indicates its emission or capture time (e, c in Fig. 1a). Assuming an exponential distribution for e and c, [4] their cumulative probability (F) satisfies (1) (1) Ln (1  F )   /    being <>, the only fitting parameter, the mean value of τc or τe. Then, <τ> can be easily calculated from the slope of plots as those shown in Fig. 1b.

3

Ln(<c>)

2

Ln(<e>)

1

53 8 ) =0 ,

) =0 E a( c

eV

E a( e

0

eV

VGS=0,8V

-1

ID=100nA

-2 2,6

,552

2,7

2,8

2,9

3,0

3,1 -1

3,2

3,3

3,4

1000/T (K ) Fig. 3. <τe> and <τc> versus temperature. Similar activation energies are obtained for both times.

Resistive Switching in Amorphous Zinc-Tin-Oxide S. Murali1, J.S. Rajachidambaram2, S.-Y. Han2, C.-H. Chang2, G.S. Herman2, and J.F. Conley, Jr.1 1 - School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR USA 2 - School of Chemical, Biological, and Environmental Engineering, Oregon State University, Corvallis, OR USA corresponding author e-mail: jconley@eecs.oregonstate.edu Resistive random access memories (RRAM), also known as memristors, are being considered as a potential next-generation replacement for non-volatile flash memory [1]. Thin film transistors (TFT) based on transparent wide bandgap amorphous oxide semiconductors (AOS) such as indium-gallium-zinc-oxide (IGZO) [2] and zinc-tin-oxide (ZTO) [3] are rapidly approaching commercialization as a replacement for amorphous Si in high performance macroelectronics applications such as liquid crystal displays (LCDs). Both IGZO and ZTO have good electron mobility, show good TFT performance, have high transparency, and can be processed at low temperatures. Recently resistive switching has been reported in IGZO [4, 5], opening the possibility of large area electronics with embedded transparent memory. In this abstract, we demonstrate bipolar resistive switching (RS) using solution deposited amorphous ZTO as the active switching material.

The ZTO active switching layer was deposited via solution deposition. A standard metal-insulator-metal (MIM) crossbar configuration with Pt as a bottom electrode and Al as the top electrode was used for electrical testing. We find that a gradual-forming (GF) process, in which the compliance current on the initial SET operation is incrementally increased until the first bipolar switching occurs, produces greatly improved RS characteristics (Fig. 1). Note that bipolar RS is observed only with an initial negative bias SET operation, suggesting a role for an interfacial layer at the Al/ZTO interface. A retention plot of HRS and LRS resistance vs. time is shown in Fig. 2(a). A resistance window of greater than 102 is sufficient for memory applications and a simple extrapolation suggests that the resistance window will remain viable for 10 years.

Conduction appears to be Ohmic in both the LRS as well the HRS at low negative bias, indicated by near unity slopes on a plot of log |current| vs. log |voltage| (not shown). For the HRS at higher negative bias, just below the SET operation, a significant increase in slope

indicates that a different conduction mechanism becomes dominant. Analysis suggests that Schottky emission is dominant in this region. Schottky conduction involves emission over a barrier, which also points to a role for an interfacial barrier in these devices [6,7].

The median resistance of the HRS and the LRS for devices with over a two-orders of magnitude range in area is shown in Fig. 2(b). The inverse dependence of the HRS resistance on the area combined with the relative lack of area dependence for the LRS resistance is consistent with a filamentary model for RS. In summary, bipolar RS was observed in the AOS ZTO. A significant advantage of ZTO over IGZO is that ZTO does not require In or Ga, two elements which are becoming increasingly expensive. Al/ZTO/Pt crossbar devices show switching ratios greater than 102, long retention times, and good endurance. RS in these devices is consistent with a combined filamentary / interfacial mechanism. Overall, ZTO shows great potential as a low cost material for embedding memristive memory with TFT logic for large area transparent electronics.

Supported by the Office of Naval Research through 200CAR262, the National Science Foundation through DMR-0805372, and ONAMI.

Fig. 1. Plot of log |current| vs. top electrode voltage for 50 μm x 50 μm device with an operating CC of 150 μA (a) without the GF process and (b) with a GF CC of 250 nA.

Fig. 2. (a) HRS and LRS resistance vs. time for a 50 μm x 50 μm device. (b) Plot of the median HRS and LRS vs. device area (error bars indicate minimum and maximum values)

References [1] D.B. Strukov, G.S. Snider, D.R. Stewart, and R.S. Williams, Nature 453, 80 (2008).

[2] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, Nature 432, 488 (2004).

[3] H.Q. Chiang, J. F. Wager, R. L. Hoffman, J. Jeong, and D. A. Keszler, Appl. Phys. Lett. 86, 013503 (2005).

[4] C.H. Kim, Y. H. Jang, H. J. Hwang, C. H. Song, Y. S. Yang, and J.H. Cho, Appl. Phys. Lett. 97, 062109 (2010).

[5] M.-C. Chen, T.-C. Chang, C.-T. Tsai, S.-Y. Huang, S.-C. Chen, C.-W. Hu, S.M. Sze, and M.-J. Tsai, Appl. Phys. Lett.

96, 262110 (2010).

[6] H.Y. Jeong, J. Y. Lee, S. -Y. Choi, and J. W. Kim, Appl.

Phys. Lett. 95, 162108 ( 2009).

[7] L.J. Brillson and Y.C. Lu, J. Appl. Phys. 109, 121301 (2011).

Temperature dependence of the Resistive Switching-related gate currents in ultra-thin high-k based MOSFETs A. Crespo-Yepes, J. Martin-Martinez, R. Rodriguez, M. Nafria, and X. Aymerich Departament d’Enginyeria Electrònica, Universitat Autònoma de Barcelona (UAB) 08193, Bellaterra, Spain.

Corresponding author, Phone: (+34) 93 581 35 21, e-mail: Albert.Crespo@uab.cat Gate dielectric breakdown (BD), one of the most important failure mechanisms in CMOS technologies [1], can be a reversible phenomenon in ultra-thin Hf based high-k gate dielectric. Thus, two interchangeable conductivity states (which differ in several orders of magnitude) can be reached in the dielectric when applying the proper stress scheme and the current during the BD transient is limited [2]. A change between different dielectric conduction states also characterizes the resistive switching (RS) phenomenon, usually investigated in MIM/MIS capacitors with a thick insulator for nonvolatile memory applications. Similarities between RS and BD/recovery mechanisms have been reported, suggesting that they can actually have the same origin [3].

In this work, the temperature dependence of the RSrelated gate currents in ultra-thin Hf based high-K dielectric is studied.

The samples were pMOSFETs with FUSI gate electrode and a dielectric stack (EOT=1.9 nm) formed by a 2.9 nm HfSiON film on top of a 1.2 nm SiO2 interfacial layer. The transistors channel length was 0.35 µm whereas the channel widths ranged from 1µm to 0.15µm.

The samples were subjected to a stress sequence which consisted in a current-limited ramp voltage stress (CL-RVS), to provoke the dielectric BD (i.e. change from the low to the high conductivity state or BD state) plus a stepped ramp voltage (S-RVS) without current limitation, to recover the dielectric (i.e. switch back to the low conductivity state, R state). S-RVS can be viewed as a series of short CVS with increasing voltage that allow BD recovery in a reasonable testing time, and to evaluate the injected charge to recovery, QR [4], which is obtained as the addition until the first recovery event of the injected charge during the different steps of the S-RVS. Both CL-RVS and S-RVS were applied to the gate with the other the terminals grounded. The iterative sequence was repeated for many cycles at increasing temperature.

Fig. 1 inset shows IG measured at 25ºC in a pMOSFET during the S-RVS of the 2ond, 3rd and 10th test

cycles. At the BD state (provoked by the previous CL-RVS), IG is larger than in the fresh device. However, a fast current drop of several orders of magnitude is observed, which indicates the BD recovery. This switch between a high and a low conductivity states in the dielectric is observed for many iterations and is qualitatively repetitive from sample to sample [3]. Fig. 1 shows the QR distributions measured on the same sample when the temperature was increased from 25ºC up to 75ºC, 125ºC and 175ºC after 20 cycles of the stress sequence. QR dispersion increases with the temperature.

Moreover, a clear decrease of the mean value of QR with temperature is also observed. It has been established that the harder the BD event, the larger QR [4], so that, the results suggest that smoother BD path is created at higher temperatures during the current-limited BD [5]. Thus, increasing temperature favors the switching to the low conductivity state. Fig. 2 shows the IG measured with cycling at VG=-0.5V after the BD transient (IBD, red circles) and after the BD recovery (IR, open circles).

Though the current through the BD path is approx. constant within each of the isothermal cycles sets, the post-BD IG decreases with temperature, which indicates smaller conductivity in the BD path after the BD transient. Contrarily, at the R-state, no temperature dependence is observed on the post-R IG. The results show new features of the gate stack conduction switching, which could be very useful for the development of models to describe the BD reversibility.

This work has been partially supported by the Spanish MICINN (TEC2010-16126 and TEC2010-10021E) and the Generalitat de Catalunya (2009SGR-783).

Fig. 1: Statistical distributions of the QR registered during cycling on the same sample, obtained from the gate current registered during the S-RVS (inset), to provoke the BD recovery (R-state). Temperature was increased every 20 cycles.

Fig. 2: IG evolution with cycling after BD transient (red circles) and after BD Recovery (open circles). Every 20 cycles temperature was increased 50ºC, starting from 25 until 175ºC. Blue lines indicate the mean values at each temperature.

References [1] J. Sune, et al, Microelectronics Reliability, vol 45, pp 18091834, 2005.

[2] W. H. Liu, et al., IEDM, pp 1-4, 2009.

[3] A. Crespo-Yepes, et al., ESSDERC, pp. 138-141, 2010.

[4] A. Crespo-Yepes, et al, IEEE TDMR, vol. 11 (1), pp. 126130, 2011.

[5] A. Chen, et al, IEEE DRC, pp. 167-168, 2011.

Scaled gate stack for gate-first implant-free In0.53Ga0.47As field effect transistors M. El Kazzi,1 L. Czornomaz,1 D. Caimi,1 C. Rossel,1 C. Gerl,1 E. Uccelli,1 M. Sousa,1 H. Siegwart,1 M. Richter,1 J. Fompeyrine,1 and C. Marchiori1 1

IBM Zurich Research Laboratory, Säumerstrasse 4, CH-8803 Rüschlikon, Switzerland

Corresponding author email: mek@zurich.ibm.com

2.0

- 30 - 30 - 60 - 30 - 30

min min min min min

100 kHz

Si2p

In3d In

1.5

InO x

Ga

Si SiO x

1.0 0.5

447

444

110 105 100

Binding energy (eV)

-1.0

-0.5

0.0

0.5

[1] M. El Kazzi, et al, Microelectronic Engineering, 88, 10661069 (2011).

[2] M. El Kazzi, et al, Appl. Phys. Lett. 99, 052102 (2011) [3] L. Czornomaz, et al, 41st IEEE ESSDERC Proceedings, 219222 (2011) ; L. Czornomaz, et al, Solid-State Electronics, in press. (2012).

[4] M. El Kazzi, et al, Appl. Phys. Lett. 100, 063505 (2012) 2

2

2.5

400C 500C 500C 530C 550C

Intensity

Capacitance (uF/cm )

3.0

References

1.0

Gate Voltage (V) Fig.1. 100 kHz C-Vs characteristics of capacitors with 1 nm aSi/1 nm Al2O3/2 nm HfO2 gate stack annealed at different temperatures (EOT = 0.83nm). Inset: In3d, Ga3p and Si2p XPS core levels before (above) and after (below) 450oC anneal. The arrows indicate changes in the electrical properties and chemical composition upon thermal treatment. Dit is reduced, InOx bonds are removed and only 0.25 nm of a-Si is oxidized.

3.0

o

Annealed at 600 C - 30 min 1 MHz 100 kHz 10 kHz 1 kHz

2.5 2.0

EOT = 0.9 nm -1

10 ID/IS current (mA/um)

Experimental Semi-insulating In0.53Ga0.47As channels were grown onto InP substrates. After surface preparation, the gate stack was deposited in-situ. A 1 nm thick a-Si layer was deposited as passivating interface layer (IL) to avoid any contact between the gate oxide and the III-V channel, while a 1 nm thick Al2O3 layer was inserted as barrier layer between the a-Si IL and the 2 nm thick HfO2 top gate dielectric to suppress Si oxidation and ensure low EOT. After the deposition of 200 nm W gate electrode, the samples were annealed in N2 at different temperatures.

The evolution of the gate stack and, especially, of the InGaAs/Si interface composition was followed by in-situ XPS at each step. Thanks to the Al2O3 and to the a-Si IL (only 0.25 nm of a-Si is consumed upon the whole process) no oxidation of the III-V surface was observed.

However, due to the rearrangement of the In0.53Ga0.47As surface atoms upon Si deposition, two possible sources of Dit were detected: 1) specific interfacial bonds (As-As, Ga-Ga, In-In, etc) and 2) In-O and Ga-O within the gate oxide upon HfO2 deposition due to the segregation of the III group elements on the top of the a-Si surface.

Although the post metallization anneal removed efficiently these III-V oxide (Fig. 1), the interfacial bonds could only be partially “cured” by the thermal treatment.

We will discuss how these defects impact device performance, how their chemical nature is mirrored in the Dit(E) distribution ad how they can be minimized.

Finally, we will discuss the electrical properties of FETs having the same gate stack. The CGVG and IDVG characteristics reported in Fig. 2 are for a 25 µm long and 10 nm thick channel FET. The device exhibits 0.9 nm EOT, 5x1012 eV-1 cm-2 peak Dit, ION/IOFF ratio of 2.6x104 and a subthreshold slope of 92 mV/decade at VD = 150 mV, and a peak mobility of 1270 cm2/V.s. The frequency dispersion of the accumulation capacitance is due to gate leakage current and not to border traps in the stack.

Gate capacitance (uF/cm )

Introduction Recently we reported on the development of thermally stable gate stacks (1nm a-Si/1nm Al2O3/2nm HfO2) for III-V based metal oxide semiconductor (MOS) devices [1,2] fabricated in a gate first flow [3]. Using these composite gate stacks, In0.53Ga0.47As MOS capacitors were obtained with sub-nm equivalent oxide thickness (EOT), 0.89 nm, and low density of interface defects (Dit), 5×1011 eV−1cm−2 in mid gap and 5x1012 eV−1cm−2 close to valence band [4]. In addition, using similar but thicker composite gate stacks, we fabricated In0.53Ga0.47As field effect transistors (FETs) with similar Dit(E) distribution and peak mobility values of 1030 cm2/V.s, for a 1.3 nm EOT [3,4].

In this contribution, by combining laboratory and synchrotron high resolution X-ray photoelectron spectroscopy (HRXPS) with electrical measurements, we review comprehensively all the growth and processing steps critical to obtain low interface defect density and low EOT. Especially, we will show how optimised conditions lead to the fabrication of sub-nm EOT gatefirst, implant-free In0.53Ga0.47As FET.

1.5 1.0 0.5

-3

10

-5

10

Vd = 150 mV Vd = 1.5 V

-7

10

-1.0 -0.5 0.0 0.5 1.0

0.0

Gate Voltage (V)

-1.0

-0.5

0.0

0.5

1.0

1.5

Gate Voltage (V) Fig.2. CG-VG characteristics measured on a FET fabricated as described in ref. [4] with 1 nm a-Si/1 nm Al2O3/2 nm HfO2 gate stack on a 10 nm semi-insulating In0.53Ga0.47As channel. Inset: ID-VG and IS-VG characteristics on the same FET measured at VD = 150 mV and 1.5 V.

Simulating the ‘clean-up’ of III-V native oxides by ALD precursors Simon D. Elliott and Sylwia Klejna Tyndall National Institute, University College Cork, Dyke Parade, Cork, Ireland simon.elliott@tyndall.ie The use of III-V materials as the channel in future transistor devices is dependent on removing the deleterious native oxides from their surface before atomic layer deposition (ALD) of a gate dielectric. ‘Clean-up’ is the observation that the ALD precursors remove oxides from the substrate before growth of the dielectric layer. The ‘clean-up’ effect has been observed especially for organometallic precursors: trimethylaluminium (TMA) or hafnium and titanium amides [1-4]. In our first principles study we show that the mechanism underlying the consumption of III-V oxides with alkylamido precursors differs from the one taking place with TMA. Self-cleaning by TMA is shown to be governed by mobility of the methyl group, which binds to metal or undergoes oxidation, transferring electrons to the surface [5, 6]. Various elementary steps are thermodynamically competitive and lead to a surprising range of by-products. By contrast, we show that alkylamide ligands are more susceptible to decomposition on the oxide surface rather than ligand migration. We predict that the surface oxide is reduced as a result of desorption of these decomposition products (mostly dimethylamine, N-methylmethyleneimine and aziridine). This finding is supported by experimental observation of the accumulation of metallic arsenic and arsenic suboxide at the interface [2]. A ligand exchange mechanism also contributes significantly to the ‘cleanup’ effect on As oxide and the main product is tris(dimethylamino)arsenic.

We are grateful to Science Foundation Ireland for funding under the strategic research cluster “FORME – Functional Oxides and Related Materials for Electronics” http://www.tyndall.ie/forme.

1. C. L. Hinkle et al., Appl. Phys. Lett. 2008, 92, 071901.

2. T. Gougousi et al., J. Electrochem. Soc. 2010, 157, H551.

3. T. Gougousi and J. W. Lacis, Thin Solid Films 2010, 518, 2006.

4. A. Delabie et al., J. Electrochem. Soc. 2008, 155, H937.

5. S. Klejna and S. D. Elliott, J. Phys. Chem. C 2011, 116, 643.

6. M. Tallarida, Appl. Phys. Lett. 2011, 99, 042906.

Modelling the statistical distribution of properties of defects. Role of disorder.

Francisco Lopez Gejo1, Al-Moatasem El-Sayed1, Alexander Shluger1 1 - Department of Physics and Astronomy, University College London, Gower Street, London WC1E 6BT, UK corresponding author e-mail: ucapflg@ucl.ac.uk Processes such as Negative Bias Temperature Instability (NBTI) and Random Telegraph Noise (RTN) have a profound impact on the stability, performance and reliability of current (and future) MOSFET devices. They are caused by the interaction between carriers and structural point defects both at the interface and within the gate dielectric layer [1]. However a consistent, reliable microscopic model of the defects involved has not yet been developed [2].

Given the current size of devices, with thickness of the oxide in the nm range, the properties of point defects become strongly dependent in their surroundings. Two important factors are the disordered structure of the oxide, which implies that each defect has virtually unique surroundings, and the proximity of the defect to the interface region, where the electronic structure differs significantly from those of the bulk materials. Due to computational limitations, atomistic models that have been employed for simulating defects at Si/SiO2 interfaces are inevitably restricted in size [3,4]. These limitations do not allow one to explore statistical distributions of defect properties at interfaces.

We have implemented a systematic procedure for generating models of the interface up to the meso-scale (dimensions up to several nano-meters) in which statistics of properties of defects could be investigated, including both the influence of disorder and distance to the interface. This procedure has been initially applied to the study of defects in the Si/SiO2 system, but we plan to extend its application towards other relevant systems, like Si/HfO2, and Si/SiOx/HfO2. Arrays of interface models

Fig.1.Model of Pb center, showing the distribution of spin density around the 3-coordinated Si site.

are initially generated using reactive force-fields [5]. This system is subsequently characterised and divided into sub-regions of sizes which are affordable for Density Functional Theory calculations. A highly efficient implementation of CP2K package [6] is used to consider models containing several hundreds of atoms. The models of interface generated display correct distributions of oxidation states, bond length and angles.

The types of defects studied include the neutral oxygen vacancies and E' centres in the SiO2 layer, and the Pb centres at the interface, and their interaction with hydrogen (see Figure 1). Oxygen deficient centres are known to introduce long-range distortions into the surrounding SiO2 network. We demonstrate that their properties are strongly affected by the position inside the SiO2 layer in the Si/SiO2/Si system and by the thickness of the oxide layer. In particular the positions of defect levels in the SiO2 band gap vary typically within 1 eV. We demonstrate that levels of some of the constrained E' centres resonate with the Si states and can thus be responsible for electron trapping from Si. We thank UK's HPC Materials Chemistry Consortium, which is funded by EPSRC (EP/F067496).

This work made use of the facilities of HECToR, the UK's national high-performance computing service, and Legion, High Performance Computing Facility at University College London. We acknowledge financial support from the FP-7 European Project MORDRED.

References [1] Fleetwood D. M., Pantelides, S. T., Schrimpf, R. D. (ed.), Defects in Microelectronic Materials and Devices.Taylor & Francis (2009).

[2] Schroder D. K. Negative bias temperature instability: What do we understand? Microel. Reliability 47, 841 (2007).

[3] Van Ginhoven R. M., Hjalmarson, H. P. Atomistic simulation of the Si/SiO2 interfaces. Nucl. Instr. Methods Phys. Res. B, 255, 183 (2007).

[4] Broqvist P., Alkauskas A., Pasquarello A. A hybrid functional scheme for defect levels and band alignments at semiconductor-oxide interfaces. Phys. Status Solidi A, 207, 270, (2010).

[5] Van Duin A. C., Strachan A., Stewman S., Zhang Q., Xu X., Goddard III W. A. ReaxFFSiO Reactive Force Field for Silicon and Silicon Oxide Systems. J. Phys. Chem. A, 107, 3803 (2003).

[6] VandeVondele J., Krack M., Mohamed F., Parrinello M., Chassaing T., Hutter J. Quickstep: Fast and accurate density functional calculations using a mixed Gaussian and plane waves approach. Comp. Phys. Comm. 167, 103 (2005).

Recent trends in the electrical characterization and reliability assessment of CMOS devices G. Groeseneken, R. Degraeve, B. Kaczer, K. Martens, In this paper we review some recent examples on how established characterization techniques that were developed for silicon based devices can be completely misinterpreted when applied to Ge or IIIV based MOS-structures, and how a siâ&#x20AC;&#x201C;mple modification of the technique can ensure a correct interpretation. We also show how novel techniques, such as TSCIS (Trap spectroscopy by Charge Injection and Sensing) were developed recently to overcome the problem of dielectric material screening for logic and memory applications. With the scaling of the devices into the nanometer regime single traps are causing large variations in the device parameters, which leads to a timedependent variability, which makes lifetime analysis difficult. Finally we show that when using the classical reliability assessment methodology based on accelerated testing, the available reliability margins are strongly reduced, especially for sub-1nm EOT (Effective Oxide Thickness) devices. As a result, we argue that the reliability community will have to look for alternative ways to ensure and guarantee the lifetime of future products.

Impact of both metal composition and oxygen/nitrogen profiles on PMOS Vt for gate last HKMG Klaus Hempel, Robert Binder, H.-J. Engelmann, Elke Erben, Joachim Metzger, Pavel Potapov, Christopher Prindle, Dina H. Triyoso and Andy Wei GLOBALFOUNDRIES Dresden, Wilschdorfer Landstrasse 101, Dresden 01109, Germany corresponding author e-mail: klaus.hempel@GLOBALFOUNDRIES.com As transistor size continues to shrink, SiO2/polySi has been replaced by high-k/metal gate to enable further scaling. Two different integration approaches have been implemented in high volume production: gate first and gate last, the latter is also known as replacement gate approach. In both integration schemes, getting the right threshold voltage (Vt) for NMOS and PMOS devices are critical. Particularly for gate last approach, Vt setting must be accomplished with the additional constraint of lower thermal budget. A number of recent studies have shown that Vt of devices are highly dependent on not just the as deposited material properties but also on subsequent device processing steps. The effective workfunction of the HKMG stack, and therefore the Vt of the devices, is defined by the workfunctions of the individual metal layers and their relative thickness.[1].

In addition, for PMOS the resulting Vt depends also strongly on the concentration of nitrogen and oxygen at the interface high k dielectric-first metal layer [2].

In order to accurately account for all of these impacts, there is a need to develop analytical methods which accurately measure material composition on device structures, rather than on unpatterned wafers. In this work we developed an advanced high-resolution EELS (Electron Energy Loss Spectroscopy) method capable of accurate measurement of material composition on device structures. Using this method we study the nitrogen and oxygen concentration at the HKMG interface on PFET transistors. We demonstrated that the required PFET Vt can be achieved by having the correct amount of nitrogen and oxygen at the HKMG interface.

The HKMG transistors are formed using gate last integration approach [3]. The metal stack consists of a very thin TiN-a layer deposited directly on the high-k dielectric. After removal of the dummy poly silicon another metal layer (TiN-b) is deposited on the high-k dielectric-TiN-a stack followed by an Al fill.

Fig.1 PFET Vt for devices processed with gate last technology. The 4 samples have different compositions of the two metal sublayers. The insert shows the Vt spread across wafer.

Fully processed devices are then measured electrically and analyzed using high-resolution EELS to determine material properties. The standard EELS method with a probe size below 0.5nm has a too low probe intensity for well measurable EELS signals. To improve the signal to noise ratio a number of line scans across the layers have been carried out and signal integration was done by an in-house developed special software.

Fig. 1. Shows Vts of samples with different composition of TiN-a and TiN-b sublayers. The very thin TiN-a layer has a strong impact on PFET Vt, but the second , thicker metal layer TiN-b modulates the Vt as well. The right combination of the two metal sublayers brings the device to Vt target. The Vt spread across wafer is shown in the insert of Fig.1. Fig.2 shows the different N and O profiles for the wafer center (higher Vt) and the wafer edge (lower Vt).

As it can be seen the resulting Vt depends as on the metal composition as on the oxygen/nitrogen profiles in the TiN-a/high k bilayer.

Since the TiN_a layer is only a few angstroms thick and it easily oxidizes, it is very difficult to have a tight control of the N and O profiles in this layer and at the interface of the high k dielectric. Maintaining a stable Vt in production environment will require tight control of queue time between deposition of metal layers.

References [1] I.S.Jeon, J.Lee, P.Zhao et al., Proceedings IEDM 2004, , p.303 [2] C.L.Hinkle, R.V.Galatage, R.A. Chapman et al., Appl.

Phys. Lett. 96, 2010, [3] K.Mistry, C. Allen, C.Auth et al, Proceedings IEDM 2007, p.247

i g .

2 H i g Fig.2 High-resolution EELS spectra for the hsample with metal stack_3. The spectrum on the left hand- side is from wafer center with higher Vt, the spectrum onr the right hand side is from the lower Vt area. The Nitrogen peak at e the high-k/TiN-a interface is more pronounced s and the Nitrogen profile stretches into the high k dielectric for the o lower Vt. l u

Characterization of MOS Interfaces based on GaN-related Heterostructures Yujin Hori1, Zenji Yatabe1, and Tamotsu Hashizume1,2 1 - Research Center for Integrated Quantum Electronics, Hokkaido University, Sapporo, Japan 2 - Japan Science and Technology Agency (JST), CREST, Tokyo, Japan corresponding author e-mail: hori@rciqe.hokudai.ac.jp positive bias range, the interface states cause stretch-out C–V curves. In the negative bias range, however, the stretch-out behavior is not observed. In this bias region, the Fermi-level is located far below the valence band maximum of AlGaN and the interface states act as negative fixed charges at the Al2O3/AlGaN interface, suggesting the difficulty for detecting the Al2O3/AlGaN interface states using the standard C–V measurement.

Figure 3 shows the photo-assisted C–V characteristics of the Al2O3/AlGaN/GaN structures with and without N2O-radical treatment. At first, we swept the gate bias from 0 to –12 V under dark condition. While holding the bias at –12 V, we exposed the sample surface to the monochromatic light with photon energies of less than the bandgap of AlGaN for 2 min. This leads to the photo-assisted electron emission from the interface states with the energy range corresponding to the photon energy (Fig. 4). After switching off the light, we restarted C–V sweeping toward 0 V. Then, we observed threshold voltage (Vth) shifts toward the negative bias direction. As shown in Fig.3 (b), particularly, the smaller Vth difference (∆Vth) between two photon energies (hν = 1.51 and 2.21 eV) indicates the lower state density at the Al2O3/AlGaN interface for the N2O-radical treated sample.

AlGaN/GaN high-electron-mobility transistors (HEMTs) are promising for high-power and highfrequency applications. An Al2O3-based MOS gate structure for AlGaN/GaN HEMTs has been recently proposed, because Al2O3 has large bandgap (~7.0 eV) and relatively high permittivity (~9.5). To obtain operational stability and reliability of MOS HEMTs, a low electronic state density at the Al2O3/AlGaN interface is necessary.

However, it is difficult to characterize the MOS HEMT structure, because it has two interfaces and extremely large time constant for electron emission from the interface states due to the wide bandgap of AlGaN (3.4 ~ 6.0 eV) Here, we report on the characterization of the Al2O3/AlGaN/GaN structures using a rigorous simulation and a photo-assisted capacitance-voltage (C–V) method.

Figure 1 schematically shows the Al2O3/AlGaN/GaN structure. At first, we formed a ring-shaped ohmic electrode on the AlGaN surface, followed by annealing at 800 oC for 1 min in N2 ambient with a SiN surface protection layer [1]. After removing the SiN film, we carried out an N2O-radical treatment. A 20nm-Al2O3 film was then deposited by atomic layer deposition. Finally, a circular gate electrode was formed.

Figure 2 shows calculated C–V curves of the Al2O3/AlGaN/GaN structures with and without assuming the electronic states at the Al2O3/AlGaN interface. We found that typical C–V curves include two characteristic features in the positive and negative bias regions. In the Ti/Al/Ti/Au ohmic electrode

ALD-Al2O3 25nm-Al0.26Ga0.74N i-GaN sapphire

2DEG

2

Capacitance (nF/cm )

Ideal

Ideal

400 300 200

-8.5

-8

-7.5

100 0 -12

CAl2O3 with interface states CAl2O3

+AlGaN

-8

without treatment ∆ Vth = 1 V 200 hν = 2.21 eV

100 1.51

Fig.1. Schematic illustration of the Al2O3/AlGaN/GaN structure.

500

[1] Y. Hori et al, Jpn. J. Appl. Phys. 49 (2010) 080201.

Capacitance (nF/cm2)

Ni/Au gate electrode

Reference

-4 0 4 Gate voltage (V)

8

Fig.2. Ccalculated C-V curves of the Al2O3/AlGaN/GaN structures with and without the interface states.

0

-12

(initial)

-10

N2O-radial treatment ∆ Vth = 0.5 V 2.21 eV 1.51

(initial)

-8 (a)

-6 -4 -12 -10 -8 -6 -4 (b) Gate voltage (V) Fig.3. Photo-assisted C-V characteristics of the Al2O3/AlGaN/GaN structures (a) without and (b) with the N2O-radical treatment.

(VG = -12 V)

hν

photo-assisted electron emission

hν < EG EF

Al2O3 / AlGaN / GaN

EC

EV Fig. 4. Schematic illustration of the band diagram of the Al2O3/AlGaN/GaN structure at V G = -12 V.

Impact of plasma treatment on leakage current density of TiO2/RuO2 based DRAM capacitor.

B. Hudec1, K. Hušeková1, J. Dérer1, R. Rammula2, A. Kasikov2, T. Uustare2, J. Aarik2 & K. Fröhlich1 1 - Institute Of Electrical Engineering, Slovak Academy of Sciences, Dúbravská Cesta 9, 84104 Bratislava, Slovakia 2 – Institute Of Physics, University of Tartu, Riia 142, Tartu, 510 14, Estonia corresponding author e-mail: boris.hudec@savba.sk TiO2-based dielectrics are considered as potential candidates for a future DRAM capacitors [1, 2], which should exhibit high capacitance and safe leakage current value (77 fF/m2 and 10-7 A/cm2) at physical thickness of 7 nm, according to ITRS [3] for 20 nm node. Their key advantage is a very high dielectric constant. In our previous work [2] we have reported the κ-value of 160 for undoped TiO2 dielectric in rutile phase, which was stabilized by adopting RuO2 bottom electrode as a seed layer. However, maintaining low leakage current levels is quite challenging as the band gap value of rutile-phase TiO2 is only around 3 eV. One of the key aspects of leakage performance of Pt/TiO2/RuO2 MIM capacitors studied in this work is the quality of its interfaces. Important technological step in fabrication of these structures with low leakage current densities is the plasma treatment. It has been shown in our previous studies [4] that the plasma treatment of RuO2 bottom electrode in Ar/O2 gas mixture prior to TiO2 dielectric layer deposition reduces the leakage current density of such capacitors by almost two orders of magnitude. Similar results were obtained by other authors using O2 or N2 plasma treatment for TiHfO [5] and TiO2 [6] dielectric oxides in MIM structures.

The RuO2 bottom electrodes were prepared by MOCVD on SiO2 substrates at 290 °C [1]. The TiO2 films were grown by ALD at 400 °C using TiCl4 and H2O as precursors. Pt top electrodes were prepared by e-beam vacuum evaporation at room temperature using shadow mask. Finally samples were annealed in O2 at 300 °C. Prior to deposition of the dielectric, the RuO2 bottom electrodes were treated by plasma generated in the 20%

O2/Ar gas mixture at a pressure of 0.3 mbar. Variation of plasma power and treatment time resulted in different leakage characteristics as shown in Fig. 1. Thickness of TiO2 in this experiment was 16 nm while the corresponding Capacitance Equivalent Thickness (CET) was 0.55 nm. As seen from Fig. 1, lowest leakage was obtained for highest plasma power used for 2 minutes.

With the increase of treatment time from 2 to 4 minutes, the leakage increased.

Results obtained for MIM capacitors prepared using plasma treated RuO2 and undoped TiO2 as a dielectric are summarized in Fig. 2. Safe leakage is obtained even for CET as low as 0.46 nm.

To evaluate the role of plasma treatment, X-ray photoelectron spectroscopy (XPS) and reflection high energy electron diffraction (RHEED) studies were performed. XPS did not reveal significant changes in the stoichiometry of RuO2 but according to RHEED data the formation of rutile phase was faster and/or more uniform on plasma-treated RuO2 electrodes than on untreated electrodes.

This work was supported by the Slovak grant agency APVV (project APVV-0509-10), VEGA (project 2/0147/11), Estonian Science Foundation (project 7845).

References [1] [2] [3] [4] [5] [6]

Fröhlich et al.: ECS Trans., 41 (2) 73 (2011).

Han et al.: Appl. Phys. Lett., 99, 022901 (2011).

ITRS 2011: http://www.itrs.net Fröhlich et al.: Microelectron. Engin., 88, 1525 (2011).

Cheng et al.: IEEE EDL, 29 (10), 1105 (2008).

Wu et al.: IEEE EDL, 33 (1), 104 (2012).

1E-5

1E-2 tphys = 16

CET = 0.55 nm

1E-6

1E-7

nm

2

w/o plasma 4 min 50% 2 min 50% 2 min 75% 2 min 100%

Current density @ 0.8V [A/cm ]

2

Current density (A/cm )

1E-4

ITRS DRAM voltage ITRS leakage limit

1E-8

1E-9 0.0

1E-3

samples with various plasma treatments plotted in Fig. 1

1E-4

ITRS target CET values

1E-5 1E-6 1E-7 1E-8

ITRS leakage limit

1E-9

0.2

0.4

0.6

0.8

1.0

1.2

Voltage (V)

Fig.1. Bottom electrode injection leakage current of Pt/TiO2/RuO2 MIM capacitors. Various plasma treatments of RuO2 bottom electrode before dielectric deposition.

0.35

0.40

0.45

0.50

0.55

CET (nm)

Fig. 2: Leakage current density at 0.8 V bias vs. CET achieved for Pt/TiO2/RuO2 capacitors. Grey curve is a guide for an eye.

Trapping properties of AlGaN/GaN based ferroelectric-semiconductor heterostructures R.B. Han, H.Z. Zeng, W.B. Luo, Z.H. Wang, Y. Lin, Y.R. Li State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, People’s Republic of China Corresponding author e-mail: zenghz@uestc.edu.cn (H.Z. Zeng) Very recently, the growth of ferroelectric BaTiO3, Pb(Zr,Ti)O3 (PZT), and LiNbO3 (LNO) materials on GaN-base systems have been successfully demonstrated.

The unique features of ferroelectric gate materials, such as polarization modulation and dielectric tunability, are promising for novel field effect devices. Unfortunately, the charge traps at ferroelectric-semiconductor interfaces cause the gate leakage reducing the effect of ferroelectric modulations, even a highly undesirable current collapses in GaN-base devices. Therefore it is crucial to understand the properties of trap states, especially in a quantitative way, for the control and optimization of the interface between ferroelectrics and GaN-base semiconductors.

In this report we adapt the frequency-dependent conductance method to study the trapping properties of ferroelectric LNO/AlGaN/GaN heterostructures.

Ferroelectric LNO layer was deposited onto the AlGaN/GaN heterostructures by pulsed laser deposition.

The ferroelectricity of LNO was confirmed by the piezoresponse force microscopy and capacitance-voltage measurements, respectively.

Frequency dependent capacitance and conductance were measured using an impedance analyzer. To evaluate the trapping properties quantitatively, the conductance measurement was performed as a function of frequency and bias voltage in a wide temperature range, as shown in Fig. 1. The density, energy level, and time constant of charge traps are determined by a model modified from Nicollian and Brews, which shows a good consistent with the experimental data.

The density of interface traps is evaluated to be (1.4-7) ×1010, (1.2-3.4) ×1011 and (3.2-11) ×1011 cm−2eV−1 at 450, 300 and 200 K, respectively. The densities of bulk traps

are remained at around (1-4) ×1010 cm−2eV−1.

The measured time constants of the interface traps increase from about 1 ms to 1 μs with increasing the dc bias, while the time constants of the bulk ones maintain at around 1 μs, especially at the high temperature. For the interface traps, an exponential dependency of time constants on the bias dependencies is evident. On the contrary, the bulk traps display the features of deep-level traps whose time constant is insensitive to the bias field.

The interface trap density of our LNO/AlGaN/GaN heterostructures is much smaller than that of PZT/AlGan/GaN, about 1012 cm−2eV−1, and is comparable with that of Al2O3/AlGaN/GaN/Si MOSHFET. The less influence of LNO films on the trapping effect than the PZT is attributed to similar crystal structures of LNO and GaN. The optimal annealing processes also help to suppress the interfacial charge traps. Considering GaNbase materials have a relative large defect density, our measurements of the traps suggest that the ferroelectric LNO gate may provide GaN-base field-effect transistors a reasonable device performance with additional modulation effects and/or memory effect by ferroelectric polarizations.

In summary, frequency-dependent conductance method is adapt to quantitatively characterize the charge traps of ferroelectric/AlGaN/GaN heterostructures. Both the interface traps and bulk traps were identified in LNO/AlGaN/GaN. The annealing process and the crystals similarity of LNO and GaN are helpful to reduce the interface trap densities between ferroelectrics and GaN semiconductors.

Financial supported from Natural Science Foundation of China under Grand No. 51002023 is acknowledged.

References

Fig. 1. Frequency dependent conductance measurement of LiNbO3/AlGaN/GaN heterostructures at the temperatures of 200, 300 and 450K. (Symbols are experimental data, and lines are fitting curves.)

[1] P. Kordos, R. Stoklas, D. D. Gregusova, and J. Novak, Appl.

Phys. Lett. 94, 223512 (2009).

[2] P. J. Hansen, Y. Terao, Y. Wu, R. A. York, U. K. Mishra, and J. S. Speck, J. Vacuum Sci. Tech. B 23, 162 (2005).

[3] T. P. Ma and J. P. Han, IEEE Electron Device Lett. 23, 386 (2002).

[4] I. Stolichnov, L. Malin, P. Muralt, and N. Setter, Appl. Phys.

Lett. 88, 043512 (2006). 536 (2004).

[5] E. H. Nicollian and J. R. Brews, MOS Physics and technology (Wiley, New York, 2003).

[6] M. A. Khan, X. Hu, A. Tarakji, G. Simin, J. Yang, R. Gaska, and M. S. Shur, Appl. Phys. Lett. 77, 1339 (2000)

Recent progress and current status of dielectrics for DRAM Woongkyu Lee, Jeong Hwan Han, Woojin Jeon, and Cheol Seong Hwang* WCU Hybrid Materials Program, Department of Material Science & Engineering and Inter-university Semiconductor Research Center, Seoul National University, Seoul 151-744, Korea corresponding author e-mail: cheolsh@snu.ac.kr The recent progress in the metal-insulator-metal (MIM) capacitor technology is reviewed in terms of the materials and processes mostly for dynamic random access memory (DRAM) applications. As TiN/ZrO2Al2O3-ZrO2/TiN (ZAZ) type DRAM capacitors approach their technical limits, there has been renewed interest in the perovskite SrTiO3 (STO), which has a dielectric constant of > 100, even at a thickness ~ 10 nm. However, there are many technical challenges to overcome before this type of metal-insulator-metal (MIM) capacitor can be used in mass-production compatible processes despite the large advancements in atomic layer deposition (ALD) technology over the past decade. In the meantime, rutile structure Al-doped TiO2 (ATO) films might find space to fill the gap between ZAZ and SrTiO3 MIM capacitors due to their exceptionally high dielectric constant among binary oxides and very low leakage current. [1] Achieving a uniform and dense rutile structure is the key technology for the TiO2-based dielectrics, which depends on having a dense, uniform and smooth RuO2 layer as bottom electrode. Although the Ru (and RuO2) layers grown by ALD using metal-organic precursors are promising, recent technological breakthroughs using the RuO4 precursor made a thin, uniform and denser Ru and RuO2 layer on a TiN electrode. A minimum equivalent oxide thickness (EOT) as small as 0.44 nm with a low enough leakage current was confirmed from an ATO film.

The recent development of novel group II precursors made it possible to increase the growth rate largely while leaving the electrical properties of the ALD STO film intact. This is an important advancement toward the commercial applications of these MIM capacitors to DRAM as well as to other fields, where an extremely high

Figure 1 shows the summary of recent extensive works on minimizing EOT of ATO films while maintaining the safe leakage current density (< 10-7A/cm2 @ 0.8 V). It can be understood that the minimum EOT of 0.44 nm can be achieved. However, further decrease in EOT abruptly increases the leakage current density suggesting that alternative dielectric films with even higher dielectric constant, such as STO, is really necessary to achieve an EOT < 0.4 nm. However, massproduction worthy ALD processes of STO films are yet to be developed even with the extensive research during the past decade. This is mainly attributed to the difficulty in appropriate control of deposition process in very thin thickness region, which is further complicated by the complex interaction between the growing film and substrate. In addition, the substrate (bottom electrode) must have a compatible crystal structure with STO, suggesting that SrRuO3 (SRO) might be necessary.

However, ALD of SRO is one of the most difficult, even more difficult than STO, ALD processes of oxide materials.

Therefore, in this talk, the authors review the problems and tasks that need to be overcome for the production of DRAM capacitors with design rules ~ 20 nm, and present recent progresses in dielectric and electrode processes. This will contain the review on the processes and properties of ATO/RuO2 and STO/SRO (or STO/Ru) combinations.

-3

ATO(HJH) ATO (Boris)

-4

ATO (250 ) ATO + TiO2

-5

ATO + TiO2(270 )

This work was supported by the IT R&D program of MKE/KEIT [KI002178, Development of a mass production compatible capacitor for next generation DRAM ], Converging Research Center Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2011K000609).

-6

ATO (280 ) ATO+PDA

References

-2

10

TiO2

10 2

Leakage Current @0.8V (A/cm )

capacitor density and three dimensional structures are necessary.

10 10 10

[1] Seong Keun Kim, Sang Woon Lee, Jeong Hwan Han, Bora Lee, Seungwu Han, Cheol Seong Hwang, â&#x20AC;&#x153;Capacitors with an Equivalent Oxide Thickness of <0.5 nm for Nanoscale Electronic Semiconductor Memoryâ&#x20AC;?, Adv. Func. Mater., 20, 18, 2989 (2010)

-7

10

-8

10

-9

10

3

4

5

6

7

8

EOT ( )

Fig.1. Plot of leakage current density measured at 0.8 V as a function of equivalent oxide thickness of ATO and ATO/TiO2 films. Bottom and top electrodes are RuO2 and Pt, respectively.

Unipolar, bipolar and complementary switching in metal oxides D. Ielmini Dipartimento di Elettronica e Informazione, Politecnico di Milano, piazza L. da Vinci 32 â&#x20AC;&#x201C; 20133 Milano, Italy e-mail: ielmini@elet.polimi.it.

Resistive switching in metal oxides is attracting a wide interest for possible application in future non-volatile storage [1]. Resistive switching memory (RRAM) devices may take advantage of fast switching [2], high endurance [3] and good scalability. Different materials and switching modes have been considered so far, including unipolar switching [4] and bipolar switching [5-7]. Most recently, complementary switching was introduced as a possible scheme to avoid sneak paths in passive crossbar arrays [8,9]. This talk will discuss the switching mechanisms and technology issues for unipolar, bipolar and complementary switching modes.

Fig. 1a shows typical I-V characteristics for HfOx-based RRAM featuring bipolar switching [9]. The bipolar switching effect was attributed to ion migration and valence change within a localized conductive filament (CF) in the metal oxide [6,7]. Ion migration is accelerated by temperature and field, thus explaining the voltage-driven kinetic of the set/reset processes [7]. Note in Fig. 1a that the current is limited to a compliance level IC during set: this allows to control the size of the CF during switching, which dictates the set-state resistance and the reset current. Sub-ÂľA reset has been demonstrated, which is promising for the development of ultra-low power RRAM [10].

Complementary switching is naturally observed in bipolar RRAM when set transition is carried out with no IC limitation [9]. This is shown in Fig. 1b, indicating set transition to a maximum-conductance level, followed by a reset transition.

This behaviour has been explained as the migration from an ion reservoir at the top electrode toward the bottom electrode.

In this process, first the CF grows by ion migration from the top reservoir, then reaches a maximum conductance as all ions in the top reservoir have joined the CF. Further increase of the voltage results in depletion of the CF and accumulation of the conductive species at the bottom electrode. A negative voltage sweep results in similar set/reset transitions, thus recovering the initial distribution of conductive species. The physical interpretation and modelling of complementary switching was shown to follow directly from thermally-activated ion

migration, which thus allows for a unified description of bipolar and complementary switching [11]. Complementary switching allows to encode the two bits in two high resistance states, thus it is highly attractive as a technological solution to achieve passive crossbar arrays with no selector [8,9].

Fig. 1c shows unipolar switching characteristics of the same HfOx device shown in Fig. 1a and b. In unipolar switching, both set and reset transitions take place at the same (e.g., positive) polarity. The coexistence of unipolar, bipolar and complementary switching suggests an active role of ion migration in all these switching modes, at least in HfOx. Unipolar switching allows the use of unipolar (e.g., p-n) diodes as selector, contrary to bipolar RRAM. Cycling endurance [9] and variability may however limit its applicability with respect to bipolar RRAM.

References [1] Waser, R., and Aono, M., Nat. Mater.

6 (2007) 833.

[2] Lee, H. Y., et al., IEDM Tech. Dig. (2010) 460.

[3] Lee, M.-J., et al., Nat. Mater. 10 (2011) 509.

[4] Baek, I. G., et al., IEDM Tech. Dig. (2004) 587.

[5] Beck, A., et al., Appl. Phys. Lett. 77 (2000) 139.

[6] Szot, K., et al., Nat. Mater. 5 (2006) 312.

[7] Ielmini, D., IEEE Trans. Electron Devices 58 (2011) 4309.

[8] Linn, E., et al., Nat. Mater. 9 (2010) 403.

[9] Nardi, F., et al., IEDM Tech. Dig. (2011) 709.

[10] Wu, Y., et al., IEEE Electron Device Lett. 31 (2010) 1449.

[11] Larentis, S., et al., IEEE IMW (2012) 53.

Fig. 1. Measured I-V characteristics of HfOx RRAM displaying (a) bipolar, (b) complementary and (c) unipolar switching [9]. In bipolar switching, the device is first set under positive voltage with a compliance current limitation (IC = 0.75 mA in the figure), to achieve the continuous CF state A. Then a negative voltage is applied for the reset transition to dissolve the CF (state B). If no compliance is used, the set transition results in the maximum conductance state C limited by the available conductive species.

Further increase of the voltage first leads to the accumulation of ions at the bottom electrode corresponding to the reset state D, then ultimately results in a unipolar set transition causing set state E. Unipolar set and reset between states D and E is then possible.

Considerations for further scaling of Metal-Insulator-Metal DRAM capacitors B. Kaczer1,*, S. Clima1, K. Tomida1, B. Govoreanu1, M. Popovici1, M.-S. Kim1, J. Swerts1, A. Belmonte1, W.-C. Wang2, V. V. Afanas’ev2, A. Verhulst1, G. Pourtois1, G. Groeseneken1,2, M. Jurczak1 1

imec, Kapeldreef 75, B-3001 Leuven, Belgium, 2KU Leuven, B-3001 Leuven, Belgium; *mailto:kaczer@imec.be

Future Metal-Insulator-Metal (MIM) DRAM capacitors will require dielectric films with a combination of sufficiently low equivalent oxide thickness (EOT) and low leakage. While low EOT requires adequately high dielectric permittivity ε, the leakage will be limited by the intrinsic direct-tunneling mechanism, which in turn depends on i) dielectric thickness tox, ii) Metal/Dielectric barrier Φb, and iii) tunnelling effective mass mtunnel. Here we investigate the interplay of these parameters needed to meet the requirements of future DRAM MIM capacitors.

For two dielectrics candidates TiO2 and SrTiO3 currently under development, typically grown in the (110) orientation, internal photoinjection measurements have determined the metal Fermi level to be pinned at midgap, i.e., Φb ~1.5 eV, independently of the electrode metal used [1]. The leakage in these non-optimized films has been shown to be controlled by defects ~1.2 eV and ~0.9 eV below the respective TiO2 and SrTiO3 conductionband minima (CBM). The respective mtunnel values, given in Tables I and II, have been extracted from the lowtemperature I-V dependences assuming trap-assisted tunnelling (TAT). Note that the used TAT equation implicitly assumed parabolic, i.e. E = h2k2/2mtunnel dispersion relation [2]. The higher extracted mtunnel value gives apparent advantage to the SrTiO dielectric.

To corroborate these values, calculations of complex band structure have been performed at the DFT/GGA level for both materials [3]. An example of the imaginary bands (IB) in the band gap of Sr-rich SrTiO is shown in Fig. 1. To conform to the TAT assumption, mtunnel is extracted from the IB using the parabolic approximation at the respective energy below the CBM. [1] Pawlak, VLSI’11; [2] Guan, EDL’11; [3] Demkov, PRB’05; [4] Brar, APL’96; [5] Kane, JAP’61; [6] Frőhlich, JVSTB’09, Hudec, INFOS’11; [7] Popovici, JES’10.

1

Table I: Extracted and calculated values for rutile TiO2.

For rutile TiO2(110) the thus calculated mtunnel matches well the experimental value, cf. Table I. Interestingly, other orientations are expected to yield higher, i.e., more favorable mtunnel, suggesting the importance of texture control (cf. the leakage of rTiO2(101) [6]).

Table II: Extracted and calculated values for SrTiO.

The calculated SrTiO3 mtunnel value is similar to that of TiO2 due to the conduction-band structure being controlled by the Ti sub-lattice 3d-orbitals. We speculate that excess Sr results in increased separation (dilution) of the Ti sub-lattice, due to both the increase of the lattice constant [7] and the Sr substituting Ti, cf. Table II. Finally, the significance of mtunnel and the interplay with other parameters is demonstrated in Fig. 2. Because the future vertical DRAM integration schemes may also stipulate maximum tox (e.g., 6 nm in Fig. 2), scaling may not be limited by the ability to achieve sufficiently high ε, but sufficiently high mtunnel.

3.0

Sr2TiO4

minimum ε (ε0) 100 150

2.5

-1

barrier (eV) Φb (eV)

E-E_CBM (eV)

0

-2 -3 -4 0.E+00

50

200

mtunnel = 0.1 me mtunnel = 0.2 me

2.0

mtunnel = 0.5 me

1.5 1.0 0.5 0.0

κ (m-1)

5.E+09

Fig.1: Calculated imaginary bands plotted vs. the absolute value of the imaginary component of the wavenumber κ, allowing for easier comparison between different materials. Recall that the intrinsic tunneling current is proportional to exp(-2 κ tox) [4].

Dashed red and solid green lines demarcate respectively the parabolic and the non-parabolic approximations [5].

0

5

10

15

20

25

minimum tox t(nm) minimum ox (nm)

Fig.2: Calculation of the minimum physical thickness tox required to obtain intrinsic direct-tunneling leakage of 10-7 Acm-2 at 1V and the corresponding ε value assuming EOT of 0.4 nm for different combinations of Φb and mtunnel. With Φb = 1.5 eV, the spec’d leakage can be reached with a modest ε but a high mtunnel is needed to accommodate integration requirements.

GaAs-based MOSHFETs with aluminum oxide prepared in situ by MOCVD P. Kordoš1,2, R. Kúdela1, R. Stoklas1, K. Čičo1, M. Mikulics3, D. Gregušová1, J. Novák1 1 - Institute of Electrical Engineering, Slovak Academy of Sciences, Bratislava, Slovakia 2 – Institute of Electronics and Photonics, University of Technology, Bratislava, Slovakia 3 – Peter Grünberg Institute (PGI-9), Research Centre Jülich, Germany corresponding author e-mail: peter.kordos@savba.sk Application of GaAs-based MOS structures, as a “high carrier mobility” alternative to conventional Si MOS transistors, is still hindered due to difficulties in their preparation with low surface/interface defect states [1]. However, recent studies show that an application of suitable gate insulator and passivation allows to suppress the density of defects, i.e. to prepare InGaAs channel MOSHFETs with suitable performance [2]. Here, aluminum oxide as a passivation and gate insulator was formed by room temperature oxidation of a thin Al layer prepared in situ by MOCVD. The structures were grown on a semi-insulating GaAs substrate. The In0.23Ga0.77As channel was 10 nm thick.

The channel carriers were achieved by silicon δ−doping in Al0.3Ga0.7As barrier layer separated from the channel by a 4 nm Al0.3Ga0.7As spacer. The Al0.3Ga0.7As barrier was capped by a 5 nm thick GaAs layer. Finally, thin aluminum layer was deposited in situ on top of the GaAs cap layer in order to prepare MOSHFET device structures. The Al-oxide was formed by inevitable oxidation of the Al layer at room-temperature. The oxide thickness was ~3 nm, verified by x-ray reflectivity measurements. Structures without Al layer were prepared for comparison too. The device preparation consisted of conventional processing steps, i.e. mesa formation, Ni/AuGe/Ni/Au ohmic contacts annealed at 450 °C and Ti/Pt/Au Schottky gate contacts. The MOSHFETs and HFET counterparts with a gate length of 2.5 μm, as well as fat-HFETs (LG = 100 μm) and large area capacitors (100×100 and 200×200 μm2) were prepared.

Typical static output I−V characteristics of the HFETs and MOSHFETs are shown in Fig. 1. The saturation drain

currents up to 260 and 480 mA/mm at VG = 1 V were obtained on the HFETs and MOSHFETs, respectively.

Higher saturation drain current in the MOS structures can be explained due to an increase of the sheet charge density ns and/or drift velocity of carriers vd, as IDS/WG = q⋅ns⋅vd. This indicates on high effectiveness of the in situ prepared Al-oxide as a gate insulator and passivation.

Capacitance measurements have shown significantly lower frequency dispersion of the MOS devices than of HFETs, as shown in Fig. 2. The sheet charge density for the MOS and HFET structures was (3.8−4)×1012 cm−2 and (2−2.3)×1012 cm−2, respectively. The drain-source conductance combined with the ns−VG data were used to evaluate mobility of the channel electrons. Peak values of the carrier mobility are 6050 and 4220 cm2/V⋅s for the MOSHFET and HFET, respectively. The MOSHFET mobility can be well compared with the highest value of 6155 cm2/V⋅s reported on GaAs-based MOS devices with ex situ deposited GdGa-based oxide [3].

Presented results demonstrate high capability of used device fabrication method in which the GaAs-based semiconductor structure and aluminum oxide as a passivation and gate insulator are prepared in situ by MOCVD. This work was supported by the VEGA Scientific Grant Agency (2/0098/09 and 1/0866/11) and the APVV Research and Development Agency (LPP-0162-09).

Fig.1. Static I-V characteristics of GaAs-based HFET and MOSHFET with Al-oxide as gate dielectric and passivation.

Fig.2. Frequency dispersion of capacitance for GaAs-based HFET and MOSHFET with Al-oxide.

References [1] Heyns, M. and Tsai, W.: MRS Bulletin 34, 485 (2009).

[2] Hong, M., et al.: MRS Bulletin 34, 514 (2009).

[3] Passlack, M. et al.: IEEE Electron Device Lett. 26, 713 (2005).

Development of HfO2/Al2O3 nanolaminates for MIM applications A.Lefevre1, H.Grampeix1, F.Lallemand2, U.Lüders3, W.Prellier3, G.Parat1, F.Voiron2 1 - CEA, LETI, MINATEC Campus, 17 rue des Martyrs, 38054 GRENOBLE Cedex 9, France.

2 – IPDIA, 2 rue de la Girafe, 14000 CAEN, France.

3 – CRISMAT CNRS UMR 6508, ENSICAEN, 6 Blvd Maréchal Juin, 14000 CAEN Cedex, France.

Corresponding: aude.lefevre@cea.fr Passives are of major importance in electronic devices to offer more options and more applications. Recent developments are focused on integrated passives near active part to realize a complete platform. In particular, silicon capacitors can be used throughout a wide range of applications covering such diverse functions as power decoupling, signal coupling, pump charging, DC/DC power conversion. However, the surface used for this has to be reduced maintaining high voltage breakdown and low leakage current. One way to increase the capacitance density is to change the dielectric for a dielectric with a higher k. However increasing dielectric constant also means reducing breakdown [1] and a compromise has to be found between these two values. In this study, Al2O3 and HfO2 as dielectrics were selected. These materials are mainly used to replace gate oxide in transistors. Their deposition by ALD is well controlled but studies are focused on very thin layers around few nm [2], although for our capacitor application, a higher thickness is required (around 20nm) to withstand higher voltage (> 10V) and to reduce the leakage to some nA/mm². The interest in combining these materials is to mix their advantages: the high dielectric constant of HfO2 (20) and the high breakdown field of Al2O3 (8MV/cm).

MIM capacitors were realized on 200mm wafers with polycrystalline silicon doped with phosphorus at 1020 at/cm3 as electrodes. The dielectric is deposited by ALD in an ASM tool and we tuned the composition of nanolaminates. Different stacks were tested (HfO2 2nm + Al2O3 2nm) repeated 5 times noted H2A2, (HfO2 3nm + Al2O3 1nm) repeated 5 times noted H3A1, (HfO2 5nm + Al2O3 5nm) repeated 2 times noted H5A5 and (HfO2 1nm + Al2O3 1nm) repeated 10 times noted H1A1 for a constant total thickness of 20nm. Dielectrics are characterized by X-Ray Reflectivity (XRR), SIMS, ATR-

FTIR and TEM. Devices are characterized by electrical measurements: variation of capacitance and dielectric losses vs. different bias and frequencies, and leakage variation vs. applied voltage.

Deposition process was first optimized on blank wafers to evaluate the number of cycles necessary for each stack. ATR-FTIR (see figure 2) did not show any crystallization of the nanolaminates, XRR and TEM confirmed the nanolaminate structure obtained by ALD deposition even for the H1A1 stack, but TEM also highlighted the oxide interlayer between silicon and dielectric. The capacitance measurements were performed on various capacitors surfaces to deduce the dielectric constant (See Fig. 3). The stack H3A1 presents a k-value of 12, and a k-value of 10 for the others stacks. Up to 15V, the capacitors were not degraded with low leakage.

Some differences were noticed, depending on the number of interfaces or on the dielectric thickness of the nanolaminate.

To conclude, we realized integrated MIM capacitors on silicon with standard microelectronic processes according to our specifications. We showed that individual properties of Al2O3 and HfO2 layers could significantly be enhanced thanks to their integration in nanolaminates. High k values of 10 to 12 and high breakdown field were achieved for a dielectric stack thickness of only 20nm. We can still optimize these devices by working on the silicon interface with dielectric to reduce the oxide interlayer.

References [1] J. McPherson, J. Kim, A. Shanware, H. Mogul and J. Rodriguez : IEDM, 633 (2002) [2] Cho et Al(2002) Applied Physics Letters, 81 (6), pp. 10711073 .

0.16

Hf-O

ATR Absorption (a.u.)

0.14 Al-O

0.12 #1(H2-Al2)x5 #2(H3-Al1)x5 #3(H5-Al5)x2 #4(H1-Al1)x10

0.1 0.08 0.06 0.04 0.02

Si-O

0 1300

1200

1100

1000

900

800

700

600

Wavenumbre (cm-1)

Fig.1. TEM on (3nm of HfO2 + 1nm of Al2O3) repeated 5 times (Total thickness = 20nm).

Fig.2. ATR-FTIR on samples: no crystallization of HfO2 and Al2O3.

Fig.3. Capacitances in nF versus surface in m² for the different stacks

An investigation of charge trapping in metal/high-k/In0.53Ga0.47As metal-oxidesemiconductor capacitors Jun Lin1, Yuri Y. Gomeniuk1,2, Scott Monaghan1, Karim Cherkaoui1, Eamon O’Connor1, Ian Povey1 and Paul K. Hurley1.

1 - Tyndall National Institute, University College Cork, Lee Maltings, Prospect Row, Cork, Ireland 2 - Lashkaryov Institute of Semiconductor Physics, 41 Prospect Nauki, 03028 Kiev, Ukraine jun.lin@tyndall.ie indicating that the trapping is predominantly localized as a line charge near the high-k/In0.53Ga0.47As interface.

These observations provide strong evidence that the charge trapping is taking place predominantly at the interface transition layer between the high-k oxide and In0.53Ga0.47As, which can contain native oxides of Ga, In and As [4]. The CV hysteresis width is observed to increase linearly with the maximum gate bias (see Figure 2), ruling out the possible contribution of a ferroelectric behavior, as reported recently for doped HfO2 layers on silicon [5]. Further results will be presented covering the unidirectional CV analysis of permanent charge trapping, and on the temperature-dependence of the CV hysteresis.

In summary, metal/high-k/In0.53Ga0.47As/InP MOS capacitors exhibit both electron and hole trapping with permanent and temporary charge trapping contributions.

The interfacial transition layer between the high-k oxide and In0.53Ga0.47As has the greatest influence on this charge trapping phenomenon.

The authors would like to thank Science Foundation Ireland for financial support of the project (09/IN.1/I2633, the INVENT project).

References

1st CV hysteresis sweep 2nd CV hysteresis sweep

0.014

Capacitance Density (F/m2)

Capacitance Density (F/m2)

[1] R. Engel-Herbert et al., J. Appl. Phys., 108, 124101 (2010) [2] G. Brammertz et al., Appl. Phys. Lett., 95, 202109 (2009) [3] E. O’Connor et al., Appl. Phys. Lett., 94, 102902 (2009) [4] R.D. Long et al., J. Appl. Phys., 106, 084508 (2009) [5] J. Müller et al., Appl. Phys. Lett., 99, 112901 (2011) 0.012 0.010

Cfb=0.01 F/m

2

0.008

upwards

0.006

delta V =0.35 V

0.004 0.002 -1.5

-1.0

-0.5

downwards 0.0 0.5

(a)

1.0

Gate Voltage (V)

1.5

1st CV hysteresis sweep 2nd CV hysteresis sweep

0.014 0.012 0.010 0.008

Cfb= 2 0.0096F/m

0.006 delta V 0.004

upwards

=1V downwards

0.002 -2.0

-1.5

-1.0

(b)

-0.5

0.0

0.5

1.0

Gate Voltage (V)

0.016 0.014

Pt/HfO2/p-In0.53Ga0.47As/InP MOS capacitor

0.012 0.010 0.008

upwards

0.006 0.004

downwards (a)

Gate voltage (V)

0.90

1.38E+13

0.75

1.15E+13

0.60

0.002 -2.5 -2.0 -1.5 -1.0 -0.5 0.0

1.61E+13

1.05

CV hysteresis (V)

Capacitance Density (F/m2)

Fig.1. CV hysteresis for (a) Pt/HfO2/n-In0.53Ga0.47As and (b) Pt/HfO2/p- In0.53Ga0.47As MOS capacitors. Note: Red line is 2nd CV sweep.

0.5

1.0

9.19E+12 (b)

Trapped charges (cm-2)

As silicon based Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) reach the limits of dimensional scaling, high-dielectric constant (high-k) gate materials in conjunction with high mobility channel materials (e.g. III-V compound semiconductors such as In0.53Ga0.47As) are being considered for future devices to improve the MOSFET performance. However, the highk/In0.53Ga0.47As MOS system exhibits a relatively high level of interface states (Dit) and fixed oxide charges (QF) [1-3], both of which induce threshold voltage shifts and degrade carrier mobility in In0.53Ga0.47As MOSFETs. Charge trapping in states located in the transition region between the high-k oxide and the In0.53Ga0.47As (referred to a “slow states” or “border traps”) is another physical process which results in device instability, but very little research relating to electron and hole trapping in the highk/ In0.53Ga0.47As MOS system has been reported in literature to date. In this work, we report on an investigation of charge trapping in metal/highk/In0.53Ga0.47As MOS capacitors analysed by capacitancevoltage (CV) hysteresis.

The studies were performed on metal/high-k/ In0.53Ga0.47As/InP MOS capacitors with either HfO2 (5nm) or Al2O3 (5nm to 20nm) formed using atomic layer deposition with Al, Pt or Pd as the metal gate electrodes.

Both n and p doped In0.53Ga0.47As epitaxial layers were used as the channel substrate to investigate both electron and hole trapping in the HfO2 film. Figure 1 shows examples of double CV hysteresis sweeps for (a) Pt/HfO2/n- and (b) p-In0.53Ga0.47As/InP MOS capacitors recorded at 1 MHz and 25oC. The measured flatband voltage shift corresponds to an electron trapping level of 5.4 x1012cm-2 for the n-type sample, and a hole trapping level of 1.5x1013cm-2 for the p-type sample. Both the electron and hole trapping levels are comparable to the estimated Dit using the approach described in [4], highlighting the importance of electron and hole trapping in the HfO2/ In0.53Ga0.47As /InP MOS system. In addition, the majority of charge trapping is observed to be a reversible process (see Figure 1). A small, non-reversible, charge trapping component is observed using unidirectional CV sweeps. Moreover, it is observed that the Al gate samples with no In0.53Ga0.47As interfacial oxide layer exhibit a much lower level of charge trapping than the Pt gate samples with about 1 nm of interface oxide (from TEM analysis, not shown). Further CV hysteresis studies carried out on Pd gate /Al2O3 (5~20nm)/ In0.53Ga0.47As/InP MOS capacitors reveal a linear increase in CV hysteresis with increasing oxide thickness,

-1.4 -1.6 -1.8 -2.0 -2.2 -2.4 -2.6 -2.8

Maximum gate bias(V)

Fig.2. (a) CV hysteresis with different gate bias ranges (b) CV hysteresis as a function of maximum gate bias

Silicon quantum dots embedded in SiO2 for tandem solar cells J. López-Vidrier1, S. Hernández1, D. Hiller2, S. Gutsch2, A. Hartel2, M. Schnabel3, P. Löper3, M. Foti4, L. López-Conesa1, S. Estradé1, F. Peiró1, M. Zacharias2, S. Janz3 and B. Garrido1 1 – MIND, IN2UB – Electronics Department, Universitat de Barcelona, Martí i Franquès 1, 08028 Barcelona, Spain.

2 – IMTEK – Faculty of Engineering, Albert-Ludwigs-Universität Freiburg, Georges-Köhler Allee 103, 79110 Freiburg, Germany.

3 – ISE – Fraunhofer Institute for Solar Energy Systems, Heidenhofstr. 2, 79110 Freiburg, Germany.

4 – ST Microelectronics – Stradale di Primosole 50, 95121 Catania, Italy. corresponding author e-mail: jlopezv@el.ub.es For years, silicon solar cells have attracted the attention of the industry due to their low fabrication and commercialization costs, as well as the well investigated electronic properties of Si. However, the low band gap energy of Si (1.12 eV) makes the absorption of the high energetic part of the solar spectrum very inefficient.

Tandem solar cells are able to avoid these thermalization losses by combining two or more different band gaps.

Recent studies have focused on the performance of an allSi tandem solar cell, consisting of a bulk crystalline Si bottom cell and a top cell made of quantum confined Si quantum dots (see the scheme in Fig. 1). Thereby, theoretical conversion efficiencies up to 42.5% can be achieved [1]. Silicon nanocrystals (Si-NCs) were demonstrated to be a suitable candidate as top cell material since the quantum confinement of the charge carriers provides a tuneable bandgap energy controlled via the Si-NC size [2].

The precise control of the NC size is therefore crucial for obtaining the desired electronic properties. Many studies have been reported on superlattices of Si-NCs in SiO2, which show a good control of the multilayer thickness and the resulting NC size [3]. By means of this approach, a reliable quantum confinement of the NC size is easily achieved.

In this work, we present a complete optical, structural and electrical characterization of Si-NCs embedded in SiOx/SiO2 superlattices deposited on both Si and quartz glass substrates by means of plasma-enhanced chemicalvapour deposition. Subsequently, the samples were annealed to induce the Si quantum dot formation and

crystallization. For each sample a different Si-NC size in the range from 2 to 5 nm was chosen, corresponding to bandgap energies from 1.7 to 1.4 eV [4].

By means of a JEOL 2010 equipped with a Gatan image filter, energy-filtered transmission electron microscopy images were obtained to estimate the thickness of the deposited superlattices as well as the NC size distribution. Raman scattering spectra, acquired with a Horiba Jobin Yvon LabRam spectrometer, allowed monitoring the precipitation and crystallization of the Si excess. Using a phonon confinement model [5], we determined very high crystalline volume fractions for the Si quantum dots (i.e., only monolayer thick a-Si shells).

The evolution of the crystallinity for annealing temperatures between 950 and 1250°C will be presented.

Photoluminescence measurements clearly demonstrated the band gap energy dependence on the NC size according to the quantum confinement model [6]. Finally, the samples were metallized with Al, and the vertical electrical conductivity was measured employing an Agilent B1500 semiconductor device analyzer (with 10 fA resolution).

For the purposes of an all-Si tandem solar cell, the samples containing approx. 4 nm NCs seem to be suitable candidates for the absorber layer of the top cell.

Moreover, the high crystallinity of the quantum dots allows for a high Si/SiO2 interface quality (i.e., few dangling bond defects). Thereby, the exciton lifetime is long enough to allow for charge carrier separation rather than ultrafast non-radiative exciton recombination. The electrical properties will be discussed in terms of the optical and structural properties of the system.

We acknowledge the financial support from the European Commission under the Seventh Framework (NASCEnT, project number NMP4-SL-2010-245977).

References [1] [2] [3] [4] [5] [6] Fig.1. Scheme of an all-Si tandem solar cell, consisting of a quantum dot multilayer stack on the top of a crystalline Si solar cell. A tunnel junction links both structures.

Conibeer, G. et al.: Thin Solid Films 516 (2008) 6748.

Godefroo, S. et al.: Nat. Nanotechnol. 3 (2008) 174.

Zacharias, M. et al.: Appl. Phys. Lett. 74 (1999) 2614.

Hartel, A. et al.: Thin Solid Films 520 (2011) 121.

Hernández, S. et al.: J. Appl. Phys. 104 (2008) 044304.

Alonso, M..I. et al.: Phys. Rev. B 82 (2010) 045302.

Impact of temperature on the forming kinetics in HfO2 based-RRAM devices P. Lorenzi1, R. Rao1, C. Cagli2, B. De Salvo2, F. Irrera1 1 – Dipartimento fi Ingegneria dell’Informazione, Elettrica e delle Telecomunicazioni, Sapienza Università di Roma 2 – CEA-Leti Minatec Grenoble (Fr) lorenzi@die.uniroma1.it The kinetics of formation of conductive filaments in films of afnia was investigated. The study was focused on the impact of temperature and electric field on the forming time (τF). τF is related to the space covered by ions, which is proportional to the film thickness (tHK) by a factor α (smaller or greater than unity), by the relation α·tHK=(τF D)1/2, which implies τF=(α·tHK)2/D. Combining that expression of τF with D=D0 exp (-EA/kBT), one gets: τF=[(α·tHK)2/D0] exp (EA/kBT)

(1)

where kB is the Boltzmann constant, and EA is the activation energy for ion migration. We set: τ0=α tHK2/D0.

When an electric field (F) is present, a field enhancement factor modifies the diffusion coefficient. Then we write: D=D0(F)·exp (-EA/kBT) and τF=τ0(F)·exp·(EA/kBT)

(2)

Experiments were performed on MIM devices of the type Pt/HfO2/Pt. 10nm thick HfO2 films (relative dielectric constant k=20) were ALD deposited on sputtered Pt, with a prevalence of the monoclinic phase. Sample area was 0.125 µm2. Preliminary quasi static condition measurements performed at 300K outlined the occurrence of a distribution of forming voltages, with an average value of 4.2 V. To characterize τF we performed transient measurements, applying pulses with 10 ns rise time and amplitude (VP) greater than 4.2 V. Pulses were displayed on channel 1 (CH1) of an oscilloscope. The voltage drop on a resistor in series to the device under test was acquired on channel 2 (CH2). The signal displayed on CH2 allowed measuring τF. The chuck temperature (T) was increased up to 500 K and VP varied. Data of τF versus 1000/T are graphed in Fig.1. As one can see, τF varied appreciably with T and VP. An assessed theory developed for describing time-dependent-dielectric-breakdown in SiO2

-1

Vp=5V Vp=5.37V Vp=5.75V Vp=6.12V Calc

10

-3

τ=τ0·exp((ΕΑ−b F)/kB T)

The quantity b was defined as b = (2+k)·p0/3 with p0 the molecular dipole moment. In particular, assuming for p0 the value 10.4 e-Å reported in [1] for cubic HfO2, we got b=76.26 e-Å for our samples. We used eq.3 to interpolate the experimental data and the calculated curves are shown in Fig.1 with lines. Values of the parameters EA and τ0 were found to depend on the electric field and the extracted values are plotted in Fig.2. We got: τ0=γ1·exp(−γ2 F) and EA=ξ1+ξ2 F

0

A

(4)

where γ1, γ2, ξ1, ξ2 are constants. The parameter EA is an average value of a distribution of energies. Increasing the electric field (> 5 MV/cm) more and more tight bonds can be broken, and the EA increases consequently. More recently [3], the theory developed in [1] was applied in HfO2 for describing the rate of Hf-O bond breakage in the case of long time constant voltage stress (CVS), with EA ≈4.4 eV. It is worth noticing that the kinetics of degradation of HfO2 in the case of long time CVS [3] and the kinetics of electroforming in HfO2 in the case of extremely short pulses (present work) are ruled by the same law (eq. 3). The impact of T on the forming kinetics in presence of different electrode materials is currently under study and results will be discussed at the conference.

[1] J. W. McPherson,R. B. Khamankar, and A. Shanware , J. of Appl. Phys. 88, 5351 (2000) [2] J. W. McPherson, J.Y.Kim, A. Shanware, H. Mogul, Appl.

Phys. Lett. 82 (13), 2121-23, (2003) [3] L. Vandelli, A. Padovani, L. Larcher, G. Bersuker, D. Gilmer, P. Pavan, Proc. of IMW 2011, in press

τ = τ ·exp((E -b F)/k T) F

(3)

10

-8

10

-9

B

5 4.8

-2

10-7

10

-10

10

-11

10

-12

10

-13

Exponential Fit

Linear Fit

4.4

-4

τ F (s)

10

-6

10

-9

10

-11

10

T

-8

10

4.8

2

2.2

2.4

4.6

4.2

5.2 5.6 6 Voltage (V)

2.6 2.8 3 -1 1000/T (K )

(eV)

τ (s) 0

10

10

ATT

-5

E

τF (s)

10

[1,2] predicts for the time to breakdown (τ):

3.2

6.4

3.4

Fig.1. τF vs T and VP. Symbols are experimental data (mean values on many samples), lines interpolations got with eq.(3)

5

5.5

6

4

Electric Field (MV/cm)

Fig.2. Data of τ0 and EA vs the electric field. Symbols are experimental data, lines interpolations got with eq.(4)

Transport Through Singlet States in Resistive Memory Materials: Magneli Phases with a General Formula, TinO2n-1 Gerry Lucovsky1, JinWu Kim2 1, 2

Department of Physics North Carolina State University, Raleigh, NC 27695-8202, USA corresponding author e-mail: lucovsky@ncsu.edu 1,2

Multivalent charge states, or simply multivalency, in transition metal (TM) elemental and complex oxides created by substitutional alloy formation is a pathway to novel device functionality.1) For example, bias dependent charge transport has been attributed to O-ion transport between the constituent layers in stacked transition metal (TM) structures using Magneli phases Ti suboxide mixtures, also characterized as TiO2-x, with x < 2.1) The most well-known Magneli phase alloy is a mixture of 2(TiO2) and Ti2O3 with a chemical formula given by Ti4O7.1) This alloy, as well as other Magneli phase compositions have been proposed for resistive memory devices.

Based on multivalency (MV) induced transport in TiO2-x alloys and other alloys, e.g., (i) GdScO3 based alloys by substitution of trivalent d1 Ti3+ for trivalent d0 Sc3+,2) and (ii) LaMnO3 alloys by substitution of divalent Sr for trivalent La.3), this paper demonstrates that multivalency is readily detected by X-ray spectroscopy.

For example, the number of features in the second derivative of the O K edge and appropriate TM L2,3 pectra, can be used not only detect MV, but also additional features due to transport-inducted conductivity which introduces additional valence states, as for example in Sr1-xTixO3, for x> the percolation threshold of ~0.165: 2 Ti3+ + => Ti4+ + Ti2+. Additional valence states are induced by local strain; e.g., the occurrence Ti2+ in Magneli phases where Ti4+ and Ti3+ are intrinsic. In alloys such as La1-xSrxMnO3, transport induced changes in valance are the basis for double exchange magnetism.

One important aspect of controlled MV provides a way of changing and/or controlling the density of Ovacancy defects. These are detected by in 2nd derivative pre-OK edge spectra.4) Electrons can be injected into the so-designated negative ion singlet states from Si, Ge, and other semiconductors, as well as metals with different offset energies.4,5) Two terminal devices with asymmetric currentâ&#x20AC;&#x201C;voltage characteristics then provide options for memory devices.1) The results presented in this paper, and described above, have identified an alternative explanation for transport in both homogeneous and multilayer structures that is based on the fundamental electronic structure associated with O-atom vacancies. In this paper we demonstrate that O-vacancies, which provide a transport path for injected and subsequently trapped electrons, are introduced by local strain associated with 5 to 10% differences in ion. The defects are vacated O-atom sites, which are located along grain boundaries of the constituent nano-grains.

References [1] Waser, R. et al.: Adv. Mater. 21 (2009) 2632.

[2] Lucovsky, G: J. Vac. Sci. Technol. B 29 (2011) 01AA01.

[3] Cox, P Transition Metal Oxides, Clarendon Press, Oxford, 1992.A. [4] Lucovsky, G. et al.: Jap. J. Appl. Phys. 50, 10PF04 (2011) 01PF04.

[5] Lucovsky G.; Zeller D.; Whitten J. L.; Mircoelectronic Eng, 88 (2011) 1471.

0.45

O K1 HfO2 4 nm

absorption (arb units)

0.4

A1g 0.35

T1u

3 nm

0.3

2 nm Eg

0.25

0.2 528

530

532

T2g

534

536

538

540

542

544

x-ray photon photonenergy energy(eV) (eV) X-ray

Fig.1. Ti L3 and second derivative L3 spectra for Magneli phase alloy. Ti4+ and Ti3+ features are from the alloy mixture, and the Ti2+ features from local transport of electrons.

Fig.2. OK edge spectra for nano-grain HfO2, annealed at 900°C in He as a function of film thickness - indicating critical thickness for observing ordered nano-grains with grain boundaries.

Spectroscopic detection of O-vacancy defects in non-crystalline SiO2, GeO2 and nano-grain HfO2 and TiO2: distinction between O-vacancies and vacated O-atom sites Gerry Lucovsky Department of Physics North Carolina State University, Raleigh, NC 27695-8202, USA corresponding author e-mail: lucovsky@ncsu.edu Three issues are addressed in the first pare of this talk: (i) X-ray spectroscopic studies of RPD-SiO2 and RPD GeO2, include band edge states and pre-existing defects, each in the OK edge spectrum, (ii) interpretation of these X-ray absorption and photoemission based on many electron theory incorporating symmetry adapted linear combinations (SALC) of atomic states appropriate the local symmetries in the bulk and in defect sites, and also include electron spin singlet and triplet states, and finally, (iii)1) the importance of separate and independent processing of interfaces of Si and Ge prior to deposition of RPD-SiO2 and RPD GeO2, as well as transition metal oxide dielectrics, e.g., HfSiON on Si, and TiO2 on Ge, and finally, (iv) the occurrence of similar vacated O-atom vacated defect sites in transition metal (TM) elemental oxides, including TiO2, ZrO2 and HfO2, as well as complex TM oxides: SrTiO3, and La(1-x)SrxMnO3.2) One of the most significant results of these studies is the identification of the local atomic structure in preexisting defects. These are vacated O-atom sites in quartz-structured SiO2 and GeO2 in which the respective O-atoms have never been resident in these sites. Bonding is stabilized by a displacive relaxation in which the two Si dangling bonds move apart. This makes the ground state energies of the singlet and triplet spin states degenerate, by reducing the exchange energies, and overlap of the radial parts of the wave functions for singlet spin arrangement. The ground state energy is further stabilized by an entropy contribution from the multiplicity of the

Fig.1. Geometry of Si and Ge dangling bonds: vacated-O and O-vacncies Solid circles; radial wave function overlap

spin states.

The insights gleaned from these studies forms a basis for the identification of remote plasma processing protocols for the formation of low defect densities interfaces on Ge,Si alloys, which can be grown pseudomorphically on Ge Si sucbstrates. This approach integrates differences in the thermal stabilities of interfacial GeOx and SiOx, x<2 transitions regions, including the identification of processing conditions for limiting thermal budgets and post-deposition annealing temperatures, including ambients. Examples will be presented wherein equivalent oxidethicknesses below 1.0 nm, and extending to ~0.5 nm have been obtained.

The intrinsic bonding defects in elemental nanocrystalline TiO2, ZrO2 and HfO2, as well as complex TM oxides. Spectroscopic studies of these nano-grain oxides indicate the minimum grain size for detection of both grain boundaries and vacated O-atom defects in about 3 to 4 mn. Changes in defect densities with nano-grain dimensions with increasing post-deposition anneal temperatures indicates vacated O-atom sites reside on grain boundaries.

References [1] Lucovsky, G. and Zeller,D.: J. Nanosci. and Nanotechnol.

11, (2011) 7974.

[2] G. Lucovsky, G, et al.: Jap. J. Appl. Phys. 50, (2011) 10PF04.

Fig.2. Total energy versus Si-Si distance for O-vacated and O-vacancies-changes in exchanbe and overlap energies

Properties of stacked SrTiO3/Al2O3 MIM capacitors M. Lukosius1, T. Blomberg2, G, Ruhl3, Ch. Wenger1 1 – IHP, Im Technologiepark 25, Frankfurt (Oder) 15236, Germany 2 – ASM Microchemistry Ltd, Väinö Auerinkatu 12A, Helsinki 00560, Finland 3 – Infineon technologies AG, Wernerwerkstr. 2, Regensburg 93049, Germany corresponding author e-mail: lukosius@ihp-microelectronics.com The further miniaturization of the microelectronic devices also requires superior properties of the integrated passive elements. Since Metal-Insulator-Metal (MIM) capacitors can occupy up to 40 % of the chip area, the achievement of the higher capacitance density per unit area is the main objective here. This can be done by the replacement of now used SiO2 [1] or Si3N4 [2] with the alternative dielectrics which have higher permittivity.

However, the requirement of capacitance density of > 10 fF/μm2, as defined by ITRS, demands the search for alternative materials with much higher k value, compared to the simple oxides, such as HfO2, Al2O3 or Ta2O5 that that been investigated as alternative dielectrics for MIM applications [3-4]. At this point, perovskite-type dielectrics exhibit a wide range of interesting properties and play an important role in the many technological applications. SrTiO3 is one of the most promising insulators mainly due to its high dielectric constant of ~ 150. However, this high k value is achieved when SrTiO3 is crystalline. On the other hand, it is well known that grain boundaries in the dielectric layer create channels for electrons and MIMs with crystalline dielectric suffer from high leakage current densities. This challenge of practical use of SrTiO3 for MIM capacitors might be solved by combining it with an excellent isolator, such as Al2O3, to form stacked dielectric structures. Therefore, in this work, we successfully applied Atomic Layer Deposition technique for the depositions of SrTiO3 and Al2O3 films for stacked MIM capacitor applications.

Dielectric thin films of Sr-Ti-O as well as of Al2O3 were deposited at 250 ºC on 200 mm Si(100)/TiN substrates in ASM Pulsar® 2000 type R&D reactor at

Fig.1. Leakage current densities versus applied voltage of single SrTiO3 (■) and stacked Al2O3/SrTiO3/Al2O3 (■) MIM capacitors

ASM Microchemistry Ltd using (1,2,4-tertiarybutylCp)2Sr + Ti(OMe)4 and Al(CH3)3 metal precursors respectively. O3 was used as the oxidizing agent. In order to crystallize SrTiO3, PDA was performed at 600 ºC. Thicknesses of the films were determined by ellipsometry and electrical properties were extracted from (C–V) and (I –V) measurements after evaporation of Au, top electrodes to form MIM structures.

The effect of depositing 50 nm SrTiO3 film between two layers of Al2O3 on the leakage current density of the complete stack is shown in Fig. 1. The reduction of it by several orders of magnitude is clearly observed, especially at lower applied voltages, compared to the on of single SrTiO3 MIM stack. However, this addition of Al2O3 has also an influence on the capacitance density of the stacked MIM capacitors as shown in Fig. 2. It can be seen that the capacitance density (~ 18 fF/μm2) of single, crystalline SrTiO3 based MIM is ~ 3 times higher than the one of stacked Al2O3/SrTiO3/Al2O3 MIM capacitor (green line in Fig. 2). This effect is attributed the differences in dielectric constant values of the oxides. The extracted k value of SrTiO3 is 95, whereas the low dielectric constant of Al2O3 (k = 8) reduces to total k value of the Al2O3/SrTiO3/Al2O3 stack to 31 due to the series capacitance. Nevertheless, SrTiO3/Al2O3 is a promising MIM stack for future investigations.

References [1] [2] [3] [4]

D. Coolbaugh et. al., Integ. Circuits (2002) 341.

J. A. Babcock et. al., Electron Dev. Lett. 22 (2001) 230.

M. Lukosius et. al., Thin Solid Films 518 (2010) 4380.

Y. Tu et. al., VLSI Tech. Dig. (2003) 79.

Fig.2. Capacitance-Voltage characteristics of the SrTiO3 (■) and stacked Al2O3 SrTiO3/Al2O3 (■) MIM capacitors

HAXPES as a non-destructive technique for RRAM investigations M. Sowinska1, T. Bertaud1, D. Walczyk1, S. Thiess2, Ch. Walczyk1, and T. Schroeder1 1 - IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany 2 - Deutsches Elektronen-Synchrotron (DESY), Notkestrasse 85, 22607 Hamburg, Germany corresponding author e-mail: sowinska@ihp-microelectronics.com Among various embedded non-volatile memory technologies currently discussed, Resistance change Random Access Memory (RRAM) is an attractive and promising candidate because it offers a comparatively easy and cost-effective integration concept and low-power possibilities [1-3]. The elucidation of the physical mechanism of the resistive switching (RS) effect is a key step to achieve a manufacturing maturity. In the literature two main models are discussed: the creation/annihilation of charged oxygen vacancies (VO··) at the top metal/dielectric interface [4], and the growth of filaments between the two electrodes [5]. Interestingly, both models highlight the importance of this top interface as the localization of the switching event. An innovative hard Xray photoelectron spectroscopy (HAXPES) is a powerful method which allows studying buried interfaces in a nondestructive way by increasing the photon energy of the exciting X-ray beam. We present here HAXPES studies performed on the Ti/HfO2/TiN RRAM devices at P09 beamline at DESY in Hamburg.

For this purpose a polycrystalline TiN bottom electrode was deposited on a (001)-oriented Si wafer by plasma assisted direct current magnetron sputtering of a titanium metal in the presence of a N2/Ar gas mixture at room temperature (RT). An amorphous HfO2 film was grown by atomic vapor deposition at 320˚C using a Hf(NMeEt)4 precursor and oxygen as a reactive gas. In the following, a Ti top electrode was deposited by plasma vapor deposition at RT. A 200×200 µm2 in size bottom electrode contact was opened by time of flight secondary ion mass spectroscopy depth profile and set to the ground potential. The RS cycles were performed using a Keithley 4200 semiconductor characterization system. HAXPES spectra were collected in normal emission geometry.

Firstly, in order to highlight the effect of the first, irreversible switching cycle (called electroforming) on the

Ti/HfO2/TiN RRAM, we studied two 1×1 mm2 samples with the layer thicknesses of 10/17/70 nm termed asprepared and electroformed (electroforming was carried out ex-situ). By choosing 5.5 and 7 keV excitation energies, the Ti/HfO2 interface can be studied nondestructively. Calculated inelastic mean free paths (IMFP) were equal to 8.4 and 10.3 nm for Ti 2p level in Ti during the measurements, respectively. Our investigations revealed significant differences in the HAXPES spectra between as-prepared and electroformed samples. Ti 2s and Hf 4d HAXPES emission lines presented in Fig. 1 show: 1) an increase of the Ti oxidation at the Ti/HfO2 interface and 2) a peak shift toward higher binding energy. These two results are linked to oxygen gettering by the Ti from the HfO2 layer, creating an enhanced Ti oxidation and oxygen vacancies (VO··) in HfO2 during electroforming [6].

Then, for a clear correlation of all relevant electrical characteristics with material properties, we performed an in-situ current voltage cycling of one and the same MIM sample with simultaneous HAXPES measurements, thanks to a setup developed at IHP. Here, the same Ti/HfO2/TiN RS systems, in size of 0.7×0.7 mm2, were dynamically monitored in order to highlight the modifications between the ON- and OFF-states. We have successfully switched the device several times at a chamber pressure around 10-7 mbar and recorded XPS spectra for both states at excitation energy of 8 keV (in that case, IMFP of Ti 2p level in Ti was equal to 11.4 nm). First results have shown peak shifts, for which the order (BEvirgin < BEOFF < BEON) is coherent with the existence of various concentrations of n-type VO·· ([V0··]virgin < [V0··]OFF < [V0··]ON) in HfO2. This result points to the possibility to describe the switching event in our Ti/HfO2-based system by a push-pull model coupled with a Schottky interface-like system [4,7]. We propose that the electroforming process induces Ti/HfO2 interface oxidation and creation of n-type VO·· in the HfO2 layer.

Next, a positive voltage applied to the top electrode repels VO·· and resets the device to the OFF-state, while a negative voltage attracts VO·· and sets the RRAM cell to the ON-state. Detailed results will be presented.

References

Fig.1. Ti 2s and Hf 4d HAXPES spectra recorded at 7 keV for the as-prepared (upper row) and electroformed (bottom row) samples. Dotted lines highlight XPS peak position shifts.

[1] Walczyk, Ch. et al., IEEE T. Electron Dev. 58 (2011) 3124.

[2] Walczyk, Ch. et al., J. Vac. Sci. Technol. B 29, 1 (2011) 01AD01.

[3] Walczyk, D. et al., Microelectron. Eng. 88 (2011) 1133.

[4] Sawa, A. Mater. Today 11 (2008) 28.

[5] Waser, R. et al., Adv. Mater. 21 (2009) 2632.

[6] Sowinska, M. et al., submitted to Appl. Phys. Lett.

[7] Bertaud T. et al., to be submitted.

memFET: a new multi-purpose resistive switching device J. Martin-Martinez1, C.G. Almudéver2, A. Crespo-Yepes1, R. Rodriguez1, M. Nafria1, X. Aymerich1 and A. Rubio2 Dept. Eng. Electrònica, Universitat Autònoma de Barcelona, 08193, Bellaterra, Barcelona, Spain 2 Universitat Politècnica de Catalunya, 08034 Barcelona (Spain) Corresponding author: Phone (+34) 93 581 3514 author e-mail: Javier.martin.martinez@uab.es method is possible, which simplifies the distinction between stored states. Note that in this new reading method, the dispersion of the current at the HRS drastically decreases, improving the performance of the device when it is used as a memory element. In addition, by applying the adequate voltages at drain and source memFET terminals, more than one RS path can be created at different locations along the channel, so that the memFET can operate as a multibit memory cell. The same principle allows the use of the device as a voltage controlled multi-directional switch. When all the RS paths are at HRS, the memFET operates as a MOSFET (Fig. 1c). Thus, four different and interchangeable operation modes of the device are possible: (i) 1 bit memory cell (ii) multibit memory cell, (iii) multidirectional switch and (iv) MOSFET transistor. To simulate the memFET behavior, first, the RS path has been modelled using a voltage controlled switch, whose ON and OFF resistances correspond to those of the RS path at the LRS and HRS. To model the memFET, the RS path model is connected between the gate and the MOSFET terminals where the RS-path(s) is (are) located (Fig. 1e). This model correctly reproduces the ID-VD curves of the memFET in a circuit simulator during the LRS/HRS (lines in Fig1.b and c).

The reconfigurable memFET device (patent pending [4]) opens new possibilities for the design of future large computation systems, where the function of all the elements could be reconfigured and adapted to the instantaneous needs.

Resistive Switching Devices (RSDs) are receiving special attention for memory applications due to their scalability, non-volatility, and high performance [1].

Usually, these devices have two terminals (2t-RSD), such as MIM/MIS structures, in which the conductivity of the dielectric can be switched between two different conductivity states, a Low Resistance State (LRS) and a High Resistance State (HRS) [1,2]. In some materials, the LRS conduction is filamentary, i.e. the current flows through a small area of the insulator (RS path). In this work, this property is exploited in a MOSFET so that a new device concept is introduced, called hereafter memFET. The proposed memFET is a four terminal field-effect device (such as a MOSFET), in whose ultra-thin gate dielectric at least one RS path has been created (Fig.1a).

We attribute the gate RS behaviour in these devices to the gate dielectric breakdown (BD), and BD reversibility [3].

In a memFET, in addition to the current through the RS path (RS current through the gate), a channel current can flow between source and drain when there is a voltage difference between these terminals (Fig. 1a), providing advantages of the memFET with respect the 2t-RSDs. Similarly to its 2t-RSD counterparts, the memFET can be used as a 1 bit memory element, but the reading of the cell is improved. When the RS path is at LRS, the ID-VD characteristic shows a resistive behaviour (Fig. 1b) and the RS current mainly determines the ID value because it is so large that the channel current is negligible. On the contrary, when the RS path is at HRS, ID is mainly controlled by the channel current and the device operates as a standard transistor (Fig. 1c). In this case, the larger the channel current, the larger the difference between the ID values for the LRS and HRS and the easier the distinction between the states is. For large enough channel current, the ID values for the LRS and HRS have opposite sign (Fig. 1d) and, therefore, a new discriminatory read

Drain Channel current

Bulk

3

VGS

b)

-0.6V

-30

-0.8V -1.0V

2

-1.2V -1.4V

1 0

e)

Dots: Experimental Lines: Simulation

-1 -1,0

-0,5

0,0

Drain Voltage (V)

0,5

c)

Dots: Experimental Lines: Simulation

-25

VGS = -1.4V

-20 -15

VGS = -1.2V

-10 VGS = -1.0V

-5 0,0

-0,5

-1,0

Drain Voltage (V)

1m

Drain current (A)

Source

RS current

Drain Current (A)

Gate

Drain Current (mA)

a)

This work has been partially supported by the Spanish MICINN (TEC2010-16126, TEC2008-01856 and TEC201010021-E) and the Generalitat de Catalunya (2009SGR-783).

References [1] R. Waser et al. Nature Materials 6, 833 (2007).

[2] M. Y. Chan et al. Microelec. Eng. 85, 2420 (2008).

[3] A. Crespo-Yepes et al. ESSDERC proc., 138 (2010) [4] PCTIB2011001257 (2011)

10µ

d) LRS

100n 1n

HRS

Symbols: VGS =-0.4V VDS=0V

0,0 -10,0µ -20,0µ

Lines: VGS=-1.4V VDS=-1V

0

10

20

30

40

50

60

70

Cycles

Fig. 1. a) memFET with a RS path located close to the drain terminal. In this work, the memFETs were pMOSFETs (p-type memFETs) fabricated with a standard CMOS process, with FUSI gate electrode and gate dielectric stack (EOT=1.9 nm) formed by a HfSiON film (physical thickness of 2.9 nm, 60% Hf) on top of a 1.2 nm SiO2 interfacial layer. If a RS path is created in the gate dielectric of a MOSFET, drain current is measured as the contribution of two mechanisms, the current through the RS path (RS current) and the current induced by field effect (channel current). b) The ID-VD experimental memFET characteristics (symbols) show a purely resistive behaviour if the RS path is at the LRS and c) the typical MOSFET behaviour is recovered if the RS path is at the HRS. d) The device can be used as a conventional 2t-RSD when no channel current is forced (dots), however, if properly biased, the memFET currents of different sign (lines) can be measured at the LRS and HRS due to the channel current contribution. e) The electrical model proposed for the memFET accurately describes the ID-VD characteristics in a circuit simulator (lines in b and c).

Charge trapping in Si:HfO2-based ferroelectric field effect transistors: A fast transient characterization using pulsed Id-Vg methodology Johannes Müller1, Ekaterina Yurchuk2, Tim S. Böscke*, Raik Hoffmann1, Uwe Schröder2, Thomas Mikolajick2, Lothar Frey3 1 – Fraunhofer Center for Nanoelectronic Technologies, 01099 Dresden, Germany, johannes.mueller@ieee.org 2 – NaMLab gGmbH / Dresden University of Technology, 01187 Dresden, Germany / *private 3 – Fraunhofer Institute for Integrated Systems and Device Technology, 91058 Erlangen, Germany With the discovery of ferroelectricity in doped HfO2 thin films new potential has been added to the field of ferroelectric memories [1-3]. Especially the rather low dielectric constant and the high coercive field of ferroelectric HfO2 are ideally suited for ferroelectric field effect transistors (FeFET, 1T FRAM solution). Excellent device performance for this fully CMOS-compatible approach has been demonstrated. Low voltage operation, switching in the nanosecond range, as well as 10-year retention suggest a promising technology [4,5].

However, due to their thin interfacial SiO2 layer and the high trap density of crystalline HfO2, parasitic charge injection plays a crucial role in the switching operation of these FeFETs. In this study the influence of the interfacial layer thickness on transient electron trapping and de-trapping mechanisms will be discussed. To visualize the trade-off between memory window (MW) and compensating charge injection directly after switching, a pulsed Id-Vg methodology (microsecond-range) was applied [6].

single pulse can be utilized to switch the device from a predefined state to the opposite state. However, as can be seen from the first up (Vt1) and down (Vt2) sweep only charge trapping in the form of a clock-wise hysteresis is observed (Fig. 1). With increasing pulse width this charge trapping becomes even more severe. Only for the second up sweep (Vt3) de-trapping has completed and the ferroelectric MW with its counter clockwise hysteresis is revealed. Due to renewed charge injection the adjacent down sweep (Vt4) once more follows the Vt2 sweep.

By increasing the interfacial layer thickness and therewith the time constant of electron de-trapping the effect, witnessed for thin interfacial layers on a microsecond scale, is now stretched out to several seconds and can be observed in the time frame of a standard memory characterization (Fig. 2). As a result, FeFETs with thick interfacial layer do not reach their full MW until several minutes have passed.

Figure 2 Fast retention of HfO2-based FeFETs with varying interfacial layer thickness. Due to electron de-trapping an artificial retention gain is observed for thick interfacial layers

Figure 1Pulsed Id-Vg methodology applied to a HfO2-based FeFET (~1 nm SiO2). MW is revealed after de-trappig.

The studied gate first, long channel PolySi/TiN/Si:HfO2/SiO2/p-Si FETs were prepared on 300 mm manufacturing equipment. The 10 nm thin ferroelectric Si:HfO2 films were grown by ALD. The SiO2 content was tuned by the precursor cycle ratio and confirmed by XPS to be around 5 mol%.

The pulsed Id-Vg methodology, initially developed for the characterization of transient trapping phenomena in HKMG transistors, offers the opportunity to capture a full Id-Vg dual sweep within a single pulse. For the FeFET this

Even though this transient (de-)trapping behaviour can be tailored by the interfacial layer thickness and/or the applied pulse width, a negative impact on high frequency operation cannot be ruled out. Special operation schemes, such as error correction and program verify algorithm, require an instantaneously stable MW after programming.

All implications on device performance and possible solutions will be discussed in detail.

Acknowledgment This work was partially supported within the scope of technology development by the EFRE fund of the European Community and by the State of Saxony (Project MERLIN) References [1] [2] [3] [4] [5] [6]

T. S. Böscke et al., Appl. Phys. Lett. 99, 102903(2011) J. Müller et al., J. Appl. Phys. 110, 114113(2011).

J. Müller et al., Appl. Phys. Lett. 99, 112901(2011) T. S. Böscke et al., Tech. Dig. IEDM., 547(2011) J. Müller et al., IEEE Electron Device Lett. 33, 185(2012) C.D. Young et al., IEEE T. Electron Dev. 56, 1322(2009)

Applicability of Ferroelectric HfO2 for Non-Volatile Memory-Cell Arrays Stefan Müller1, Ekaterina Yurchuk 1, Johannes Müller2, Stefan Slesazeck1, Till Schlösser3, Dominik Martin1, Raik Hoffmann2, Jan Paul2, Roman Boschke3, Ralf van Bentum3 , Martin Trentzsch3, Uwe Schröder1 and Thomas Mikolajick1 1 – NaMLab gGmbH / Dresden University of Technology, Noethnitzerstr. 64, 01187 Dresden, Germany E-Mail: stefan.mueller@namlab.com 2 – Fraunhofer Center for Nanoelectronic Technologies, Koenigsbruecker Str. 180, 01099 Dresden, Germany 3 – GLOBALFOUNDRIES Dresden Module One LLC & Co. KG, Wilschdorfer Landstraße 101, 01109 Dresden During the last decade, Flash memories have gained significant importance for various non-volatile data storage applications. Nevertheless, especially with respect to the ongoing search for highly scaled devices, flash memory cells face significant roadblocks [1].

Recently, ferroelectric properties capable of establishing non-volatile data storage have been discovered in doped HfO2 thin films [2-4]. First ferroelectric field effect transistors were fabricated by incorporating ferroelectric HfO2 into the gate stack therewith effectively realizing two distinguishable binary states due to the shift in threshold voltage [5].

The main goal of our present study is to evaluate the tolerance of HfO2-based FeFETs towards disturb signals occurring within real memory cell arrays. As an example, Fig. 1 shows an elementary AND-cell array for which the most significant disturb scenarios can clearly be identified.

We verify and validate our theoretical concepts by mixed-mode finite element analysis (FEA) as well as by experimental investigations on ferroelectric field effect transistors down to the 28nm technology node.

Experimental investigations are of significant importance especially with respect to cumulative disturb effects which are hard to model and are therefore difficult to predict using simulation. We were already able to show that for appropriate choice of the disturb signal amplitude, threshold voltage states can be maintained for up to 106 disturb cycles. For our measurements, the binary states were realized using programming and erase voltages of -

J. V. Houdt, Current Applied Physics, 2011, 11, e21.

T. S. Boescke et al., Appl. Phys. Lett., 2011, 99, 102903.

J. Müller et al., J. Appl. Phys. 2011, 110, 114113.

J. Müller et al., Appl. Phys. Lett. 2011, 99, 112901.

J. Müller et al., IEEE Electron Device Lett., 2012, 33, 185.

L = 0.5µm

L = 30nm

g g -2.00E+00 -1.50E+00 -1.00E+00 -5.00E-01 0 .00E+005.00E-0 -1.00E+00-5.00E-010.00E+005.00E-011.00E+001.50E+00 1 1E-3

WL2

WL1

WL2

BL1

BL2

SL1

SL2

Program

VDD

VDD/3

0

2/3 VDD

0

2/3 VDD

Erase

-VDD

-VDD/3

0

-2/3 VDD

0

-2/3 VDD

Read

VR

0

0.1

0.1

0

0

Fig.1. FeFET-AND architecture for VDD/3 cell scheme.

Programming and erase disturbs are limited to a maximum of one third of the operational voltage.

1E-7 1E-9

1E-5

+5V 1E-7 -1.5V -2V 1E-9 -3V

1

+5V -3V -4V -5V

1

-5V +3V +1V +0.5V

1

1

1 1E-11 1E-11 -2.00E+00 -1.50E+00 -1.00E+00 -5.00E-01 -1.00E+00-5.00E-010.00E+005.00E-011.00E+001.50E+00 0 .00E+005.00E-0 1.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1 1E-3 -1.0 -0.5 0.0 0.5 1.0 1E-3 Gate Voltage [V] Gate Voltage [V] 1 1E-5 1E-5

1E-7 1E-9 1E-11

Drain Current [A]

WL1

1E-5

Drain Current [A]

1E-3

BL2

SL2

[1] [2] [3] [4] [5]

Drain Current [A]

BL1

References

Drain Current [A]

SL1

5V and +5V (100ns pulse width) respectively. Different disturb voltages of opposite state polarity were applied 106 times in order to investigate cumulative effects especially for amplitudes close to VDD/3. For long channel devices, 1.5V disturb signals of 100ns pulse width did not lead to a degradation of the established threshold voltage state and could therefore be used for VDD/3 architectures.

Due to significant under-diffusion of source and drain regions, threshold voltage roll-off was visible for short channel devices. Nevertheless, cumulative disturb effects could be minimized by adjusting the respective amplitudes.

So far, the described and investigated VDD/3 disturb characteristics correspond to the worst case scenario for the highlighted cell in Fig. 1. Additional disturb scenarios for the remaining elementary cells as well as for alternative cell concepts were evaluated within further experiments and simulations.

Acknowledgements: The work for this conference was supported within the scope of technology development by the EFRE fund of the European Community and by funding from the Free State of Saxony (Project HEIKO).

-5V 1E-7 +1.5V +2V 1E-9 +2.5V

-1.0 -0.5 0.0 0.5 1.0 Gate Voltage [V]

1E-11 1.5 -2.0 -1.5 -1.0 -0.5 0.0 Gate Voltage [V]

1 1

0.5

Fig.2. Threshold voltage shift from an initially written state (red) caused by 106 disturb cycles (blue) for 0.5 µm and 30nm technology nodes.

Tri-states memory using ferroelectric-insulator-semiconductor hetero-junctions for fifty percent increased data storage Min Hyuk Park*, Hyun Ju Lee, Gun Hwan Kim, Yu Jin Kim, Jeong Hwan Kim, Jong Ho Lee, and Cheol Seong Hwang WCU Hybrid Materials Program, Department of Material Science & Engineering and Inter-university Semiconductor Research Center, Seoul National University, Seoul 151-744, Korea corresponding author e-mail: pmh1983@snu.ac.kr Figures. 2 (a), (b), and (c) show the switching current density-time curves (for write voltages of -10, -5, 5, 10, 15, and 20V) of the MFISM capacitors. The switching charges could be calculated by integrating the switching current density-time curves in Figs. 2(a), (b), and (c) and being multiplied by -1 for sake of convenience. Figs. 2(d), (e) and (f) show the change in switching charge as a function of the write pulse voltage of the MFISM capacitors. In this MFISM structure, the P-V loops showed two coercive voltages (two peaks in the Jsw–V diagram) that coincide well with the pulse switching results. The occurrence of a plateau with the switching charge of ~10-15 µC/cm2 suggests that polarization switching occurs partially within this voltage range.

Therefore, the data strongly suggests that the compensating charges are stored separately in the structure at different interfaces, and have different threshold voltages.

In summary, a feasible structure and actual operation of a tri-state memory function for high density FeRAM using stacked Pb(Zr,Ti)O3/Al2O3/ZnO layers with Pt top and bottom electrodes was presented. This new mechanism can increase the memory density by 50% compared to the conventional FeRAM at a given cell size.

This study was supported by the Converging Research Center Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2011K000609).

-60 -25 -20 -15 -10 -5 0 5 10 15 20 25

-20 -40 -60 -25 -20 -15 -10 -5 0 5 10 15 20 25

Voltage [V]

A

B

0.5 0.0 -0.5 -1.0 -1.5 -25 -20 -15 -10 -5 0 5 10 15 20 25

Voltage [V]

Current Density [A/cm2]

Current Density [A/cm2]

1.0

1.0

150 100

0 -20 -40 -60 -25 -20 -15 -10 -5 0 5 10 15 20 25

Voltage [V]

Voltage [V]

1.5

1.5

ds=20nm

20

50

B

0.5 0.0 -0.5 -1.0 -1.5 -25 -20 -15 -10 -5 0 5 10 15 20 25

Voltage [V]

1.0

A

0 -50 -100 -150 0.0

B

0.5

100

-12V/3µs read

1.5

A

150

(a) ds=5nm

80

1.0µ

2.0µ

-10V/5µs write -5V/5µs write +5V/5µs write +10V/5µs write +15/5µs write +20/5µs write

3.0µ

-1.0

Voltage [V]

Fig.1. P-V hysteresis (upper panel) and current response (lower panel) curves measured using a TF analyzer 2000 with a 1000Hz triangular pulse with an amplitude of 4, 8, 12, 16, 20, 24 V of MFISM capacitors using Pt top electrode with (a) 5-nm-thick ZnO, (b) 10-nm-thick ZnO, and (c) 20-nm-thick ZnO. Al2O3 thickness was 5.5 nm.

0 -10

1

5µs 20µs 50µs

20

-1.5 -25 -20 -15 -10 -5 0 5 10 15 20 25

-50 -100 -150 0.0

1.0µ

2.0µ

-10V/20µs write -5V/20µs write +5V/20µs write +10V/20µs write +15/20µs write +20/20µs write

3.0µ

-5

0

2

20

5

10

Vpulse[V]

15

20

25

0 -10

-12V/3µs read

0

-10V/50µs write -5V/50µs write +5V/50µs write +10V/50µs write +15/50µs write +20/50µs write

-50 -100 -150 0.0

80

(e) ds=10nm

40

(c) ds=20nm

50

4.0µ

Time [s]

1.0µ

2.0µ

3.0µ

4.0µ

Time [s]

(f) ds=20nm

60

60

40

-0.5

100

0

80

(d) ds=5nm

150

(b) ds=10nm -12V/3µs read

4.0µ

Time [s]

60

0.0

50

J [A/cm2]

0

40

-5

0

2

1

5µs 20µs 50µs

QSW[µC/cm2]

-40

20

60

J [A/cm2]

-20

(c)

ds=10nm

QSW[µC/cm2]

0

40

[1] Park, M. H., Lee, H. J., Kim, G. H., Kim, Y. J., Kim, J. H., Lee, J. H., Hwang, C. S.: Adv. Funct. Mater. 21 (2011) 4305.

J [A/cm2]

20

60

References

QSW[µC/cm2]

(b)

ds=5nm

Polarization [µC/cm2]

40

Current Density [A/cm2]

60

Polarization [µC/cm2]

(a) Polarization [µC/cm2]

FeRAM is considered as one of the best candidates for universal memory. On the other hand, difficult scaling of the memory cell size has hindered the realization of high density FeRAM. Given that size scaling is inherently limited by the complicated crystal structure and processing of ferroelectric materials, the highly stable and step-wise three memory state of one cell can be another pathway to high density FeRAM. This presentation reports a feasible structure and actual operation of a tristate memory function for high density FeRAM with novel mechanism.[1] Figure 1 shows the P-V hysteretic (upper panel) and switching current density (Jsw) response curves (lower panel) of the metal-ferroelectric-insulator-semiconductormetal (MFISM) structures measured using a standard ferroelectric tester in virtual ground mode, where the materials are Pt/PZT/Al2O3/ZnO/Pt. A notable finding is that the P-V loops in the positive V region shows a hump, whereas those in the negative region do not. This can be seen even more clearly from the Jsw-V curves. The split of the Jsw peak under a positive bias could be observed in all samples. It means that the charges compensating for the polarization bound charges of the ferroelectric were divided into two groups; each flowing under different bias conditions. Peak splitting would not be observed if all the compensating charges were located at the metal electrode or PZT/Al2O3 interface. Therefore, it was assumed that the compensating charges were separated and stored on the PZT/Al2O3 and Al2O3/ZnO interfaces, where the threshold voltages of the charges of the two interfaces to flow are different.

40 20

5

10

Vpulse[V]

15

20

25

0 -10

-5

0

2

1

5µs 20µs 50µs 5

10

Vpulse[V]

15

20

25

Fig.2. Switching current as a function of time (Upper panel) and switching charge integrated from the measurement as a function of Vpulse (Bottom panel) for the case of the samples (Al2O3 thickness =4.0 nm) with (a) 5-nm-thick ZnO film, (b) 10-nm-thick ZnO film and (c) 20-nm-thick ZnO film, respectively.

Perimeter and Area Current Components in HfO2 and HfO2-x MIM Capacitors F. M. Puglisi1, A. Padovani2, L. Larcher2, P. Pavan1 1 - Dipartimento di Ingegneria dell’Informazione – Università di Modena e Reggio Emilia 2 - Dipartimento di Scienze e Metodi dell’Ingegneria – Università di Modena e Reggio Emilia corresponding author e-mail: francescomaria.puglisi@unimore.it In this paper we present an experimental analysis on current conduction mechanisms in HfO2 and HfO2-x highk oxides. These materials are nowadays of great interest for reliable and fast CMOS devices as well as for novel NVMs (non-volatile memories) [1]. Among high-k dielectrics, hafnia seems to be a good candidate since it is compatible with CMOS back-end of line. Novel devices with this material have been successfully implemented [2] but further investigation is needed. Experiments on current conduction are performed on MIM structures with stoichiometric and sub-stoichiometric hafnium oxide. I-V curves are obtained for devices with different. J-V curves show the same current density for all samples with substoichiometric oxide, whereas samples with stoichiometric oxide exhibit an increasing current density, as area is scaled-down, see Fig.1. Hence, assuming that current depends upon two components, the former related to the area (Ia) and the latter to the perimeter (Ip), we can model this current using: I = Ia+Ip = a∙l2 + b∙4l

(1)

being l the side size of a square device. Fig.2 shows both area and perimeter current components vs. side size of devices at room temperature. In stoichiometric devices, area and perimeter currents curves intersect defining a cross-point, while this does not happen for substoichiometric devices in which perimeter-related current is many order of magnitude smaller than the area-related one. It has been proven that current in HfO2 flows along grain boundaries (GBs) [3] with dimensions ranging from few to tens of nm. GBs are preferential paths for the charge transport as they are a natural segregation spot for

Fig.1. J-V curves for different- area devices at room temperature for sub-stoichiometric (upper curves) and stoichiometric (lower curves) samples Different behaviors are evident.

O vacancy defects, which assist charge Trap-Assisted Tunneling (TAT) [4]. The density of GBs and the O vacancy defects is believed to increase at the device perimeter, thus explaining the perimeter current increase as dimensions are scaled down. On the other hand substoichiometric HfO2-x naturally exhibits a larger defect density throughout the whole oxide volume, thus leading to a more uniform leakage current distribution. For stoichiometric devices, we can define a critical side size of the device at the cross-point where perimeter and area currents have the same value, see Fig. 2. A further dimensional shrinking would result in an increase in the perimeter- w.r.t. the area-related current. This critical size, which changes with temperature (results not shown) and voltage (see Fig. 2), allows monitoring of current distribution in scaled samples, indicating the minimum side beyond that the device (e.g. MOSFET) scaling down is less effective in reducing the leakage current. Oxide breakdown (BD) is also analyzed in HfO2 and HfO2-x devices, finding that perimeter and area current components have a different impact on breakdown voltage (results not shown). From this perspective, BD voltages measured in large samples underestimate breakdown predictions in small samples, due to the strong influence of perimeter region. These features can be of great interest for a correct design of novel, highly scaled MOSFETs and RRAMs.

References [1] [2] [3] [4]

L. Vandelli et al., IMW, 2011.

H.Y. Lee at al., IEEE EDL, Vol. 31, No. 1, 2010.

G. Bersuker et al. Proc. ESSDERC, 2010, pp. 333-336.

L. Vandelli et al., IEEE-TED, Vol. 58, No. 9, 2011

Fig.2. I-l curves at room temperature with 0.5 V and 1 V applied bias for stoichiometric (left) and sub-stoichiometric (right) devices. Cross-point is indicated in the left graph.

Surface Passivation and Reliability Characteristics of Rare Earth (Ce, Dy, La, Gd) Oxides on High Mobility Ge Substrates M. S. Rahman1, 2, E. K. Evagelou2, N. Konofaos3, A. Dimoulas3 1 – Detector Laboratory-GSI, 64291-Darmstadt, Germany 2 – Department of Physics, University of Ioannina, 45110-Ioannina, Greece 3 – Department of Informatics, Aristotle University of Thessaloniki, Greece 4– MBE Laboratory, NCSR, DEMOKRITOS, 15310-Athens, Greece corresponding author e-mail: M.S.Rahman@gsi.de Rare-earth oxides (REO), e.g. CeO2, Dy2O3, La2O3, and Gd2O3 grown on high mobility Germanium substrates, are friendly with Ge, demonstrating better passivation and electrical properties. It is imperative to study a number of reliability concerns such as charge trapping, defects generation, SILC, oxide degradation and dielectrics relaxation under bias condition before they can be considered for implementation in future MOS devices.

Regarding the reliability characteristics, they depend strongly on the quality of the passivating layer and the corresponding interfaces.

REO films were prepared by MBE on both p- and ntype Ge substrates of a resistivity of 1.6–1.9 Ω-cm, at a temperature range of 225-336 oC. Pt was used as the gate electrode while the back ohmic contact was realized using eutectic In–Ga alloy. When REOs are directly deposited on high mobility Ge substrates they show excellent passivation forming germanate (RE-O-Ge) interfacial layer (il) and very good electrical properties [1]..

Charge trapping is an inherent drawback of high-k dielectrics which of course precludes accurate extraction of mobility, flatband (threshold) voltage shift of the devices. It is found that that charge trapping in CeO2 is six time larger that SiO2 [2]. One measure of the quality of the relevant MOS devices is the study of the so-called Border traps (Nbt) which can be obtained by proper analysis of the C-V hysteresis curves. In Fig. 1 the densities Nbt [3] of different REOs such as CeO2, Dy2O3 and La2O3, are compared. Peaks A and B represent

interfacial ( Nit) and bulk traps respectively [2]. In Nbt analysis of CeO2 and Dy2O3 dielectrics two peaks (A, B) were always present which may be related to the poorer overall quality of the devices and is probably due to the created germante. However, with the La2O3 films which show better passivation properties only a single peak (B) was detected which is attributed to i/f defects.

Fig. 2 shows the Nox, Nbt, and Nit as a function of stress time (CVS @ 3V) in CeO2 dielectrics on Ge substrates. The convolutions of the three different traps are illustrated under CVS with respect to successive stresses. The creation of Nit more pronounced than others.

In the Nbt calculation the Nit is contributing (see Fig. 1) also these two traps very difficult to distinguish. We found previously anomalous charge trapping characteristics in CeO2 [4]. More results would be presented in the workshop.

In conclusion, results on REOs grown by MBE on Ge substrates show a direct correlation between passivation and reliability characteristics, while an analysis of bulk and interface traps can explain this behavior.

Fig.1. Border Traps or near interface traps analysis [3] of CeO2, Dy2O3, and La2O3 on Ge substrates. The A and B are interface traps and border traps respectively.

Fig.2. The evolution of Oxide traps (Nox), Border traps (Nbt), and interface traps (Nit) of CeO2 at CVS @ 3V under 10 successive stresses of 1000s each.

References [1] Dimoulas, A., Panayiotatos, Y., Sotiropoulo,s A., Tsipas, P., Brunco D., et al. : Solid State Electron, 51(2007 1508.

[2] Evangelou, E., Rahman, M., and Dimoulas, A.: IEEE Ttrans. Electron Dev. 56 (2009) 399.

[3] Fleetwood, D.: IEEE Trans. Nulc. Sci., 39(1992) 269.

[4] Rahman, M., Evangelou, E., Androulidakis, I., Dimoulas, A. Mavrou, G., and Tsipas,P.,: JVST-B. 27 (2009) 439.

SILICON NANOCRYSTAL - BASED LIGHT EMITTING DEVICES J. M. Ramírez1, A. Tengattini2, Y. Berencén1, D. Navarro-Urrios3, O. Jambois1, A. Anopchenko2, N. Prtljaga2, L. Pavesi2 and B. Garrido1.

1 – Departament d'Electrònica, Universitat de Barcelona, Carrer Martì i Franquès 1, Barcelona 08028, Spain.

2 - Nanoscience Laboratory, Department of Physics, University of Trento, Via Sommarive 14, Povo (Trento) 38123, Italy.

3 -Catalan Institute of Nanotechnology (CIN2-CSIC), Campus UAB, edifice CM3, 08193 Bellaterra, Spain.

corresponding author e-mail: jmramirez@el.ub.es

2

0

10

-2

10

S1 S2 M1 M2 M3 M4

EL (a.u.)

Injected current (A)

10

4

2

600

800

Wavelength (nm) -4

10

-6

10

-8

10

-10

10

10

20

30

40

50

|Voltage| (V)

Fig.1: Forward I(V) curves for all devices. The inset shows the spectrum obtained at 2mA (S1 and S2) and at 200 A (M1).

Fig. 1). In addition, a correlation between the EL and the injected current has been plotted (Fig. 2) and the power efficiency has been obtained. Moreover, a study as a function of the silicon excess has been done for the multilayer structures (M1, M2, M3 and M4). Also, the electroluminescence (EL) spectra of multilayer devices have been compared with the ones provided by the SRN devices (Fig.2). The emerging transport mechanisms under external electric fields and the EL dynamics (decay and rise times) of the system have been also studied in all devices.

Finally, a pulsed polarization scheme has been proposed for the improvement of the optical characteristics and the device lifetime.

Table 1 S1 S2 M1 M2 M3 M4

Si3N4 50 nm (LPCVD) +Si Ion impl. 20% Thermal SiO2 3 nm + Si3N4 (LPCVD) 27 nm + Si Ion. Impl.

4E16 cm-2 LPCVD ((2nm 0% + 3 nm 20%) x 10) + 2 nm 0% LPCVD ((2nm 0% + 3 nm 25%) x 10) + 2 nm 0% LPCVD ((2nm 0% + 4 nm 20%) x 8) + 2 nm 0% LPCVD ((2nm 0% + 4 nm 25%) x 8) + 2 nm 0%

References [1] G. Franzò, A. Irrera, E. C. Moreira, M. Miritello, F. Iacona, D. Sanfilippo, g. Di Stefano, P. G. Fallica, F. Priolo, Appl.

Phys. A. 74 (2002) 1.

[2] J. Linros and N. Lalic, Appl Phys. Lett. 66 (1995) 3048.

[3] B. Jalali and S. Fathpour, J. Lightwave Technolo. 24 (2006) 4600.

[4] Y. Berencén, J. Carreras, O. Jambois, J. M. Ramírez, J. A. Rodríguez, C. Domínguez, Charles, E. Hunt and B. Garrido, Opt. Express, 19 (2011) A234.

[5] A. Anopchenko, A. Marconi, E. Moser, S. Prezioso, M. Wang, L. Pavesi, G. Pucker and P. Belluti, Journ. Appl.

Phys. 106 (2009) 033104.

Electroluminescence (a.u.)

In the last years, an intense research was triggered towards the development of silicon-based light emitting devices to achieve fully silicon-compatible optoelectronic devices. The emerging of new methods to efficiently obtain light emission from silicon has sparked the study and the optimization of all-silicon LEDs [1, 2] providing useful guidelines and a promising overview for the fabrication of functional integrated optics [3]. Then, several perspectives were expected using silicon nanocrystals (Si-ncs) as they provide a higher radiative recombination ratio and good device reliability. In addition, alternative matrices (silicon nitride) were proposed to modify the spectral emission in order to achieve a better color rendering, improve the luminous efficacy of radiation (LER) and obtain a high light quality [4]. Furthermore, new geometries and structures were designed in order to improve the control over the Si-nc size and hence obtain better electro-optical properties [5].

Therefore, by merging all the capabilities presented above, a good scenario for the development of cheap, reliable and functional LEDs is foreseen.

In this work, Metal-Oxide-Semiconductor Light emitting Devices (MOSLEDs) with different structural composition have been designed, fabricated and characterized. The oxide has been replaced by three different active layers: a silicon-rich oxide (SRO), a silicon rich nitride (SRN) and a multilayer structure composed by a sequential deposition of thin SRO and SiO2 layers. A heterogeneous structure of SRO and SRN has also been characterized. All samples have been annealed at 1000ºC for 1h. Table 1 summarizes the composition of the different active layers studied in this work. Electro-optical characterization has been done in devices, obtaining the I(V) curves for each device (Fig. 1) and the EL spectrum for a given injected current (inset of

7

10

6

10

S1 S2 M1 M2 M3 M4

5

10

4

10

10

-7

-6

10

10

-5

-4

10

10

-3

10

-2

Injected current (A)

Fig.2: Electroluminescence as a function of the injected current for the studied samples.

Electrical instability of LaLuO3-based MOSCAPs and role of the metal electrode R.Rao, F. Irrera Sapienza University of Rome and IUNET, Via Eudossiana 18 00184 Roma Italy rao@die.uniroma1.it In this work some aspects of trapping and the specific role of different nitride metal electrodes in the instability of flat band voltage (VFB) are studied in TiN/LaLuO3/IL/Si and TiN-AlN/LaLuO3/IL/Si MOSCAPs. The interlayer (IL) film is silicate/SiO2. LaLuO3 physical thickness is 6 nm; the relative dielectric constant is 30; Si-doping is 1015cm-3; area is 7x10-4cm2. Electrical characterization is performed by the pulsed C-V technique optimized to study fast trapping/detrapping phenomena on a microsecond timescale and to characterize the metal/highk interface electrical quality [1-4]. As for n-type samples, positive voltage pulses are applied to the gate (VP).

Measured data of ∆VFB are plotted in Fig.1.. Electrons are injected from the substrate and trapped thereby. Electron trapping increases monotonically with TP and VP. As for p-type samples, negative pulses are applied. Holes can be trapped at the bottom interface (or in the IL), while electrons are captured by traps located close to the metal interface. The dynamics of VFB depends on the relative contribution of those two mechanisms. The shift of VFB is plotted in Fig.2, for the TiN (closed symbols) and the AlN (open) metal electrode. Curves with the same VP but different metal electrodes are almost superimposed. Data of ∆VFB are already all negative at 100 µs and monotonically become more negative. This indicates that electron trapping at the metal interface does play a minor role in instability, and this does not depend on the specific metal-nitride contact. The contribution from trapped holes dominates always, and increases with time. This behaviour is quite surprising for high-k films. In fact, for comparison, the curve referring to another high-k/metal system (Al2O3/TaN) is drawn (circles) in the inset of Fig.2 together with the present curve of LaLuO3 @-2 V (triangles). In Al2O3/TaN the concurrence of fast electron capturing at extremely short times and (slower) hole trapping at the bottom interface gives rise to that peak and to the prevalence of hole trapping at longer times [1]. We can conclude that, respect to other high-k/metal systems [1,3], the systems LaLuO3/TiN and LaLuO3/AlN exhibit

good interface electronically, as if chemical reactions between LaLuO3 and metal-nitrides were of less entity.

Finally, energy levels of traps in LaLuO3 are extracted from fit of ∆VFB data, with a model recently proposed in literature [5] which derives a power-law dependence of ∆VFB on time: ∆ V FB = a ⋅ t b + c , where a, b, c depend on the electric field and the reacting trap energy level (ET0).

Calculated curves are drawn in Figs.1,2 with solid lines.

A uniform bulk density is used in the model (NT = 1.2x1018 cm-3, derived from measurements reported in [6]). In the Table, distances of ET0 from levels EV and EC of LaLuO3 are listed. Levels around 1 eV below EC are associated to oxygen vacancies with positive charge state V0+ [7]. Voltage acts as a probe: increasing band bending, traps closer to bands may interact with free charge.

Authors thank Dr. J. Schubert of Julich University for samples fabrication.

TABLE ET0-EV @ ET0-EV @ -2.00V [eV] -2.50V [eV] 1.90 1.59 EC-ET0 @ EC-ET0 @ EC-ET0@ 2.65V [eV] 2.80V [eV] 2.90V [eV] 1.06 1.00 0.94

ET0-EV @ -3.00V [eV] 1.28 EC-ET0 @ 3.00V [eV] 0.93

References [1] R. Rao, P. Lorenzi, G. Ghidini, F. Palma, F. Irrera IEEETrans. on Electron Devices, 54, 3, pp. 637-643, 2010.

[2] R. Rao, F. Irrera J. Appl. Phys., 107, 10, pp. 103708, 2010.

[3] R. Rao et al.J. of Vacuum Science and Technology B.,29,1, pp. 01A902, 2011.

[4] W. D. Zhang et al. IEEE Electron Device Lett., 29, 9, pp.

1043-1046, 2008.

[5] R. Rao et al. Appl. Phys. Letters .97, 16 pp.163502, 2010.

[6] Y. Lai et al., presented at 16th Workshop on Dielectrics in Microelectronics (WoDiM) 2010.

[7] K. Xiong, J. Robertson Appl. Phys. Lett., vol.95 no.2, pp.

022903, 2009.

Injection of holes from the substrate and electrons from the gate

0 -0,2

-2.0 V [V]

-0,6

0.4 0.3

FB,initial

∆VFB [V]

-0,4

-2.5 V

0.2

-0,8 -1

- ∆V

-1,2

∆V

0.1 0

-3.0 V

-0.1

FB

-0.2

-4

10

Al2O 3

-0.3

Power-Law Interpolation

LaLuO3

-0.4 -5 10

10

-3

10

-4

10

-3

10

-2

10

-2

10

-1

0

10

-1

10

10

1

0

10

1

10

2

10

3

10

Pulse Time TP [s]

Fig.1 ∆VFB vs. TP and VP for the TiN/LaLuO3/IL/n-Si capacitors. Continuous lines are power-law interpolations.

Fig.2 ∆VFB vs. TP and VP. Metal Electrodes are TiN (open symbols) and AlN (full symbols). Inset: comparison between TiN/LaLuO3 (circles) and TaN/Al2O3

Defect energy levels in MGeOx (M: Hf or La) H Li, J Robertson Engineering Department, Cambridge University, Cambridge, UK corresponding author e-mail: jr214@cam.ac.uk

Reference [1] K. Kita, et al., Jpn. J. App. Phys., 47 2349 (2011)

[2] A. Dimoulas, et al., Appl. Phys. Lett, 96 012902 (2010) [3] M. Oshima, et al., Appl. Phys. Lett, 83 2172 (2003) 6

6

Ge of La2Ge2O7 La of La2Ge2O7 O of La2Ge2O7

4

2

2

0 -10

a

Ge of HfGeO4 Hf of HfGeO4 O of HfGeO4

PDOS

4

PDOS

Ge is proposed as high mobility channel material.

However, the passivation of Ge is more difficult than that of Si. This is mainly due to the volatile GeO problem [1], which means that GeO2 is not suited as a gate dielectric material. Hf and La are found to react strongly with interfacial GeO2, which absorbs germanium and oxygen from the interfacial region, leading to the formation of abrupt metal germinate/Ge interface without GeOx transition region [2]. Oxygen vacancy induced defects in high K dielectrics is widely accepted as an important reason for device degradation. In this work, we studied the defect energy levels in crystalline HfGeOx and LaGeOx. The calculation uses CASTEP. The atomic structure is relaxed by GGA functional in 48~64 atoms’ supercell containing one oxygen vacancy. The band structure is calculated by screened exchange (sX) which does not need band gap correction.

Figure 1 shows the partial density of states of triclinic La2Ge2O7 and tetragonal HfGeO4. The band gap of La2Ge2O7 is ~5 eV and ~5.5 eV for that of HfGeO4. The lower part of the conduction band mainly consists of 5d orbital of metal.

Figure 2 and Figure 3 show two defect configurations and the wave function of the defect in +2, +1, 0 and -1 charge states of La2Ge2O7, where the vacancy is surrounded by two La and one Ge or two Ge and one La, respectively. The wave function shows that S1 state is Ge like mid gap state, while S2 state is La like near conduction band minimum. From Fig. 4(a) we can see all the defect states do not lie within Ge band gap. It is noteworthy in Fig 3(b) that two Ge atoms are attracted towards the vacancy and rebond to each other to form GeGe bond. From Fig. 4(b) we can see that Ge-Ge rebonding in V+1 forming bonding and antibonding states repels defect level away from the Ge band gap.

Figure 4 summarizes the defect energy levels of La2Ge2O7, HfGeO4 and HfSiO4 aligned to Ge/Si band gap. Band alignment in Fig. 4(a-c) is from ab-initio calculation of epitaxial interface models of metal germinate on Ge, while Fig 4(d) uses experimental data.

We found that S1 states of HfGeO4 is more deeper donor states than that of HfSiO4, we also found that (picture not shown) S1 state of V+1 of HfGeO4 is more localized.

In conclusion, we have calculated the energy levels of the various charge states of the oxygen vacancy in LaGeOx and HfGeOx. Most of the defect states are deeper than the equivalent states of HfO2, which means charge trapping will be less prevalent and slower in these two metal germinate. Wave functions of the defect states are also shown.

-5

0 5 Energy(eV)

10

0 -10

b

-5

0 5 Energy(eV)

10

Fig. 1(a) PDOS of La2Ge2O7 , (b) PDOS of HfGeO4.

a

b

c

d

Fig. 2 Wavefunction of S1 and S2 defect states of (a) V-1 (b) V0 (c)V+1 (d)V+2 of La2Ge2O7 (the first vacancy configuration).

b

a

c

d

Fig.3 Wavefunction of S1 and S2 defect states of (a) V-1 (b) V0 (c)V+1 (d)V+2 of La2Ge2O7 (the second vacancy configuration).

4 2

spin down spin up

S2 S2 •

S1 • • S1 • •

-

a

c

4 2 0 -2 -4

−1

G

VO

VO+1

VO+2

b

La2Ge2O7 S2 S2 •

-4

spin down spin up

S2

S2

S2 S2

S1

S1 S1 • • S1 • • S1 •

G

V O− 1 V O0

V

+1 O

HfGeO4

V O+ 2

d

4 2 0 -

S1

S1 • S1 •

G

S2 S1

S2 S2

S2 •

-2

S1 •

S2

S2

0

S1

V O0

spin down spin up

2

S2 S1

S2

S2

0 -

4

spin up and down states splitting less than 0.1 eV are not shown separately

S1 • • S1 •

V O− 1

V O0

La2Ge2O7

S2 S2 •

V O+ 1

+2

VO

spin down spin up

S2

S2 S2

S2 S1

S1 S1• • S1 • • S1•

Si

V O− 1

V O0 V O+ 1 V O+ 2

HfSiO4

Fig. 4 Defect energy level of (a) the first and (b) the second kind of vacancy in La2Ge2O7, (c) HfGeO4 and (d) HfSiO4[3].

Approaches for the reduction of the influence of parasitic capacitances on local IV characteristics for conductive AFM M. Rommel1, J.D. Jambreck1, K. Murakami2, M. Lemberger1, A.J. Bauer1, L. Frey1,2 1 â&#x20AC;&#x201C; Fraunhofer Institute for Integrated Systems and Device Technology, Schottkystrasse 10, 91058 Erlangen, Germany 2 â&#x20AC;&#x201C; Chair of Electron Devices, University of Erlangen-Nuremberg, Cauerstrasse 6, 91058 Erlangen, Germany corresponding author e-mail: mathias.rommel@iisb.fraunhofer.de Conductive AFM (cAFM) is a powerful technique for studying electrical properties of SiO2 and high-k materials on the nanoscale [1-3]. Next to imaging lateral property variations by current mapping at a fixed bias voltage, cAFM enables the recording of local current-voltage (IV) characteristics trough the dielectrics with nanometer resolution (mainly limited by the size of the tip apex). This allows for the localized evaluation of current conduction mechanisms (e.g., to compare between grains and grain boundaries of high-k films [3]). Note that the relevant tipdielectric-semiconductor capacitance is extremely small (i.e., in the aF range [4]). cAFM IV curves are obtained by applying a voltage sweep with a sweep rate sr.

However, the sensitivity of acquired IV curves by cAFM is usually limited by high parasitic currents for small bias voltages (i.e., minimum current densities (J) of cAFM characteristics which can surely be attributed to the leakage currents through the dielectric are very high, see Fig. 1 and e.g. [2]). As will be discussed, this is mainly due to rather large parasitic capacitances Cpar (in the pF range) between the cantilever or the tip holder and the sample which are more pronounced in the centre of a sample [4]. Cpar will lead to approx. constant displacement currents which are proportional to sr (see Fig. 2 for tip B). In addition, for abrupt changes in current, transient effects occur which are due to the high sensitivity cAFM current amplifier and Cpar (again more pronounced for higher sr, see Fig. 2). Thus, smaller sr cause smaller parasitic currents. However, small sr also lead to higher electrical stresses during the sweep due to the longer measurement times and high current densities, especially when measuring in the Fowler-Nordheim tunnelling regime [2].

In addition, significant charge trapping will already occur in high-k materials during the first sweep.

In this work, therefore, different approaches will be presented to increase the sensitivity of cAFM (i.e., to increase the current density range available for evaluating current conduction mechanisms) even for moderate and high sr. In particular, the advantage of using special

shielded tips (tip B) rather than commercially available silicon tips coated with Pt/Ir (tip A) is demonstrated (see Fig. 2). Tips B have a strip line design realized by focused ion beam processing.

On the other hand, different approaches to correct the measured data for both, displacement current and transient effects will be presented and critically discussed. As an example, Fig. 3 shows the corrected IV curves of Fig. 2 for high sr using an approach where both, forward (from 0 V to -5 V) and reverse (from -5 V to 0 V) sweep directions are considered. For tips B, corrected currents of 20 fA with a noise of 100 fA are obtained, even for very high sr and in the centre of the sample. This is due to the reduced Cpar of tips B. As will be shown, for sr of 1 V/s and below, average currents of 3 fA with noise levels of 40 fA (noise level of the amplifier [1]) can be achieved.

All measurements were performed using a Bruker Dimension Icon system with a Nanoscope V controller.

Next to the results for 5 nm SiO2 samples presented in Figs. 2 and 3, experiments for larger voltage ranges and HfO2 high-k samples with smaller effective oxide thickness will be shown. Other aspects like absolute noise level and offset current as well as the observed transient effects will be discussed and recommendations for optimized measurement and evaluation procedures will be given.

Summarizing, the use of shielded tips together with proper data evaluation procedures allows to minimize the influence of Cpar on local cAFM IV measurements which enables to access strongly increased current ranges for the localized evaluation of current conduction mechanisms.

References [1] P. De Wolf, E. Brazel, and A. Erickson, Mat. Sci. Semicond.

Proc. 4 (2001) 71.

[2] V. Yanev, T. Erlbacher, M. Rommel, A. J. Bauer, and L. Frey, Microelectron. Eng. 86 (2009) 1911).

[3] K. Murakami, M. Rommel, V. Yanev, A.J. Bauer, and L. Frey, AIP Conf. Proc. 1395 (2011) 134.

[4] G. H. Buh, Ch. Tran, and J. J. Kopanski, J. Vac. Sci. Technol. B 22 (2004) 417.

limited sensitivity

Fig.1.Comparison of conventional and cAFM JV characteristics (4 nm SiO2).

V is applied to the semiconductor.

Fig.2. As-measured cAFM IV curves with Fig.3. Displacement current corrected IV different sr and tips for 5 nm SiO2 curves with sr of 10 V/s (from Fig. 2). at the centre of the sample.

Dielectric Material Options for Integrated MIM Capacitors G. Ruhl1, M. Lukosius2 1 – Infineon Technologies AG, Wernerwerkstrasse 2, 93049 Regensburg, Germany 2 – IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany corresponding author e-mail: guenther.ruhl@infineon.com With continuous progress in miniaturization of microelectronic components for mobile communications and automotive applications, also passsive components, like capacitors, have to be miniaturized. Currently highcapacity capacitors are generally mounted as discrete SMD devices. In order to reduce footprint, there is the need to integrate capacitors in Si devices, either monolithically as System-on-Chip (SoC) or separately as System-in-Package (SiP) solutions. Maximizing the specific capacity by forming three-dimensional capacitors is going to face its limits set by trench etch technology. Thus increasing the dielectric constant k of the capacitor dielectric is a further option. However, there is the intrinsic drawback of high leakage current density with increasing k-value.

In this work an extensive material screening has been performed utilizing deposition techniques, like ALD or AVD®, which yield high step coverages required for 3D capacitor fabrication. Also metal electrodes have been investigated, which are necessary to build MIM capacitors with high quality factors. It was found that at operation voltages of  3 V leakage current density requirements of ≤ 10-7 A/cm² can only be achieved with k-values below 50 (figure 1).

The introduction of leakage current blocking layers leads to the formation of stacked dielectrics with improved leakage behaviour (figure 2). However, a compromize has to be accepted for the dielectric constant.

Supported by experimental data, the potential of stacked dielectrics is investigated.

Another important parameter for dielectrics is breakdown field strength. Based on an universal model for the breakdown field dependence on the dielectric

constant [1], the potential of single layer and stacked layer dielectrics with respect to maximizing specific capacity at a given breakdown voltage is discussed.

Finally it can be shown that stacked layer dielectrics are a possible approach for maintaining low leakage current densities at reasonable specific capacities.

Fig.1. Leakage current density vs dielectric constant of several dielectrics studied in a material screening experiment.

Fig.2. Leakage current density of a SrTiO3/Sr2Ta2O7 dielectric stack with varying current blocking layer thickness.

This work was supported by the grant from German BMBF (grant No. 13N9926).

References [1] J. McPherson, J. Kim, A. Shanware, H. Mogul, J. Rodriguez, IEDM `02 Digest (2002) 633.

Non-volatile data storage in 28nm ferroelectric FETs U. Schroeder1), J. Mueller3), E. Yurchuk1), S. Mueller1), D. Martin1), C. Adelmann4), and T. Mikolajick1)2) 1

NaMLab GmbH, Noethnitzer Str. 64, 01187 Dresden, Germany Institut fuer Halbleiter und Mikrosystemtechnik, TU Dresden, Noethnitzer Str. 64, 01187 Dresden 3 Fraunhofer Center for Nanoelectronic Technologies, Koenigsbruecker Strasse 180, 01099 Dresden 4 IMEC, Kapeldreef 75, 3001 Leuven, Belgium 2

Ferroelectric materials have a high potential for nonvolatile data storage. The range of applications is determined by the properties of the used materials.

Conventionally materials like lead zirconate titanate (PZT), which possess only limited compatibility with standard semiconductor processing, are implemented. Integration into transistor devices is only possible with thick interfacial barriers and ferroelectric layers thicker than 100 nm need to be used in order to achieve nonvolatility2. Hence, no easy scaling of the devices according to current technology node requirements can be realized.

Recently doped hafnium oxide was shown to be ferroelectric3. This discovery opens up an interesting pathway to build highly scalable ferroelectric devices.

The polarization hysteresis of this novel ferroelectric shows a remnant polarization of up to 25 μC/cm².

These properties are caused by specifically chosen dopand/HfO2 compositions as well as by mechanically confining the ferroelectric layer using TiN electrodes. Since ferroelectricity necessitates the formation of a non-centrosymmetric crystallographic phase, the existence of an orthorhombic phase of space group Pbc21 at the boundary between the monoclinic and the tetragonal phase was proposed3.

In general, varying the dopant content from 0-10 mol% is causing the formation of different HfO2 phases: a mainly monoclinic lattice for pure HfO2, appearance of the orthorhombic phase for ~5 mol% dopant and the formation of the high temperature phases, tetragonal or cubic, for higher dopant contents.

Parallel to the crystallographic transformation a change of the dielectric properties from paraelectric to ferroelectric then antiferroelectric and back to paraelectric is visible.

Dopant atoms with an atomic radius ranging from ~40% smaller (e.g. Al, Si) to ~15% larger (e.g. Y, Gd) compared to hafnium showed to enable this effect in HfO2 layers down to 6 nm thickness4-6. No dead layer effects like in PZT films have been observed. The (anti-) ferroelectric effect can be found for trivalent and tetravalent substitution and even in the case when both materials have similar atomic radii like for Hf and Zr. In all cases a ferroelectric hysteresis of metal/ferroelectric /metal capacitors is visible. Switching times as short as a few nanoseconds could be observed by PUND measurements.

In addition, 28nm ferroelectric field effect transistors (FeFET) were successfully fabricated. A memory window of 1.2 V was obtained7. Retention and endurance characteristics were measured in a wide temperature range. A remaining memory window after 10 years of 0.7 V was extrapolated.

Acknowledgments The work for this paper was supported within the scope of technology development by the EFRE fund of the European Community and by funding from the Free State of Saxony (Project MERLIN).

References: [1] H. P. McAdams at al., IEEE Journal of Solid State Circuits, Vol. 39, No. 4, p. 667, 2004 [2] L.V.Hai et al., Proceedings of IEEE International Memory Workshop, p. 1, 2011 [3] T. S. Böscke at. al, Appl. Phys. Lett., vol. 99, p. 102903, 2011.

[4] J. Müller et al., Appl. Phys. Lett., vol. 99, p. 112901, 2011.

[5] J. Müller et al., J. Appl. Phys., vol. 110, p. 114113, 2011.

[6] S. Mueller et al., Adv. Func. Materials, 2012, 10.1002 [7] J. Müller at al., IEEE Electron Device Letters, vol. 33, 2, p.

185, 2012

Influence of strain on dielectric properties of rare earth oxides D. Schwendt1, P. Shekhter2, M. Eizenberg2, and H. J. Osten1 1

2 Institute of Electronic Materials and Devices Department of Materials Engineering Leibniz Universität Hannover Technion–Israel Institute of Technology corresponding author e-mail: schwendt@mbe.uni-hannover.de

Recent years have opened the door to several novel devices concepts and the hope of their successful integration with conventional electronics. In parallel, increasingly complex oxides are being incorporated into high performance logic and memory devices. For both, the development of oxides is required with a quality comparable to that of high-purity semiconductors to create systems with novel functionalities for a broad range of electronic applications. A very promising way to realize advanced future devices is using single-crystalline, closely lattice matched oxides, which will be deposited on the substrate of choice. Such an approach will annihilate the risk of re-crystallization, prevent the formation of interfacial layers and enable controllable interface properties. Moreover, oxide layers which are lattice matched to Si may enable epitaxial growth of semiconducting layers on the oxide itself, enabling novel devices, such as resonant tunnelling diodes and quantumwell devices. In addition, binary crystalline rare earth oxides have proved to be a very promising group of dielectrics for epitaxial deposition, either on Si, Ge, or GaAs. These oxides suggest high enough K-values and a relatively large energy band gap with symmetrical conduction and valance band discontinuities to the relevant semiconductor substrates. Thin crystalline gadolinium oxide films epitaxially grown on silicon exhibit dielectric constants above 20 although the known bulk value is only 13. The reason for this effect is not fully understood yet.

Many of the rare earth oxides are isomorphic miscible in one another. This property opens the possibility to induce changes in the lattice constant (and finally the dielectrical properties) without altering the equilibrium

unit cell symmetry. This approach can lead to the realization of rare earth oxides with tuneable lattice mismatch and electrical properties. Controlling the oxide composition in ternary thin films therefore should tune the K-value of the dielectric layer, while retaining the ability for epitaxial growth. For that purpose, we chose Gd2O3 (with a slightly smaller unit cell compared to silicon) and Nd2O3 (with a larger unit cell). First we investigate the effect of oxide strain level on the ability to epitaxially grow thin oxide layers on Si. Figure 1 shows the X-ray diffraction patterns of (Gd1-xNdx)2O3 thin films grown on Si(111) with x ranging from 0 (binary Gd2O3) to 1 (binary Nd2O3). It clearly shows that already both thin binary layers exhibit an out-of plane lattice constant which is significantly different from the bulk values. The peaks for the ternary compounds show that we are able to tune the out of plane lattice constant. Figure 2 shows the results electrical investigations on ternary oxides with different (Gd1-xNdx)2O3 compositions and therefore varying strain.

Open symbols indicate values obtained at the Technion.

Binary oxides show the known behaviour of epitaxial rare earth oxides on Si, while a lower misfit level results in bulk-like K-values.

Acknowledgment The authors would like to acknowledge the partial support of the work by the Deutsche Forschungsgemeinschaft (DFG Project OS 112/5-1).

Fig.1. Θ-2Θ scans of the (444) peaks of different (Gd1-xNdx)2O3 layers grown on Si(111). The dashed lines indicate bulk values taken from the literature.

Fig.2. Dielectric constants for various (Gd1-xNdx)2O3 layers grown epitaxially on Si(111). The values were extracted from CV measurements on ~6 nm thick layers. Open symbols indicate values measured at at the Technion.

References [1] V. V. Afanas’ev, M. Badylevich, A. Stesmans, A. Laha, H. J. Osten, A. Fissel, W. Tian, L. F. Edge, and D. G. Schlom: Appl. Phys. Lett. 93 (2008) 192105c.

[2] N.W. Grimes and R.W. Grimes:J. Phys.: Condens. Matter 10 (1989) 3029.

Local Oxide Capacitance as a Crucial Parameter for Characterization of Hot-Carrier Degradation in High-Voltage n-MOSFET I. Starkov1,â&#x2039;&#x2020; , H. Enichlmair2 , and T. Grasser1 1

Institute for Microelectronics, Vienna University of Technology, Wien, Austria Process Development and Implementation Department, Austriamicrosystems AG, Unterpremstaetten, Austria â&#x2039;&#x2020; corresponding author e-mail: starkov@iue.tuwien.ac.at Hot-carrier degradation (HCD) is associated with the build- Additionally, to ensure that the device geometrical peculiariup of interface states and oxide trapped charges (with densities ties are taken into account, a parametric system (1) was exNit and Not ) of an MOS transistor. Therefore, quantitative amined on the two artificial devices with Lch =0.5Âľm but with information on the defect spatial distributions is essential to different oxide thicknesses of tox,0 (x)=tox,0 and tox,2 (x)=tox,0 + reveal and understand the physical mechanisms of the HCD 2â&#x2C6;&#x2020;tox (x). A comparison of the simulation approach [3] and phenomenon. For this purpose, the charge-pumping (CP) tech- model (1) for tox,{0,1,2} shows a good agreement in Fig.1. nique is widely used [1]. Most methods for extraction of the latFor characterization of the Nit (x) evolution with the stress eral defect profiles from CP data employ a constant transistor time we employed the analytical Cox (x) distributions incorpooxide capacitance, namely Cox =Îľox /tox,0 , where tox,0 is the ox- rated into the scheme described in [5]. One can see in Fig.2 ide thickness at the center of the device and Îľox is the dielectric that the extracted defect profiles features two peaks starting permittivity (e.g. [2]). In such an approach the MOS structure from â&#x2C6;ź 102 s. Moreover, Fig.2 demonstrates that these peaks is considered as an ideal infinite parallel-plate capacitor or, in just correspond to the maxima of the electron and hole accelother words, the oxide electric field is assumed uniform. How- eration integrals [6]. This result is confirmed by the findings of ever, accounting of the fringing effect is of great importance our HCD model [6] which shows that these peaks are related for the characterization of the defect spatial distributions after to the contributions induced by primary channel electrons and hot-carrier stress because the Nit (x) peak is located near the secondary generated holes. The obtained defect profiles were drain end of the gate [1]. In literature we were able to find subjected to further validation as input parameters to simuconsideration of the oxide capacitance coordinate dependence late the Idlin degradation. Comparison of simulated and exonly in the work of Lee et al. [3]. This approach is based on the perimental curves once again confirms the applicability of the simulation of the local threshold voltage shift induced by the developed model (see Fig.1, inset). It should be noted that the given unifirm oxide charge distribution and requires adequate change of the Idlin degradation slope appearing at â&#x2C6;ź 102 s for computational resources. Thus, an compact analytical model both devices can be linked to the contribution of the hole Nit for simplification of the defect profile extraction technique is peak to the total defect density. of great importance even nowadays. For the solution of this We have shown that the accurate consideration of the oxproblem we use the conformal-mapping method which is most ide capacitance dependence on the lateral coordinate is essenhelpful for fringing the electric field in simple 2D boundary con- tial for the proper extraction of the defect profiles from CP ditions [4]. Following the standard calculation procedure [4], data. Presented analytical model for Cox (x) was verified by the Cox (x) can be then defined as representing Idlin degradation in 5V n-MOSFETs with various

channel lengths. Obtained results demonstrate a good agreex = tox,1 (x)(Ď&#x2022; + exp(Ď&#x2022;))/Ď&#x20AC; (1) ment with our physics-based HCD model.

Cox (x) = Îľox /(tox,1 (x) + tox,1 (x) exp(Ď&#x2022;))

2

Oxide thickness of transistor is interpreted as tox,1 (x)=tox,0 + â&#x2C6;&#x2020;tox (x), where â&#x2C6;&#x2020;tox (x) is the thickness gradient component, which increases closer to the end of the gate contact. For validation of the developed analytical approach we use two 5V n-MOSFETs with identical architecture differing only in channel lengths (Lch =0.5 and 2.0Âľm). The drain-sided gate edge is the origin of the x-axis for the both devices. Transistors were fabricated on a standard 0.35Âľm technology and subjected to a hot-carrier stress at the gate voltage Vgs =2.0V and the drain voltage of Vds =6.25V up to 105 s. For charge-pumping current measurements we use an experimental scheme suggested in [5].

Fig.1. The Cox,{0,1,2} (x) (indexes correspond to the considered oxide thicknesses) calculated using the approach of [3] (symbols), compared with the developed analytical model (lines) in the case of Lch =0.5Âľm. Inset: the relative Idlin change vs. stress time experiment and simulation results for Lch =0.5 and 2.0Âľm.

References

[1] Heremans, P., Witters, J., Groeseneken, G., and Maes, H.: IEEE Trans. Electron Dev. 36 (1989) 1318.

[2] Mahapatra, S., Parikh, C., Rao, V., Viswanathan, C. and Vasi, J.: IEEE Trans. Electron Dev., 47(2000)789.

[3] Lee,R.G.-H., Su, J.-S., and Chung, S.S.: IEEE Trans. Electron Dev. 43 (1996) 81.

[4] Pesonen, N., Kahn, W., Allen, R., Cresswell, M., and Zaghloul, M.: IEEE Trans. on Instr. and Meas., 53 (2004) 812.

[5] Chim, W.K., Leang, S.E., and Chan,D.S.H.: Journ. Appl.

Phys., 81 (1997) 1992.

[6] Tyaginov, S. et al.: Proc. of the SISPAD, Osaka, Japan, 8-10 Sep., 2011, p. 123.

Fig.2. The evolution of interface state density profiles with stress time for Lch =0.5 and 2.0Âľm. Peaks of Nit (x) correspond to the maxima of electron (AIe,{0.5,2.0} ) and hole acceleration integrals (AIh,{0.5,2.0} ) [6].

Spectroscopic study of polysilicon traps by means of fast capacitance transients M. Toledano-Luque1,*, B. Tang2, R. Degraeve1, B. Kaczer1, E. Simoen1, J. Van Houdt1, G. Groeseneken3 1 – imec, B-3001 Leuven, Belgium (*corresponding author e-mail: toleda@imec.be).

2 – Liverpool John Moores University, L3 3AF Liverpool, United Kingdom.

3 – also with ESAT Dept., KU Leuven, B-3001 Leuven, Belgium Polycrystalline silicon is a key component in 3D SONOS memories [1-2], TFTs [3], and solar panel construction [4] due to the simple processing and low cost. In order to achieve high performance for all these applications, low defective polysilicon is required to avoid the degradation of carrier lifetime and mobility by recombination in deep traps and/or scattering. For this reason, research centres are urgently demanding an effective poly-Si characterization technique. In this work we present a simple methodology based on deep level transient spectroscopy (DLTS) to assess the energetic position of the traps inside the polysilicon band gap, but without the experimental complexity of the standard systems [5]. This methodology relies on the ability of the fast Agilent E4980A Precision LCR meter to register the capacitance transients observed after applying a disturbing gate voltage to a polysilicon capacitor. The temperature dependence of the capacitance transients is transformed to a trap energetic profile.

50×50m2 capacitors formed by 10nm-SiO2 gate dielectric and 100nm-polysilicon deposited on n-type monocrystal silicon were under study. The capacitance transients were registered at VSENSE~VFB after removing a positive-filling-gate-pulse with a magnitude close to VTH and 2s-duration (see Fig. 1(a)). The transients were measured between 20ms and 200s at temperatures ranging from 80K to 300K. The filling and sense voltages were kept between VFB and VTH in order to only induce silicon band bending and to avoid the injection of charge in the dielectric. Indeed, no capacitance transients were observed for a capacitor without the 100nm-poly-Si layer

for all the temperature range, indicating that the dielectric is not the responsible of these capacitance variations.

During the positive filling gate pulse, the device is forced to deep depletion and electrons are captured in the polysilicon traps. Afterwards, at sense conditions, the increase of the capacitance w.r.t. the value prior to the filling pulse indicates a positive shift of VFB, i.e. electron trapping. These trapped electrons placed over the Fermi level are gradually emitted and VFB returns to its original value. ΔVFB defined as the difference of VFB at two sampling times (t1=20ms and t2=5s) is related to the number of emitted electrons. ΔVFB depends on temperature T since the emission of electrons trapped in the silicon gap in a fixed time window depends on T. As shown in Fig. 1(b), electrons placed at shallow positions are emitted at low temperatures, while the deep traps are discharge at high temperatures. Therefore, a temperature sweep allows scanning different energetic intervals. Fig. 2 shows the correspondence between temperature (top axis) and the trap energy ET (bottom axis) considering eqs. (1) and (2) in Fig. 1 [5].

Fig. 2 shows the ΔVFB (~number of traps) obtained after transforming ΔC through the CV curve [6] as a function of EC-ET. Two defect levels clearly appear at 0.31eV and 0.58eV for the as-deposited poly-Si. A spike anneal of the poly-Si at 1100ºC for 2s reduces by more than a factor of two the intensity of both peaks, i.e. the number of traps.

In conclusion, we have demonstrated a simple methodology to assess the energy spectrum of defects in the polysilicon band gap. An important reduction of the poly-Si trap density can be achieved by spike annealing.

Refs: [1] J. Choi and K. Seol, VLSI11; [2] J. Jang el al., VLSI09; [3] L. Li et al., TED2012; [4] B. Hekmatshoar et al.; IEDM2011; [5] D.V. Lang, JAP, 45 (1974); [6] M. Toledano-Luque et al., TED (2011).

Fig.1. (Left) Capacitance transients measured after a positive pulse (VFILLINGE~VTH) on as-deposited poly-Si for temperature ranging from 80 to 300K with steps of 10K. (Right) Different energetic intervals are scanned as a function of temperature and experimental timing window. Eqs. (1) and (2) provide the correspondence between the theoretical and experimental emission times.

Fig.2 Poly-Si trap spectra for as-deposited and spike anneal samples. Two defect levels are observed at 0.31eV and 0.58eV below the poly-Si conductions band. A significant reduction of the intensity of the bands is observed for the annealed sample.

Toward a Streamlined Projection of Small Device BTI Lifetime Distributions M. Toledano-Luque1,*, B. Kaczer1, T. Grasser2, Ph. J. Roussel1, J. Franco1,3, G. Groeseneken1,3 1

imec, Kapeldreef 75, B-3001 Leuven, Belgium, 2TU Wien, Vienna, Austria, 3KU Leuven, Leuven, Belgium; *mailto:toleda@imec.be

With the continuous downscaling of CMOS device dimensions, i) the number of gate oxide defects in each device decreases to numerable level [1-3], while their relative impact on the device characteristics increases [46]. ii) The properties of each defect, such as its capture and emission times, its impact, etc., have been shown to be voltage and/or temperature dependent and widely distributed [7-10]. iii) The occupation kinetics of each defect appears to involve metastable states and is known to be stochastic [11-12]. All of these results in each of the nominally identical nm-scaled devices behaving very differently during operation, resulting in increasing timedependent variability (heteroskedasticity). Consequently, the lifetime of nm-sized devices cannot be predicted individually, and can be only described in terms of time(or workload-) dependent distributions.

It is, however, practically impossible to study the above-listed contributions or even to merely measure a sufficiently large number of devices of each new device variation and/or process split. Here we therefore discuss a possible path for obtaining the small device lifetime projections from combining measurements of a reasonably small sample set of nanoscaled devices and a few large area devices typically fabricated for test purposes on the same chip. We identify the sources of discrepancies in this approach.

Fig. 1 shows the relaxation traces after a BTI stress, each trace revealing the combined response of multiple defects in a device perturbed by the accelerated test. The figure further illustrates the wide variation in the behavior of individual devices. We have previously shown that this variation can be described analytically [5], see Fig. 2, by means of two parameters: the mean total ∆VTH and the mean impact on VTH per trap η, i.e., 〈∆VTH〉 = η×NT, with NT the mean number of active traps. The 〈∆VTH〉 increase

with temperature is reflected in an escalated NT. The ∆VTH’s obtained from both nanoscaled and large pFETs follow an Arrhenius law with similar activation energy (~118mV, Fig. 3). However, ~5× larger degradation is observed in small devices at all stress conditions. Since 〈∆VTH〉small = (η×NT,small / η0×NT,large) × ∆VTH,large, η0 being q/COX, the 5× increase is due to i) the larger impact per charged trap (η/η0~2) caused by channel percolation effects in small devices [1-3], and ii) the higher trap density in smaller devices likely due to edge-related processing effects.

Considering these findings, BTI lifetime distributions can be obtained by combining i) ∆VTH measured on large devices at different stress conditions and ii) the η and the NT impact determined from a reduced sample size of the technology under study.

Refs: [1] Asenov et al., TED50, 1254 (2003); [2] Bukhori et al., TED57, 795 (2010); [3] Ghetti et al., TED56, 1746 (2009); [4] Huard et al., IRPS08; [5] Kaczer et al., EDL31, 411, (2010); [6] Franco et al., IRPS12; [7] Kaczer et al., IRPS 2009; [8] Grasser et al., PRB82, 245318 (2010); [9] Toledano et al., Micr.Eng.88, 1243 (2011); [10] Toledano et al., VLSI11; [11] Grasser et al., IRPS2010; [12] Grasser et al., IRPS2012.

Fig.2: Cumulative small device distributions of the total ∆VTH after stress (a) at different temperatures shown in Weibull plots. (Lines) Total ∆VTH CDFs for different NT values [5] match excellently the experimental data. (Inset) Complementary cumulative distributions (1CDF) of step heights due to single oxide defects follow an exponential distribution with the average step height η = 3.4mV.

Fig.1: Bias temperature instability (BTI) relaxation transients obtained on W×L=90×45 nm2 0.8nm-SiO2/1.8nm-HfSiO pFETs. Steps due to single-carrier discharge events are evident. The large dispersion is due to the stochastic distributions of NT and the impact of each trap.

Nevertheless, the average relaxation resembles the curve taken on a large area device indicating that identically behaving traps are responsible of BTI on small and large area FETs.

Fig.3: The ∆VTH’s at 1ms relaxation time obtained on small, 90×45 nm2 and large, 10x0.5µm2 pFETs follow Arrhenius law with apparent activation energy of 118mV. 5× larger degradation is observed for the nano-scaled pFETs for the technology under study.

Bound states within the ‘notch’ of the HfO2/GeO2/Ge stack Zhong Wang, Jason Ralph, Naser Sedghi and Steve Hall Department of Electrical Engineering and Electronics, University of Liverpool, Liverpool, UK Corresponding author e-mail: Z.Wang4@liv.ac.uk calculated for various applied voltages. In the first simulation the thickness of high-κ layer was kept constant at tHK = 4 nm, and the thickness of IL, tIL, was changed from 1 nm to 2.5 nm (Fig. 2, top graph). In the second simulation tIL is kept constant at 1 nm and tHK is varied from 4 nm to 15 nm (Fig. 2, bottom graph). When tHK is constant, N does not have a strong dependence on tIL and saturates to about 5 or 6 at oxide voltage above 2 V. Whereas in case of constant tIL the number of states has a strong dependence on tHK, particularly at oxide voltages above 1.6 V. For scaling down Ge MOS transistors, the technology roadmap for the 22 nm node requires equivalent oxide thickness of 1 nm, which implies a reduction of the IL thickness to 0.25 nm [6]. The supply voltage for this node is below 1 V. Significantly, for a 2 nm high-κ layer with IL thickness of 0.25nm and 0.5 nm, the number of bound states in the notch was found to be only 2 to 3 for oxide voltages above 1.7 V, and there are no bound states at voltages below one volt. This suggests that the potential charge trapping may not be an issue for highly scaled devices.

Future work will be to calculate the steady state charge that can accumulate within the ‘notch’, using the bound states obtained in this paper and the capacitive energy of the bound electrons. The possibility for resonant tunnelling leakage current will also be investigated.

The work was funded by the EPSRC UK. References [1] C. O. Chui et al.: IEEE Electron Device Lett. 23(2002), 473.

[2] S. K. Wang et al. :J. Appl. Phys. 108 (2010) 054104.

[3] G. Lucovsky, et al.: Appl. Surf. Sci., 254 (2008), 7933.

[4] L. Linet al.: Appl. Phys. Lett. 97 (2010), 242902.

[5] V. V. Afanas’ev and A. Stesmans: Appl Appl. Phys. Lett.

84(2004), 2319.

[6] International Technology Roadmap for Semiconductors (ITRS) Report (http://www.itrs.net), 2011.

Number of states within 'notch' N

Number of states within 'notch' N

High-κ dielectric on germanium (Ge) is a promising combination for high performance MOS devices which can benefit from both high mobility of Ge and high dielectric constant of the gate oxide [1]. GeO2 is used as the passivating, interfacial layer (IL) between Ge and high-κ dielectric. However, it appears that it is more problematic than its counterpart in Si devices, due to some issues such as thermal instability, water absorbency, and in particular, desorption of the volatile GeO [2]. In this work, another issue for high-κ/GeO2 gate stacks is addressed: the appearance of a possible charge trapping centre. The band gap of GeO2 is smaller than that of the most common high-κ dielectrics and the conduction band offset between the two dielectrics creates a so-called ‘notch’ at positive gate voltage, as shown in Fig. 1.

Electrons injected from the inversion layer of the Ge channel to the notch could be trapped in quantized bound states associated with the potential well. It is useful therefore to study the quantized bound states within the notch and their variation with applied voltage and dielectric thickness. The conduction band offsets for Ge:GeO2 and Ge:HfO2 are 0.8 eV and 2 eV, respectively [4,5].The energy eigenvalues of the bound states are calculated using numerical diagonalization of the stack Hamiltonian matrix. Computer simulations are used to find the number of bound states, N, within the notch for various oxide voltages and thicknesses of IL and high-κ layers. Bound states can occur when the energy eigenvalues En are lower than Elmax and Ermax, the highest energy of the left and right edge of the ‘notch’, respectively (Fig.1), and the rates of thermal activation and barrier tunneling are sufficiently low. Thermal activation is governed by kT, where k is Boltzmann's constant and T is absolute temperature; tunnelling through the barrier can be related to the area of the barrier above En. The number of bound states within the notch was

tIL

6

tHK=4nm

1 nm 1.4nm 1.6nm 2nm 2.5nm

4 2 0 20 18 16 14 12 10 8 6 4 2 0

tHK

tIL=1nm

4nm 6nm 8nm 10nm 15nm 0.5

1.0

1.5

2.0

2.5

3.0

3.5

Oxide voltage across HfO2/GeO2 stack Vox (V)

Fig. 1. The energy band diagram of HfO2/GeO2 gate stack. The number of bound states is calculated between lines 1 and 2.

Fig. 2. Number of bound states in the notch as a function of oxide voltage and thickness of IL (top) and high-κ (bottom).

Detailed leakage current analysis of MIM capacitors with ZrO2, ZSZ and ZAZ as dielectric and TiN electrodes Wenke Weinreich1, Albena Paskaleva2, Konrad Seidel1, Jonas Sundqvist1, Martin Lemberger3, Anton J. Bauer3 1 Fraunhofer Center Nanoeletronic Technologies, Koenigsbruecker Str. 180, 01099 Dresden, Germany 2 Institute of Solid State Physics, Bulgarian Academy of Sciences, 72 Tzarigradsko Chaussee, 1784 Sofia, Bulgaria 3 Fraunhofer Institute of Integrated Systems and Device Technology, Schottkystrasse 10, 91058 Erlangen, Germany corresponding author e-mail: wenke.weinreich@cnt.fraunhofer.de There is a great interest on ZrO2 as high-k dielectric in MIM capacitors for various applications like DRAM and eDRAM as well as buffer and decoupling capacitors as integrated passives in SiP or SoC systems. Since all applications require high reliability intensive material tuning and optimization of the electrical properties (CET, leakage current - LC) is essential. Thus, this paper will give a systematic and detailed study on the electrical properties of ZrO2-based MIM capacitors. Many parameters influencing the LC like dopant concentration, layer thickness, crystallinity, interfaces, ALD process, PDA and PMA will be discussed in dependence of voltage polarity.

The ZrO2 films with nominal thicknesses of 7, 8 and 9nm were grown by ALD (TEMAZ, O3, 275°C) and partially doped either by 2 cy Si (3DMAS, ZSZ) or by 5 cy Al (TMA, ZAZ) in the middle of the layer. For one set of samples the O3 pulse time in the ZrO2 ALD process was varied (2, 5, 10, 30s). Several annealing steps were analysed for the optimized pulse time (PDA at 650°C in N2 or NH3, PMA at 650°C). As top and bottom electrode TiN is used.

The dielectric constant in the range of 26 to 39 for all films depends mainly on the dopant concentration and the crystallinity. The O3 pulse time increase causes an enhanced layer growth due to CVD effects. This is also visible by higher CETs (Fig.1.). The optimum LC and CET can be achieved with 5s O3 pulse time. Thin films with Al doping and low O3 pulse time are only partially crystalline after top electrode deposition at 450°C showing a higher CET than thicker, but crystalline films.

A detailed analysis of leakage current mechanisms (LCM) will be given for films with 5s O3 pulse time and several anneals (Fig. 2.). Generally, trap-assisted tunnel processes (TAT) dominate in thin films and Poole Frenkel

Fig. 1. J versus CET for ZSZ and ZAZ films with different O3 pulse times. Numbers are nominal thicknesses.

(PF) emission is more notable in 9nm films. The main trap depth can be extracted at 1,3eV which is comparable to simulations [1,2] and can be assigned to oxygen vacancies. The dependence of vacancy charging on thickness and doping will be further discussed in the paper. Additionally, a strong voltage polarity asymmetry will be addressed resulting from an internal field which affects tunnelling and PF emission in different ways.

Doping of crystalline ZrO2 has only minor effects on the general occurrence of LCMs like a change of FowlerNordheim tunneling to TAT at high fields. But the discussion of partially crystalline films will show significant differences with an enhanced voltage polarity asymmetry of the LC and PF domination even in 7nm films. The reason for that is a two phase system near the bottom electrode with higher defect density. Applying a PDA in N2, these films can be crystallized having now the same properties like an undoped crystalline ZrO2. The use of a PMA causes higher voltage polarity symmetry of the LC. Although a PDA in NH3 crystallizes the films it results also in a two phase system by the incorporation of nitrogen near the bottom inter-face inducing the electrical properties of a partially crystalline film.

In summary, this paper will give a detailed understanding of MIM capacitors with ZrO2 based dielectrics demonstrating the potential of this material for various applications above all as DRAM dielectric below the 20nm generation.

References [1] G. Jegert , A. Kersch, W. Weinreich, U. Schröder, and P.Lugli, Appl. Phys. Lett. 96, 062113 (2010) [2] G. Jegert , A. Kersch, W. Weinreich, and P.Lugli, , IEEE Trans. Electron Devices 58, 327-334 (2011)

Fig. 2. Comparison of j-E curves of 7nm film stacks with

5s O3 pulse time and various anneals.

Effect of Fin Doping and Orientation on Negative Bias Temperature Instability C. D. Young, J. Pater, K. Akarvardar†, K. Matthews, M. Minakais, S. Deora, G. Bersuker, D. Veksler, I. Ok, K.-W. Ang, M. Rogers*, S. Gausepohl*, C. Hobbs, P. Kirsch, and R. Jammy SEMATECH, Albany, NY; †GLOBALFOUNDRIES, Albany, NY; *CNSE, Albany, NY chadwin.young@SEMATECH.org The fin-shaped, multi-gate field effect transistors (MugFETs) are a leading candidate for the 22 nm node of the ITRS roadmap and beyond. One MugFET type of particular interest is the FinFET where the top gate is decoupled from device operation due to the presence of a hardmask on top of the fin. The sidewall channel orientation of these devices – typically (110)<110> or (110)<110> – can impact performance [1-3].

Also, in order to modulate the threshold voltage (Vt) for multiVt circuit applications, incorporating dopant in the typically lowly doped (~1015/cm3) fin provides a simpler approach to Vt modulation [3] compared to a high-k/metal gate (HK/MG) combination that induces a desired dipole to shift the Vt. Previous work on the orientation dependence of NBTI has been done before [4], but compared MugFETs using only stress voltage and did not consider stress overdrive (Vg-Vt) or stress field (different tinv). We invoke a systematic study that includes stress overdrive and field to evaluate the orientation and fin doping dependence of NBTI on FinFETs with HK/MG along with a comparison to similar (110) and (100) planar devices.

Experiment Silicon-on-insultor (SOI) FinFETs were processed with channels formed on (100) and (110) planes. Hafnium-based high-k (~2nm) with SiO2-like interfacial layer (~1nm) and midgap metal gate (~10nm) with a poly cap formed the gate stack.

The process flow included an n-type fin body doping (~1x1018/cm3) as one condition for use as the doped pMOS devices while the typical background concentration for the ‘undoped’ fin body is actually ~1015/cm3. The gate first, bulk-Si planar MOSFETs used for comparison had a similar Hafniumbased high-k and TiN metal gate (HK/MG) stack, with channels formed on (100) and (110) surfaces. NBTI stress was done at 125°C with various stress bias conditions where Id-Vg sense measurements were collected to monitor the threshold voltage shift (Vt) and subthreshold slope (SS) change on FinFETs and planar transistors with Lg = 1 m.

Results and Discussion Figure 1 shows the orientation dependence on NBTI for various overdrive conditions of the a) ‘undoped’ and b) doped o

120

160

Vg-Vt = 1.7

4

'Undoped'

80

Doped

120

Vt [mV]

Vt [mV]

(110)<110>

100

60

80 60

40

40

20 0

0

10

a)

20

Closed: (110) <110> Open: (100) <100> 1

10

2

10

3

10

Stress Time [sec]

4

10

0

Closed: (110) <110> Open: (100) <100> 0

10

1

10

2

10

3

10

Stress Time [sec]

b)

Fig.1. Time evolution of Vt shift for several stress conditions for a) undoped and b) doped pMOS FinFETs.

a)

'Undoped' fin body Doped fin body Planar pMOSFET

'Undoped' FinFET

35

~4.5 %

0.20

30 Threshold Voltage Subtreshold Slope

25 20 15

E=

Vg - Vt tinv

0.15

0.10

~4.5 %

10

0.05

5 0

4

10

(100)<100> 0.25

40

140

100

[1] M. Yang, et al., IEEE TED, 53, p. 965, 2006.

[2] C.D. Young, et al., VLSI, p. 18, 2011.

[3] K. Akarvardar, et al., IEEE EDL, 33, p. 351, 2012.

[4] S. Maeda, et al., IRPS, p. 8, 2004.

o

Vg-Vt = 1.5

Vg-Vt = 1.7

References

125 C

Vg-Vt = 1.3

180

Vg-Vt = 1.5

NBTI measurements were conducted on undoped and doped HK/MG FinFETs. Results demonstrate that (110) channel surfaces experience larger levels of degradation compared to (100) with FinFETs exhibiting lower overall degradation compared to planar at similar stress fields.

4

125 C

Vg-Vt = 1.3

Summary

Percent Degradation @ 10 sec [%]

140

FinFETs. Results demonstrate that the (110) orientation is slightly worse than (100) for both cases. This orientation dependence is plausible because it is expected that there are more Si interface bonds available for bond breakage in the (110) plane as compared to (100) [4]. This same orientation dependence was seen in the planar devices as well. There are no significant process dependencies between FinFET samples [i.e., TEM, tinv, initial subthreshold slope (SS)]. Since there appears to be no process dependence involved the differences seen between undoped and doped finFETs, further in-depth analysis can commence. In HK/MG devices, Vt shift is caused by a convolution of charge buildup (trapped charge and/or trap generation) and interface state generation. This is illustrated in Fig. 2a where the percent change in SS degradation (a sign of interface state generation) cannot account for all of the Vt shift, but does seem to explain the difference seen between the two orientations (i.e., ~4.5%). Because the devices have different Vt values due to the fin doping along with different tinv for planar, careful consideration for comparing the degradation in a more quantitative way is required rather than comparing at a fixed stress bias [4]. Therefore, using the electric field (Fig. 2b) allows the data to be normalized for a robust comparison between orientation and doping content. Fig. 2b shows the overall dependence of the sidewall orientation and doping levels in conjunction with planar transistors on both orientations. The results demonstrate that FinFETs have less NBTI degradation compared to planar, contrary to [4] done on SiON.

Vt @ 10 sec [V]

Introduction

1.3V

1.5V

1.7V

1.3V

1.5V

Vg - Vt Condition

1.7V

0.00

Closed: (110) <110> Open: (100) <100>

4

6

8

10

12

Electric Field [MV/cm]

b)

Fig.2. a) Percent degradation at 104 sec for Vt and SS demonstrating that SS does not account for all the Vt shift. b) Comparison of pMOS FinFETs and planar transistors with different orientations.

Materials Engineering of Ge Interfaces with Insulators and Metals Akira Toriumi1,2 1 – The University of Tokyo, Tokyo, Japan 2 – JST-CREST, Tokyo, Japan corresponding author e-mail: toriumi@material.t.u-tokyo.ac.jp Recent Advancements in Ge/GeO2 Gate Stacks Ge FET performance has been improved dramatically in recent years, particularly in n-MOSFETs, and Ge CMOS will be a realistic candidate for the nextgeneration CMOS. Thus, the objective of this paper is to share the current understanding of Ge potential (materials, processes and devices), and to discuss opportunities and challenges of Ge CMOS. Ge oxidation is quite different from Si one thermodynamically. Since pGeO (p: partial pressure) at 1atm O2 is quite high, GeO desorption should always be considered in the Ge front-end process. We clarified that the O atom diffusion should occur from the top surface to interface (Vo, oxygen vacancy, diffusion from the interface to the top) in the GeO desorption process (1).

From engineering point of view, it was expected that the “high-pressure O2 oxidation” (HPO) should be quite effective for suppressing the GeO desorption (2).

HPO made C-V characteristics significantly better in GeO2/Ge MISCAP, and HPO followed by the “low temperature O2 annealing” (LOA) further improved C-V, as shown in Fig. 1 (3). In addition, we found that a small amount of rare-earth (RE) metal introduction into GeO2 interface layer by oxidizing the deposited Y2O3 in HPO decreased Dit at GeO2/Ge interface (4).

The inversion layer mobility (μeff) is the key parameter for describing the intrinsic device potential. Significant and rapid progress of electron μeff in Ge n-FETs suggests that Ge has highly promising material potential toward Ge CMOS (5). The highest electron and hole peak μeff values so far obtained are 1,920 and 720 cm2/Vsec (6). It is reasonable that (111) Ge shows the highest electron mobility in terms of the effective mass consideration.

New Ge FETs Although no systematic study of short channel Ge MOSFETs has so far been reported, DIBL and GIDL will be intrinsic drawbacks to its miniaturization of Ge FETs due to the narrower band gap and higher dielectric constant of Ge than those of Si. To overcome those challenges, we investigated extremely thin (ET) GeOI MOSFETs and demonstrated good operation of both nand p-MOSFETs fabricated on 9 nm-thick GeOI (7).

The junction-less (JL) FET concept was proposed and its good operation of Si JL-FETs was demonstrated by J. P. Colinge et al.(8). We noticed that the majority carrier mobility in Ge was much higher than that in Si (9), and studied Ge JL-FETs, in which we found the relatively flat μeff-Ns characteristics (10).

It is known that Schottky barrier heights (SBHs) on Ge for any metals are strongly pinned near the valence band edge of Ge (11). Thin insulators were inserted between Ge and metal to weaken the pinning, resulting that clear

transitions from ohmic to Schottky in p-Ge and from Schottky to ohmic in n-Ge were observed (12). This fact suggests us to realize the metal source/drain MOSFET operation without any impurity doping in the source/drain region (12). In fact, pure metal source/drain Ge FET operation was demonstrated.

Summary and Future Outlook Ge technology is obviously not new, but its recent progress is in marked contrast to the past research. Ge CMOS is quite promising not only from the high mobility but also from possibly smaller CMOS area than the case of “III-V for n-MOS and Ge for p-MOS”. Furthermore, versatile device opportunities and applications such as ET-GeOI FETs, metal source/drain FETs or junction-less FETs have been already demonstrated. Moreover, new Ge opportunities such as the low thermal budget process for 3D-LSIs will open a new world of Si-based ULSIs.

References (1) (2) (3) (4) (5) (6) (7) (8) (9)

S.K. Wang et al., JAP 108(2010) 054104.

C. H. Lee et al., APEX 2 (2009) 071404.

C. H. Lee et al., T-ED 58 (2011) 1295.

T. Nishimura et al., APEX 4 (2011) 064201.

A. Toriumi et al., IEDM 2011.

C. H. Lee et al., IEDM 2010.

C. H. Lee et al., SOI Conf. 2011.

J. P. Colinge et al., Nature Nanotech. 5 (2010) 225.

S. M. Sze: Physics of Semiconductor Devices, 2nd ed., (1981).

(10) D.D. Zhao et al., JJAP, 51 (2012) 04DA03.

(11) T. Nishimura et al., APL 91 (2007) 123123.

(12) T. Nishimura et al., APEX 1 (2008) 051406.

Fig. 1. Dit spectra for HPO- and (HPO+LOA)grown GeO2 on Ge. They show the simple U-shape curves. LOA has a significant effect for Dit reduction. Dit was estimated by the low temperature conductance method.

Gate stack options for future CMOS logic Martin M. Frank IBM T.J. Watson Research Center, 1101 Kitchawan Road, Yorktown Heights, NY 10598, USA mmfrank@us.ibm.com High-k dielectrics and metal gate electrodes have entered complementary metal-oxide-semiconductor (CMOS) logic technology, integrated in gate-first and gate-last schemes. We review gate-first high-k / metal gate (HKMG) options for continued scaling at the 22 and 14 nm nodes and beyond. First, we summarize some of the insight that allowed early HKMG challenges such as equivalent oxide thickness (EOT) and threshold voltage (Vt) control to be overcome. Then, we discuss (i) EOT scaling via oxygen scavenging, demonstrating the viability and limitations of this approach for SiGe channel (cSiGe) p-channel MOSFETs (pFETs), and (ii) pitch scaling, enabled by full metal gate electrodes that support the formation of borderless (â&#x20AC;&#x2DC;self-alignedâ&#x20AC;&#x2122;) source/drain (S/D) contacts. We will also provide an outlook on nonplanar devices and high-mobility channels. (i) Aggressive SiGe channel pFET scaling via oxygen scavenging: Biaxially strained cSiGe on Si for pFETs has recently received much attention for its ability to reduce the Vt of Hf-based HKMG transistors [1-3]. We show for the first time that aggressive gate dielectric scaling in cSiGe pFETs can be achieved via remote interfacial SiO2 layer (IL) scavenging by metal-doped TiN gates (Fig. 1a), analogous to cSi nFETs [4,5], rendering remote IL scavenging an attractive option for dual-channel CMOS. We reach an inversion thickness (Tinv) of 0.86 nm (EOT ~ 0.45-0.5 nm), with some Vt and hole mobility tradeoffs (Fig. 1b). Increased charge trapping under negative bias temperature instability (NBTI) stress (Fig. 1c) necessitates careful materials and process optimization. (ii) Full metal gate electrodes for pitch/density scaling: Gate-first HKMG technologies in production

employ metal-inserted poly-Si stacks (MIPS), in which poly-Si serves as an oxygen barrier preventing high-k/Si IL regrowth during RTA and as a precursor for low-sheetresistance (Rs) silicides on the gates. An encapsulated full metal gate (FMG) would enable borderless S/D contacts and thus aggressive pitch scaling (Fig. 2a). However, FMG that match or exceed MIPS in terms of gate stack parametrics and Rs along the gate lines have been elusive.

The main challenge is O down-diffusion through the metal [6,7]. An O barrier for FMG is thus needed.

Motivated by MIPS work on TiN and TaN alloyed or doped with O-scavenging metals ([4,5,8] and section i), we have evaluated W/TaMN/TiN FMG with an Oscavenging metal M as O barrier (Fig. 2a). We show that the TaMN resolves the challenge of IL regrowth, reduces W Rs over W/TiN, permits EOT scaling to ~0.5 nm by IL scavenging, and delivers equivalent nFET and superior pFET properties (reduced Vt and enhanced mobility at lower EOT) vs. MIPS (Fig. 2b-d). Fully encapsulated, this FMG enables borderless contacts to be formed [9].

Fig.1. (a) TEM images of Si-capped cSiGe pFETs with Al2O3 cap. Dependence of cSiGe pFET (b) hole mobility and (c) C-V hysteresis under NBTI stress on Tinv.

Fig.2. (a) Schematic illustration of FMG with borderless source/drain (S/D) contacts; (b) pFET inversion split C-V for FMG and MIPS; (c) nFET electron and (d) pFET hole mobility at high effective field (1 MV/cm) vs. EOT for FMG and MIPS.

References [1] [2] [3] [4] [5] [6] [7] [8] [9]

Krishnan, S., et al.: IEDM Tech. Dig. (2011), p. 634.

Franco, J., et al.: IEDM Tech. Dig. (2010), p. 70.

Witters, L., et al.: VLSI Tech. Dig. (2010), p. 181.

Ando, T., et al.: IEDM Tech. Dig. (2009), p. 423.

Ando, T., et al.: Appl. Phys. Lett. 96 (2010) 132904.

Akasaka, Y., et al.: VLSI Tech. Dig. (2006), p.164.

Narayanan, V., et al.: IEEE El. Device Lett. 27 (2006) 591.

Choi, K., et al.: VLSI Tech. Dig. (2009), p. 138.

Seo, S.-C., et al.: VLSI Tech. Dig. (2011), p. 36.

This work was performed by the Research Alliance teams at various IBM Research and Development facilities.

WoDiM 2012 17th Workshop on Dielectrics in Microelectronics June 25 - 27, 2012 in Dresden, Germany

-Abstracts-

(poster presentations)

Analysis of pore sealing processes and TiN diffusion barrier deposition on a porous ultra low-k dielectric by ellipsometric porosimetry and PALS N. Ahner1, R. Ecke2, M. Jungmann3, R. Krause-Rehberg3, A. Preusse4, S.E. Schulz2 1 – Center for Micortechnologies, Chemnitz University of Technology, Reichenhainer Str. 70, 09126 Chemnitz 2 – Fraunhofer ENAS Chemnitz, Technologie-Campus 3, 09126 Chemnitz 3 – Department of Physics, Universtiy Halle, Von-Danckelmann-Platz 3, 06120 Halle 4 – GLOBALFOUNDRIES Dresden Module One LLC & Co. KG, Wilschdorfer Landstraße 101, 01109 Dresden corresponding author e-mail: nicole.ahner@enas.fraunhofer.de As feature dimensions of integrated circuits continue to shrink, the signal delay of the interconnect system described by the RC-product increases, e.g. due to parasitic capacitances. One approach to overcome those issues is the integration of porous ultra low-k dielectrics for isolation [1, 2]. The porous structure of those materials leads to many integration challenges; one of them is the deposition of the diffusion barrier after patterning. Porosity may provide diffusion paths for metal species or metal-organic CVD precursor molecules deep into the material bulk, which leads to the degradation of the dielectric [3, 4].

In this study we investigate several plasma pore sealing processes applied to a porous CVD SiCOH-dielectric to achieve a densification and therefore sealing of top layer of the material to inhibit contaminant diffusion [5]. By ellipsometric porosimetry the effectiveness of the pore sealing is analyzed. Additionally we investigate the effects of pore sealing and CVD TiN-barrier deposition on the porous structure of the dielectric by Positronium Annihilation Spectroscopy (PALS) using the radiation source ELBE at the Forschungszentrum Rossendorf. This method is able to give information about pore sizes and porosity even after the material’s surface has been sealed or a diffusion barrier layer has been deposited. By

analyzing the Doppler widening of the annihilation spectra, changes of the chemical structure of the dielectric can be found.

Ellipsometric porosimetry showed that the application of a nitrogen plasma was able to seal the porous dielectric’s surface (Fig. 1). The same was found for the deposition of a 10nm thin CVD TiN layer. PALS analysis was able to give information about the decrease in porosity of the surface near region of the dielectric. The Doppler analysis additionally showed that the chemical structure of the dielectric is modified by both processes deep down into the bulk of the material (Fig. 2). This could give rise to the assumption that metallic species were able to penetrate into the material much deeper than presumed. It was shown that PALS and the analysis of the Doppler widening of the annihilation spectra are very sensitive methods to investigate porous ultra low-k materials and can be successfully applied as a supplement to ellipsometric porosimetry.

Acknowledgement: The project described in this publication has been funded in line with the technology funding for regional development (ERDF) of the European Union and by funds of the Free State of Saxony. All graphics generated by Fraunhofer ENAS.

References [1] [2] [3] [4] [5]

Fig.1. Ellipsometric porosimetry results of the porous dielectric after a plasma pore sealing process (N2, 300W plasma power)

K. Maex, M.R. Baklanov, J. Appl. Phys. 93, (2003) 8793 A. Grill, V. Patel, J. Appl. Phys. 94 (2003), 3427 L. Zhao, M. Baklanov, ECS Trans. 33 (2010), 117 T.L. Tan, C.L. Gan, J. Appl. Phys. 106 (2009), 043517 W. Puyrenier, V. Rouessac, Microporous and Mesoporous Materials 106 (2007), 40

Charge Trapping Analysis of Al2O3 Films Deposited by Atomic Layer Deposition Using H2O or O3 as Oxidant M.B. Gonzalez*, J.M. Rafí, O. Beldarrain, M. Zabala and F. Campabadal Institut de Microelectrònica de Barcelona (IMB-CNM, CSIC) Campus UAB, 08193 Bellaterra, Spain *corresponding author e-mail: mireia.bargallo.gonzalez@csic.es The on-going research to meet the CMOS roadmap requirements has created the necessity of developing new materials and alternative device structures. Gate stacks dielectrics with high permittivity (high-k) allow reducing the gate leakage which is an essential factor to further continue the gate dielectric downscaling. Among other dielectric deposition techniques, atomic layer deposition (ALD) is a powerful method capable of producing highquality films with the desired thickness control [1].

In this work, we focus on the charge trapping behavior of Al2O3 layers deposited by ALD. The goal is to give insight into the effects of the oxidant source and the postdeposition anneal (PDA) on the charging phenomena and the generation of new defects during electrical stress. For this purpose, current-voltage (I-V) and capacitancevoltage (C-V) characteristics of Al/10nm Al2O3/p-Si capacitors are analyzed before and after constant voltage stress (CVS), and several parameters such as interface state density, fixed oxide charge and effective trap centroid are investigated. The studied Al2O3 films were deposited by ALD using Trimethylaluminium (TMA) and either H2O or O3 as oxidant precursor and were processed with and without a PDA. The capacitors also received a post-metallization anneal (PMA). Ultra High ResolutionTransmission Electron Microscopy (UHR-TEM) indicates that there is no evidence of an interfacial layer.

Figure 1 shows the time dependent current density of O3 based Al2O3 capacitors under gate injection during 500s CVS. It is observed that for stressing voltages (Vstress) lower than 7.5V, the current decreases with stress time.

This decrease can be attributed to an anti-field contribution produced by the trapped electrons [2].

However, for higher Vstress, a progressive increase of the current density with increasing the stress time is detected (Fig.1.b). This fact can be explained by SILC (stress induced leakage current) due to defect generation [3]. At Vstress higher than 7.9V the dielectric breakdown arises.

compared to fresh capacitors (Fig.2.a) [4]. Furthermore, the contribution of SILC is evidenced at higher Vstress.

(a) (b) Fig.2. Gate current density vs. voltage of non-PDA O3 based capacitors (a) and its comparison with non-PDA H2O based samples (b) before and after 500s CVS.

In Fig.2.b, it is shown that there is less electron trapping for the non-PDA H2O based layers, compared to their ozone counterparts. Therefore, Al2O3 layers fabricated with O3 as an oxidant source and/or with PDA treatment are more capable to store negative charges, even before stress (Fig.3). This capability reduces the injected charge during CVS (Fig.2.b) and as a result increases the stressing voltage needed to breakdown.

Fig.3. Maximum voltage @ 500s CVS where the dielectric breakdown has not been observed (circles-left) and fixed negative charge density in fresh capacitors extracted from C-V characteristics (squares-right).

During the conference, a detailed analysis of the I-V and C-V characteristics after CVS will be given, where the generation of oxide traps, interface states and the presence of positive effective charges close to the Al2O3/Si will be discussed.

Acknowledgements This work has been partially funded by the Spanish Ministry of Science and Innovation through project TEC2008-06698-C02-01 and by the Consejo Superior de Investigaciones Científicas (CSIC) under Contract “Junta para la Ampliación de Estudios”, JAE-Doc. (a)

(b)

Fig.1.Transient of current density (a) and current density increase (b) during CVS of non-PDA O3 based capacitors.

The electron trapping in the Al2O3 near the metal gate is detected by means of the current density vs. gate voltage, which shifts toward a more negative gate voltage

References [1] [2] [3] [4]

Rafí, J.M, et al.: J. Electrochem. Soc. 158 (2011) G108.

Chang, C-H, et al.: J. Appl. Phys. 105 (2009) 094103.

Nigam, T, et al.: Proc. IRPS. (1999) 381.

Kerber, et al.: J. Appl. Phys. 94 (2003) 6627.

Characterization of HfO2/La2O3 layered stacking deposited on Si substrate Duo Cao1, Xinhong Cheng1, Tingting Jia1, Youwei Zhang1, Dawei Xu2, Zhongjian Wang1, Chao Xia1, Yuehui Yu1 1 - State Key Laboratory of Functional Materials for Informatics , Shanghai Institute of Micro-system & Information Technology, Chinese Academy of Sciences, Changning Road 865, Shanghai 200050, People’s Republic of China 2 - Forschungszentrum Jülich GmbH, Jülich 52425, Germany corresponding author e-mail: xh_cheng@mail.sim.ac.cn High dielectric constant (High-k) materials would be a commendable candidate to reduce leakage current intensities without an increase of equivalent oxide thickness (EOT). So far, hot topics of the silicon-based high-k material in the international research were focus on the three: rare earth-based oxide, Hf-based oxides and binary alloy gate dielectric stacking structure [1]. HfO2 and La2O3 were consummate high-k dielectrics, due to their relative high dielectric constant, a wide energy gap with good thermal stability. In addition, the stacking structure of the binary alloy gate dielectric had good properties among the so many researches. Therefore, in this work, two-layer and four-layer HfO2/La2O3 layered stacking were prepared by plasma enhanced atomic layer deposition (PEALD) at a lower growth temperature with in situ plasma treatment which could decrease the dielectric interfacial defects.

The two-layer and four-layer HfO2/La2O3 layered stacking were both grown on Si substrate. They were deposited by PEALD at 200℃ with in situ pre-O2, preNH3 and post-O2 plasma treatment. For S1 both 20 cycles La2O3 and HfO2 were grown; for S2 10cycles La2O3 an HfO2 were grown; then repeated once to form a four-layer structure. Immediately after the ALD process, both films were treated with rapid thermal annealing (RTA) process at 500℃ in the nitrogen atmosphere.

High resolution transmission electron microscopy (HRTEM) shown in Fig.1 indicated both films were no crystallized. No obvious interface in both samples, and the thickness for S1 and S2 was about 7.3nm and 7.2nm respectively. Atomic Force Microscope (AFM) suggested the roughness of the films were 0.1nm. X-ray

photoelectron spectra (XPS) indicated that the main component of the interfacial layer consisted of Hf-Si-O and La-Si-O bonds. It had a relatively high permittivity, good thermal stability and a lower interface state with Si substrate. The electrical measurements indicated that the leakage current densities of the two-layer and four-layer were 0.02mA/cm2 and 0.01mA/cm2 at gate bias with the condition |Vg-Vfb|=1V, and the equivalent oxide thicknesses with a frequency of 500KHz calculated to be 1.2nm and 1.5nm respectively. To calculate the densities of interfacial state, C–V and G–V measurements were employed as simple methods [2, 3]. Interface state densities of the two could be extracted to be 1.71×1012eV1 cm-2 and 1.32×1012eV-1cm-2. Easy to find the four-layer sample had good performance, this was due to the Hf and La atoms’ interdiffusion which could reduce the interfacial defects.

In conclusion, binary alloy gate HfO2/La2O3 layered stacking was successfully deposited by PEALD with in situ plasma treatment. It had a small leakage currents and low interface state density. In order to improve the electrical performance, the atom ratio of Hf to La should be further optimized.

References [1] YANG Y F,QI X,AN J,et al.[Z] .IEEE Tran on E D,2003,50(2) :433 [2] M.J.Uren, J.H.Stathis, and E.Cartier, J.Appl.Phys. 80, 3915(1996).

[3] R.J.Carter, E.Cartier, A. Kerber, L. Pantisano, Appl.Phys.Lett. Vol. 83, 2003

3500

C(nF/cm2)

3000 2500 2000

-3

-2

1500

4000 -1

1

2

3

500k

3000

cm2)

-500

-3

f=500kHz

EOT=1.2nm

1000

0

Dit=1.71*1012eV-1cm-2

1.5x1012

1.0x1012 0

Gate voltage(V)

3500

500

Fig.1. High-resolution TEM image of HfLaO on Si

100k

I= 0.02 mA/cm2

100k

5.0x1011

1000k

Dit(state/(eVcm2))

Leakage current(mA/cm2)

4000

0.0

2500 -2

-1

0

1

2000 Gate voltage(V)

2

3

0

Gate voltage(V)

Fig.2. Electrical characteristics of capacitance, leakage current and interface state densities of HfLaO.

Investigation of structural and electrical properties of atomic layer deposited terbium scandate E. Cianci* , A. Lamperti, G. Congedo and S. Spiga Laboratorio MDM, IMM-CNR, via C. Olivetti 2, 20864 Agrate Brianza (MB) - Italy *Corresponding author e-mail: elena.cianci@mdm.imm.cnr.it

A promising class of materials satisfying requirements for continuous miniaturization of both high-performance Complimentary Metal-Oxide-Semiconductor (CMOS) logic and mass storage memory devices are rare earth (RE) scandates. The incorporation of scandium in RE oxides increases the k value respect to that of the respective binary oxides, without reduction of band gap and band offsets, which remain similar to those of scandium oxide.

Furthermore, RE scandates can fulfill process requirements, including thermal stability inside the gate stack and compatibility with other materials used in the CMOS process and with the process itself. Besides the most studied LaScO3, GdScO3 and DyScO3 [1,2], recent reports on thin films of TbScO3, deposited by evaporation [4,5], show that films stay amorphous even upon high temperature annealing and possess high dielectric constant and low leakage current.

In this work terbium scandate thin films have been deposited by atomic layer deposition (ALD) on SiO2/Si and Si3N4/SiO2/Si stacks and their structural and electrical behavior as a function of annealing temperature has been investigated. Films are grown using β-diketonate-based precursors and ozone at 300°C. The composition of the ternary TbScOx oxide is tuned combining the processes developed for the two binary oxides Tb2O3 and Sc2O3 and varying the number of the optimized pulses of Tb(thd)3/O3 and Sc(thd)3/O3 in the ALD cycle. A metal precursor pulsing ratio of 1:1 allows to obtain a metal ratio Tb:Sc = 1.13, as estimated by Total X-ray Fluorescence.

The film crystallization in the cubic phase is induced

Fig.1 . GIXRD of 17-nm thick TbScOx film on 4.5nm-SiO2/Si as a function of annealing temperature

as film thickness increases and enhanced by thermal annealing (Fig. 1). The thermal stability of ALD TbScOx films and of their interfaces with SiO2 and Si3N4, investigated by time-of-flight secondary ion mass spectrometry depth profiles, is preserved after thermal treatment at 600°C, and their electrical characterization shows well-shaped capacitance-voltage curves, from which a k value of 16-18 is extracted. Annealing at 900°C largely affects the TbScOx/SiO2 interface (Fig. 2a), causing the formation of an intermixed layer and silicon diffusion in the film resulting in a reduction of its k value down to 12. On the contrary TbScOx/Si3N4 stack results stable upon 900°C thermal treatment (Fig. 2b), indicating the feasibility for terbium scandate integration as high k dielectric in charge trap memory devices.

Partial financial support from research project EU-FP7 GOSSAMER contract n. 21443 is acknowledged.

References [1] P. Myllymäki, M. Roeckerath, J. M. Lopes, J. Schubert, K. Mizohata, M. Putkonen, and L. Niinistö, J. Mater. Chem. 20, 4207 (2010).

[2] A. Lamperti, E. Cianci, U. Russo, S. Spiga, O. Salicio, and G. Congedo, and M. Fanciulli, J. Vac. Sci. Technol. B 29, 01AE03-1 (2011).

[3] I. Geppert, M. Eizenberg, N. A. Bojarczuk, L. F. Edge, M. Copel and S. Guha, J. Appl. Phys. 108, 024105 (2010).

[4] M. Roeckerath, J.M.J. Lopes, E. Durgun Özben, C. Sandow, S. Lenk, T. Heeg, J. Schubert, S. Mantl, Appl. Phys. A 94, 521 (2009).

Fig.2. ToF-SIMS depth profiles of 17-nm TbScOx/4.5-nm SiO2/Si stack (a) and 17-nm TbScOx/6-nm Si3N4/4.5-nm SiO2/Si stack (b), as deposited (full line) and 900°C-annealed (dot line).

Spin Dependent Tunnelling in SiC:H for Interlayer Dielectrics C.J. Cochrane1, T. Pomorski1, P.M. Lenahan1, S. King2 1 – Pennsylvania State University, University Park, PA 16802 2 – Intel Corporation, Hillsboro, OR 97125 corresponding author e-mail: cjc203@psu.edu For multiple reasons, SiC dielectrics show great promise for interlayer dielectrics. They show potential for use as etch stop layers and Cu diffusion barriers. They may also exhibit quite low dielectric constants. In our study, we investigate SiC based films with dielectric constant as low as 2.8.

We utilize an electrically detected magnetic resonance (EDMR) method known as spin dependent tunnelling (SDT) to observe trap assisted tunnelling through SiC:H capacitors.[1] SDT makes it possible to directly detect defects involved in the trap assisted tunneling which cause dielectric leakage current and are likely related to important reliability problems such as time dependent dielectric breakdown. SDT takes place in these films because the tunneling process involves defects with unpaired electrons. Tunneling transport between such defects is spin dependent, thus allowing magnetic resonance at the defects to influence the currents. The spin dependent current of a capacitor can be detected by appropriately biasing a device and applying constant microwave radiation. A large external magnetic field is swept while simultaneously monitoring the current to search for resonance. Resonance is achieved when the energy of the microwave photons equals that of the energy difference in the spin states of the electrons at the defect site. As a result, we can detect the defects involved in trap assisted tunneling via magnetic resonance detected through the leakage current.

The devices used in this study were provided by Intel: 50Å amorphous SiC:H dielectric films on silicon substrates with titanium caps. The SDT measurements were made on a custom built EDMR X-band spectrometer

at room temperature.

Figure 1 illustrates a representative SDT spectrum with 1 V applied to the titanium gate and the substrate grounded. We see dominating center line located at g ≈ 2.0032 with a width of 15G. The g is defined by g=hυ/βH, where h is Planck’s constant, υ is the microwave frequency, β is the Bohr magneton, and H is the magnetic field at resonance.[2] The g depends upon the orientation of the defect in the magnetic field. The breadth of the line is consistent with that expected from a defect in an amorphous material because the full range of g values are expressed in the line width.[2] The breadth suggests that the spectrum is more likely associated with silicon dangling bonds than carbon dangling bonds as the range of g values depends on spin orbit coupling, larger for the silicon case than the carbon case.

Figure 2 illustrates both the leakage and the SDT amplitude as a function of bias for a representative sample. Note the close similarity between the two plots.

No signal could be detected at all voltages below 0.7V, including voltages between 0 and -1.5V. A comparison of the EDMR amplitude versus bias and Si/SiC/Ti band diagrams [3] versus bias clearly demonstrates that the observed defects levels are located at the upper edge of the SiC bandgap.

Fig.1. This is an EDMR trace acquired via SDT on a SiC:H high dielectric 50Å capacitor with a bias of 2MV/cm. We see a center line of g = 2.0032 with a width of 15G in width.

Fig.2. A comparison of the leakage current versus applied bias versus the EDMR amplitude as a function of applied bias.

References [1] J.T Ryan et al, J. App.l Phys. Lett., 95, 103503 (2009).

[2] J.A. Weil et al., Electron Paramagnetic Resonance, (1994).

[3] R.G. Southwick et al., IEEE TDMR, 6, 136, (2006).

Linear dichroism and electrochemical properties of TiO2 grown by atomic layer deposition on Si. Chittaranjan Das1, Massimo Tallarida1, Katarzyna Skorupska2,3, Hans-Joachim Lewerenz2,4, and Dieter Schmeisser1 1 – Applied Physics-Sensors, Brandenburg University of Technology, Konrad-Wacshmann-Allee, 17, 03046 Cottbus, Germany 2 – Insitute for solar fuels and energy storage materials, Helmholtz Zentrum Berlin, Hahn-Meitner Platz 1, 14109 Berlin, Germany 3 – Max-Planck-Institute of Colloids and Interfaces, Wissenschaftspark Potsdam-Golm, Am Mühlenberg 1 OT Golm, Germany 4 – Joint Center for Artificial Photosynthesis, California Institute of Technology, Pasadena, CA, 91125, USA corresponding author e-mail: Chittaranjan Das, chittaiit@yahoo.com TiO2 is universally known as a multifunctional material with a high dielectric constant, and unique photocatalytic properties. Its use for energy harvesting with (dyesensitized)-photovoltaic cells as well as for electrochemical water splitting has been extensively documented [1]. Recently, ALD films have been considered for physical stabilization of photoelectrodes that can be used in water splitting applications or for photovoltaics at the semiconductor-liquid junction [2].

Here we describe the atomic layer deposition of TiO2 on Si(111) and Si(100) with Titanium-tetra-iso-propoxide (TTIP) and water as precursors. The growth of thin layers was performed on, both, etched and oxidized surfaces at 250°C. In-situ characterization of TiO2 ALD growth was made using synchrotron radiation photoelectron spectroscopy (SRPES) and absorption spectroscopy, performed at the beamline U49-2/PGM 2 at BESSY-II, Helmholtz Zentrum Berlin (HZB), Germany [3].

The photoemission spectra show a constant growth mode after an initial nucleation delay of about 30 cycles. Ti 2p spectra reveal the presence of, both, Ti3+ and Ti4+ species for very thin films (Figure 1). Soft XPS valence band spectra show a continuous change of the electronic properties during TiO2 ALD, which is attributed to a

Ti2p @ 640eV

varying O 2p-Ti 3d hybridization. X-ray absorption spectroscopy at both Ti L2,3 and O K edges showed similar changes (Figure 2). The line-shape of the thicker film closely resembles that of bulk-like anatase TiO2, while for thinner films peaks positions and intensity ratios continuously change (Figure 2). The use of synchrotron radiation with linear polarization allowed the detection of a linear dichroism of TiO2 films with varying thickness.

Selected samples with TiO2 thicknesses ranging between 1 and 5nm were electrochemically characterized using cyclic voltammetry under illumination and in dark that show stabilization effects but also a positive influence of titania on the photoresponse of the system.

References [1] K. Hashimoto, H. Irie, A. Fujishima, Japanese Journal of Applied Physics 1 44 (2005) 8269–8285.

[2] Q. Peng, J.S. Lewis, P.G. Hoertz, J.T. Glass, G.N. Parsons, Journal of Vacuum Science and Technology A 30 (2012) 010803.

[3] D. Schmeisser, P. Hoffmann, G. Beuckert, Materials for Information Technology, Devices, Interconnects and Packaging, Engineering, Springer, New York, 2005.

XAS Ti L2,3

4+

Ti

3+

Ti

468

466

464 462 460 458 Binding energy (eV)

456

Fig.1:. Ti2p photoemission spectra of TiO2/Si after 10, 20, 30, 60, 130 ALD cycles

450

455

460 465 Photon energy (eV)

470

475

Fig.2: XAS spectra at the TiL2,3 edge of TiO2/Si after 10, 20, 30, 60, 130 ALD cycles

Electron trapping by Ge defects in bulk silica Al-Moatasem El-Sayed, Matthew Watkins and Alexander Shluger Department of Physics and Astronomy and London centre for Nanotechnology, University College London, Gower Street, London WC1E 6BT, UK corresponding author e-mail: al-moatasem.el-sayed.10@ucl.ac.uk The use of SiGe alloy materials in advanced electronic devices has allowed the discovery of new devices and the improved performance of existing silicon devices. The structure of a SiGe device is formed by implantation of germanium into silicon followed by oxidation. The native oxide formed is mainly SiO2 due to the highly negative free energy of formation of SiO2 which rejects the germanium forming a sharp germanium rich layer at the interface[1]. Nevertheless, several studies have investigated the concentration of Ge in the native oxide under various processing conditions [2,3,4]. It is found that Ge persists in the oxide, and that the Ge present in the oxide exists as GeO2 and not as elemental Ge clusters, which was originally thought to exist due to the processing conditions [5]. The existence of Ge in the oxide has mainly been discussed in the context of processing techniques.

In this contribution the microscopic structure and electronic structure of the GeO2 unit in silica have been studied at the density functional theory level under periodic boundary conditions. For a more accurate description of the electron density, the HSE hybrid functional was used as implemented in the CP2K code.

The electron trapping properties of the germanium impurity have been studied in both alpha quartz and amorphous silica in cells of various sizes containing up to 648 atoms. The neutral Ge impurity induces a local distortion of the structure, inducing the longer Ge-O bonds (1.72Å) with respect to the Si-O bonds (1.61Å).

The neutral Ge impurity introduces an unoccupied state below the conduction band minimum into which an electron was placed and the atomic coordinates were

optimised revealing a strong localisation of the electron on Ge (see Fig. 1). This localisation causes two of the neighbouring oxygen atoms to relax away from the Ge atom, extending the Ge-O bonds to 1.90 Å and opening the O-Ge-O angle from 109° to 150.1°. The calculated spin density, plotted in Figure 1, demonstrates the strong localisation of the electron on the Ge atom. The occupied electronic state associated with the Ge impurity relaxes to 4.2 eV below the conduction band, acting as a deep electron trap. These results generally agree with the previous results by Pacchioni et al. employing a cluster model [6]. However, the structural relaxation obtained in our periodic calculations is much stronger resulting in longer Ge-O bonds and wider O-Ge-O angle, which allows for a greater portion of the spin density to localise on the surrounding oxygen atoms, as can be seen in Figure 1. The induced lattice distortion is analysed in unit cells of various sizes and the defect’s distortion field is found to be long-ranged, extending to more than 15 Å, with the structure of the defect converging in cells containing at least 243 atoms. The calculated hyperfine constant, -30.5 mT, is in excellent agreement with the experiment, -28.0 [7]. We obtained the distribution of incorporation energies and defect parameters in the amorphous SiO2 structure.

The authors would like to thank UK's HPC Materials Chemistry Consortium, which is funded by EPSRC (EP/F067496). This work made use of the facilities of HECToR, the UK's national high-performance computing service, which is provided by UoE HPCx Ltd at the University of Edinburgh, Cray Inc and NAG Ltd, and funded by the Office of Science and Technology through EPSRC's High End Computing Programme. The authors would also like to thank UCL for the use of the Legion High Performance Computing Facility, and associated support services, in the completion of this work

References

Fig.1. Spin density of germanium electron trap in alphaquartz. The unpaired electron localizes on the Ge atom and surrounding oxygen atoms causing the O-Ge-O angle to extend.

[1] Jang, J. H., Wantae, L., Phen, M. S., Siebein, K., Pearton, S. J., Craciun V.: Appl. Phys. Lett. 94 (2009) 202104 [2] Lee, I. M., Takoudis, C. G.: J. Vac. Sci. Technol. A 15 (1997) 3154 [3] Long, E., Azarov, A., Klow, F., Galeckas, A., Kuznetsov A. G., Diplas, S.: J. Appl. Phys. 111 (2012) 024308 [4] Kilpatrick, S. J., Jaccodine, R. J. Thompson, P. E.: J. Appl.

Phys. 93 (2003) 4896 [5] Paine, D. C., Caragianis, C., Schwartzman, A. F.: J. Appl.

Phys. 70 (1991) 5076 [6] Pacchioni, G., Mazzeo, C.: Phys. Rev. B 62 (2000)5452 [7] D. L. Griscom, in Glass—Science and Technology, (1991) 151

A complimentary study of vacuum ultraviolet curing procedures on high tensile stress SiXNYHZ PECVD silicon nitride layers T. Fischer1, L. Prager2, J. Hohage3, H. Ruelke3, S. E. Schulz1,4, R. Richter3, T. Gessner1,4 1 - TU Chemnitz 2 - IOM Leipzig 3 - GLOBALFOUNDRIES Dresden 4 - Fraunhofer ENAS corresponding author e-mail: tobias.fischer@zfm.tu-chemnitz.de Strain engineering for decreasing transistor switching time has become an important field in nanoelectronics engineering. In case of n-channel MOS transistor one approach is the deposition of high tensile stressed silicon nitride (SiN) contact etch stop liners. For increasing the as deposited stress in PECVD liners many techniques like in-situ nitrogen plasma treatments, multi-layer-deposition and subsequent vacuum ultraviolet (VUV) treatments have been developed. In contrast to industrial standard VUV procedures with broadband lamps ≥ 220 nm wavelengths, we investigated to the response to higher energetic photons in the films. Therefore we studied the influence of single wavelength treatments at 172 and 222 nm on chemical bonding changes as well as stress behavior. As result we could find a combination of both wavelengths leading to two-step-VUV-curing procedure that is able to increase the as deposited tensile stress by about +900 MPa. For our experiments silicon nitride films with a thickness of 63 nm and an initial stress of +450 MPa were deposited at 400°C on an Applied Materials Precision 5000 PECVD tool on 6’’ Wafers. After radiation all wafers were separated to 2 x 6 cm samples to guarantee a homogeneous radiation in our lab UV exposure tool. For characterization stress changes a bow measurement by an autofocus system, as well as characterization by ellipsometry was done. The resulting stress was calculated

by Stoney’s equation. An additional chemical network analysis was done by transmission absorption Fourier

transform infrared spectroscopy (FTIR). Chemical network compounds were calculated using the methods of Lanford/Rand and Bustarred. Measurements were done before and after VUV treatment at 450°C for different times.

In our experimental study we give a correlation analysis of changes in chemical structure of the described SiN compounds and their changes in stress in consequence of VUV treatment. Our study shows that high energetic photons irradiated by Xe* excimer lamp at 172 nm wavelength can lead to strong dehydrogenization whereas only a small crosslinking of Si-N-Si compounds could be reached. In contrast to this photons irradiated by a KrCl* excimer lamp at 222 nm are able to create a higher amount of stoichiometric SiN compounds whereas the decrease of hydrogen containing compounds is less. Both effects, dehydrogenization as well as crosslinking of SiN-Si, are needed to create high tensile stressed films.

These results led to a combination of both wavelength treatments, resulting in a dual combined VUV curing procedure. The samples treated with this procedure show, compared to the as deposited samples, a lower amount of hydrogen compounds as well as a high amount of stoichiometric SiN compounds leading to a total stress increase of +900 MPa. This shows a high potential for producing highly stressed tensile films and thus a further enhancement of n-channel charge carrier mobility.

References [1] References are styled with References style, TimesNewRoman 9pts, left aligned, italic.

[2] Cambel, V., Fedor, J., and Haigh, S.: Supercond. Sci. Technol. 18 (2005) 417.

[3] Baxter, R.: Exactly Solvable Models in Statistical Mechanics, 3rd ed., Academic Press, New York, 1982.

[4] Gömöry, F.: Proc. of the 6th EUCAS 2003, Sorrento, Italy, 14-18 Sep. 2003, p. 149.

Fig.1. Comparison of stress increase for single wavelength VUV treated to dual combined treated SiN liners (time for 222 nm plotted, 40 min precuring at 172 nm) with initial stress level of +450 MPa

Influences of ozone concentration on the properties of ALD-Al2O3 thin films Annett Freese1, M. Geidel2, L. Wilde3, E. Erben1, S. Jakschik1 and T. Mikolajick1,2 1

Namlab GmbH, 01187 Dresden, Germany Institut für Halbleiter und Mikrosystemtechnik, Technische Universität Dresden, 01062 Dresden, Germany 3 Fraunhofer-Center Nanoelectronic Technologies, 01099 Dresden, Germany corresponding author e-mail: annett.freese@namlab.com 2

1E+14

TProcess=300 °C, FGA

1E+13 1E+12 1E+11 1E+10

150 °C and 300 °C confirming literature results [4]. The Al 2p spectra of the XPS depth profiles showed a higher amount of Al-OH-bonds in the H2O processed Al2O3 films than in O3 processed films. The C 1s signal revealed a strong presence of either C-O or C-H bonds in ozone deposited films. The results indicate formation of methoxy groups (Al-O-CH3) on the surface as illustrated

by Prechtl [3] preventing the ligand elimination. The Dit and negative Nfix exhibited similar values for the 40 g/m³ and 80 g/m³ ALD processes and remained unchanged with increasing temperature. On the other hand the Nfix and Dit values for the 250 g/m³ films are in general higher (Fig. 1) and increased by roughly one order of magnitude in the 300 °C process (Fig. 2). The results suggest a temperature dependent desorption of H2O leading to a decrease of OH-coverage and an oxygen rich surface which allows no further reactions with the precursor molecules, as proposed by Elliott [4]. Films from a TMA+H2O process had the lowest Nfix and Dit due to the OH-surface saturation in the first half reaction resulting in a nearly ideal film growth. A forming gas anneal (FGA) reduced the Dit by one order of magnitude. Contrary, the FGA has no significant influence on the Nfix values (Fig. 2).

In summary, modifications of O3 concentration enables tuning the Nfix and Dit in Al2O3 thin films by ALD. Upcoming investigations on combining 80g/m³ and 250g/m³ O3 in one process are targeting for high Nfix but lower Dit. This work was supported by the German BMBF in the project KONDOR.

References [1] [2] [3] [4]

Dingemans, G.: Phys. Status Solidi RRL 4 (2010), p. 10 Seoung Keun Kim: J. Electrochem. Soc. 153 (2006), p. 1 Prechtl, G.: IEDM 2003, p. 245.

Elliott, S. D.: Chem. Mater. 18 (2006), p. 3764.

Dit (eV-1cm-2), Nfix (cm-²)

Dit (eV-1cm-2), Nfix (cm-2)

Al2O3 is a well established high-κ dielectric used in different applications of electronic devices. It is known from literature [1-2] that its density of dielectric fixed charges (Nfix) and interface traps (Dit) can be tuned by different deposition methods and process parameters to achieve beneficial electrical properties e.g. a good surface passivation in p-doped silicon due to high negative Nfix. In our work we focused on ALD Al2O3 thin films for which the influence of the O3 concentration on the Nfix and Dit was in detail investigated.

Al2O3 thin films were grown by ALD on p-type Si(100) substrates with a 1-2 nm thick wet chemical SiO2 interface in a crossflow hot wall reactor (BENEQ TFS 500). TMA and O3 were employed as metalorganic precursor and oxidant using O3 concentrations of 40 g/m³, 80 g/m³ and 250 g/m³, respectively. Ozone was injected as an O3/O2 gas mixture into the reaction chamber during the first half ALD reaction. The pulse time was fixed at 3 s. Nitrogen was purged for 1,5 s before and 0,25 s after the 0,75 s TMA pulse, respectively. The TMA+O3 films were compared with Al2O3 thin films grown in an ALD process with TMA and H2O as oxidant. Pulse times of the reference were fixed at 0,75 s/ 0,25 s/ 0,75 s/ 0,25 s for H2O pulse/ N2 purge/ TMA pulse/ N2 purge. Deposition temperatures were 150 °C and 300 °C. Representative samples were annealed in forming gas ambient (H2(10 %)/N2) at 500 °C for 10 min. The film thickness was determined by UV/VIS ellipsometry. The impurity content and chemical composition of the films was investigated by X-ray photoelectron spectroscopy (XPS) depth profile analysis. After evaporating a 400 nm Al top electrode C-V measurements were performed to extract the Nfix and Dit of metal-insulator-semiconductor capacitors.

Films within the thickness range of 5 to 19 nm were grown. The growth rate per cycle (GPC) was higher for the TMA+H2O process than for the TMA+O3 process at

1E+14

1E+12 1E+11 1E+10

H2O

80g/m³ O3 250g/m³ O3

Dit

Nfix

Fig.1. Density of interface traps (Dit) and negative fixed charges (Nfix) of annealed Al2O3 thin films grown at 300 °C with H2O and O3 concentrations of 80 and 250 g/m³, respectively.

250 g/m³ O3, TProcess=150 °C

1E+13

Dit

as deposited

Nfix

FGA

Fig.2. Density of interface traps (Dit) and negative fixed charges (Nfix) of as deposited and annealed Al2O3 thin films grown at 150 °C with an O3 concentration of 250 g/m³.

The role of ZrN capping layer deposited on high-k Zr-doped yttrium oxide for metal gate MIS applications Pi-Chun Juan1, Chuan-Hsi Liu2, and Cheng-Li Lin3, Fan-Chen Mong1 1 - Department of Materials Engineering and Center for Thin Film Technologies and Applications, Ming Chi University of Technology, New Taipei City 243, Taiwan 2 - Department of Mechatronic Technology, National Taiwan Normal University, Taipei 106, Taiwan 3 - Department of Electronic Engineering, Feng Chia University, Taichung 407, Taiwan corresponding author e-mail: pcjuan@mail.mcut.edu.tw high-k dielectrics after 8500C annealing. The outdiffusion of Zr atom is sustained when ZrN capping layer is added. The amount of Zr with capping layer is much larger than that without capping layer, which contributes to higher dielectric constant. Binding energies of O 1s, Si 2p, Ti 2p, Y 3d, Zr 3d will be discussed in this paper. Fig. 2 (a) and (b) show the XRD patterns with incident angles of 0.30, 0.50 and 10 without and with ZrN capping layer, respectively. A silicate peak is observed for the sample without ZrN cap, which is attributed to the Si atom interdiffusion near the silicon surface. Fig. 2 (c) and (d) are the I-V characteristics for structures without and with ZrN cap, respectively. Due to the silicate formation, the lower leakage current is found for the sample without capping layer at high temperature annealing. C-V hysteresis, flatband shift and dielectric constant will be discussed later.

HfO2 and ZrO2 are the two more promising candidates to replace SiO2 as the gate dielectric material in MIS transistors while the physical thickness reaching its scaling limit. Recently, researches on the EOT of HfO2 gate stack to less than 1 nm have been extensively studied. However, HfO2 is a poor barrier to oxygen diffusion, which causes the uncontrolled growth of a lowinterfacial layer between HfO2 and the Si substrate during high-temperature postannealing. Several approaches including surface nitridation, HfOxNy and HfN/HfO2 gate stacks with a HfN capping layer have been suggested to improve the thermal stability, EOT, work function, and leakage current [1][2][3]. In contrast, there are no reports using ZrN as the capping layer for ZrO2 and Zr-based dielectrics. In year 2009, prof. Veprek from Technical University Munich obtained the hardness data as TiN> HfN>ZrN modelled by the first principle, density function and gradient approximation. It indicates the sheer stress and stress release are lower and better than TiN and HfN when ZrN contacts with adjacent high-k materials, respectively [4]. Wittmer showed the resistivity and formation energy of ZrN are the lowest as compared to TiN and HfN [5]. The oxygen solubility in Hf is also twice as in Zr [6]. Therefore, it is worth to study the ZrN as the capping layer for Zr-based dielectrics.

Fig. 1 shows the XPS depth profiles of TiN/Y2O3:Zr /Y2O3/Si structures with and without ZrN capping layer.

The Ti atom is seriously out-diffusion through Y2O3

References [1] H. Y. Yu, et al., Tech. Dig. - Int. Electron Devices Meet., 2003, p. 99.

[2] J. F. Kang, et al., Electrochem. Solid-State Lett., 8, G311 2005.

[3] J. F. Kang, et al., J. Electrochem. Soc., 154, H927 2007.

[4] R. F. Zhang, S. H. Sheng, and S. Veprek, Appl. Phys. Lett., 94, 121903 2009.

[5] M. Wittmer, J. Vac. Sci. Technol. A, 3, pp. 1797 1985.

[6] S. P. Murarka, J. Vac. Sci. Technol. 17, pp. 775 1980.

Ti(3nm)/Y2O3:Zr(3.5nm)/Y2O3(3.5nm)/Si

80

#2 Si #1 Si

#2 Ti #1 Ti

#2 Y #1 Y

#2 Zr #1 Zr

silicate

RTA:850oC

0.3o 0.5o 1o

(a)

(b)

60

#1

#2

TiN (3 nm)

40

20

ZrN (1.5 nm)

TiN (3 nm)

Y2O3:Zr (3.5 nm)

Y2O3:Zr (3.5 nm)

Y2O3 (3.5 nm)

Y2O3 (3.5 nm)

100

p-Si

p-Si

10-1

30

40

30

50

10 0

70

80

Ti/Y2O3:Zr/Y2O3/Si RTA 5500C

10-3 10-4 10-5 -6

10

-7

10

10-8

(c)

10-9

1.6

2.6

3.6

4.6

5.6

Sputtering Time (min)

Fig.1. XPS depth profiles of Ti/Y2O3:Zr(3.5 nm)/Y2O3(3.5 nm)/pSi structures with and without ZrN capping layer.

-2

-1

0

1

Applied Voltage (V)

2

3

4

Ti/ZrN/Y2O3:Zr/Y2O3/Si RTA 550 C Ti/ZrN/Y2O3:Zr/Y2O3/Si RTA 7000C Ti/ZrN/Y2O3:Zr/Y2O3/Si RTA 8500C

10-5 10-6 10-7 10-8

(d)

10-9

5

80

10-4

-11

-3

70 0

10

10-10 -4

60

10-3

-11

-5

50 2θ (Degree)

-2

-10

10

40

100

Ti/Y2O3:Zr/Y2O3/Si RTA 8500C

10

30

10-1

10

0.6

20 101

Ti/Y2O3:Zr/Y2O3/Si RTA 7000C

-2

20

60

2θ (Degree)

101

Current Density (A/cm 2)

50

Current Density (A/cm 2)

Atomic Percentage (%)

70

Ti(3nm)/ZrN(1.5nm)/Y2O3:Zr(3.5nm)/Y2O3(3.5nm)/Si

0.30 0.50 10

RTA 8500C

Intensity (Arb. Unit)

#2 O #1 O

Intensity(Arb. Unit)

90

10

-5

-4

-3

-2

-1

0

1

2

Applied Voltage (V)

Fig.2. X-ray diffraction patterns of (a) without and (b) with ZrN cap. I-V characteristics of (c) without and (d) with ZrN cap.

3

4

5

Frequency dependency of TDDB of 28nm High-k/Metal Gate NFETs S. Knebel1, G. Roll1, S. Kupke1, S. Slesazeck1, R. Agaiby, G. Krause2, G. Kurz2, M. Trentzsch2, T. Mikolaijick1,3 1 – Namlab gGmbH, Nöthnitzer Straße 64, 01187 Dresden, Germany 2 – GLOBALFOUNDRIES, Wilschdorfer Landstrasse 101, 01109 Dresden, Germany 3 – Institut für Halbleiter- und Mikrosystemtechnik, TU Dresden, 01187 Dresden Corresponding author e-mail: steve.knebel@namlab.com Reliability issues are one of the major concerns for modern technology nodes. Understanding the evolution of stress induced leakage current (SILC) and the time dependent dielectric breakdown (TDDB) behavior is important for accurate lifetime estimations. The main focus of our investigations lies on the TDDB of high-k dielectric/metal gate stack (HK/MG) CMOSFETs. Hfbased HK/MGs exhibit different TDDB distributions depending on measurement methodology. Results of DC and AC TDDB tests are presented for ultra small area (USA) NFETs. Ultra small area (A1 = 0. 032 µm²) HK/MG NFETs were fabricated by GLOBALFOUNDRIES using a gate first, high-k metal gate technology on silicon on insulator substrates. TDDB measurements are done using a PCI card based data acquisition setup on wafer level at 125°C [1].

Figure 1 shows the principle of DC and AC TDDB test setup. For DC stress a constant voltage is applied as illustrated in the upper panel. SILC was periodically monitored at a lower sense voltage within 1 ms for breakdown detection. Under unipolar AC stress the stress voltage was altered between stress bias and 0 volts at different frequencies with a fixed duty cycle of 50%.

SILC was monitored under same voltage conditions for both, DC and AC measurement.

In the past, for SiO2 based dielectrics, DC stress was regarded as worst case scenario in CMOSFET lifetime investigations. In contrast, AC stress improves lifetime [2]. However, the TDDB behavior of Hf-based dielectric gate stacks with a SiO2 interface layer shows a frequency dependency. Figure 2 compares the time-to-breakdown (Tbd) for DC and AC stressed NFET devices. It is obvious that for an AC frequency below 10 kHz the

0

References [1] Kerber, A.: IRW Final Report, 2004, 41- 45 [2] Hofmann, P.: Microelectronics Reliability, 2008, Vol. 48, Issues 8–9,, pp. 1189-1192, [3] Bersuker, G.: IEDM (2008) 1 [4] Lee K. T.:IRPS (2011)

2

Stress Sense

0 2

This work was financially supported by the HEIKO project (100064806), Free State of Saxony and the EFRE fund.

DC Stress

Bias

ln(-ln(1-F))

Voltage

2

failure time is reduced compared to the DC case. As explained in [3], the SiO2 interfacial layer controls the degradation and breakdown of the high-k gate stack. The inlay of Fig. 2 depicts the band diagram for sense conditions. The defect bands for HfO2 and SiO2 are marked in grey as published by Bersuker et al [3].Based on this microscopic picture, our results point to a trap generation within the SiO2 interface layer close to the interface to the high-k layer. Under AC stress these traps are discharged at the lower bias. Thus the evolution of SILC is suppressed, but the degradation is increased for lower frequencies resulting in decreased TDDB. For unipolar AC stress, no hot-hole generation takes place and the model proposed by Lee [4] cannot be applied.

Therefore we conclude, that the enhanced degradation can only be related to the discharge of occupied traps. At higher frequencies traps cannot respond to the change of the applied field anymore and hence, the lifetime increases again and approaches the same values as under DC stress conditions.In summary we characterized the frequency dependency of the TDDB behavior of an Hfbased gate oxide with SiO2 interfacial layer. Lifetime reduction was observed for low frequency AC measurements. At higher frequency Tbd behaves similar to DC stress case.

1 0 -1

-3

AC

-4

Time

10Hz 100Hz 1kHz 10kHz DC

-2

Sense

Fig.1 Voltage time traces during DC and AC TDDB measurement. Under AC stress the voltage is altered between stress and bias level.

1.1V

1

10

100

1000

Tbd(sec) Fig.2. TDDB failure distribution for DC and AC stress at different frequencies. It is clearly visible that lifetime is reduced for low frequency AC stress. Band diagram for Vg = 1.1V indicates possible leakage mechanisms.

Deposition Dependent Study of Silicon Nitride Films for MIM Application WM Davey1, N Sedghi1, T Dowrick1, IZ Mitrovic1, SD Connor2, PH Mason2, J P Perring2 and S Hall1 1 - Liverpool University, Liverpool, UK, 2 - Plessey Semiconductors Ltd., Great Western Way, Swindon, UK E-mail address of corresponding author: w.m.davey@liv.ac.uk Silicon nitride is a candidate dielectric in integrated capacitors because of its relative ease of processing and integration, low leakage current and thermal stability. We report here MIM capacitors formed with a slow deposition rate which exhibit low temperature coefficient less than 30 ppm/°C, voltage coefficient of 21 ppm/V, relatively high dielectric constant of 7.5, breakdown field strength of 9.7 MV/cm, and low leakage current.

Layers were deposited on silicon by low pressure chemical vapour deposition (LPCVD) and standard CVD at two different deposition rates. A plasma-enhanced chemical vapor deposition (PECVD) method was used for deposition on an Al alloy bottom plate on Si. A 10×15 parallel MIM capacitor array with total area of 3×105 µm2, was fabricated by patterning the top and bottom Al alloy electrode. Spectroscopic ellipsometry showed that the LPCVD nitrides had superior refractive indices compared to the CVD layers deposited at a high deposition rate. However, CVD deposition at a lower rate improved the optical constants, similar to those of the LPCVD layers. Similarly the absorption observed for the LPCVD and slow deposition rate CVD layers was similar with the films having a bandgap of ~4.9eV and a short defect tail. The fast deposition rate CVD layers however exhibited a defect tail over 1eV larger than the other deposition techniques. The FTIR study of Fig.1 shows that the peaks attributable to Si-H bonding at around 2000-2100cm-1 (fig.1) were much lower in the fast deposition rate CVD layers, whereas the other techniques had a similar magnitude. It can be concluded that the slower deposition rate allowed more hydrogen to be incorporated within the film, thus passivating a larger proportion of the traps present [1,2].

The layers were further assessed to determine the leakage current conduction mechanism, variation of

capacitance with frequency, voltage, and temperature over the range 15-140 °C. Reliability was studied using constant voltage stress, time to breakdown and charge to breakdown (QBD). HFCV measurements show negligible frequency dispersion up to 200 kHz. There is less than 10% deviation between 200 kHz and 1 MHz, which is deemed to be due to series resistance. The voltage variation of capacitance at different temperatures is shown in Fig. 2. An excellent fit can be seen to the standard empirical quadratic equation [3] with average variation of 21 ppm/V and 18 ppm/V2. The variation of normalized differential capacitance (referenced to C0 = 15°C) with temperature was linear, with a temperature coefficient of 30 ppm/°C. The linear variation of C(T) is believed to be due to temperature dependence of ionic susceptibility of the dielectric and its contribution to relative dynamic permittivity [4].

The variation of leakage current with time after application of constant voltage stress was observed to have a logarithmic relationship with stress time, and looks to be dominated by electron trapping in the dielectric. The extracted time to breakdown versus voltage was found to be in agreement with linear field model [5]. The QBD is in the range of 2.8×10-3 to 1.4×10-2 C/cm2 depending on the stress voltage.

Acknowledgments: The work was funded by the Technology Strategy Board, UK: project ‘PPM2’. The Authors also thank Perkin Elmer who carried out the FTIR analysis.

References [1] [2] [3] [4] [5]

H.J. Stein, et al, J. Electrochem. Soc. 124 (1977) 908.

W.J. Kapoor, et al, J. Vac. Sci. Technol. A 1 (1982) 600 P. Gonon et al, Appl. Phys. Lett. 90 (2007) 142906-1.

S. Bécu, et al, Appl. Phys. Lett. 88 (2006), 052902-1.

J. C. Lee et al., IEEE T. Electron Dev. 35 (1988), 2268.

897

Capacitance, C [pF]

896

140 °C

895 894

80 °C

893 892

15 °C

891 890 -10

Fig.1.Hydrogen related features in FTIR comparing slow and fast dep. CVD with LPCVD layers

140 °C 80 °C 15 °C

-5

0

Voltage, V [V]

5

10

Fig.2. Capacitance versus voltage and temperature.

The lines with symbols show quadratic fitting [3].

Small-signal admittance model as a characterization tool of the MOS diode B. Majkusiak and J. Jasiński Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa 75, Warsaw, Poland corresponding author e-mail: majkusiak@imio.pw.edu.pl Reduction of the gate insulator thickness to the range of a single nanometer as a result of the scalling process affects characterization procedures basing on the MOS capacitor as a diagnostic tool. If the oxide layer is extremely thin and the tunnel current is large, the leakage conductance affects the series equivalent circuit capacitance especially strongly for small frequencies, contrarily to the series resistance effect, which in turn, affects the parallel capacitance of the small signal admittance especially at high frequencies. We investigate these effects with the use of a theoretical model and verify it as a characterization tool of the MOS tunnel diodes by comparison with experimental data. The developed model is based on a steady–state algorithm which includes the time-dependent phenomena by means of relaxation times.

The small-signal equivalent circuit of the MOS tunnel diode includes the parasitic elements: series resistance RS and the leakage resistance RL. The measured small-signal response can be expressed in the form of the series equivalent circuit with elements CSm and RSm or the parallel circuit with elements CPm and RPm. The circuit transformations lead to simple relations between them.

Fig. 1 and Fig. 2 show the theoretical gate voltage dependencies of capacitances Cmos(LF), Cmos, CSm, CPm and resistances RL(LF), RL, RSm, RPm with the oxide thickness as a parameter for the Al-SiO2-Si(n) tunnel diode of Nd = 1016 cm-3, series resistance Rs=100 and the gate diameter d=0.1mm. In turn, Fig.3 shows the measured and simulated current-voltage characteristics of the test tunnel diode with the gate diameter 0.2mm. Fig. 4 and 5 compare the measured and simulated small-signal capacitances and resistances. The extracted series resistance was equal to 14.8.

Concluding the results one can state that the developed model of the static and small-signal characteristics of the MOS tunnel diode can serve as an effective characterization tool of MOS structures with high-k gate stacks where the leakage conductance is a very important parasitic parameter.

Acknowledgment. The work is supported by Ministry of Science and High Education, Poland, no. N N515 524838.

Fig.3. Measured and simulated static IV characteristics.

Fig.1. Theoretical small-signal capacitances of the MOS diode.

Fig.4. Measured and simulated capacitances of the MOS diode.

Fig.2. Theoretical small-signal resistances of the MOS diode.

Fig.5. Measured and simulated resistances of the MOS diode.

Influence of chemical and plasma treatments on AlGaN/GaN MIS-HEMTs electric properties R. Meunier1, A. Torres1, M. Charles1, R. Escoffier1, C. Petit-Etienne2, O. Renault1, T. Billon1 1 - CEA-Leti, MINATEC Campus, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France 2 - CNRS-LTM, MINATEC Campus, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France corresponding author e-mail: richard.meunier@cea.fr AlGaN /GaN heterostructures are very promising for the elaboration of high-power and high frequency devices because of their excellent electric properties such as a high breakdown voltage and a high saturation electron velocity. Current transistor architecture is based on Schottky gate structure. The Metal Insulator Semiconductor (MIS) gate structure with the introduction of high dielectric constant (high-Îş) materials as a gate dielectric represents one of the most promising ways to achieve viable power electronic devices [1]. In order to enhance those different features, surface treatments are interesting to reduce to its minimum the surface contamination before the device processing, thus eliminating the poor native oxide and reducing the electron traps that might hinder electronic properties [2].

This work is focused on the surface analysis of an Al0.28Ga0.72N/GaN heterostructure grown by MOCVD on Si. Surface characterization is performed through X-ray Photoelectron Spectroscopy (XPS) and Atomic Force Microscopy (AFM) in order to determine semiconductor surface composition and roughness.

In order to reduce to its minimum the oxygen contamination, HCl, NH4OH, SC1 (NH4OH+H2O2), SC2 (HCl+H2O2), HF and BOE solutions [3] were tested at different concentrations, temperatures and time of dip. As for the carbon contamination, forming gas, N2, NH3 and oxygen plasmas [4] with different power and time of exposition were analyzed. In both cases, the aim is to keep the stoechiometry and the composition of the AlxGa1-xN surface.

As illustrated in Fig.1, an NH4OH dip at a relatively low concentration and high temperature proved to be the most effective in removing the oxygen contamination. We attained low oxygen contamination of only 3% regarding Ga-oxydes, while Al-oxides were under the threshold of the XPS detection. The minimum carbon presence of 10% was achieved through low energy O2-plasma, which corresponds to the carbon residue due to the epitaxial growth conditions. While not being as effective as the NH4OH for the oxide removal, halogen containing treatments proved to add fluoric or chlorinated contamination.

As we can see in table 1, ammoniac based treatments were effective in preserving both stoechiometry and surface composition, whereas chloride treatments removed N and Ga. Long O2 based plasmas also proved to remove a lot of N. Ongoing analysis show that N-based plasma-treatments seem to restore fully or partially the III-N stoechimoetry. (We expect to add quantitative results in the final version of the paper) Ongoing electrical studies are currently evaluating which treatment is the most effective on the electric properties of AlGaN/GaN based devices, through the elaboration of Schottky and MIS. We are also investigating several high-k dielectrics that should be used as passivation layer and gate dielectric to achieve the best electric properties.

References [1] Hashizume T. and al., Japanese Journal of Applied Physics, The Japan Society of Applied Physics, 43 (2004) L777-L779.

[2] Vetury R. and al., Electron Devices, IEEE Transactions on, 48 (2001) 560-566.

[3] King S. W. and al., Journal of Applied Physics, AIP, 84 (1998) 5248-5260 [4] Kim J. H. and al., Japanese Journal of Applied Physics, The Japan Society of Applied Physics, 49 (2010)

45 40 35 30 25 20 15 10

Treatment

SC1

SC2

HCl

NH4OH

III-N Stoechiometry

1,2 : 1

1,2 : 1

0,9 : 1

1,1 : 1

AlxGa1-xN (%)

27%

33%

36%

26%

5 0 SC1

SC2 %O

%C

HCl %AlO/Al

NH4OH

%GaO/Ga

Fig.1. Carbon and oxygen contamination after high temperature chemical treatments

Table.1. III-N stoechiometry and surface composition after high temperature chemical treatments.

AC level effect on interface state density extractions in high-k/III-V MOSCAPs Scott Monaghan1, Éamon O’Connor1, Brendan J. Sheehan1, Karim Cherkaoui1, Fahmida Ferdousi2, Rafael Rios2, Anisur Rahman2, Kelin Kuhn2, and Paul K. Hurley1 1 – Tyndall National Institute, University College Cork, Lee Maltings, Cork, County Cork, Ireland.

2 – Intel Components Research, 2501 NW 229th Avenue, Hillsboro, OR 97124, USA. Corresponding author e-mail: scott.monaghan@tyndall.ie The scaling of metal-oxide-semiconductor field-effect transistors (MOSFETs) has been advanced in recent years with the introduction of high dielectric constant (high-k) gate oxide materials on silicon in conjunction with the metal replacement of doped polysilicon gate electrodes [1]. As scaling progresses beyond the 45nm and 32nm nodes, replacement of the silicon semiconductor channel material is necessary to improve the performance in future planar and non-planar MOSFET architectures [2].

Compound semiconductor material systems such as In0.53Ga0.47As are under investigation for their suitability to replace silicon in PMOS (n-channel) field-effect transistors (n-MOSFETs) as a result of the predicted high electron mobility that could be achieved in the nMOSFET channel [3]. Detrimental scattering of electrons due to the presence of a high interface state defect density (Dit) at the high-k/In0.53Ga0.47As interface is a major issue [4]. Advances have been made recently at reducing Dit in MOS capacitors (MOSCAPs) [5-6], and this progress has been successfully transferred to MOSFET devices [7].

As optimisation of the high-k/In0.53Ga0.47As interface continues, an accurate estimate of Dit is important to ensure performance enhancements can be achieved in resulting MOSFETs. An important metrology issue is the influence of the test signal (AC) level parameter selection on the Dit extraction for AC impedance-based capacitance-voltage (CV) and conductance-voltage (GV) measurements at AC frequencies ranging from ~100 Hz to ~1 MHz. The Conductance Method and the High-Low Frequency CV Method manipulate some or all of this data to obtain the Dit estimates [8]. Maximising the AC level reduces measurement noise, but continued transistor scaling reduces the operating voltage which necessitates a

smaller voltage step size. It would be reasonable to expect significant error in the measurements as the voltage step size becomes comparable to, and less than, the AC level.

This work looks at the effect on Dit estimates when different AC level/bias step size ratios are selected.

Preliminary electrical results are shown below for a Au/Ni/Al2O3 (8nm)/n-In0.53Ga0.47As/n-InP MOSCAP. Figure 1 shows the approximate Conductance Method extracted Dit versus gate voltage for AC levels of 30mV, 90mV, and 150mV. The inset shows the GV data. Figure 2 shows the High-Low Frequency CV Method extracted Dit, with the inset showing the CV data. The respective methods show a maximum of ~10%/4% Dit change at ~ 1.8V/-1.6V for a 0.3 to 1.5 AC level/step size (100mV) ratio change, which is a surprisingly small change given the five times ratio increase. We will present additional Dit results using different AC level/step size ratios for both n-type and p-type In0.53Ga0.47As MOSCAPs.

Fig. 1: Approximate Conductance Method extracted Dit versus gate voltage for three AC levels. Inset: Conductance (S/m2) versus gate voltage for the same AC levels at 1 kHz and 1 MHz. Dit is influenced by both the GV and CV (Fig. 2 inset) responses.

Fig. 2: High-Low Frequency CV Method extracted Dit versus gate voltage for three AC levels. Inset: Capacitance density versus gate voltage for the same AC levels at 1 kHz and 1 MHz. The difference in Dit to Fig. 1 is common and will be discussed.

Funding for this work was provided to Dr. Paul K. Hurley by Intel Components Research. We acknowledge the support of Intel Ireland, particularly Roger E. Nagle.

References [1] [2] [3] [4] [5] [6] [7] [8]

Mistry, K., et al.: Tech. Dig. – Int. Elec. Dev. M. (2007) 247.

Ferain, I., et al.: Nature 479 (2011) 310.

Del Alamo, J. A.: Nature 479 (2011) 317.

Frank, M. M.: Proc. Of ESSDERC, 12-16 Sept. (2011) 25.

Trinh, H. D., et al.: Appl. Phys. Lett. 97 (2010) 042903.

O’Connor, É., et al.: Appl. Phys. Lett. 99 (2011) 212901.

Djara, V., et al.: Trans. Elec. Dev. 59 (4), (2012) In Press.

Nicollian, E. H., Brews, J.: MOS Phys & Tech, Wiley 1982.

Optimization of in situ plasma oxidation of Gd metallic thin films deposited by high pressure sputtering on Si M. A. Pampillón1, P. C. Feijoo1, E. San Andrés1, M. L. Lucía1 1 - Departamento de Física Aplicada III (Electricidad y Electrónica). Facultad de Ciencias Físicas. Universidad Complutense de Madrid E-28040, Spain. corresponding author e-mail: mpampillon@fis.ucm.es The need of industry to scale down the MOSFETs dimensions and to increase switching speeds has made possible that high k dielectrics are being introduced in CMOS routes. For future high k generations, rare-earth scandates are promising candidates [1, 2]. This work is focused on the study of the properties of Gd2O3, obtained by high pressure sputtering (HPS), in order to be combined in the future with Sc to produce GdScO3. The main problem with high k materials is that they must meet certain requirements as chemical and structural stability on Si, low interfacial density of states, minimizing the regrowth of an undesirable interfacial SiOx film that would reduce the permittivity and increase the equivalent oxide thickness (EOT), etc. In this work, in order to achieve this former requirement, we have deposited Gd metallic thin films by HPS on Si and, without extracting the sample from the system, we have oxidized the films in situ through plasma oxidation. We have studied the effect on the films of several plasma oxidation conditions.

For growing the Gd2O3 films we have used a two-step process: first we deposited a Gd metallic thin film on Si

by HPS in a pure Ar atmosphere from a 99.95% purity Gd target. The plasma conditions were 0.50 mbar of pressure and 30 W of rf power. Afterwards, to oxidize the metallic films, we introduced a 5% flux of oxygen and we studied different plasma oxidation conditions, by changing the applied rf power (10, 20 or 30 W), the oxidation step duration (150, 225 or 300 s) or the starting Gd thickness (4, 6 or 8 nm). The pressure was fixed to 0.50 mbar.

Bonding structure was analyzed by Fourier transform infrared (FTIR) spectroscopy. To obtain the electrical characteristics, we fabricated MIS devices with several

different top electrode metals (inert and oxygen scavengers). We performed a forming gas anneal (FGA) at 300 ºC during 20 min. C-V and G-V curves of MIS devices were measured with an Agilent 4294A impedance meter and J-V characteristics, with a Keithley 2636A. Fig.1 shows the absorbance spectra in the range of 900 to 1200 cm-1 for samples with different rf power during plasma oxidation. It can be observed a peak centered at ~1040 cm-1. This peak is related to substoichiometric SiOx [3]. We can see that this peak is more intense for 30 W than for lower powers. In the inset of this figure, which represents the peak area as function of power, we observe a great increase in the SiOx thickness for 30 W. In Fig.2 we represent the gate capacitance versus the gate voltage for the samples with different oxidation powers, with Ti as metal electrode. We observed that 20 W is the optimum oxidation power, since 30 W presents lower capacitance due to the growth of interfacial SiOx, and samples with 10 W present a distorted capacitance that could be due to a formation of an oxygen-deficient GdOx. Concerning the effect of oxidation time, we found that the effect was marginal, and increasing the starting Gd thickness gave devices with lower conductances but also lower capacitances.

This work was funded by the project TEC2010-18051 and the FPU grant AP2007-01157.

References [1] Zhao, C. et al.: Appl. Phys. Lett. 86 (2005) 132903.

[2] Roeckerath, M. et al.: Appl. Phys. A 94 (2009) 521.

[3] Pai, P.G. et al.: J. Vac. Sci. Technol. A 4 (1986) 689.

-0,009

18

0,10

16 0,08

14 0,06

10

-0,010

-0,011

-0,012 900

20

C/A (fF/µm2)

SiOx area (a. u.)

Absorbance (rel. units)

-0,008

30

Power (W)

10 W 20 W 30 W 950

12 10 8 6 4

10 W 20 W 30 W

2 1000

1050

1100 Wavenumber (cm-1)

1150

1200

Fig.1. Absorbance spectra for different plasma oxidation rf power. Inset: SiOx integrated area as a function of applied rf power.

0 -1,5

-1,0

-0,5

0,0

0,5

1,0

Vgate (V)

Fig.2. Gate capacitance curves as function of gate voltage measured at 10 kHz for different plasma oxidation rf powers.

Diode-Embedded Resistive Memory Using Stacked Ferroelectric/Dielectric Layer Min Hyuk Park*, Hyun Ju Lee, Yu Jin Kim, Jong Ho Lee, Woongkyu Lee, Han Joon Kim, and Cheol Seong Hwang WCU Hybrid Materials Program, Department of Material Science & Engineering and Inter-university Semiconductor Research Center, Seoul National University, Seoul 151-744, Korea corresponding author e-mail: pmh1983@snu.ac.kr Ferroelectric random access memory (FeRAM) has been regarded as one of the most promising nonvolatile memories because of its two reversible polarization states.

Most of the former researches were focused on the charge based operation of the ferroelectric material in FeRAM, which suffers from the scaling problems as the DRAM does. Therefore, many researches migrated to resistancebased memory using the ferroelectric layer.[1,2] However, it has been quite difficult to achieve the reasonable ferroelectric polarization switching with the concurrent presence of high switchable leakage current.

High leakage current based on the defect-mediated current mechanism degrades generally the ferroelectric performances. On the other hand, tunneling-based current mechanism has a relatively low on/off ratio and requires ultra-thin (<< 10 nm) epitaxial ferroelectric films. In this study, a different type of ferroelectric resistive memory was fabricated and its physical and electrical characteristics were examined.

Figure 1a shows the structure of the suggested resistive memory which is comprised of 150-nm-thick Pb(Zr,Ti)O3, 2-nm-thick Al2O3 and 20-nm-thick TiOx films sandwiched between top and bottom Pt electrode.

Pt, PZT, and TiOx are of the poly-crystalline nature and Al2O3 is amorphous. Figure 1b shows the representative IV characteristics of the sample. The ratio of the current of low resistive state (LRS) to that of high resistive state (HRS) is as high as ~105 which is the highest among reported ferroelectric-based resistive memories. In addition, the diode-like behaviour, which is very promising I-V characteristics for crossbar array

architecture for next generation non-volatile memory, can be also found.

Figure 2a shows I-V curves of four consecutive DC sweeps. The four sets show almost identical hysteresis showing the repeatable switching operation of the sample as a memory. Figure 2b shows the exemplary operation scheme of this sample with Set (0+10V), Read (03V), Reset (0-10V), and Read (0-3V). The read and reset process shows almost identical I-V curves in the range of 0~-3V. This means that -3V read does not affect the resistive state of the memory.

To summarize, a novel self-rectifying ferroelectric resistive memory behavior of PZT/Al2O3/TiOx heterostructure was reported. ILRS/IHRS was ~105 at read voltage of -3V, and the rectification ratio of the embeded diode was >104. The current density of LRS was >10 mA/cm2, which is high enough for the resistance-based memory. It shows a great potential as a next-generation resistive memory in a simple crossbar array architecture.

This study was supported by the Converging Research Center Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2011K000609).

References [1] Garcia, V., Fusil, S., Bouzehouane, K., Enouz-Vedrenne, S., Mathur, N. D, Barthelemy, A., Bibes, M.: Nature 460 (2009) 81.

[2] Jiang, A. Q., Wang, C., Jin, K. J., Liu, X. B., Scott, J. F., Hwang, C. S., Tang, T. A.: Adv. Mater. 23 (2011) 1277.

-4

-4

10

-6

Current[A]

10

-7

10

-8

10

-9

10

-10

10

-11

10

10

-6

10

-7

10

-8

10

-9

10

-10

10

(b) -10

Set 1 Set 2 Set 3 Set 4

-5

-11

-5

0

5

10

Voltage[V]

Fig.1. (a)Structure of the novel resistive memory and (b)its current-voltage(I-V) characteristics with four DC voltage sweeps(010V, 010V, 0-10V, and 0-10V)

10

10

-6

10

-7

10

-8

10

-9

10

-10

10

(a)

+10V -3V -10V -3V

-5

10

Current(A)

10 Pt

-4

10

+10V +10V -10V -10V

-5

Current[A]

(a)

(b)

-11

-10

-5

0

5

Voltage[V]

10

10

-10

-5

0

5

10

Voltage(V)

Fig.2. (a)I-V hysteresis of Repetitive four sets of DC voltage sweeps(010V, 010V, 0-10V, and 0-10V) and (b)exemplary memory operation consists of Set(010V), Read(0-3V), Reset(0-10V), and Read(0-3V)

Electronic Transport and Defects in SiOC Low Dielectric Constant Films T.A. Pomorski1, B.C. Bittel1,2, Corey Cochrane1 , P.M. Lenahan1 S.W. King2 1 – The Pennsylvania State University, University Park, PA, USA 2 – Intel Corporation, Hillsboro, OR, USA Tzp124@psu.edu Low k materials are of great interest for use as inter layer dielectrics in integrated circuits.

The electronic transport and reliability of these dielectrics is of great importance. In this study we explore the link between electronic transport and defect structure in a leading family of low k materials, those based on SiOC. In this study we utilize electron spin resonance (ESR) via conventional and fast passage measurements as well as electrically detected magnetic resonance (EDMR) via spin dependent trap assisted tunnelling (SDT). We have also explored electronic transport as a function of field and temperature.

We have explored materials systems based on SiOC with dielectric constants ranging from 2.0 to 3.9.

We observe conductivity as a function of temperature consistent with the expression σ A exp B/ T where A and B are constants and n is, in most cases, 0.5. (see Fig 1 for representative results) This result is consistent with variable range hopping transport.[1] In a wide range of SiOC based dielectrics we observe ESR measurements observe a narrow center line of about 4 Gauss with a g value of 2.0026. (The g is defined by the expression g hυ/βH where h is Planck’s constant, ν is the microwave frequency, β is the Bohr magneton, and H is the magnetic field.) We find that the paramagnetic defect density is linked to the conductivity of these samples and note that UV exposure consistently increases both paramagnetic defect density and leakage current.[2] (See Fig 2 for representative results) We have made a tentative identification of these defects. In low temperature fast passage[3] ESR measurements (5K) we observe a pair of widely separated weak side peaks in the ESR spectra of some SiOC films which correspond to an integrated intensity of about 0.5% each of the center line.

(See Fig 3) Since 1.1% of carbon nuclei have a nuclear spin of ½, the ESR spectrum of a carbon dangling bond defect would exhibit a strong center line and 2 weak side peaks each with an intensity of about 0.55% of the center line.[4] Thus, these results strongly suggest that the dominating defects are carbon dangling bonds. It should

Fig.2. Temperature dependence of a representative SiOC film.

We observe a T1/2 dependence at 2MV/cm.

be noted that we observe an additional line at somewhat lower fields with a spectrum which is at least qualitatively consistent with that of an O 2 - center. This additional line corresponds to only a few percent of the overall ESR intensity.

References [1] N. Mott, Conduction in Non-Crystalline Materials, Oxford University Press, New York, (1987).

[2] B .C. Bittel, P.M. Lenahan, and S.W. King, Appl. Phys. Lett., 97, 063506 (2010).

[3] J. S. Hyde, Phys. Rev. 119, 1483 (1960).

[4] J.A. Weil, J.R. Bolton, J.E. Wertz, Electron Paramagnetic Resonance, John Wiley and Sons, New York, (1994).

Fig.1. ESR and leakage data for a SiOC sample exposed to UV light. Note the increase in ESR amplitude and leakage current with the exposure to the light.

Fig.3. Fast passage ESR data for SiOC. The integrated intensity of the outer most peaks is about 0.5%. The uppermost trace is raw ESR data at high gain. The middle trace is the superposition of the 4 lines shown in the bottom trace which represent the 2 hyperfine line, center line, and O 2 - line.

Modelling the Maxell-Wagner Instabilities in Gate Stack Dielectrics E. K. Evagelou1, M. S. Rahman1, 2,*, N. Panagiotides1, and A. Dimoulas3 1 – Department of Physics, University of Ioannina, 45110-Ioannina, Greece 2 – Detector Laboratory-GSI, 64291-Darmstadt, Germany 3 –MBE Laboratory, NCSR, DEMOKRITOS, 15310-Athens, Greece *corresponding author e-mail: M.S.Rahman@gsi.de In order to achieve better electrical properties on Gebased MOS devices an interfacial buffer layer (il) (e.g. rare earth oxides) is used between the high-k dielectrics (such as HfO2) and Ge substrates, thus forming gate stacks. However this structure itself is responsible of charge trapping between il and the high-k layer, while the latter may add dielectric relaxation effects in the device.

The resulting current instability also is usually termed as Maxwell-Wagner Current Instability (M-W) and the corresponding MOS devices show current decay transients (J-t) due to these effects.

Jameson et al. [1] proposed a model to explain the above mentioned current decay due to M-W after considering both charge accumulation and relaxation effects in the gate stacks. The model can explain the experimental data when the leakage current is extremely low (at very low CVS condition) and relaxation effects dominate [2]. But it was reasonable in this model to assume that the current decay was due to relaxation effects mainly (J~t–n where n=0.96). However, while the model is based on existence of a leakage current through the dielectric which is ohmic, the corresponding analytical expression for J(t) never reaches a saturation level.

Recently Miranda et al. [3] proposed a model and described the decay of J-t transient by using a combination of dielectric relaxation, series and parallel resistive elements where the creation of new traps in the dielectrics could also be modelled. This new model explains the experiment data until a limited stress time, t ≥100s) (see Fig. 1).

In the present work we propose a model that calculates the J(t) decay from first principles by solving a system of

ordinary differential equations for the flow of current through each layer of the gate stack which is expressed as follows:

Fig.1. Fit (solid line) to the experimental (symbols) data using Miranda’s model [3] to Pt/HfO2/ Dy2O3/p-Ge MOS capacitor subjected to CVS at accumulation.

Fig.2. Experimental J-t data (red circle, same data as Fig.1) and fitting (solid line) using Eq. 1. In Fig.2 we use the stress time (1 to 500s), however it can describe the longer CVS data (t>1ks)

J=

( j1' + j1 ) ⋅ (d1 / k1 ) + ( j2' + j2 ) ⋅ (d 2 / k 2 ) --- (1) (d1 / k1 ) + (d 2 / k 2 )

where j1,2 is relaxation current, j΄1,2 displacement current assumed to follow an ohmic behavior (j΄i=σiEi), k1,2 is the dielectric constant, and d1,2 the thickness of the dielectrics of high-k and il low-k dielectrics respectively.

With this model we can describe the decay transient (see Fig. 2) for longer stress time and in particular for times larger than few thousands of seconds.

It is worth to mention here that the relaxation behaviour (decay transient) in gate stack is different from classical dielectric relaxation characteristics, which is useful for studying future bilayer gate stacks and oxide degradation.

One of the authors, MSR would like to thanks IKY (Greek State Fellowship) and Marie Curie Fellowship (MC-PAD) for his research funding.

References [1] Jameson, J., Griffin, P., Plummer, J, and Nishi, Y.,: IEEE Trans. Electron Dev., 53 (2006) 1858.

[2] Rahman, M., and Evangelou, K., IEEE Trans. Electron Dev., 58 (2011) 3549 [3] Miranda, E., Mahata, C., Das, T., and Maiti, C., : Microelectron Reliab., 51 (2011) 1535.

Low temperature thermal ALD of silicon nitride thin films using Si3Cl8 Stefan Riedel1, Jonas Sundqvist1, Thomas Gumprecht2,3,Frans Munnik4 1 Fraunhofer Center Nanoeletronic Technologies, Koenigsbruecker Str. 180, 01099 Dresden, Germany 2 Fraunhofer Institute for Integrated Systems and Device Technology IISB, Schottkystr. 10, 91058Erlangen, Germany 3 Erlangen Graduate School in Advanced Optical Technologies SAOT, Paul-Gordan-Str. 9, 91052 Erlangen, Germany 4 Institute of Ion Beam Physics and Materials Research, Helmholtz-Zentrum Dresden-Rossendorf, 01314 Dresden corresponding author e-mail: stefan.riedel@cnt.fraunhofer.de

1.5

SiN ALD SiN Ref SiN LPCVD

1.0

significantly enhances the sensitivity to simultaneously analyze variations of optical properties, thickness and film composition. The improved sensitivity is obtained by the typically increased optical absorption of materials in the VUV region.

The refractive index was determined to be 1.76 at 632nm by this method, which is smaller than values reported for stoichiometric Si3N4 [4], indicating a substoichiometric nitride. The optical bandgap was determined to be 4.1eV, which is in a typical range of SiN:H. The film composition was determined by ERDA and XPS. XPS composition mapping over a 300 mm wafer showed an uniform N/Si ratio of >1 and relatively low amount of chlorine contamination below 5%-at.

Additionally the wet etch behaviour in diluted HF was investigated.

Simple MIS devices were prepared by evaporation metal dot electrodes on the deposited SiN layers in order to perform a basic electrical characterization by means of C-V and I-V measurements. The layers show a significant hysteresis, which is typical for charge trapping SiN layers.

The k-value was determined to be ~6, which is similar to values recently reported for PEALD SiN films [5].

References [1] A. Nakajima, T. Yoshimoto, T. Kidera, and S. Yokoyama, Appl. Phys. Lett. 79, 665, (2001) [2] K. Park, WD Yun, BJ. Choi, HD Kim, WJ Lee, SK Rha, CO Park, Thin Solid Films 517, 3975–3978, (2009) [3] H. Knoops, E. Langereis, M. van de Sanden, W. Kessels, J. Electrochem. Soc. 157, G241, (2010) [4] Handbook of Optical Constants of Solids I, edited by E. D. Palik (Academic, Orlando, FL, 1985.

[5] S.King, J. Vac. Sci. Technol. A 29(4), (2011) 0.25

capacitance density [µF/cm²]

refractive index n

extinction coefficient k

Thin dielectric SiNx layers are of high interest for various applications in microelectronic devices, for instance as liner or as charge trap layer in SONOS (silicon oxide, nitride, oxide, silicon) and TANOS devices (TaN, Al2O3, SiO2, SiNx, Si). Driven by the decreasing feature sizes and recent trends of 3D integration, especially for Flash devices, ALD (atomic layer deposition) processes are of high importance for these applications due to the superior step coverage and thickness control of this deposition method. However, ALD growth of SiN has proven to be challenging at low temperatures below 550°C without plasma activation [1,2]. In order to coat highest aspect ratio features, thermal ALD processes are preferred, since plasma assisted processes may suffer from surface radical loss induced non-conformality [3].

In this paper we present data on SiNx films deposited on 300mm Si wafers, which were grown by ALD, based upon a chlorine based silicon precursor (Octachlorotrisilane, OCTS) and ammonia. A deposition could be achieved at substrate temperatures down to 450°C, which is lower than values previously reported for thermal SiN [1,2]. ALD growth was investigated between 450°C and 550°C and a step coverage of >80% could be achieved in structures with an aspect ratio of 1:70 The deposited films were characterized by spectral ellipsometry (=250 to 750nm), vacuum ultra-violet (VUV) reflectometry (=120 to 800 nm) and X-Ray reflectometry. Dielectric materials like Si3N4 and SiO2 show similar optical properties and dispersion in the wavelength region above 200 nm to near infrared. Thus it is a challenge to determine the thickness and refractive index especially of thin SiN films by spectral ellipsometry. Extending reflectometry beyond the lower limits of deep ultra-violet at 300 nm into the vacuum ultraviolet (VUV) region between 100 nm to 200 nm

0.5 0.0 3.0 2.5 2.0

0.20

0.15

0.10

0.05

1.5 1.0 200

300

400

500

600

700

800

wavelength [nm]

Fig 1. Dispersion curves determined by VUV reflectometry for ALD deposited SiN compared to LPCVD SiN and reference data from[4]

0.00 -2

-1

0

1

2

3

4

5

voltage [V]

Fig 2. C-V curve hysteresis of 23nm ALD deposited silicon nitride

6

Defect energy levels in MGeOx (M: Hf or La) H Li, J Robertson Engineering Department, Cambridge University, Cambridge, UK corresponding author e-mail: jr214@cam.ac.uk

Reference [1] K. Kita, et al., Jpn. J. App. Phys., 47 2349 (2011)

[2] A. Dimoulas, et al., Appl. Phys. Lett, 96 012902 (2010) [3] M. Oshima, et al., Appl. Phys. Lett, 83 2172 (2003) 6

6

Ge of La2Ge2O7 La of La2Ge2O7 O of La2Ge2O7

4

2

2

0 -10

a

Ge of HfGeO4 Hf of HfGeO4 O of HfGeO4

PDOS

4

PDOS

Ge is proposed as high mobility channel material.

However, the passivation of Ge is more difficult than that of Si. This is mainly due to the volatile GeO problem [1], which means that GeO2 is not suited as a gate dielectric material. Hf and La are found to react strongly with interfacial GeO2, which absorbs germanium and oxygen from the interfacial region, leading to the formation of abrupt metal germinate/Ge interface without GeOx transition region [2]. Oxygen vacancy induced defects in high K dielectrics is widely accepted as an important reason for device degradation. In this work, we studied the defect energy levels in crystalline HfGeOx and LaGeOx. The calculation uses CASTEP. The atomic structure is relaxed by GGA functional in 48~64 atoms’ supercell containing one oxygen vacancy. The band structure is calculated by screened exchange (sX) which does not need band gap correction.

Figure 1 shows the partial density of states of triclinic La2Ge2O7 and tetragonal HfGeO4. The band gap of La2Ge2O7 is ~5 eV and ~5.5 eV for that of HfGeO4. The lower part of the conduction band mainly consists of 5d orbital of metal.

Figure 2 and Figure 3 show two defect configurations and the wave function of the defect in +2, +1, 0 and -1 charge states of La2Ge2O7, where the vacancy is surrounded by two La and one Ge or two Ge and one La, respectively. The wave function shows that S1 state is Ge like mid gap state, while S2 state is La like near conduction band minimum. From Fig. 4(a) we can see all the defect states do not lie within Ge band gap. It is noteworthy in Fig 3(b) that two Ge atoms are attracted towards the vacancy and rebond to each other to form GeGe bond. From Fig. 4(b) we can see that Ge-Ge rebonding in V+1 forming bonding and antibonding states repels defect level away from the Ge band gap.

Figure 4 summarizes the defect energy levels of La2Ge2O7, HfGeO4 and HfSiO4 aligned to Ge/Si band gap. Band alignment in Fig. 4(a-c) is from ab-initio calculation of epitaxial interface models of metal germinate on Ge, while Fig 4(d) uses experimental data.

We found that S1 states of HfGeO4 is more deeper donor states than that of HfSiO4, we also found that (picture not shown) S1 state of V+1 of HfGeO4 is more localized.

In conclusion, we have calculated the energy levels of the various charge states of the oxygen vacancy in LaGeOx and HfGeOx. Most of the defect states are deeper than the equivalent states of HfO2, which means charge trapping will be less prevalent and slower in these two metal germinate. Wave functions of the defect states are also shown.

-5

0 5 Energy(eV)

10

0 -10

b

-5

0 5 Energy(eV)

10

Fig. 1(a) PDOS of La2Ge2O7 , (b) PDOS of HfGeO4.

a

b

c

d

Fig. 2 Wavefunction of S1 and S2 defect states of (a) V-1 (b) V0 (c)V+1 (d)V+2 of La2Ge2O7 (the first vacancy configuration).

b

a

c

d

Fig.3 Wavefunction of S1 and S2 defect states of (a) V-1 (b) V0 (c)V+1 (d)V+2 of La2Ge2O7 (the second vacancy configuration).

4 2

spin down spin up

S2 S2 •

S1 • • S1 • •

-

a

c

4 2 0 -2 -4

−1

G

VO

VO+1

VO+2

b

La2Ge2O7 S2 S2 •

-4

spin down spin up

S2

S2

S2 S2

S1

S1 S1 • • S1 • • S1 •

G

V O− 1 V O0

V

+1 O

HfGeO4

V O+ 2

d

4 2 0 -

S1

S1 • S1 •

G

S2 S1

S2 S2

S2 •

-2

S1 •

S2

S2

0

S1

V O0

spin down spin up

2

S2 S1

S2

S2

0 -

4

spin up and down states splitting less than 0.1 eV are not shown separately

S1 • • S1 •

V O− 1

V O0

La2Ge2O7

S2 S2 •

V O+ 1

+2

VO

spin down spin up

S2

S2 S2

S2 S1

S1 S1• • S1 • • S1•

Si

V O− 1

V O0 V O+ 1 V O+ 2

HfSiO4

Fig. 4 Defect energy level of (a) the first and (b) the second kind of vacancy in La2Ge2O7, (c) HfGeO4 and (d) HfSiO4[3].

Approaches for the reduction of the influence of parasitic capacitances on local IV characteristics for conductive AFM M. Rommel1, J.D. Jambreck1, K. Murakami2, M. Lemberger1, A.J. Bauer1, L. Frey1,2 1 â&#x20AC;&#x201C; Fraunhofer Institute for Integrated Systems and Device Technology, Schottkystrasse 10, 91058 Erlangen, Germany 2 â&#x20AC;&#x201C; Chair of Electron Devices, University of Erlangen-Nuremberg, Cauerstrasse 6, 91058 Erlangen, Germany corresponding author e-mail: mathias.rommel@iisb.fraunhofer.de Conductive AFM (cAFM) is a powerful technique for studying electrical properties of SiO2 and high-k materials on the nanoscale [1-3]. Next to imaging lateral property variations by current mapping at a fixed bias voltage, cAFM enables the recording of local current-voltage (IV) characteristics trough the dielectrics with nanometer resolution (mainly limited by the size of the tip apex). This allows for the localized evaluation of current conduction mechanisms (e.g., to compare between grains and grain boundaries of high-k films [3]). Note that the relevant tipdielectric-semiconductor capacitance is extremely small (i.e., in the aF range [4]). cAFM IV curves are obtained by applying a voltage sweep with a sweep rate sr.

However, the sensitivity of acquired IV curves by cAFM is usually limited by high parasitic currents for small bias voltages (i.e., minimum current densities (J) of cAFM characteristics which can surely be attributed to the leakage currents through the dielectric are very high, see Fig. 1 and e.g. [2]). As will be discussed, this is mainly due to rather large parasitic capacitances Cpar (in the pF range) between the cantilever or the tip holder and the sample which are more pronounced in the centre of a sample [4]. Cpar will lead to approx. constant displacement currents which are proportional to sr (see Fig. 2 for tip B). In addition, for abrupt changes in current, transient effects occur which are due to the high sensitivity cAFM current amplifier and Cpar (again more pronounced for higher sr, see Fig. 2). Thus, smaller sr cause smaller parasitic currents. However, small sr also lead to higher electrical stresses during the sweep due to the longer measurement times and high current densities, especially when measuring in the Fowler-Nordheim tunnelling regime [2].

In addition, significant charge trapping will already occur in high-k materials during the first sweep.

In this work, therefore, different approaches will be presented to increase the sensitivity of cAFM (i.e., to increase the current density range available for evaluating current conduction mechanisms) even for moderate and high sr. In particular, the advantage of using special

shielded tips (tip B) rather than commercially available silicon tips coated with Pt/Ir (tip A) is demonstrated (see Fig. 2). Tips B have a strip line design realized by focused ion beam processing.

On the other hand, different approaches to correct the measured data for both, displacement current and transient effects will be presented and critically discussed. As an example, Fig. 3 shows the corrected IV curves of Fig. 2 for high sr using an approach where both, forward (from 0 V to -5 V) and reverse (from -5 V to 0 V) sweep directions are considered. For tips B, corrected currents of 20 fA with a noise of 100 fA are obtained, even for very high sr and in the centre of the sample. This is due to the reduced Cpar of tips B. As will be shown, for sr of 1 V/s and below, average currents of 3 fA with noise levels of 40 fA (noise level of the amplifier [1]) can be achieved.

All measurements were performed using a Bruker Dimension Icon system with a Nanoscope V controller.

Next to the results for 5 nm SiO2 samples presented in Figs. 2 and 3, experiments for larger voltage ranges and HfO2 high-k samples with smaller effective oxide thickness will be shown. Other aspects like absolute noise level and offset current as well as the observed transient effects will be discussed and recommendations for optimized measurement and evaluation procedures will be given.

Summarizing, the use of shielded tips together with proper data evaluation procedures allows to minimize the influence of Cpar on local cAFM IV measurements which enables to access strongly increased current ranges for the localized evaluation of current conduction mechanisms.

References [1] P. De Wolf, E. Brazel, and A. Erickson, Mat. Sci. Semicond.

Proc. 4 (2001) 71.

[2] V. Yanev, T. Erlbacher, M. Rommel, A. J. Bauer, and L. Frey, Microelectron. Eng. 86 (2009) 1911).

[3] K. Murakami, M. Rommel, V. Yanev, A.J. Bauer, and L. Frey, AIP Conf. Proc. 1395 (2011) 134.

[4] G. H. Buh, Ch. Tran, and J. J. Kopanski, J. Vac. Sci. Technol. B 22 (2004) 417.

limited sensitivity

Fig.1.Comparison of conventional and cAFM JV characteristics (4 nm SiO2).

V is applied to the semiconductor.

Fig.2. As-measured cAFM IV curves with Fig.3. Displacement current corrected IV different sr and tips for 5 nm SiO2 curves with sr of 10 V/s (from Fig. 2). at the centre of the sample.

High pressure sputtering as a viable technique for future high-k on III-V integration: Gd2O3 on InP demonstration M. A. Pampillón1, C. Cañadilla1, P. C. Feijoo1, E. San Andrés1, A. del Prado1 1 - Departamento de Física Aplicada III (Electricidad y Electrónica). Facultad de Ciencias Físicas. Universidad Complutense de Madrid. E-28040. corresponding author e-mail: esas@fis.ucm.es At present high-k dielectrics are becoming mainstream in the CMOS microelectronics industry. The material of choice is HfO2. To overcome its limitations a myriad of materials is currently being researched. Among them one of the families that show promising properties are the rare-earth scandates [1]. Within them, we have focused on GdxSc2-xO3 since it presents the higher-k value of many RE-scandates. On top of that, gadolinium oxide has proved its compatibility with III-V substrates [2]. In this work we have studied the electrical properties of Gd2O3, obtained by high pressure sputtering (HPS) on Si and InP substrates. In the near future we will combine it with Sc to obtain GdScO. The HPS technique poses another advantage very important for 3D structures, like FinFETs: the working pressure is in the mbar range, and thus the mean free path of species is between two to three orders of magnitude smaller than conventional sputtering systems [3]. Thus, the species suffer many more collisions before reaching the substrate. This way it is expected that the angular distribution of the incoming species is more uniform and the step coverage improves.

To prevent damage of the semiconductor substrate we have used an optimized two-step sputtering procedure for high-k deposition: in the first step a thin Gd metallic film was sputtered by HPS by using a metallic Gd target and a pure Ar atmosphere. In a second step, without extracting the sample from the system, by adjusting gas composition and plasma parameters, we have obtained the Gd2O3 films in situ through an optimized plasma oxidation.

Identical MIS devices were grown on n-Si and n-InP wafers, both with 100 orientation and a resistivity of ~1-5 Ω.cm. For MIS fabrication, both wafers were covered with 300 nm of e-beam evaporated SiO2, which was used as field oxide. Contact pads are placed on top of this oxide to avoid damaging the high-k film by the measuring needle during characterization. To define the

active area of the device, square openings were etched on the SiO2 by 8:1 BHF. After that, the substrates were cleaned (RCA for Si, Iodic acid for InP). Just before introducing the samples to the sputtering chamber, the native oxide was eliminated by a 30 s dip on 1:50 diluted HF. Then, a 6 nm thick Gd2O3 was deposited. The top electrode (8 nm of Pt / 50 nm of Al) was defined by a negative photoresist procedure. After that, backside contact was evaporated (100 nm Ti / 200 nm Al for Si, 100 nm AuGe / 100 nm Au for InP). Finally, we performed a forming gas anneal (FGA) at 300 ºC for 20 min. The C-V and G-V curves of the MIS devices were measured at 10kHz, followed by the I-V measurement.

The devices were measured before and after FGA anneal.

Fig.1 shows the area normalized capacitance-voltage characteristics of representative devices of each sample.

We can observe that in both cases the devices are fully functional, showing the accumulation - inversion transition. The Si devices show a small “hunch” in the depletion region, but the InP curves do not show this feature. The distortion of the C-V curve can be related to the Dit, thus, the results point to a smaller density of defects in the InP case. Also, the capacitance of the InP device is higher (around a 30%, with a difference in CET between samples of about 1.5 nm). In Fig.2 we show several J-V curves of those samples. We can observe that in both cases the leakage is very low, but in the InP case the values are higher. Since the Gd2O3 should be identical in both devices, the difference should come from a higher interfacial re-growth in the Si case. Further results will be presented at the conference.

This work was funded by the project TEC2010-18051.

References [1] Zhao, C. et al.: Appl. Phys. Lett. 86 (2005) 132903.

[2] M. Hong et al. Science. 283 (1999),, 1897.

[3] E. San Andrés et al. J. Vac. Sci. Technol. A 23 (2005) 1523.

-3

-4

10

70

GdO on InP

60

-5

2

J [A/cm ]

-8

2

Norm. Capacitance [x10 F/cm ]

10 80

50 GdO on InP 40 30

10

-6

10

-7

GdO on Si

10

GdO on Si

20 -8

10

10 0

-9

-5

-4

-3

-2

-1

0

1

2

Vgate [V]

Fig.1. Gate capacitance vs gate voltage measured at 10 kHz of plasma oxidized Gd2O3 deposited on Si (solid lines) or InP (dashed lines).

10

0.0

0.2

0.4

0.6

0.8

1.0

Vgate [V]

Fig.2. Gate leakage vs gate voltage of plasma oxidized Gd2O3 deposited on Si (solid lines) or InP (dashed lines).

A Model for Hole Trapping in LaLuO3 Based on the 3-Pulse CV Technique N. Sedghi1, T. Dowrick1, O. Engström2, I. Z. Mitrovic1, and S. Hall1 1 - School of Electrical Engineering and Electronics, University of Liverpool, Liverpool, UK 2 - Microtechnology and Nanoscience, Chalmers University of Technology, Goteborg, Sweden corresponding author e-mail: nsed@liv.ac.uk Charge trapping in high-κ dielectric gate stacks is a rather fast process which cannot be detected by conventional characterization methods, due to the influence of charge trapping or de-trapping during the measurement. We have already reported a three-pulse CV technique by which trapping and de-trapping of both negative and positive charges can be studied independently [1, 2]. Several models on electron trapping in high-κ dielectrics have been reported in the past few years [3, 4], however, knowledge about hole traps, their origin, and distribution is rather limited.

In this work the effect of hole trapping in lanthanum lutetium oxide (LaLuO3) gate dielectric stack on p-type silicon substrate has been investigated using the threepulse CV technique. The flat band voltage shift of CV plots due to trapped charge and its variation with charging time and charging voltage are studied. Two distinctive trapping regimes with different dependence on charging time have been observed at low and high electric fields, which can be ascribed to the lowering of trap energy levels in the high-κ layer, with the applied voltage. A model for hole trapping is proposed and used to study the trap distribution in energy and space.

The 3-pulse CV measurements were performed on LaLuO3/SiOx/p-Si MOS capacitors with 10 and 20 nm high-κ dielectric physical thickness. The device fabrication [5] and measurement procedure and setup [1, 2] have been described elsewhere.

The variation of flat band voltage shift with charging time at various pulse amplitudes for 20 nm thick device (Fig. 1), shows a power relationship with charging time at voltages with absolute values less than 5.5 V and a logarithmic relationship at higher voltages. The same behaviour was observed on a 10 nm thick sample, however, the transition between the two regimes occurred

at lower voltages (Fig. 2).

The proposed model is based on the direct tunneling of holes from the silicon accumulation layer to traps in the lower half of the dielectric band gap. The tunnelling probability was calculated using Wentzel-KramersBrillouin (WKB) approximation with further thermal activation to the trap states. The band bending due to trapped charge in the oxide was also included in the model. The trap energy levels and densities were varied to achieve the best fit to the experimental data (solid lines).

It reveals that the dominant trap energy levels are within 0.5 to 1 eV and few shallow traps within 0.1 eV from the valence band edge of high-κ dielectric with density of 5×1018 to 5×1019 cm-3. The model did not show a good fit at very low voltages, suggesting that direct tunneling may not be the dominant process at these voltages.

In conclusion, a hole trapping model is used to explain the trapping in LaLuO3 gate stack and to investigate the trap distribution in energy and space. The work was partially funded by the Nanosil EC network of excellence and the EPSRC, UK. Jürgen Schubert, Research Centre Jülich, Germany, and Marcelo M. J. Lopes now in Paul-Drude-Institut, Germany, are acknowledged for sample preparation. An undergraduate student, Xinya Bian, now at Cambridge University is acknowledged for performing some of the pulsed CV measurements.

References [1] [2] [3] [4]

Sedghi et al.: Elec. Soc. T. 35 (2011), 531.

Sedghi et al.: J. Vac. Sci. Technol. B 29 (2011), 01AB03-1.

M. Cho, et al.: Solid State Electron. 54 (2010), 1384.

D. Ruiz Aguado et al.: IEEE T. Electron Dev. 57 (2010), 2726.

[5] J. M. J. Lopes et al.: Microelectron. Eng. 86 (2009), 1646.

0.0

-0.2

VL = -4 V VL = -4.25 V VL = -4.5 V VL = -4.75 V VL = -5 V VL = -5.25 V VL = -5.5 V VL = -5.75 V VL = -6 V

-0.4 -0.6 -0.8 -1.0 -1.2 -1.4 10-3

10-2

10-1

100

101

Charging Time, tcharge [s]

Flat Band Voltage Shift, ∆VFB [V]

Flat Band Voltage Shift, ∆VFB [V]

-0.2

-0.4 -0.6 -0.8 -1.0

Charging Voltage -3V - 3.5 V -4V - 4.5 V -5V

-1.2 -1.4 -1.6 -1.8

10-3

10-2

10-1

100

101

102

Charging Time, tcharge [s]

Fig.1. Variation of flat band voltage shift as a function of charging time at different voltages for 20 nm thick sample. The solid lines show the fitting to the model.

Fig.2. Experimental data (symbols) and fitting to the model (solid lines) for 10 nm thick sample..

Thermodynamic Foundations of Solid-State Cooler Based on Multiferroic Materials A. Starkov1 , O. Pakhomov1 , and I. Starkov2,⋆ 1

Institute of Refrigeration and Biotechnologies, St. Petersburg National Research University of Information Technologies, Mechanics and Optics, St. Petersburg, Russia 2 Institute for Microelectronics, Vienna University of Technology, Wien, Austria ⋆ corresponding author e-mail: starkov@iue.tuwien.ac.at In view of the increasing requirements on energy saving, as well as the necessity to cool the growing number of on-chip components, the alternative cooling principles not associated with the traditional refrigerants become more and more actual. The most promising are the solid-state cooling devices, among which are widely used systems based on the Peltier effect. However, due to the low refrigerating factor of these systems, methods of cooling based on the caloric effects [1, 2] seem more perspective.

Caloric effects describe the change of temperature or the thermodynamic entropy of the system by the application (or removal) of an external force. If this external force is the electric field there is the electrocaloric effect (ECE), if the magnetic – the magnetocaloric effect. In the case of the elastic stress application it is the piezocaloric effect. Such an effects are more intensive near the phase transition points, where the internal parameters of the system as the polarization, the magnetization and the deformation are strongly dependent on the temperature. In literature we were able to find consideration of the impact of various external fields on the temperature independently from each other. At the same time, extremely promising and attracting the attention type of materials are multiferroics [3], in which there are at least two of the three possible interactions between these fields. In particular, for multiferroics-ferromagnetics the main feature is the relationship between the electric and magnetic fields (magnetoelectric effect) that allows to control the electric field using the magnetic and vice versa. It is offered to use this physical feature in order to create a fundamentally new solid-state cooler.

We have investigated the temperature dependence of the multiferroic sample subjected to a periodic electrical, magnetic and elastic fields (the heat exchange with the environment is taken into account). It is possible to increase the sample temperature by controlling of the electric field employing the magnetic field. The change of the temperature during one cycle is proportional to the magnetoelectric coefficient. As a consequence, for a large number of applied cycles the resulting temperature change may reach value in 5-10 times higher than in the case of the only electric field presence. Such a result is very promising for practical realization of a high-performance solid-state cooler devices.

Numerical calculations performed in [4] on the basis of simplified model demonstrate a significant increasing in the electrocaloric effect employing the modulation of the electric field by an elastic force. It is obvious

that the additional opportunity for influence the electric field by magnetic field result in more effective ECE reinforcement. A simple case of periodic changes in the electric and magnetic fields has to be considered: E = E0 sin(wt), H = H0 sin(wt + ϕ), (1) where E0 , H0 are the amplitudes, ω is the frequency, ϕ is the phase shift. The time dependence of the sample temperature is shown in Fig.1. One can see that the difference between initial and steady-state temperatures depends strongly on the phase shift.

We have proposed an approach for reinforcement of the ECE in order to refine the cooling parameters of refrigerator, which is designed on multiferroics. This work has presented basic physical ideas how to improve the solid-state cooler parameters. These ideas are supported by calculations, thereby making them vital. Our study may provide a theoretical basis and physical insights for the further refinement of solidstate cooler characteristics.

References [1] Muller, K., Fauth, F., Fisher, S., Koch, M., Furrer, A., Lacorre, Ph.: Appl. Phys. Lett., 73 (1998) 1056.

[2] Strassle, Th., Furrer, A., Hossain, Z., Geibel, Ch.: Phys. Rev. B, 67 (2003) 054407.

[3] Khomskii, D.: Physics, 2 (2009) 20.

[4] Starkov, A., Pakhomov, O., Starkov, I.: Tech.

Phys. Lett.,37 (2011) 105.

Fig.1. The time dependence of the sample temperature in response to periodic oscillations of the applied electric and magnetic fields with a relative phase shift of (a) φ = −π/2, (b) φ = −π/6 and (c) φ = −π/8.

A study of ferroelectric multilayer structures based on BST films containing high concentration of magnetic ions A.A. Semenov1, A.I. Dedyk1, P.Y. Belavsky1, Yu.V. Pavlova1, S.F. Karmanenko1, O.V. Pakhomov2, A.S. Starkov2, I.A. Starkov3 1 - Petersburg State Electrotechnical University, 5, Prof. Popova St., Saint-Petersburg, 197376, Russia 2 - Saint-Petersburg State University of Low Temperature and Foodstuff Technologies, 9, Lomonosova St., Saint-Petersburg, 190002, Russia 3 - Institute for Microelectronics, Technische Universität Wien A–1040 Wien, Austria corresponding author e-mail: starkov.ivan@gmail.com Acknowledgment This work was supported by the federal program “Scientific and Scientific–Pedagogical Personnel of Innovative Russia 2009–2013” and the analytic program “Development of Scientific Potential of Higher Education 2009–2013”.

References [1] Ozgur U., Alivov Ya., Morkoc H.: J.Mater Sci Mater Electron. 20 (2009) 911.

[2] А.A. Semenov, S. F. Karmanenko, V. E. Demidov et all. : Appl. Phys. Lett. 88 (2006) 033503.

1,2

C, pF

0,88

1,1

0,84 150

C, pF

A combination of ferroelectric and ferromagnetic materials allows realizing electronic tuning in ferriteferroelectric structures by means of magnetoelectric (ME) and electrodynamic effects (ED). The investigated structure could be realizing as layered ferrite-ferroelectric system as well as heterophase system of the ferroelectric mixed with compounds containing magnetic ions.

This work presents the results of the investigation of influence of Mn ions concentration on dielectric properties of Cu-Cr/BSTO/α-Al2O3 and CuCr/BSTO/GGG film structures and to the results for multilayer structures study such as CuCr/BSTO/YIG/GGG. The films BSTO (BaxSr1-xTiO3; x = 0,5 – 0,6) and YIG (Y3Fe5O12) had thickness 0,3 – 0,5 µm and 5 – 8 µm respectively. The Mn ion concentration was changed in the region 0 – 20 wt%. The measurements of capacitance-voltage characteristics C(U), the dependencies tanδ(U) and temperature dependencies C(T) of the planar capacitors were carried out at the frequencies 1 MHz and 29,7 GHz. The structure and phase composition of the samples were studied by means of XRD and PIXE (Particle Induced X-ray emission) analysis.

It was shown that presence of Mn additives of 0 – 2 wt% leads to decrease of lattice parameter of BST films.

At Mn concentration ~ 2 wt% the second phase was detected (Ba,Sr)(Mn,Ti)O3-z. The dielectric permittivity and tunability coefficient K of the investigated structures (K – the ratio of initial capacitance value to the one at biasing voltage) are considerably decreased at Mn concentration increase for the indicated region. The coefficient K equals to 1,2 – 1,3. However, Mn concentration increase to 15 wt% leads to tunability coefficient increase up to ~ 2,0.

The C(U) characteristics of Cu-Cr/BSTO/YIG/GGG structures was studied in magnetic field with intensity 2000 Oe (see Fig.1). Some change of the characteristic is connected with ME effect. The magnetic field applied to the ferrite layer leads to deformation of its crystal lattice due to magnetostrictive effect. Good mechanical contact of YIG and BST films provides a transfer of mecahnical tension to ferroelectric layer, where piezoelectric effect takes a place, so the dielectric constant is changed and it is displayed in capacitance value.

U, V

200

1,0

H = 0 Oe H = 2000 Oe

0,9 0,8 -200

-100

0

U, V

100

200

Fig.1.Capacitance-voltage dependence of CuCr/BSTO/YIG/GGG structure

Comparative Study of Metalorganic Chemical Vapour Deposition of HfO2 and Al2O3 Gate Insulators on SiC for Power MOSFET Applications Eisuke Tokumitsu1,2, Isahaya Yamamura1, Shiro Hino3, Naruhisa Miura3, Masayuki Imaizumi3, Hiroaki Sumitani3 and Tatsuo Oomori4 1 Precision and Intelligence Laboratory, Tokyo Institute of Technology 2 Green Device Research Center, Japan Advanced Institute of Science and Technology 3 Advanced Technology R&D Center, Mitsubishi Electric Corporation 4 Power Device Works, Mitsubishi Electric Corporation corresponding author e-mail: tokumitu@neuro.pi.titech.ac.jp 4H-SiC MOSFET is promising as a next generation power device. However, improvement of the SiO2/SiC interface properties is still a major concern for power MOSFET applications to obtain high channel mobility and low on-state resistance. We have previously demonstrated high-channel-mobility-SiC-MOSFETs with deposited Al2O3 gate insulator which was fabricated by metalorganic chemical vapor deposition (MOCVD) at low temperature [1.2]. In this work, we deposited HfO2 thin films on SiC substrates instead of Al2O3 by MOCVD and fabricated HfO2/SiC MOSFETs. In particular, electrical properties of HfO2/SiC MOSFETs are compared with those of Al2O3/SiC MOSFETs. Lateral n-channel MOSFETs were fabricated on a ptype epitaxial layer with a carrier concentration of 8x1015 cm-3, which was grown on 8o off-axis 4H-SiC(0001) substrate. The fabrication process is similar to that of our previous works [1,2] except that a Hf precursor, tetrakisdiethylamino-hafnium, Hf[N(C2H5)2]4, was used to deposit HfO2 thin films [3]. At first, n+-source/drain regions were formed by P+ ion-implantation followed by activation annealing. Then, after the sacrifice oxidation process, a very thin thermal oxide layer was grown on the SiC surface as a buffer layer. The thickness of the thermal oxide was varied from 0 to 3 nm. Next, approximately 50nm-thick HfO2 gate insulator was deposited at 190oC or 280oC with Hf[N(C2H5)2]4, and O2. Finally, gate and source/drain electrodes were formed by Al evaporation for the electrical measurements.

A channel mobility as high as 130 cm2/Vs was obtained for a HfO2/SiO2/SiC MOSFET with a SiO2 buffer layer of 0.9 nm when HfO2 was deposited at 190oC, as shown in Fig.1. This is significantly higher than the channel mobility observed in the conventional SiO2/SiC structure (20-30 cm2/Vs). When the thickness of the SiO2 buffer layer was more than 1 nm, the channel mobility decreases as shown in Fig. 2, which is similar tendency to Al2O3/SiO2/SiC MOSFETs [2]. This is probably because the interface traps were generated during the thermal oxidation process. On the other hand, when the deposition temperature was 280oC, thick (about 3 nm) SiO2 buffer layer was necessary to obtain transistor operation. This is in contrast with Al2O3/SiO2/SiC MOSFETs, where high channel mobility can be obtained even when the deposition temperature of Al2O3 is 280oC, if the SiO2 buffer layer thickness is 1 nm. These results suggest that the deposition of HfO2 causes more damage at the interface than that of Al2O3 especially at 280oC.

References [1] S. Hino, T. Hatayama, J. Kato, E. Tokumitsu, N. Miura and T. Oomori, Appl. Phys. Lett., 92 (2008) 183503.

[2] T. Hatayama, S. Hino, N. Miura, T. Oomori and E. Tokumitsu, IEEE Trans. Electron Devices, 55 (2008) 2041.

[3] S. Hino, M. Nakayama, K. Takahashi, H. Funakubo and E. Tokumitsu, Jpn. J. Appl. Phys.,42 (2003) 6015.

µeff

100 40

20

0

ID

0

50

µFE

1

0 2

SiO2-Equivalent Electric Field(MV/cm)

Fig.1. ID-EG characteristics of HfO2/SiO2/SiC MOSFETs with a 0.9 nm-thick SiO2 buffer layer.

150

Peak mobility (cm2/Vs)

Drain Current(µA)

60

Chanel Mobility(cm2/Vs)

150

VDS=0.1V

190oC 280oC 100

50

0

0

1

2

3

Thickness of SiO2 buffer layer (nm)

Fig.2. Peak channel mobility of HfO2/SiO2/SiCMOSFETs as a function of thickness of the SiO2 buffer layer.

Giant dielectric constant in TiO2/Al2O3 nanolaminates prepared by pulsed laser deposition P. Walke1, A.Lefevre2, G.Parat2, F.Lallemand3, F.Voiron3, B. Mercey1 and U. Lüders1 1 - CRISMAT, CNRS UMR 6508, ENSICAEN, 6 Boulevard Maréchal Juin, 14050 Caen cedex 4, France 2 - CEA, LETI, MINATEC Campus, 17 rue des Martyrs, 38054 GRENOBLE Cedex 9, France.

3 – IPDIA, 2 rue de la Girafe, 14000 CAEN, France. corresponding author e-mail: walke.pravin@ensicaen.fr the migration of the charges and TiO2 to exploit the particular oxygen exchange with Al2O3 [1,2]. The nanolaminates of Al2O3 (εr ~7) and TiO2 (εr ~50-80) are prepared by pulsed laser deposition (PLD) on n-Si substrate with controlled sublayer thickness less than one nanometer. We obtain giant dielectric constant values of the order of 104 based on the combination of these binary oxides. Furthermore, the dielectric constant is widely tunable by manipulating the sub-layer thicknesses of the component oxides influencing the density of carrier traps at the interface, number of interfaces and oxygen redistribution. The present work establishes thus a novel architecture for the development of high dielectric constant materials based on the nanolaminates of oxides easy to integrate into existing devices.

Authors would like to acknowledge the Marie Curie Training Network SOPRANO and OSEO innovation project PRIIM for their support.

[1] Li et al. Appl. Phys. Lett. 96, 162907 (2010) [2] Li et al. J.Appl. Phys. 110, 024106 (2011)

104

103

102 102

TiO2(nm)-Al2O3(nm)

Dielectric loss

dielectric constant (ε)

The dielectric constant enhancement is a major research concern due to the wide range of applications for capacitors, such as multichip modules (MCM), dynamic random access memory (DRAM), microchip energy storage for next development of renewable energy generation/storage systems. One of the major issues in microelectronic industry is the miniaturization of capacitive devices which requires development of new materials allowing the enhancement of the surface capacitance in capacitors. In order to enhance this value keeping the capacitor surface constant, an enhancement of the dielectric constant is inevitable. Researchers are introducing several ways to improve the dielectric constant of materials by modifying/tuning chemical composition via doping, substitution etc. and furthermore explore novel materials. Such materials classification contain binary oxides (e.g., HfO2, ZrO2, Ta2O5, TiO2) with moderate values of the dielectric constant, or perovskite oxides (e.g., BaTiO3, SrTiO3) with dielectric constants being 3 orders of magnitude higher, but the complex structure of these materials hinders the integration into existing technology.

Instead of searching for novel materials, the aim of this study was to develop nanolaminates showing high dielectric constants based on the Maxwell-Wagner relaxation at interfaces. Here, the excitation of confined electrons is used to create artificial dipoles. We chose the combination of high band gap Al2O3 (8.8 eV) to prevent

0.7-0.7 0.9-0.7 0.9-0.8 0.7-0.6

0.7-0.7 0.9-0.7 0.9-0.8 0.7-0.6

2

10

101

100

103 104 Frequency (Hz)

105

Fig.1. Dielectric constant as a function of frequency for various sub-layer thicknesses of nanolaminates showing TiO2 and Al2O3 thickness in nanometer scale respectively.

102

103 104 Frequency (Hz)

105

Fig.2. Dielectric loss as a function of frequency for various sublayer thicknesses of nanolaminates showing TiO2 and Al2O3 thickness in nanometer scale respectively.

Advanced oxide molecular beam epitaxy as synthesis tool for complex dielectrics L. Alff, E. Hildebrandt, and J. Kurian Institute of Materials Science, TU Darmstadt, 64287 Darmstadt, Germany Vapor phase deposition of oxides is an increasingly important field in electronics. The first reason for this is of course the simple fact that for many technological applications oxides in form of thin films are required. The second reason is that vapor phase deposition in itself is a synthesis method sui generis. During thin film deposition, synthesis can be performed far away from thermodynamic equilibrium conditions, allowing for the composition of a huge variety of meta-stable compounds. In this sense, vapor phase deposition of oxides is a formidable tool in the search for new and tailored materials properties.

For complex materials with several different cations, oxide molecular beam epitaxy (MBE) is a less common technique due to the involved advanced technology [1].

However, similar to the success of MBE based tailoring of semiconducting materials for electronic devices it allows the highest level of process control and offers the widest range of available oxide materials. As a last very important point it is to mention that in general vapor phase deposition allows for the synthesis of hetero or hybrid materials. The combination of different materials on an atomic scale creates new hybrid thin film matter with novel functionalities. Even more, at interfaces between different oxides completely new effects occur that currently excite the community in particular in the field of oxide electronics.

As an example of the possibilities offered by MBE, we discuss the growth of controlled oxygen deficient hafnia [2]. We have shown that hafnia can be reduced to such an extent that a defect band forms providing charge carriers leading to conduction corresponding to a resistivity of about 300 µΩcm. Hall measurements have revealed that the charge carriers are hole-type having a density of up to 6 times 1021 cm-3, and mobilities of 2 cm²/(Vs).

Using oxide MBE which is an excellent tool for oxygen engineering, also other dopants can be introduced in combination with oxygen defects. Using magnetic dopants such as Fe or Ni, the possibility to induce ferromagnetism in a semiconductor with tunable charge carrier concentration can be tested. X-ray magnetic dichroism (XMCD) can be used as an unambiguous technique to identify mechanism of magnetic coupling in such a compound. We will discuss first results based on Ni doped oxygen deficient hafnia thin films.

In general, oxygen defect engineering by oxide MBE is a formidable tool to design novel electronic materials.

Figure 1: Set-up of a state-of-the-art oxide MBE. References [1] L. Alff, A. Klein, P. Komissinskiy, and J. Kurian. "Vapor phase deposition of oxides" in Ceramics Science and Technology, Volume 3: Synthesis and Processing, I.-W. Chen and R. Riedel eds., pp. 269-290, Wiley-VCH Verlag GmbH, Weinheim, Germany (2011.)

[2] E. Hildebrandt, J. Kurian, M. M. Muller, T. Schroeder, H. J. Kleebe, and L. Alff, Appl. Phys. Lett. 99 (2011).

Nanoscale and device level electrical behavior of annealed ALD Hf-based gate oxide stacks grown with different precursors A. Bayerl1, M. Lanza1, L. Aguilera1, M. Porti1, M. Nafría1, X. Aymerich1, S. De Gendt2 1

Dept. Eng. Electrònica, Universitat Autònoma de Barcelona, 08193, Bellaterra, Barcelona, Spain.

2 IMEC Kapeldreef 75, B-3001 Leuven, Belgium. albin.bayerl@uab.es

Two of the main factors influencing the electrical properties of Atomic Layer Deposited (ALD) high-k materials are the precursor used during the growing process and their capability to withstand high temperatures during the manufacturing process. In this work, the electrical properties of 2nm HfO2 films grown

by ALD (using different precursors: HfCl4/H2O and TEMAHf-O3, from now on ALD and MOALD samples, respectively) on a 1nm SiO2 interface layer were investigated at the nanoscale (with Conductive Atomic Force Microscope, CAFM) and at the device level. The effect of a post high-k deposition and post metallization (with a TiN/Poly electrode) annealing process (PDA and PMA respectively) at TA=1030ºC was also considered.

Device level tests on 1x1μm2 fully-processed MOS capacitors (Fig. 1) show that, in non-annealed samples (black curves), at low fields (when conduction is controlled by the high-k layer [1]) MOALD structures show a larger conductivity than ALD capacitors. On the other hand, the breakdown voltage (VBD) and the conductivity at high fields (controlled by the SiO2 layer) are similar. These results suggest a worse quality of the high-k layer in MOALD samples (higher leakage currents at low fields), probably related to a larger density of defects when using organic precursors. When an annealing is applied, the PDA ALD sample (red circles in Fig.1) shows the typical post-breakdown (BD) behavior.

On the contrary, the PDA seems to have no remarkable effects on the conductivity of the MOALD sample (red diamonds in Fig.1). PMA ALD and MOALD samples show the largest VBD compared to those without annealing (inset in Figure 1). Moreover, the PMA samples also show the smallest conduction at high fields (Fig.1).

The current images obtained with CAFM (Fig. 2) after the gate electrode removal at VG, minimum gate voltage needed to measure current above the noise level (high

field region in Fig. 1) further support this analysis. In particular they show: i) the conductivity of the nonannealed ALD and MOALD samples is similar; ii) PDA ALD sample shows the largest conduction; iii) PMA ALD and MOALD samples have the smallest electrical conduction, demonstrating a clear link between the nanoscale and device level properties. The nanoscale conduction homogeneity of the gate oxide stack was also studied from nanoscale IV curves (not shown). The dispersion of VTH (voltage at 5pA) obtained on the different samples is shown in Fig. 2 (table). PDA samples show the largest dispersion of VTH (especially the ALD one), i.e., their conduction is more inhomogeneous.

However, no remarkable differences are observed between non-annealed and PMA samples, independently of the precursor. Finally, topographic maps of the PDA ALD sample (Fig.2) show some voids that can be the origin of the post-BD behavior observed at device level.

In the PMA samples, smoother surfaces are observed, which could explain, among other factors, the reduction of leakage current and the increase of VBD observed in those samples (ALD and MOALD). Therefore, the annealing seems to have beneficial effects only when it is carried out after the gate electrode deposition.

This study was supported by the European Union (APROTHIN), Spanish MICINN (TEC2007-61294/MIC, TEC2010/16126) and the Generalitat de Catalunya (2009SGR-783).

[1] L.Aguilera, M.Porti, M.Nafría and X.Aymerich, Elec.

Dev. Lett. 27(3), pp. 157, 2006.

1E-6

High fields Analysis of the homogeneity from nanoscale IV curves Precursor

1E-9

ALD PDA ALD PMA ALD MOALD PDA MOALD PMA MOALD

1E-12

1E-15

0

1

2

3

cumulative failure ln(-ln(1-F))

Current (A)

1E-3 Low fields

1

MOALD non-annealed (VBD63%=3.75V)

0

ALD

MOALD

Annealing

Non annealed

PDA

PMA

Non annealed

PDA

PMA

Deviation VTH (V)

0.13

0.90

0.10

0.21

0.39

0.15

-1 -2

MOALD ann-after (VBD63%=5.25V)

-3

3,5

4,0

4,5

5,0

5,5

VBD [V]

4

5

6

7

8

Voltage (V) Fig.1. Typical I-V curves obtained in MOS structures with different grown dielectrics. The inset shows the cumulative failure Weibull distribution of some of the samples.

Fig.2. Current and topographic CAFM maps for all the samples.

Table. Dispersion of VTH (voltage at 5pA) obtained from I-V curves.

HfLaOx Film Deposited on GaAs Substrate by Plasma Enhanced Atomic Layer Deposition (PEALD) Tingting Jia, Xinhong Cheng, Duo Chao, Dawei Xu, Zhongjian Wang, Chao Xia, Youwei Zhang, Yuehui Yu State Key Laboratory of Functional Materials for Informatics , Shanghai Institute of Micro-system & Information Technology, Chinese Academy of Sciences, Changning Road 865, Shanghai 200050, People’s Republic of China Corresponding author e-mail: xh_cheng@mail.sim.ac.cn With the development of CMOS technology and continuous scale of key feature size, alternate channel materials with high carrier mobility and gate dielectric films with high permittivity (high-k) are emerging and studying. III-V compound semiconductor substrates with high-k gate dielectrics will achieve high performance. [1] HfLaOx films have less Fermi-energy pinning than HfO2 in MOSFETs[2], the k value is beyond 20, and are amorphous when annealing at high temperature of 900℃ [3] . Moreover, HfLaOx has already been studied as gate dielectric on Si and grapheme, but there’s a little reports on GaAs. [4] The plasma enhanced atomic layer deposition (PEALD) method is expected to increase the activation of precursors, reduce thermal budget, purify chemical composition, widen the process window, and achieve compact films. Therefore, in this paper, we deposited HfLaOx film on GaAs as potential high-k gate dielectric candidate for MOS device application by low-temperature PEALD. HfO2 film was also deposited for comparison.

Prior to film deposition, in situ NH3-plasma cleaning process was performed in order to eliminate the native oxides and arsenic element at GaAs surface. Following, HfLaOx gate oxide film was deposited at 200°C using Tetrakis(ethylmethylamino) hafnium [(CH3)(C2H5)N]4Hf (TEMAH) and Tris(bis[trimethylsilyl]amido) lanthanum (La[N(TMS)2]3) as a hafnium precursor and lanthanum precursor, oxygen plasma as an oxygen reactant.

The x-ray photoelectron spectroscopy (XPS) results show a significant reduction of Ga oxide component, however, the peaks from As oxide are still detected.

Cross-sectional transmission electron microscopy (TEM) images show the interfacial structure of HfLaOx/GaAs and HfO2/GaAs gate stack after postdeposition annealing (PDA) at 700 °C in N2 (Fig.1). The HfLaOx film stays amorphous, but HfO2 is fully crystallized. The interfacial

layer between HfLaOx film and GaAs is thinner than that between HfO2 film and GaAs. It reveals that the Hf and La binary oxide increases the crystalline temperature and suppresses the formation of interfacial layer. High frequency capacitance-voltage (C-V) curves measured at 1.5 MHz of Pt/HfLaOx/n-GaAs MOS capacitors shows an equivalent oxide thickness (EOT) of about 0.5 nm and a hysteresis of 73mV. A small leakage current density of 0.02 mA/cm2 is measured at∣Vg-Vfb∣=1V. (Fig.2) In summary, deposition of HfLaOx by PEALD exhibits a small EOT due to the thin interfacial layer with a bigger dielectric constant k. The low leakage current property means that an HfLaOx film is useful in improving the electrical property of the high-k gate dielectrics. Thus, it is concluded that HfLaOX will be a dielectric material system for amorphous high-k gate insulator in further advanced complementary metal oxide semiconductor.

This work was supported by the surface of the National Natural Science Foundation of China. Research Grant Nos. 11175229.

References [1] Matthias Passlack, IEEE Transactions On Electron Devices 57 (11) (2010).

[2] H. Y. Yu X. P. Wang, M.-F. Li, C. X. Zhu, S. Biesemans, A. Chin, Y. Y. Sun, Y. P. Feng, A. Lim, Y.-C. Yeo, W. Y. Loh, G. Q. Lo, and D.-L. Kwong, IEEE Electron Device Lett. 28 (4) (2007)258.

[3] Y. Yamamoto, K. Kita, K. Kyuno, and A. Toriumi, Applied Physics Letters, 89 (3) (2006) 032903.

[4] Joong Gun Oh, Yunsang Shin, Woo Cheol Shin, Onejae Sul, and Byung Jin Cho, Applied Physics Letters, 99 (19) (2011) 193503.

8x103

6x103 5x103 3

102 101

J (mA/cm2)

(b) Capacitance (nF/cm2)

(a)

7x103

100 10-1 10-2 10-3 10-4 -1.0

4x10

-0.5

0.0

0.5

1.0

1.5 MHz

Voltage (V)

3x103

EOT=0.5nm

2x103

Hysteresis: 73mV

3

1x10

0 0

1

2

3

Gate voltage (V)

Fig.1. Cross-sectional TEM images of HfLaOx film (a) and HfO2 film (b) on GaAs deposited by PEALD after PDA at 700 °C.

Fig.2. Capacitance-voltage (C-V) curves of Pt/HfLaOx /nGaAs MOS capacitor measured at 1.5MHz. The inset in the upper left shows the electrical leakage current densityvoltage (J-V) curve for the MOS capacitor.

Studies of H2O-based atomic layer deposited Al2O3 dielectric on graphene * 1

You-Wei Zhang 1, 2, Xin-Hong Cheng 1, Li Wan 2, Zhong-Jian Wang 1, Ting-Ting Jia1, Da-Wei Xu ,Chao Xia 1, Duo Cao 1,Yue-Hui Yu 1

1.State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem & Information Technology, Chinese Academy of Sciences,Changning Road 865, Shanghai 200050, China 2. Wenzhou University, Wenzhou 325000, China *Corresponding author: xh_cheng@mail.sim.ac.cn Graphene, which is a new carbon crystal with a twodimensional honeycomb lattice, has captured extensive concerns throughout the world due to its high electronic mobility and other unique transport and physical properties. Graphene is currently counted as one of the most promising materials that could allow the Moore's law to be tracked for several more years after the silicon road map ends. Acknowledgment can be placed between the abstract main text and references as a separate paragraph.

To fabricate a high-performance graphene-based field effect transistor, it is necessary to prepare a high-quality high-k gate dielectric on graphene surface. Atomic layer deposition (ALD) is a promising technique used for growing high-κ gate dielectric layers, because it offers distinct advantages of excellent thickness control and good uniformity [1]. But it is difficult to deposit uniform high-κ gate dielectric layers on graphene with normal H2O-based ALD processes, due to the hydrophobic nature of graphene basal plane and the lack of nucleation sites in the perfect graphene plane [2]. Lee group[3] reported that Al2O3 film could be uniform grown on graphene by ALD deposition with TMA/ O3 after ozone pretreatment, but ozone pretreatment would be likely to degrade the performance of graphene devices. How to deposit an atomically uniform gate dielectric on graphene and avoid damage to the graphene, is still a challenge.

The growth temperature is an very important parameter for ALD processes, but a systemic research for influence of deposition temperature on depositing high-κ dielectric on graphene using H2O -based ALD process is

absent. In this letter, Al2O3 dielectric films were deposited directly onto graphene at different growing temperature by ALD with H2O as oxidant.

The atomic force microscopy (AFM) was used to analyze the surface morphology of Al2O3 films deposited on graphene flakes at different temperature. According to AFM results, we found that the growing temperature in the H2O-based ALD process had significant impact on the initial nucleation and the growth of Al2O3 films. The main cause for this phenomenon is that the distribution of physically adsorbed H2O molecules on the surface of graphene decided the morphology of Al2O3 film. When the growth temperature is around 100°C~130°C, a uniform coverage Al2O3 film is successfully deposited on graphene as can be seen in Fig. 1.

In order to investigate the effect of ALD process on graphene, Micro-Raman spectra were collected from same site of a single layer graphene before and after the deposition of metal oxides. As shown in Fig. 2, no considerable change of the D band, 2D band and G band can be observed, indicating that metal-oxides deposition process used in this study does not introduce detectable defects into graphene lattice.

References [1] Anand, D., Ronald, I., Gregory, J., and Christos, T.: J. Appl. Phys. 99 (2006) 094102.

[2] Adam, P., Robert, W., and Luigi, C.,: Appl. Phys. Lett.

95(2009) 133106.

[3] Lee ,B., Park, S., Kim H., Cho, K., Vogel, E., Kim, M., Wallace ,R., and Kim ,J.: Appl. Phys. Lett. 92(2008) 203102.

ntensity(arb.units)

2D

G

(b)

D

(a) 1400

1600

2600

2800 1

Fig.1. AFM images of Al2O3 films deposited on graphene flakes at 120 ℃.

Fig.2. Raman spectra of a mechanically exfoliated graphene flake (a) as-cleaved, (b) after deposition of Al2O3.

Charge Capture in Nanocomposite SiO2(Si) Films obtained by Ion-Plasma Sputtering A. Evtukh, O. Bratus’, V. Ievtukh V. Lashkaryov Institute of Semiconductor Physics corresponding author e-mail: evtukh@rambler.ru The properties of MIS structures with silicon nanocrystals in a dielectric matrix are under intensive investigation for creation on there basis of electronic and optoelectronic devices such as light emitting diodes, single-electron transistors and nonvolatile memory. The silicon enriched films of SiOx at high temperature annealing transform into nanocomposite SiO2(Si) films containing Si nanocrystals in silicon dioxide matrix.

Nowadays the nonvolatile nanocrystal memory is promising approach for creation of new generation memory with enhanced parameters. As the storage medium in such devices can be nanoscale semiconductor or metal clusters. In this work the results of investigation of the electrical properties of layered structures with silicon nanoinclusions, their relationship to the structure of nanocomposite SiO2(Si) films and dependence on technological conditions at deposition by ion-plasma sputtering technique for use as a medium for the accumulation of charge in the elements of nonvolatile nanocrystal memory are presented.

Ion-plasma sputtering technology for deposition of silicon enriched silicon oxide SiOx films has been developed. The process of sputtering includes the heating of cathode and emission of electrons in the cathode space, which at moving towards the anode ionize the working gas atoms forming plasma. The target is under the negative potential (1-3 kV) in relation to the anode. There is the occurrence of an abnormal glow discharge and intense bombardment of silicon target by positive ions of the plasma. The target atoms fly to the substrate and deposited on it. At obtaining the silicon oxides the oxygen adds into the deposition chamber. The silicon target atoms oxidize in there path to the substrate and deposit on the

1200

1 st - Virgin 2 st +5V for 50s 3 st -8V for 50s

1,0

1000

1

0,8

3

0,6

T1=900 oC

800

2

C,pF

C/C0

substrate in the form of oxide.

The effect of the accumulation of electric charge in the nanocomposite SiO2(Si) films obtained by ion-plasma sputtering with using C-V characteristics of MIS structures has been observed (Fig. 1). The amount of storage charge increases with the amplitude and length of the pulse voltage. The sign of captured charge depends on the polarity of applied to the gate voltage supplied – at positive voltage negative charge is captured and vice versa. The negative differential capacitance of C - V characteristics of MIS structures with nanocomposite SiO2(Si) film as an insulator in the condition of majority charge accumulation on the silicon surface has been revealed. The negative differential capacitance depends on the charge state of the nanocrystals. In case of fully charged nanocrystals in MIS structure the negative differential capacitance hasn’t observed. The kinetics of negative differential capacitance formation at transformation of silicon enriched SiOx film into nanocomposite SiO2(Si) film during high temperature annealing has been obtained (Fig.2). The negative differential capacitance value increases with growth of annealing temperature.

The physical model of negative differential capacitance in MIS structures with nanocomposite SiO2(Si) film as the dielectric has been proposed. The model is based on parallel connection of capacity of the nanocrystals and the capacity of insulator. The nanocrystals capacity depends on the charge state of nanocrystals, their size and concentration.

Acknowledgment. The research described in this publication was in part supported by the projects 1.1.7.30/9 and 53/85/11-H from National Academy of Sciences of Ukraine.

0,4

600

T2=1000 oC

400

T3=1100 oC

0,2

200 0,0

-6

-4

-2

0

U, В

2

4

6

0 -2 -1 0 1 2 3 4 5 6 7 8 9 10

U,V Fig. 1. Typical C-V curves of the MIS structure with Si nanocrystals in insulators.

Fig. 2. Influence of temperature at nanocrystal formation on shape of C-V curves.

Optimization of Gadolinium Oxide Growth Deposited by High Pressure Sputtering through Scavenging Techniques P.C. Feijoo1, M.A. Pampillón1, E. San Andrés1 1 – Dpto. Física Aplicada III: Electricidad y Electrónica. Fac. de CC. Físicas. Universidad Complutense de Madrid corresponding author e-mail: pedronska@fis.ucm.es Gadolinium oxide has been widely proposed as an interesting high-permittivity dielectric for applications in flash memory devices and CMOS transistors [1-2]. It has a permittivity (κ) value around 14, a band gap of around 5.3 eV, and very good thermal stability with Si [2-3], which make it suitable for these applications. In this work, gadolinium oxide was deposited on Si by means of high pressure sputtering (HPS) [4] and the influence of the choice of metal electrode is studied.

The stacked structures were fabricated on single side polished n-Si (100) wafers, with a resistivity of 1.5 5.0 Ω cm. Before high-κ deposition, substrates were cleaned using a standard RCA clean and submerged in a diluted HF solution (1:50) to remove all SiO2 from the surface. GdOx was deposited by HPS from a high purity Gd2O3 target in a pure Ar atmosphere. Several values of pressure and rf power were studied: Pressure ranged from 0.25 to 1.3 mbar and the power from 30 to 50 W. For electrical characterization, 100 nm of Ti or 16 nm of Pt were e-beam evaporated, followed by 200 nm of Al, used as a capping layer. Squares of different sizes ranging from 50×50 to 630×630 µm2 were defined by a lift-off procedure. Then, a 300 nm thick Al layer was evaporated on the backside to obtain the substrate ohmic contact.

After fabrication, samples were annealed in forming gas (FGA process) during 20 min at 450 °C. Samples were structurally and electrically characterized. Physical properties of the films were studied through transmission Electron Microscopy and Fourier Transform Infrared Spectroscopy, among other techniques. C-V and G-V curves were measured by an Agilent 4294A. Density of interfacial defects Dit was estimated by the conductance method.

Figure 1 shows a C-V curve of a representative

2

References [1] Gupta J.A., Landheer D., McCaffrey J.P. and Sproule G.I.: Appl. Phys. Lett. 78 (2001) 1718.

[2] Dueñas S., Castán H., García H., Gómez A., Bailón L., Kukli K., Hatanpää T., Lu J., Ritala M., and Leskelä M.: J. of the Electrochem. Soc. 154 (2007) G207.

[3] Kwo J., Hong M., Kortan A.R., Queeney K.T., Chabal Y.J., Mannaerts J.P., Boone T., Krajewski J.J., Sergent A.M. and Rosamilia J.M.: Appl. Phys. Lett. 77 (2000) 130.

[4] Feijoo P.C., del Prado Á., Toledano-Luque M., San Andrés E. and Lucía M.L.: J. Appl. Phys. 107 (2010) 084505.

(a) Pt gate Before FGA After FGA

12

10

Ti gate Pt gate

-2

2 0 20 (b) Ti Gate 16 Before FGA 12 After FGA 8 4 0 -1.5 -1.0 -0.5

100 kHz

-1

Capacitance (fF / µm )

4

This work was possible thanks to the FPU grant AP2007-01157 and the research projects TEC2010-18051 (Spanish Ministerio de Ciencia e Innovación) and GR58/08 (Universidad Complutense de Madrid).

Dit (eV cm )

6

samples (1.3 mbar, 40 W) before and after the FGA process. In Fig. 1 (a), it can be observed that the annealing does not modify significantly the curve when the top metal is Pt. However, as it can be seen in Fig. 1 (b), the capacitance in accumulation increases strongly. This means that the Ti gate is scavenging the interface during the FGA. The equivalent oxide thickness (EOT) of the stack dramatically decreases from 6.2 to 2.3 nm.

The dependence of the Dit is studied in function of the deposition pressure. The results can be observed in Fig. 2.

The most important conclusion that can be extracted is that higher deposition pressures give rise to interfaces of better quality.

This work deals with structural and electrical characterization of metal/GdOx/Si stacks grown by HPS for different conditions of pressure and rf power and the study of the influence of the choice of the top electrode metal, comparing Pt and Ti.

0.0

0.5

100 kHz 1.0 1.5

Gate voltage (V)

Fig.1. C-V characteristics at 100 kHz for samples with Pt gate (a), and Ti gate (b), before and after the FGA at 450ºC.

11

10

10

10

0.5

0.7 0.9 1.1 1.3 Deposition pressure (mbar)

Fig.2. Density of interfacial defects Dit in function of the deposition pressure estimated by the conductance method.

Influence of growth and annealing temperatures on the electrical properties of Nb2O5 based MIM capacitors.

H. Garcia1, H. Castan1, E. Perez1, S. Dueñas1, L. Bailon1, T. Blanquart2, J. Niinistö2, K. Kukli2, M. Ritala2 and M. Leskelä2 1 - Department of Electronics, University of Valladolid, E.T.S.I. Telecomunicación, 47011 Valladolid, Spain.

2 – Department of Chemistry, University of Helsinki, P. O. Box 55,FI-00014 Univ. Helsinki, Finland. corresponding author e-mail: hecgar@ele.uva.es The aggressive downscaling of DRAM cells can result in large leakage currents and poor voltage linearity, so the use of high-k dielectrics in MIM capacitors is mandatory in order to achieve the necessary packing density [1].

Al2O3, ZrO2 and HfO2 high-k materials have received the main attention. However, materials with very high permittivity are of interest for DRAM capacitors, where very low EOT values are mandatory. This led to the study of SrTiO3, (Ba,Sr)TiO3 or TiO2 doped with Al [2]. In the case of SrTiO3 films, the dielectric properties are sensitive to the stoichiometry. The latter is difficult to control accurately. On the other hand, Nb2O5 and Ta2O5 can also be considered as alternatives due to their possibly higher k values in the crystalline phase (up to 200).

Atomic layer deposition (ALD) appears to be a promising technique to grow the dielectric layers as it can fulfil the requirements for growing very thin and conformal layers for the very high aspect ratio capacitors used in DRAM memories. Unfortunately, few successful Nb2O5 processes have been reported.

In this work, we present an electrical study of niobium oxide based MIM capacitors for memory applications.

Nb2O5 layers were grown by atomic layer deposition using a novel precursor chemistry: tBuN=Nb(NEt2)3 (tertbutylimido)tris(diethylamido)niobium) was used as niobium precursor and ozone (O3) was used as the oxygen precursor [3]. Different deposition temperatures were used (250, 275 and 300 ºC). After dielectric deposition, a thermal annealing was performed in an N2 atmosphere during 20 minutes. Niobium oxide layers were deposited on TiN, and after thermal annealing Al top electrodes were evaporated.

Different Al/Nb2O5/TiN/Si/Al capacitors were measured. Thicknesses of Nb2O5 films ranged from 25 to 40 nm, measured by means of X-ray reflectivity (XRR).

Figure 1 shows C-f measurements (no bias applied) for samples deposited at 300 ºC. Capacitance density increases when increasing annealing temperature. Film thicknesses are about 31.4 nm for all the samples. This led to a k value of about 26 for the as-deposited capacitor and a value of 50 for the annealed capacitors. When annealing the capacitors, dielectric films may change the crystalline structure, increasing the permittivity value.

The change of crystalline structure when annealing the films can also improve the leakage current, as we can see in figure 2, where current-voltage characteristics are shown for samples grown at 300 ºC. The deposition of Nb2O5 films (not annealed), could result in polycrystalline or nanocrystalline material, with high leakage currents due to grain boundaries.

The conduction mechanisms in niobium oxide films have also been studied by measuring the leakage current at several temperatures, from the liquid nitrogen temperature (77 K) to room temperature.

References [1] D.Roy, et al., Appl. Phys. Lett.. 62,1056 (1993).

[2] J.A. Kittl, et al., Microel. Eng. 86, 1789 (2009).

[3] T. Blanquart et al., Chem.Mater. Accepted (2012).

10-2 10-3

2.0x10-6

10-4

1.8x10-6

10-5

-6

1.6x10

I (A)

C (F/cm2)

1.4x10

-6

500 ºC annealed

1.0x10-6

as-deposited

10-6

650 ºC annealed

-6

1.2x10

500 ºC annealed

10-7 10-8

650 ºC annealed

-9

10

8.0x10-7

10-10

6.0x10-7

10-11

as-deposited

4.0x10-7

10-12 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8

2.0x10-7 1k

10k

100k

1M

Vtop (V)

f (Hz) Fig.1. C-f measurements for samples deposited at 300 ºC

Fig.2. Current - voltage measurements for samples deposited at 300 ºC

Interface quality of Sc2O3 and Gd2O3 films based MIS structures using Al, Pt, and Ti gates: effect of buffer layers and scavenging electrodes.

A. Gómez1, H. García1, H. Castán1, S. Dueñas1, L. Bailón1, M.A. Pampillón2, P.C. Feijoo2, and E. San Andrés2 1 – Departamento de Electricidad y Electrónica, E.T.S.I. Telecomunicación, Universidad de Valladolid, 47011 Valladolid, Spain.

2 – Departamento de Física Aplicada III (Electricidad y Electrónica), Facultad de Ciencias Físicas, Universidad Complutense de Madrid E-28040, Spain.

Corresponding author e-mail: alfgom@ele.uva.es Nowadays, an exhaustive research about requirements and development of high permittivity (high-k) dielectrics for future CMOS technologies and memory applications is required to replace silicon oxide. Specifically, rareearth scandate films (REScO3) stand out for mentioned task [1,2]. As first step towards the use of these rare-earth materials we have studied the electrical properties of metal-insulator-silicon (MIS) structures based on scandium and gadolinium oxides deposited by high pressure reactive sputtering (HPRS) because of good properties of GdScO3 [2].

On the other hand, most of high-k materials in direct contact with Si generate a non-controlled interlayer that decreases the permittivity value. To avoid this undesirable behaviour, a SiO2 or SiNx low-k layer is deliberately deposited between silicon and insulator. Among other things, interface scavengers are used to reduce interlayer thickness after dielectric film deposition, so that, in this work, three different gate electrodes (Al, Pt and Ti) were used to check this interface scavenging [3].

The substrates used were n-type Si (100) and resistivity 1.5–5 Ω·cm. Sc2O3 and Gd2O3 thin films were obtained by sputtering metallic Sc and Gd targets by HPS in a pure Ar plasma, and were subsequently oxidized in a mixed Ar/O2 atmosphere. Square-shaped MIS structures were obtained by a standard process of photolithography.

The three different electrodes were e-beam evaporated and lifted-off. Then, samples were annealed in forming gas atmosphere at 300ºC during 20 min. Finally, the electrical measurements were carried out on gate

350

samples.

Gate metal/(Sc-or-Gd)2O3/SiOx/n-Si/Ti/Al metals used were Al, Al/Pt and Al/Ti. 1 MHz C-V curves of Sc2O3-based MIS structures with three different electrodes are shown in Fig. 1. As expected, the samples with Ti electrode have highest capacitance values because of Ti is an oxygen scavenger [3]. Therefore, SiOx interlayer thickness has been reduced, however, this induces a worse interface quality, as indicates the DLTS technique (not shown here).

Fig. 2 shows flat-band voltage transients recorded by keeping constant the capacitance at flat-band condition at several temperatures corresponding to the Sc2O3-based sample with Al electrode. Flat-band voltage transient measurements at different temperatures provide valuable information about assisted tunnelling mechanisms [4] and the activation energy of soft optical phonons that produces the ionization of traps existing in the band gap of the insulator was estimated by means of an Arrhenius plot (see Fig. 2 inset).

Analysis of these results and additional measurements of electrical characterization (DLTS, conductance transient, and I-V) will be reported at the conference.

References [1] [2] [3] [4]

H. Gang, et al., Prog. Mater Sci. 56, 475 (2011).

J.A. Kittl, et al., Mic. Eng. 86, 1789 (2009).

H. Kim, et al., J. Appl. Phys. 96 (2004).

S. Dueñas et al., J. Electrochem. Soc. 154, G207 (2007).

0.20

Ti electrode

300 Al electrode

200 150 100

-1

0.10 ln(VFB-VFBinitial)

VFB-VFBinitial (V)

C (nF·cm-2)

250

275 K 0.15

0.05

50 Pt electrode

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

VG (V) Fig.1. C-V curves at 295K for all Sc2O3-based samples.

-3

150 K 0

250

500

EA = 83.2 meV

-4 -5

0.00

0

-2

3

750

4

5

1000/T (K -1)

1000

6

7

1250

Time (s) Fig.2. Flat-band transients measured at several temperatures corresponding to the Sc2O3-based sample with Al electrode.

Abnormal degradation of thin oxide layers by C-AFM electrical measurement A.Grandfond, B.Gautier, L.Militaru, D.Albertini, A. Descamps-Mandine Lyon Institute of Nanotechnologies, University of Lyon, UMR CNRS 5270, 7 Avenue Jean Capelle, 69621 Villeurbanne, France antonin.grandfond@insa-lyon.fr A Dimension 3100 from Bruker (Veeco) was used together with so-called tunneling-AFM (TUNA) mode.

36 voltage ramps were applied on a 36 points matrix.

Ramps reange from 0 V to -10 V applied on the sample at a speed of 0,5 V/S. After AFM imaging (fig.1), oxide layers was eliminated with HF (5%). As it is possible that different mechanisms take place at the same time [5]. The impact of stress level has been adjusted (by application or not of a current limit at 100pA). The impact type of doping was evaluated too.

In all cases, it was found that holes are created on the substrate (fig. 2). .It suggests, contrary on other works [5], the apparition of hillocks may be due to substrate oxidation rather than electro-thermal effect. Nevertheless, a constant ratio between hillocks height and holes depth wasn't found (fig.3).

As a conclusion, hillocks are lead to a degradation of substrate, maybe due to oxidation, but the full mechanism has still to be described.

References [1] M.Porti and al., Electrical characterization of stressed and broken down SiO2 films at a nanometer scale using a conductive atomic force microscope, J. Appl. Phys., vol 91, vol.

4, p.2071 (2002) [2] M.Porti and al., Atomic force microscope topographical artifacts after the dielectric breakdown of SiO2 films , Surface Science, vol.532, p.727-731 (2003) [3] L.Zang and al., Structural and electrical evolution of gate dielectric breakdown observed by conductive atomic force microscopy, Applied Physics Letters, vol 88, n°3, p.032906 (2006) [4] W.Polspoel and al., Physical Degradation of gate dielectrics induced by local electrical stress using conductive atomic force microscopy, Journal of Applied Physics, vol. 106, n°2, p.024101,2009 [5]W.Hourani and al, Study of the Physical and electrical degradation of thin oxide films by atomic force microscopy, J. Vac. Sci. Technol. B, vol. 29, n°1, (2011)

depth of holes (nm)

The miniaturization of microelectronic devices creates news technological problems. Particularly, leakage currents appears through the gate oxide thin films in MOS structures. A better understanding of these oxide breakdown mechanisms requires techniques of electrical characterization with a nanometric spacial resolution.

Some of these techniques are based on Atomic Force Microscopy as C-AFM (Conductive-AFM) witch makes it possible to obtain I-V measurements on a nanometric surface. C-AFM is a contact mode which uses a conductive tip. A polarization is applied on the AFM tip or on the sample. It is possible to obtain an current map at the same time as the topographical image and very local intensity-voltage characteristics.

Application of a negative polarization on the AFM tip or positive polarization on the sample electrode leads to the oxidation of this oxide (SiO2 or high-k)/silicon interface. So, a hillock appears. On air, there is a water layer on the sample allowing OH- anions to be injected through the thin oxide layer to the interface during the application of voltage.

Application of a positive voltage on the tip (negative on the substrate) can't lead to the injection of anions, nonetheless, hillocks on the oxide surface are observed too[1]. Three explication have been proposed.

1-Hillocks on AFM topographical images are only artefacts due to the interaction between the conductive tip and negatives charges injected during the oxide stress [2].

2-An inflation of the silicon substrate leads to the hillock's apparition. This inflation is caused by an electrothermal effect due to an important power dissipation[3].

3-Cathodic oxidation is a third explanation. The Si substrate is oxidized on surface, although OH- anions can't be injected [4].

In this work, we address this question, focusing especially on the two last explanations. Oxidation mechanism leads to the creation of holes on the substrate surface whereas electro-thermal effect leads to the creation of hillocks. Therefore, we have eliminated the oxide layer with hydrofluoric acid after electrical stress to observe the substrate's topography by AFM .

5 4 3 2 1 0

Fig. 1: Contact AFM image (8X8µm) of stressed area

Fig. 2: Semi-contact AFM image (8X8µm) of substrate

0

2

4 6 8 height of hillocks (nm)

10

Fig. 3: Holes depth vs. hillocks height

12

Effect of Doping on Charge Trapping in Silicon Nitride Maria E. Grillo*, Simon D. Elliott Tyndall National Institute, University College Cork, Lee Maltings, Cork, Ireland The use of a SiO2 sealing layer improves the charge retention in TAONOS (Al2O3/SiO2/Si3N4/SiO2/Si) memory cells. 1 Here we report how a first-principles defect formation energy approach can be used to understand this observation.

The calculations reveal that oxygen donors substituted into lattice nitrogen sites of β-Si3N4 compensate unoccupied levels originating mainly from native silicon-rich defects 2. The resulting decrease in density of traps, and shift of trap-energies are consistent with the observed trap density spectra and with electrical data from retention simulations 3 for TANOS cells (Al2O3/Si3N4/SiO2/Si) featuring silicon oxynitride (SiON) films as compared to stoichiometric SiN films. According to our formation energies, Al doping of β-Si3N4 might have a lower impact on charge retention compared to oxygen. Nonetheless, aluminium would also reduce charge trapping of native Si-rich defects through the charge transition Al-1 --> Al0 at about

1 eV below the conduction band of silicon

nitride.

* Current address: Lauterer str. 17ª, D-81545 Munich, Germany GOSSAMER project, http://www.fp7-gossamer.eu/, (2010).

2 M. E. Grillo, S. D. Elliott, and C. Freysoldt, Phys. Rev B 83, 85208 (2011).

3 A. Suhane, A. Arreghini, R. Degraeve, G. Van den bosch, L. Breuil, M. B. Zahid, M. Jurczak, K. De Meyer, and J. Van Houdt, IEEE Electron Device Lett. 31, 77 (2010).

1

1

Oxygen vacancy induced p-type conductivity in HfO2-x thin films grown by Reactive Molecular Beam Epitaxy E. Hildebrandt1, J. Kurian1, M. M. Müller1, H.-J. Kleebe1, T. Schroeder2, and L. Alff1 1 – Institute of Materials Science, TU Darmstadt, 64287 Darmstadt, Germany 2 – IHP, 15236 Frankfurt / Oder, Germany corresponding author e-mail: emh@oxide.tu-darmstadt.de Hafnium oxide has proven to be among the best candidates to replace SiO2 as a gate dielectric in state-ofthe-art microelectronics. Besides extensive research activities related to complementary metal oxide semiconductor (CMOS) integration, possible applications for hafnium oxide thin films in resistive random access memory (RRAM) or spintronics have opened up new research directions. The physical properties; dielectric permittivity, resistance switching as a function of applied voltage, and room temperature ferromagnetism, on which the mentioned applications are based on, are all more or less related to the concentration of oxygen vacancies. In this study, reactive molecular beam epitaxy (RMBE) has been applied to vary and control the concentration of oxygen vacancies in HfO2-x thin films revealing unexpected results for optical and electrical properties.

Hafnium oxide thin films have been grown on c-cut sapphire substrates from Hf metal (99.9% purity, MaTecK) evaporated using e-gun, and rf-activated oxygen (99.995% purity) supplied from an oxygen radical source. Film thicknesses ranged from a view nm up to 200 nm, oxygen content was varied in situ by controlling oxidation conditions during growth.

All films stabilised in the most stable monoclininc structure known for Hafnia, regardless of oxygen content.

Stoichiometric HfO2 thin films do lead to highly textured (-111)-oriented films, whereas film orientation could be switched as a function of oxidation conditions [1].

Oxygen deficient HfO2-x thin films appeared darker in comparison with the transparent stoichiometric films, the lower the oxidation conditions, the darker the resulting films (see inset of Fig. 1). Optical characterisations reveal

a decrease in optical band gap as a function of oxidation conditions and the formation of a defect band in the vicinity of the conduction band [2]. Electrical measurements reveal resistivities of oxygen deficient HfO2-x in the range of 300 µΩcm for highly reduced samples, more than 14 orders of magnitude lower than obtained for stoichiometric HfO2 (see Fig. 1). For resistivities below 1,000 µΩcm, metallic ρ-T behaviour is obtained. Hall measurements identifiy holes as charge carriers with charge carrier densities as high as 6 times 1021 cm-3, and mobilities of 2 cm²/(Vs). Presumably the low mobility is owing to the high charge carrier concentration. Conductivity moderated by crystalline and amorphous metal Hf distributed in an HfO2 matrix could be ruled out by high resolution transmission electron microscopy (HRTEM), see Fig. 2.

R-MBE has proven to be a versatile tool to in situ control oxygen vacancies in metal oxides and thus controlling a variety of physical film properties, such as film structure, optical band gap, and resistivity. R-MBE at first allows engineering of oxide materials by oxygen vacancy control as demonstrated for Hafnia.

We acknowledge Mrs Gabi Haindl for professional photography.

References [1] E. Hildebrandt, J. Kurian, J. Zimmermann, A. Fleissner, H. von Seggern, and L. Alff, J. Vac. Sci. Technol. B 27, 325 (2009).

[2] E. Hildebrandt, J. Kurian, M. M. Muller, T. Schroeder, H. J. Kleebe, and L. Alff, Appl. Phys. Lett. 99 (2011).

106

ρ (µΩcm)

105

104

low ρ vs. T variation

103 metallic behaviour 102

0.2

0.4 0.6 oxygen flow rate (sccm)

0.8

1.0

Fig.1. ρ vs. T as a function of oxidation conditions. Films with resisitivities below 1000 µΩcm show metallic behaviour. Inset shows film appearance as a function of oxygen flow rate.

Fig.2. HRTEM picture of an HfO2-x thin film confirming (i) the textured nature of HfO2-x and (ii) the formation of HfO2-x in contrast to metal Hf.

Charge relaxation and charge retention in single- and double-layer nanocrystal MOS non-volatile memory cells using capacitance measurements V. Ievtukh1*, A. Nazarov1, V. Turchanikov1, V. Lysenko1 and A. Nassiopoulou2 1 - V.E. Lashkaryov Institute of Semiconductor Physics NAS Ukraine, Pr. Nauki 41, 03028 Kyiv, Ukraine 2 - IMEL, NCSR ‘‘Demokritos’’, P.O. Box 60228, 15310 Ag. Paraskevi, Athens, Greece Valerii Ievtukh – e-mail: proghammer@email.ua This paper is devoted to the thorough investigation of a single- and double-layer Si nanocrystal MOS memory structure using the electrical capacitive method. The nanocrystal memory (NCM) shows significant advantages compared to the conventional floating-gate (FG) memory structure of the so called “Flash” non-volatile memory (NVM). The main advantage is the distributed charge storage in NCMs that permit a more aggressive scaling down of the MOS dielectric and consequently a decrease in programming voltages. The size of the nanocrystals (NCs) is an important parameter in NCMs, since NCs of a size of few nm show quantum effects that affect the NCM operation. The investigation of such fundamental effects and the revelation of their role in NCM operation make the development of state-of-the art investigation methods very demanding.

In this work we further extent the use of capacitance measurements to the investigation of metal-oxide-silicon (MOS) nanocrystal memory cells by applying monotonically changing successive pulses for charging the memory cell. Conventionally, the high frequency (1MHz ) C-V characteristics at flat-band conditions (Vfb) of the MOS structure are measured after applying a programming voltage pulse of a given amplitude and duration. The charge heterogeneities generation in the dielectric layer of the MOS structure are extracted from the derivative of the measured capacitance as a function of the applied voltage (dC/dV). For further understanding the NCM operation physics, in this work we performed the following measurements: First, the memory window formation included the application of a series of monotonically changing programming/erasing pulses and the simultaneous measurement of Vfb. This experiment permits to elucidate the existence of two distinct states in the double-layer NCM structure and the possibility to programme and erase the memory cell by voltage pulses of the same polarity (unipolar recharging effect [1]).

Second, the charge relaxation measurement consisted of applying a quasi-continuous programming pulse to the memory structure with simultaneous measurement of Vfb with the aim to explore how the programming pulse duration impacts the charge state in the NC layer within the dielectric. Third, the charge retention measurement that gives the actual lifetime of the memory, was performed by sequential measurement of Vfb after a single or a series of applied programming pulses that reveal the velocity and pattern of charge leakage from the nanocrystal layer. This method permits to analyze the influence of different physical mechanisms on the charge redistribution processes inside the charging medium.

The above methods were employed to samples with one and two Si nanocrystal layers within the SiO2 of the MOS structure of an NCM. The Si nanocrystal layers were formed by low pressure chemical vapour deposition (LPCVD) of silicon from silane on an oxidized Si wafer, followed by high temperature thermal oxidation. The nanocrystals of the top Si NC layer were larger in size than those of the bottom layer. A control oxide was added on top of the NC layers. For more details on sample fabrication one can see reference [2].

It was shown that under the same conditions the single and double Si NC layer structures have a different behaviour. Under the same polarity of bias, the sign of the charge trapped in the single Si NC layer is opposite to that in double NC layers (Fig.1). In the case of the single NC layer, a net positive charge is found to be trapped in the charging layer, while in the case of samples with a double NC layer, a net negative charge in the dielectric stack is observed. Secondly, there is a difference in the “erase” process behaviors. In the single-layer NCM structure a stair-like erase process occurs, that could be explained by sequential negative charge de-trapping processes between shallow and deep energy levels in the NC layer, during interruptible biasing. Qualitatively different result is observed during the relaxation process of the double-layer NCM structure. In this case the field is reversed, which could be attributed to a remaining charge within the upper NC layer that cannot escape to the substrate due to the potential barrier created by the bottom NC layer. Charge relaxation does not show stair-like behavior. Thirdly, a significant difference in the “erase” process dynamics is observed in the double layer structure. The signal relaxes about ten times faster than in the single layer structure.

Peculiarities in behavior of other characteristics of the double-layer Si NCM structure are discussed.

Fig.1a. Single-layer NCM Fig.1b. Double-layer NCM relaxation curve. relaxation curve.

[1] Turchanikov, V., Nazarov, A., Lysenko, V., Ostahov, V., Winkler, O,. Spangenberg, B., and Kurz H. Microelectronic Reliability 47 (2007) 626 .

[2] Theodoropoulou, M., and Nassiopoulou, A. G., Microelectronic Engineering 85 (2008) 2362.

Effect of HfO2 polycrystallinity on distribution of the CAFM-induced TDDB in high-k gate stacks.

V. Iglesias1, T. Erlbacher2, M. Rommel2, K. Murakami3, A. J. Bauer2, L. Frey2,3, M. Porti1, J. Martín-Martínez1, R. Rodríguez1, M. Nafria1, X.Aymerich1, G. Bersuker4 1

Dept. Eng. Electrònica, Universitat Autònoma de Barcelona, 08193, Bellaterra, Barcelona, Spain.

Fraunhofer Institute for Integrated Systems and Device Technology, Schottkystrasse-10, 91058 Erlangen, Germany.

3 Chair of Electron Devices, University of Erlangen-Nuremberg, Cauerstrasse 6, 91058 Erlangen, Germany.

4 SEMATECH, 2706 Montopolis Drive Austin, TX 78741 USA 2

With the introduction of high-k dielectrics, bimodal TDDB distributions can be observed [1,2], which have been explained by the different defect generation rates in the high-k and interfacial layer of the stack [2]. On the other hand, polycrystallization of the high-k layer implies a non-homogeneous electrical behaviour of the gate stack at the nanoscale due to the different electrical properties of grains (G) and grain boundaries (GB) [3]. In this work, the impact of polycrystallization of HfO2 gate stacks on the TDDB distributions will be analyzed in detail. This analysis will be performed with Conductive Atomic Force Microscope (CAFM), since its nanoscale resolution allows to study Gs and GBs independently.

The dielectric stack consists of a 5nm ALD HfO2 film deposited on a 1nm SiO2 layer, which was grown on the Si substrate. The stack was annealed at 1000ºC to simulate the thermal budget of the gate first fabrication process that results in further crystallization (compared to as-deposited) of the high-k film [3]. BD was induced by applying Constant Voltage Stresses (8.2V, injection from the gate) with the tip of the microscope at different random locations (Gs and GBs) and tBD was estimated from the I-t curves. Note that the global TDDB distribution (Fig. 1) shows a bimodal behaviour. To investigate its origin, G and GBs sites have been analyzed independently. Since GBs are leakier than Gs in HfO2 [3], the current at t=0s [I(t=0s)] of the measured positions of Fig. 1 has been considered as parameter to determine which sites correspond to Gs and GBs. Fig 2 shows the cumulative probability of I(t=0s). Note that two regions can be distinguished, which have been attibutedto Gs (low currents) and GBs (high currents). The TDDB distributions of Gs and GBs (separately) and their Weibull parameters are shown in Fig. 3. Note that the data measured at both sites can be fitted to Weibull

(1)

HerePGB is the probability of having a GB under the AFM tip, and FG and FGB are the Weibull distributions for the Gs and GBs cases (same β has been considered for both distributions, assuming that BD is actually triggered on the SiO2, Fig. 3). This model fits very well the global Weibull distribution of Fig. 1, with parameters that are qualitatively similar to those in Fig. 3 (small deviations can be attributed to some uncertainty in determining whether the CAFM tip was placed on a G or GB).

Therefore, these results suggest that differences in electrical properties of Gs and GBs, lead to a bimodal TDDB distribution in high-k based stacks.

[1] P. Delcroix et al., Microelec. Eng. 88, 1376 (2011) [2] T. Nigam et al., IRPS 2009, p. 523 [3] V. Iglesias et al., Appl. Phys. Lett. 97, 262906 (2010) [4] G. Bersuker et al., IEDM 2008, p. 791-794 This study was supported by Spanish (TEC2010/16126) and the Generalitat de

-2 -4

-2

Experimental PGB = 0.30

99,5 95

0

2

4

ln(tBD) Fig.1. TDDB distribution of the gate stack (squares), showing a bimodal behaviour, and fitting to the model proposed in eq.1 (red line). Dashed lines are guide to the eye to show the two modes.

70 40 10 1

0,01

Grain

Grain boundary

0,01

0,1 I0 (nA)

2

ln(-ln(1-F(t)))

β = 1.14 ηGB = 3.17s 0 η = 26.41s G PGB = 0.31

Probability

ln(ln(1-F(t)))

F (t )= PGB ·FGB (t , β ,η GB ) + (1 − PGB )·FG (t , β ,η G )

MICINN Catalunya

(2009SGR-783).

2

-6

distributions with similar slopes. However, smaller tBD(63%) are measured at GBs, which is compatible with the fact that BD preferentially occurs at the leakiest positions (GBs), probably due to an excess of O vacancies. Since different mechanisms are expected to control the BD of Gs and GBs, the observation of similar slopes suggests that the stack BD could be controlled by the underneath SiO2 layer, as was already pointed out in [4]. The excess of O vacancies at GBs can lead to a larger applied voltage drop across the underlying SiO2 film, leading to the smaller observed tBD [3].

The impact of two different BD processes in the high-k dielectric, which compete in the same SiO2 layer on the global TDDB distribution has been analyzed by presenting the global TDDB distribution, F(t), as a combination of distributions for G and GB related BDs:

1

Fig. 2. Cumulative distribution of I(t=0s). Two regimes, one at low currents (G) and another at high currents (GB) can be distinguished.

0 -2 -4

Grain boundary β 0.89 η = 13.55 s Grain β 1.08 η = 24.62 s

-6 -2 2 4 of the6 Fig. 3. 0TDDB distributions positions attributed to G and GBs and ln(t) their Weibull parameters.

Electrical properties of Thin Y2O3-doped Indium Zinc Oxide Films (IZO) by RF Magnetron Sputtering System Young-Jun Lee and Joo-Hyung Kim Department of Electronic Engineering, Chosun University, Seoseok-dong, Gwangju, Korea Corresponding author e-mail: joo-hyung.kim@chosun.ac.kr Amorphous semiconducting indium-zinc oxide (IZO) has been considered as a prominent candidate for thin film transistors (TFTs) in flat panel displays and transparent sensors/actuators. Especially, IZO-based system is the most attractive candidate due to the excellent TFT performance with large field effect mobility. However, it is required to control the carrier concentration because IZO film has a high carrier concentration.

In this paper, yttrium oxide (Y2O3) was selected to control the carrier concentration of IZO film and the effect of O2/Ar ratio on structural, electrical and optical properties of thin yttrium doped indium zinc oxide (YIZO) films was investigated. Thin YIZO films were deposited at room temperature on glass substrate using radio frequency (RF) magnetron co-sputter with an IZO target and a pure Y2O3 target. The system was pumped down to reach a based pressure lower than 5 × 106 Pa using a turbo-molecular pump. During the depositions of YIZO films, total gas flow (Ar+O2) was fixed by regulated continuous flow of 25 standard cubic centimeters per minute (sccm) while the O2/Ar ratio was changed. As a result, the amorphous phase is only observed under pure Ar gas condition. However, (100) peak is observed as oxygen gas flow increases. The surface roughness of the YIZO films shows very smooth surface, while characterized electrical properties of thin YIZO films are very dependant to O2/Ar gas conditions.

The measured carrier concentrations and corresponding mobilities of grown YIZO films are in the range of 8.46 × 1015 - 1.16 × 1020 cm-3 and 2 - 21 cm2 V-1S-1, respectively.

Measured overall transmittance of YIZO films over 84%

Fig.1. Measured XRD data of thin YIZO films grown under different O2/Ar gas conditions

in visible range is obtained. Also, in order to evaluate YIZO film as a semiconducting channel layer, the device performance of YIZO TFT was characterized. The YIZO TFT shows a good on/off ratio (Ion/off) of more than 106, but relatively high threshold voltage is observed.

Acknowledgements The authors thank to Dr. Kwang-Young Kim and Dr. Byeong-Yun Oh (Kitech) for kind cooperation during this research.

References [1] A. N. Banerjee, C. K. Ghosh, K. K. Chattopadhyay, Hideki Minoura, Ajay K. Sarkar, Atsuya Akiba, Atsushi Kamiya, Tamio Endo, Thin Solid Films, 496 (2006) 112.

Fig.2. Measured resistivity, carrier concentration and Hall mobility of as grown YIZO films under different gas conditions.

Cellulose-ZnO Hybrid Composite for Flexible Transistor Hyun-u Ko1, Byung-Wook Lim2, Sang Yeol Yang1, Jaehwan Kim1, Joo-Hyung Kim2 * 1

Creative Research Center for EAPap Actuator, Dept. of Mechanical Engineering, Inha University, Incheon 402-751, South Korea 2 Lab. of Nano-Micro Devices, Dept. of Electronic Engineering, Chosun University, Gwangju 501-759 South Korea * Corresponding author e-mail: joo-hyung.kim@chosun.ac.kr Recently, cellulose has attention as a smart material due to its unique material property such as piezoelectricity and insulting properties, which can be modified by chemical process similar to Si-based technologies.

Recently, it was reported that carbon nanotube bonded cellulose based transistor was demonstrated as a new flexible type transistor.

In this study, to form the nano-scaled semiconducting channel layer on pure cellulose substrate, we investigated the effect of ZnO seeding layer on flexible regenerated cellulose substrate. ZnO is a promising and widely investigated material due to its semiconducting and piezoelectric properties for potential device applications.

Moreover, utilizing the size effect in nanostructure of ZnO compared to macro-sized ZnO and quantum tunnelling effect along the nanorods, higher material performance of nano-sized ZnO has been suggested.

Generally ZnO is a wide bandgap (~3.4 eV) semiconducting and has a high hole-electron binding energy (~ 60 meV). The seeding layer for nano-scaled ZnO rod can be easily fabricated by simple hydrothermal process and controlled by different concentrations of ZnO derivative.

Typically, the ZnO growth on polymer substrates was performed by hydrothermal method. The main advantage of hydrothermal process is that only low temperature process lower than 100°C is required, which is proper to flexible and temperature sensitive materials such as polymer substrates. Most polymers are hydrophilic, which means that they require relevant treatments for hydrophilic surface. Because cellulose itself is hydrophilic due to hydroxyl (OH) groups of chemical structure, therefore it does not require any other surface treatment process.

To control the ZnO nanorod growth on cellulose,

ZnO seeding layer play an important role for ZnOcellulose composite. Zn(NO3) and triethanolamine (TEA) were selected to control the growth of ZnO seeding layer.

To achieve our goal, different concentrations of ZnO seeding layer were selected from 25 mM (mole) to 150 mM. Also to prevent thermal effect from flexible substrate, process temperature was maintained at 60 °C. By increasing the concentration of ZnO seeding layer, the number of ZnO cluster also increases. Interestingly, the rod shape particles are also formed on cellulose substrate. From our observation, in low concentration from 20mM to 50mM, the size of ZnO rod increases as the seeding concentration increases. However, in high concentration, flower shaped ZnO structure is observed, which indicates that the flower shape is due to clustering effect during the growth of ZnO rods. This result indicates that superabundant derivative can decrease an uniform directivity of ZnO particles in seeding layer.

More detailed ZnO-cellulose based transistor is also investigated and discussed.

Acknowledgements This work was supported by the Creative Research Initiatives (EAPap Actuator) and basic science research program (2011-0005781) of NRF/MEST, Korea.

References [1] Manekkathodi, A., Lu,M. –Y., Wang, and C. W. Chen, LihJuann: Adv. Mater. 22 (2010 [2] ) 4059.

[3] John, A., Ko, H. U., Kim D. G., and J. Kim: Cellulose 18(2011), 675.

[4] Yamabi, A., and Imai, J: J. Mater. Chem., 2002, 12, 37733778

Vgate=2V

Ids(mA)

0.010

0.005

Vgate=0V 0.000 0

2

4

6

8

Vds(V) Fig.1. SEM image after seeding : (a)50mM, (b) 100mM

Fig.2. I-V curve of the cellulose ZnO transistor

Plasma-Assisted Atomic Layer Deposition of Alumina at Room Temperature M. Lemberger1, T. Fromm2, M. Rommel1, A. J. Bauer1, L. Frey1,2 1 Fraunhofer Institute for Integrated Systems and Device Technology, Schottkystrasse 10, 91058 Erlangen, Germany 2 Chair of Electron Devices, University Erlangen-Nuremberg, Cauerstrasse 6, 91058 Erlangen, Germany corresponding author e-mail: martin.lemberger@iisb.fraunhofer.de Plasma-assisted atomic layer deposition (PE-ALD) allows for expanding the ALD temperature window even down to room temperature [1], thereby achieving high quality dielectrics. Thus, novel applications like thin-film transistors on temperature sensitive substrates, (reference systems for) printed electronics, or encapsulation of biosensors can be addressed.

Al2O3 films were deposited using PE-ALD (FlexAL from Oxford-Instruments) on Si and TiN substrates. TMA and O2 plasma were used as precursors. The deposition temperature TDep varied between 30°C and 400°C with focus on the sub-150°C range. Part of the samples were annealed (PDA) at 400°C for 30 min in N2. MIS and MIM capacitors were formed via all room temperature TiN/Al sputtering, lithography, and dry chemical etching.

For analysis and optimization on varying TDep, all steps of the ALD process were taken into consideration.

Although growth per cycle (GPC) increases for TDep below 125°C (Fig. 1), a pure ALD process with no indication of side-reaction (e.g., TMA condensation or desorption at low TDep prior to reaching ALD process window) was established down to TDep of 30°C. TMA dosing, oxygen plasma oxidation as well as oxygen plasma purge (step potentially could be even skipped) are independent on TDep. Solely TMA metal purge duration tpm to reach saturation of GPC (Fig. 1, inset) turned out to depend on TDep and has to be prolonged for decreasing temperatures (Fig. 1).

On both substrates, alumina thin film grow without inhibition and linear relation of film thickness vs ALD cycles is obtained.

Processed MIS and MIM capacitors show well behaved capacitance-voltage (CV) characteristics (e.g.,

parabolic MIM CV curves with about 570 to 730 ppm/V2 and -110 to -60 ppm/V for TDep of 30°C and 125°C, respectively). Extracted dielectric constant increases with increasing TDep from about 6.6 (30°C) to 7.3 (125°C) (Fig. 2a). In MIM stacks, k tends to be slightly higher compared to MIS capacitors. Fixed oxide charge and interface trap density are about 2*1012 1/cm2 and 2*1011 1/cm2eV, respectively. Annealing has minor or even no influence.

For comparison, annealed 350°C MIS capacitors show kvalue of about 8. Current density-electric field (JE) curves show low leakage (e.g., 10-7 A/cm2 at 6 MV/cm, Fig. 2b).

However, films deposited at lower temperatures show slightly higher current densities and a discussion on thickness vs barrier lowering effect with TDep will be given. Leakage current mechanism examined via temperature dependent JE show domination of Poole-Frenkel conduction (e.g., at TDep of 30°C, two trap energies of 1.5 eV (5 MV/cm) and 2.1 eV (8 MV/cm) can be evaluated for MIS capacitors for gate injection). Correlation to an alternative a-V evaluation method [2] of JE will be discussed. Based on extracted data from MIS and MIM capacitors, a model for the band diagram of alumina deposited via PE-ALD at low temperatures will be presented.

This paper addresses process development of even room temperature PE-ALD of high quality alumina thin films. CV and JE of MIS and MIM capacitors are closely examined. A band diagram for low-temperature alumina is presented and discussed.

Fig.1. PE-ALD process optimization: GPC and TMA metal purge duration tpm depending on TDep. Inset shows saturation of tpm.

Fig.2. a) Extracted k-value of alumina. b) Temperature dependent JE curves for MIS capacitors at TDep of 30°C and 75°C. Inset shows Arrhenius-plot for trap depth evaluation.

References [1] E. Kessels et al., Plasma ALD, in: N. Pinna, M. Knez. (eds.), ALD of Nanostrucured Materials, 1st ed., Wiley, 2012.

[2] K. Murakami et al., J. Appl. Phys. 110 (2011) 054104.

Epitaxial growth of SrTiO3 on GaN(0002) by TiO2/MgO bilayer buffer

Wenbo Luo1,2, Jun Zhu1, Huizhong Zeng1, Yao Shuai1,2, Shengqiang Zhou2, and Heidemarie Schmidt2 1 - State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China 2 - Institute of Ion Beam Physics and Materials Research, Helmholtz-Zentrum Dresden-Rossendorf, P. O. Box 510119, Dresden 01314, Germany corresponding author e-mail: w.luo@hzdr.de, luowb@uestc.edu.cn.

There is an increased interesting in integration of pervoskite oxide materials with GaN semiconductors, for the high power, high frequency and high temperature devices.[1] However, itâ&#x20AC;&#x2122;s hard to obtain epitaxial pervoskite films directly on GaN template because of the large lattice mismatch. SrTiO3 (STO) is a focus material which has a large dielectric constant about 300 at room temperature. Recently, epitaxial STO films on GaN were fabricated by using rutile TiO2 buffer layer[2]. Nevertheless, the band offsets of TiO2 on GaN indicated that the band lineup is not favorable for device application. Itâ&#x20AC;&#x2122;s noted that MgO had a wide bandgap of about 7.8ev, which gives a large valence and conduction band offsets in MgO/GaN heterostrure and is well suited to high-temperature applications[3]. MgO has been epitaxially grown on GaN even at room temperature and shown a low interface state density with GaN[4]. On the other side, MgO has been widely used as bufferlayer to integrate pervoskite oxide with semiconductor materials, such as Si and GaAs. However, there is no report about pervoskite epitaxial growth on MgO buffered GaN to our best knowledge.

In this letter, (111) oriented STO films were fabricated on TiO2/MgO buffered GaN (0002)

Fig.1. RHEED patterns of MgO(a), TiO2 (b), STO(c)and XRD spectrum of the heterostructure(d) .

surface by laser molecular beam epitaxy (LMBE). The deposition processes were in-situ monitored by reflective high energy electron diffracation (RHEED). As shown in figure 1, the RHEED patterns and X-ray diffractions indicate that STO films were epitaxially grown on GaN. The effects of MgO layer on leakage current were also studied. In order to do this, Au/Ni Schottky contact and Ti/Al/Ti/Au Ohmic contact were deposited by E-beam evaporating respectively. It was found that the leakage current was reduced obviously as shown in figure 2. This reduction may be result from the large band offsets caused by MgO. These results provide a new opportunity to make GaN MOS-HEMT with high-k dielectrics for gate oxides using PLD-grown STO. References [1] Stephen J. Pearton, Fan Ren. GaN electronics. Adv. Mater., 12(2000) 1571.

[2] W. B. Luo, J. Zhu, H. Chen, X. P. Wang, Y. Zhang, and Y. R. Li. J. Appl. Phys. 106 (2009) 104120.

[3] J. J. Chen, B. P. Gila, M. Hlad, et al.. Appl. Phys. Lett., 88 (2006) 042113.

[4] Y. Irokawa, Y. Nakano, M. Ishiko, et al.. Appl. Phys. Lett., 84(2004) 2919

Fig.2.I-V curves of different heterostructures (a)STO/AlGaN/GaN(b)STO/TiO2/AlGaN/GaN (c)STO/MgO/AlGaN/GaN(d)STO/MgO/TiO2/AlGaN/GaN

Non-Volatile Si based Memory FET With Negative Differential Resistance Used the Pt Nanocrystals as storage media and High-k dielectric blocking layer V. Mikhelashvili1, B. Meyler1, Y. Shneider, G. Atiya2, T. Cohen-Hyams2, W. Kaplan2, S. Yofis1, J. Salzman1, M. Lisiansky3, Y. Roisin3, G. Eisenstein1.

1 - Electrical Engineering Dept., Technion, Haifa 32000, Israel 2 - Materials Engineering Dept., Technion, Haifa 32000, Israel 3- Tower-Jazz,Migdal Haemek, Israel Corresponding author e-mail: beso@ee.technion.ac.il We report the structural and electrical characteristics of non-volatile memory metal-insulator-semiconductor (MIS) capacitor and MIS Field Effect Transistor (FET), using Pt nanocrystals (NC) (with average sizes of about 5.5 nm and densities of 1.5x1012 cm-2) as charge storage nodes. The devices, comprise Pt NCs placed between a thermal SiO2 (3.7 nm) tunneling and a 30 nm atomic layer deposited HfO2 blocking layers. The structural details of the NCs and their size distribution were obtained from plan view and cross-section images using high resolution scanning and transmission electron microscopy which are shown in Fig.1. The capacitance-gate voltage (C-Vg), source to drain current versus source to drain voltage (ISDVSD) and transfer (ISD-Vg) characteristics of the MIS capacitor and FET measured at different Vg or VSD delay times (td) ranging from 0.1 ms to 500 ms are shown in Fig. 2. For optimal conditions, the MIS capacitor and FET are characterized by flat band and threshold voltages shifts (VFB and Vth) at the write and erase modes, respectively of 2.36 V, -2.76 V and 1.65 V, -2 V. Hence, the total memory windows (V) obtained at a sweeping voltage of ±5 V and td of 10 ms are equal to 4.12 V and 3.65 V. The resulting total charge density (Ncharge) accumulated in the Pt NCs within the MIS capacitor and FET, respectively are 2.5x1013 and 2.2x1013 cm-2. At a sweeping voltage of ±10 V, the V of the ISD-Vg hysteresis reaches 11.3 V (Ncharge=6.9x1013 cm-2). In Fig. 2c and 2e we compare the ISD-VSD curves measured at different td of applied VSD. At td larger than 0.1 sec, the measured ISD-VSD characteristics exhibit a non-monotonic behavior (see Fig. 2e). The initial quick rise and the following conventional saturation of the ISD is observed at td smaller than 0.1 ms (see Fig. 2c), while the ISD-VSD curves measured at td larger than 0.1 ms exhibit a negative differential resistance (conductance) (NDR). This phenomenon was not observed for MIS FET with analogous gate dielectric stack, but without Pt NCs (see Fig. 2d). This effect is apparently caused by physical mechanisms which were never observed in MIS type NVM structures with NCs or defect type traps as charge storage nodes. There are no obligatory conditions of realization neither carriers quantum mechanical band-toband tunneling or resonant tunneling through the doublebarrier diodes nor formation of hot electrons in narrowed channel region usually causing the NDR. The only mechanism causing of formation of the NDR type ISD-VSD characteristics is the trapping process of the carriers

injected from substrate toward NC sites under vertical applied voltage between gate terminal and source. The Peak to valley ratio of source to drain current (PVCR) shown in Fig. 2f changes strongly with td and varies weakly in a wide range of the applied gate voltages. The maximum value of about 5x103 is observed at td of 500 ms, while at a td of 1 ms, the PVCR is about 50. The large storage capability and observed NDR effect make the suggested NVM MIS capacitors and FETs very attractive for different functional logic circuits.

Fig.1 (a) Plan view HRSEM and (b) HRTEM cross section images of structure with Pt NCs.

Fig. 2 (a) C-Vg characteristics of MIS capacitor, (b) ISD-Vg curves of FET,(c) ISD-VSD curves, measured (td=0.1 ms),(d) ISDVSD curves of FET without Pt NCs (td=50 ms), (e) ISD-VSD curves of FET with Pt NCs (td=50 ms),(f) PVCR versus appplied gate voltage obtained at different delay times.

Spatial Distribution of Filamentary Leakage Current Paths in Circular Area Pt/HfO2/Pt Structures E. Miranda1, D. Jiménez1, J. Suñé1, E. O’Connor2, S. Monaghan2, K. Cherkaoui2, and P.K. Hurley2 1 – Departament d’Enginyeria Electrònica, Universitat Autònoma de Barcelona, Barcelona, Spain 2 – Tyndall National Institute, Cork, Ireland Corresponding author e-mail: enrique.miranda@uab.cat The spatial distribution of filamentary leakage current paths in 30 nm-thick HfO2 layers generated by electrical stressing circular area MIM capacitors is investigated.

The filamentary paths are clearly visible on the top metal electrode (Pt) as a random point pattern and are the consequence of important localized thermal damage. The formation of these paths is not only relevant for reliability and scaling issues but also for the multifilamentary resistive switching effect in MIM devices. It is shown using spatial statistics techniques [1] that the spots follow a 2D homogeneous Poisson process though for the largest area devices investigated in this work some anomaly in the distribution is detected. This deviation from complete spatial randomness (CSR) is analyzed in detail.

Figure 1 shows the current increase associated with the generation of the filamentary paths. Devices with different areas (radius from 56 m to 423 m) were investigated. The inset illustrates a typical distribution of spots over the top electrode. The outer dark ring is the dielectric layer beneath the top electrode. Histograms for interpoint distances corresponding to different device areas are shown in Fig. 2 (for the sake of clarity just the four smallest areas were included). The solid lines were calculated from the theoretical probability distribution: f ( x) 

2x  2 x x2  1  x  cos  1      R 2   4 R 2   2 R  R

are the experimental data and the solid line is the theoretical relationship for CSR: M=0.905R. The number of spots recorded after electrical stress is also indicated.

Notice that whereas the first four points follow the expected curve, the points N=182 and N=322 corresponding to the two largest areas are below the solid line, which indicates deviation from CSR. Even for devices with a higher number of spots (N=969 and N=1444), the deviation is still detectable. As can be seen in the intensity plot and spot radial distribution (f(r)=2r/R) of Fig. 3, the observed deviation is a consequence of the lower number of spots in the periphery of the devices.

Similar departure from CSR is also detected in the interevent histograms as a shift toward smaller distances (not shown here). This anomaly is ascribed to some fabrication process-related effect, presumably the lift-off process.

[1] J. Illian, A. Penttinen, H. Soyan, D. Stoyan, in Statistical analysis and modelling of spatial point patterns, Wiley, 2008 [2] H. Solomon, in Geometric Probability, SIAM, 1978.

0  x  2R

which can be derived from Crofton’s fixed point theorem [2]. x is the distance between two points and R the device radius. The agreement with the experimental data is excellent in these cases. The inset in Fig. 2 shows the median of the distances (M) as a function of R. Symbols

Fig.2. Experimental and theoretical distribution of the interpoint distances. The inset shows the relationship between M and R.

Fig.1. Evolution of the I-V characteristic during the generation of the filamentary paths. The insets show the array of circular capacitors and the distribution of spots in a particular sample.

Fig.3. Intensity plot for the spots and radial distribution. Notice the lower density of spots in the periphery of the device.

Double gate dielectric stacks with Gd2O3 layer for application in NVSM devices Jakub Jasiński1, Robert Mroczyński1, Heinrich Gottlob2, Mathias Schmidt2 1

Institute of Micro- and Optoelectronics, Warsaw University of Technology, Koszykowa 75, 00-662 Warsaw, Poland AMO GmbH, Otto-Blumenthal-Strasse 25, 52074 Aachen, Germany corresponding author e-mail: rmroczyn@elka.pw.edu.pl

2

1.

Introduction Due to scaling issues there is no doubt that future generations of non-volatile semiconductor memories (NVSM) will be based on high-k dielectric materials.

Among rare earth oxides, gadolinium oxide (Gd2O3) with its relatively high permittivity value was proven recently as thermally stable in the gate first process integration scheme which makes him a possible candidate as a replacement MOS gate insulator [1]. In this work we present the feasibility of application Gd2O3/SiO2 stack in NVSM devices. The results reported in our recent work [e.g. 2] have proven that a gate stack which is composed, in contrary to commonly found in the literature, of only two gate dielectric layers, demonstrates a great hope of application in NVSM devices. The quality of double gate dielectric stack was investigated by means of split-CV and I-V characteristics analysis. Memory characteristics were assessed by monitoring the shift of threshold voltage (Ut) of MOSFET upon the program and erase operations (Up/e) at elevated temperatures (up to 85°C). Moreover, the comparison with previously reported results with ALD high-k layers was performed.

2. Experimental procedures nMOSFETs have been fabricated on <100> bulk silicon using a gate first integration approach at the Advanced Microelectronic Center Aachen (AMICA), AMO GmbH (Germany). Double gate dielectric stack was obtained by thermal oxidation of silicon to form 4nm SiO2 pedestal layer followed by 10nm Gd2O3 e-beam evaporation [3]. For gate electrode, a mid-gap TiN metal has been used. The electrical measurements were performed with the Keithley 4200–SCS equipped with SUSS PM-8 Probe Station.

3. Results and discussion Basic electro-physical parameters of obtained MOS devices have been evaluated. The equivalent oxide

Fig.1. Transient characteristics of transistor with investigated double gate dielectric stack after Up/e=±5 V; LxW=5x20 µm.

thickness (EOT) value of gate dielectric stack ~5.6nm was determined. Interface traps density (Nit) of the order of 2x1011cm-2 was calculated and compared to results obtained by CP method. Depending of the device geometry relatively low mobility values varied in the range of 80÷140cm2/Vs were calculated. This is a result of relatively high value of series resistance (RSD), which was presented in our recent work. The analysis of I-V characteristics proved a low leakage current ~0,1µA @7V in the accumulation direction. In order to examine the memory behavior of the studied MOS structures, at first, flat-band voltages (Ufb) values were measured as a function of stress voltage. Maximum memory window of the order of ~0.8V was obtained which is a slight lower in comparison to previously reported double gate dielectric stacks with ALD HfO2 and Al2O3 layers. However, taking into account MOSFET’s behavior we have obtained relatively wide Ut shift ~1,8V upon +/-5V Up/e (Fig.1).

The retention time (at 25°C) extrapolated at 10 years is estimated at ~1,67V, while in the case of 85°C the memory window decreased to a value ~0,86V (Fig.2).

These results make the Gd2O3/SiO2 stack as a potential candidate for low voltage memory applications.

4. Conclusions In this paper we have shown first experimental results that are promising for the application of double gate dielectric stack with gadolinium oxide in NVSM devices. However, further studies are needed to prove its feasibility in the case of mass production.

Acknowledgments This work was supported by the Polish Ministry of Science and Higher Education under grant No. N N515 081137.

References [1] D. Landheer et al., Appl. Phys. Lett. 79, 2618 (2001).

[2] R. Mroczyński et al., accepted in Appl. Surf. Sci. (2011).

[3] H.D.B. Gottlob et al., Micr. Eng. 86 (2009).

Fig.2. Retention time of studied in this work Gd2O3/SiO2 stacks as a function of temperature; Up/e=±5 V, LxW=5x20 µm.

A Novel Plasma Enhanced Low Temperature Oxidation for Dielectrics J. Niess1, A. Gschwandtner1, W. Lerch2, W. Kegel2, K. Seidel3, V. Beyer3, K. Biedermann3, S. Riedel3, M. Drescher3, M. Czernohorsky3 1 - HQ-Dielectrics GmbH,Postfach 49, 89156 Dornstadt, Germany 2 - centrotherm thermal solutions GmbH + Co. KG, Johannes-Schmid-Straße 8, 89143 Blaubeuren, Germany 3 - Fraunhofer Center Nanoelectronic Technologies, Königsbrücker Str. 180, 01099 Dresden, Germany corresponding author e-mail:juergen.niess@hq-dielectrics.eu Thermal processes in semiconductor manufacturing have radically changed their temperature-time cycles over the past 10 years. On the one hand side there is a tendency towards always shorter heat pulses at increasing temperatures, nowadays realized by millisecond and submillisecond pulsed heating up to temperatures of 1300 °C for highest dopant activation. On the other hand side there is a tendency towards temperatures only slightly above room temperature in order to form high quality dielectrics while ensuring a minimum dopant redistribution and minimum dopant deactivation. Especially in case of oxides there is still no general solution, how the temperature could be decreased below ~ 850 °C without sacrificing on oxide quality and growth rates. This paper characterizes low temperature plasma enhanced oxides grown at temperatures below 450 °C in a new microwave plasma oxidation tool (PlasmOxLT) with unique features addressing the aforementioned extreme low temperature process regime already discussed in the 1980s [1].

The tool is equipped with 10 individually tunable microwave plasma sticks which are located above the wafer (Figure 1). Further options for process tuning are plasma composition and the distance to the plasma sticks.

Maximum wafer temperatures for the tested processes were all below 450 °C. Various thicknesses of the LTPOx process ranging from 2.7 to 12.1 nm were fabricated on blanket 300 mm wafers and evaluated by spectroscopic ellipsometry.

Electrical characterization was done by use of Ni MIS caps having a dielectric area of 50 kµm² each. SiO2 reference samples were prepared featuring different oxidation technologies: RTO, furnace oxidation and ALD grown SiO2. No post treatments like FGA or PDA were applied to the investigated oxides.

Figure 2a shows the TEM cross-section of a MIS cap with 6.2nm LTPOx used for the electrical characterization. The LTPOx layer has an atomically flat interface to Si (not shown here) and void-free SiO2 (Figure 2a). The good conformality at the vertical structures and the good corner rounding is demonstrated as TEM cross-section in Figure 2b. The oxidation rates of Si3N4 and Si are similar. ToF-SIMs analysis reveals similar Si/O composition over the SiO2 layer of LTPOx and furnace oxides. IV characterization shows higher breakdown fields compared to similar oxidation processes[2], but similar leakage characteristic to the thermal oxides (RTA and furnace). Also CV characterization was applied indicating Dit values only slightly higher than RTO or furnace, with further process variations ongoing to decrease that down to at least RTO levels.

The above evaluation demonstrates a new plasma enhanced low temperature oxidation process on 300mm wafers. Leakage and breakdown characteristics are comparable with conventional thermal oxides. Further process optimization is ongoing to reduce the about 50 % higher Dit compared to RTO down to a thermal oxides level. Being processed at lower temperature than RTO and furnace the LTPOx performs considerably better in all electrical results than alternative low temperature oxides such as ALD-based SiO2.

References [1] A.K. Ray, A. Reismann, J. Electrochem. Soc. 128(11) (1981) 2424-2428 [2] J. Watanabe, Y. Kawai, N. Konishi, T. Ohmi, Jpn. J. Appl. Phys. 34 (1995) 900-902

Plasmastick Quartztube Wafer

Nitride

Process chamber

580 nm

Edge guard ring Wafer support Support pins

Silicon

z-lift and rotation axis

Figure 1: Schematic of PLASMOX LT chamber for low temperature plasma enhanced oxidation.

(a)

(b)

Figure 2: TEM images of LTPOx based SiO2 layer a) 6.2nm oxide in the Ni MIS cap used for characterization b) step coverage in STI trench.