VARUN SENTHILKUMAR 1561, Warburton Avenue, Apt 10 Santa Clara, CA-95050.
480.329.7108
vsenthil@asu.edu
OBJECTIVE SoC design.
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EDUCATION MS, Electrical Engineering, Specialization: Mixed-Signal Circuit Design Arizona State University, Tempe, USA.
GPA 3.41 May 2014
BE, Electronics and Communication College of Engineering, Guindy, India.
GPA 3.45 May 2012
TECHNICAL SKILLS Languages : Verilog HDL, System Verilog, PERL, Tcl, Hspice, C, C++. Tools Front End BackEnd
Model Sim, Active HDL, Xilinx (FPGA). Cadence RTL compiler, SoC Encounter.
Circuit Design & Simulation
Cadence Virtuoso, Spectre, Hspice.
Device Modeling
Silvaco ATLAS.
PCB Design
Altium.
System Model
MATLAB, MS Office, Eclipse.
EXPERIENCE ASIC design and verification intern,SSR labs, Menlo Park, California.
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RTL Design support on SERDES, FIFO and comparator in the HMC Co-processor interface. Worked on the top level module of a CDR block in a Serial Link.
Hardware design and integration engineer intern, EDGE 3 Technologies, Tempe, Arizona.
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8/13 - 12/13
Designed innovative schematic and PCB layout for constant current LED circuits in Computer vision application. Designed reverse switching circuits using Power MOSFETs for camera application. Successfully tested and found 6 errors in High-speed IO circuits for electrical validation, using high speed oscilloscopes. Created schematic symbol and layout foot print for the IC’s in Altium library, saving engineer’s time for the complicated design. Soldered Custom PCB’s and was praised for attention to detail and correct output.
Independent Research - Study of Power Management of EXYNOS 5 Octa-core chip
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6/14 - 9/14
9/13 - 4/14
Modeled the DVFS technique in ARMbig.LITTLE architecture by running various applications in Android platform. Work - load performance, power consumption, temperature and frequency of the cores were monitored using Perl Scripts. Linux scripting to swap the application between the Cortex A7 and A15 cores based on the work-load and running frequency.
ACADEMIC PROJECTS Design and verification of Asynchronous FIFO
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Design of asynchronous FIFO for given spec of write frequency being 10 times faster than read frequency. Verified it through layered test bench with Bus Functional Modules, Checkers, Scoreboard & automatic stimulus generation.
Error detection and correction block for a microprocessor
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Designed a 128 bit SECDED module using Verilog.Module was synthesized using Cadence RTL. Performed backend design flow of chip using the Encounter tool (Floorplan, CTS, Nano Route and Post-Route). Physical verification of layout ( DRC and LVS check ) implemented in 45nm technology. STA sign off for design was also performed.
Design and characterization of standard cell blocks with 45nm technology
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Designed a custom layout of VTG, VTH, VTL models for 3-input NOR, Full-Adder and Low Transparent Latch using 45nm PDK. Performed hspice simulation & validation for worst case i/p and varying process corners ( TT, SS, FF). Performed cell characterization for all types of cell at TT, SS, FF process corners using Cadence ELC.
Single Event Upset mitigation in SRAM using RC feedback network
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Modeled single event upset (SEU) of SRAM due to ionizing radiation
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The circuit was simulated in a HSPICE environment using Silvaco ATLAS tool. Radiation hardening technique was done to prevent the bit flip of SRAM cell.
Implemented a Cache replacement policy using SRRIP
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Implemented 2-bit Static Re-reference and Interval Prediction (SRRIP) Cache with Hit Promotion algorithm in simple scalar simulator. Compare the performance of SRRIP against LRU (Least Recently Used) policy for different benchmarks.
RELEVANT COURSE WORK VLSI Design, Computer Architecture, Hardware System Design, Advanced Analog Integrated Circuits, Digital Signal Processing, TCAD, Mixed-signal and RF Test.