Comparison of Dynamic Power saving with software and hardware DVFS for Low-Power Embedded Systems

Volume 2, Spl. Issue 2 (2015)

e-ISSN: 1694-2310 | p-ISSN: 1694-2426

Comparison of Dynamic Power saving with software and hardware DVFS for LowPower Embedded Systems Narender kumar1, Tejinder Singh2, Sanjeev Kumar3 Department of Electronics and Communication Engineering, Baddi University of Emerging Sciences and Technology, Baddi, Solan narender.k.s@baddiuniv.ac.in1 , tejinrdersingh@baddiuniv.ac.in2 , sanjeevbhatti@baddiuniv.ac.in3

Abstract-New age embedded systems to operate under an increasingly diverse range of power and performance constraints; they must be power aware, not just low-power. Nowadays, chip vendors are devoted to developing new power saving techniques in order to extend the battery life of portable devices such as mobile phone, multimedia player, portable media player and notebook etc.

Power consumption is a key issue in the design of portable embedded systems nowadays as it directly affects their battery life.

Still battery technologies are not very much efficient to match the advancements in the hardware design that drives these systems in the recent years. In this paper, a study of both software and hardware power saving methods is done. Moreover, there is extensively explored and emphasis is on many novel power management methods, ranging from voltage and frequency scaling.

Keyword- Dynamic power management (DPM), dynamic voltage scheduling frequency scaling (DVFS), EMA (Exponential Moving Average).

I. INTRODUCTION Mobile devices and embedded systems have been developed at very rate nowadays. In comparison to traditional desktop systems, embedded devices demand not only high processor performance but also have low power consumption. Energy consumption has become one of the most important design constraints for modern embedded systems especially for mobile systems that operate with a limited battery source.

For these Systems, the design process is characterized by a trade off between a need for high performance and low power consumption. Emphasis is on high performance to meeting the performance constraints while minimizing the power consumption. Lowering the power consumption not only improve the battery lifetime in portable mobile devices but is also a critical factor in minimizing the packaging and the cooling pad costs of embedded systems. Since most mobile devices are usually run on battery, a proper method in power consumption management will extend the battery life significantly. Efficiency in power consumption requires careful design for both hardware and software. Nowadays, chip vendors are devoted to developing new power saving techniques in order to extend the battery life of portable devices such as cell phone, media player, portable media player, palmtop etc.

In general, these techniques can be categorized into two types: Dynamic techniques and static techniques [1].

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Static techniques include different low-power modes, and clock gating etc.

The dynamic techniques are those that dynamically scale the CPU working frequency and voltage (CPU requires higher voltage when it runs at higher frequency) according to the performance requirement of current applications running on the CPU and achieve the goal of energy saving [1]. In theory, this technique comes from the formulas below: F (1) F*t (2) From the equations above, it can be seen that scaling down the frequency can only reduce the power in watt but can’t save the energy in joule consumed by a operation, because for a given operation, F*t is a constant. To minimize the energy consumption the voltage should also be scaled down when the frequency is decreasing.

Currently many VLSI chips support the dynamic voltage frequency scaling (DVFS) [1], [2], [3] feature. But the only supporting DVFS is not enough to save energy effectively.

The extensive design of software and hardware is needed.

II. DVFS WORKFLOW DVFS workflow consists of following steps: Step 1: Monitoring the signals related to the workload acquiring and calculating the current task workload. This task can be performed by either hardware or software. Most of the time software does this by installing hooks to the system calls especially the scheduler and calculating the workload according to the frequency these system calls are called.

Step 2: From calculated current workload, prediction of the performance requirement of system in the next time slice is done. Prediction can be done by either hardware or software as suitable for application.

Step 3: Predicted performance requirement is translated into frequency and adjusted the CPU clock accordingly.

Step 4: Calculated the new voltage corresponding to the new frequency and this information given to the power source block. Power source block adjust the voltage to CPU. The frequency and voltage should be adjusted in specific manner. Voltage should be decreased when frequency is 240

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adjusted from high to low. In the case of frequency up scaling, the voltage should be raised before the frequency is scaled up.

Figure 1 illustrates the simple workflow of DVFS

e-ISSN: 1694-2310 | p-ISSN: 1694-2426

All the algorithms above have their own advantages and disadvantages. For example LMS is similar to adaptive filter and can adjust parameters automatically but it faces convergence issue.

DVS feature is demonstrated in ARM with developed Vertigo. In this software based method the estimate of workload, deadline and performance is given by following equations: ( as described in, 8, 9, 10, & 11) Task’s Workload

(8)

Fig.1. Workflow of Prediction Based DVFS

In general the embedded system designers adopt software method to predict performance requirement of CPU according to the sequence of event priority in the software scheduler [4].

Workload Estimate

III. DVFS Realization Based on Software

Deadline Estimate

In the implementation of software based DVFS the hooks are installed to the system calls in the kernel. With the help of hooks generally usage data is collected about system call and system work load is estimated. The hooks are installed generally scheduler, read/write interfaces and timer etc.

Hooks are installed in Linux kernel is presented in following figure:

Fig.2. Conventional software DVFS [2]

When one predicts the system workload of next timing cycle, the acquired workload data of previous several time slots can be used [2]. The predicted workload can be gotten from

(3) The prediction algorithm varies with different values of h.  Previous Value o W[n+1] = w[n] (4)  Moving Average Workload o Hn[k]= 1/N ¥(n,k) (5)  Exponential Weighted Average o Hn[k]= α-1 (6)  Least Mean Square o Hn [k]=hn[k]+µ[n]w[n-k] (7)

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(9)

(10) Performance Estimate

(11)

This algorithm works well for those OS tasks whose workload changes slowly, e.g., MPEG decoder. In the Vertigo architecture, as soon as predictor finishes performance estimation it submits the result to a policy manager. The policy manager takes care of whether to accept the prediction result and adjust the performance setting [1].

Traditionally, the researchers and designers adopt software method predicts performance requirement of CPU according to the sequence of event priority in the software scheduler [4]. Fig. 4 shows one of the software DVFS method, which is still used according to the priority of all tasks in the operating system. This method is efficient in lowering power only in case when CPU frequency is not too high. It becomes difficult to further increase in frequency because software method cannot estimate the performance of CPU correctly in time. Moreover, what’s even more disconcerting is that the conventional software DVFS need to be called frequently in the operating system. To some degree, it is tedious to change the dynamic voltage and frequency by means of software scheduler. In a summary, the current approaches to DVFS can hardly keep up with the dormant frequency increase of new CPU so that new DVFS technology has to be considered [5].

IV. Hardware Realization of DVFS The job of load tracking and performance prediction can be performed by hardware designed CPU the use of hardware method provide the reliable way of load calculation and

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Volume 2, Spl. Issue 2 (2015)

e-ISSN: 1694-2310 | p-ISSN: 1694-2426

tracking and also reduces the overhead that generally required for estimation and calculation work load. Another limitation of this method is choice of prediction algorithm but this can somehow fixed by choosing proper prediction parameters.

Figure 3: Hardware architecture of DVFS [2] Fig.3 represents a block diagram of the implementation of this hardware architecture [2], which includes timing tracking, averaging, threshold checking and performance switching.

Freescale’s i.MX31 is a good example for this. An ARM core is integrated into this chip with inbuilt DVS technique from ARM and derives DVFS. In this chip, hardware automatically predict and tracks CPU. The CPU workload track diagram is shown in figure 4.

performance degradation within certain limits that so that it will not degrade to undesired level. Design of power management policies has been an active research area nowadays and several policies have been proposed in the past also. DPM is an inherently online problem and involves prediction or estimation real world load, which is pretty much unpredictable in nature. This is what makes it an extremely challenging and exciting research problem.

REFERENCES [1] Karl Lu Senior System and Architecture Engineer, Freescale Semiconductor (China) Limited, “Power saving with dynamic voltage and frequency scaling Low-Power,” EE Times-India, January 2007.

[2] Tiefeng Li, Caiwen Ma, Wenhua Li, “The Dynamic Voltage and Frequency Scaling Based On the On-Chip Microcontroller System,” Journal of Theoretical and Applied Information Technology, Vol. 51 No.1, 10th May 2013.

[3] Padmanabhan Pillai and Kang G. Shin, “Real-Time Dynamic Voltage Scaling for Low-Power Embedded Operating Systems,” Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science the University of Michigan.

[4] MinYeolLim, Vincent W. Freeh, David K. Lowenthal. “Adaptive transparent CPU scaling algorithms leveraging inter-node MPI communication regions,” Parallel Computing, Vol. 37(10–11), pp.

667-683 October–November 2011.

[5] Soheil Aminzadeh and Alireza Ejlali, “A Comparative Study of System-Level Energy Management Methods for Fault-Tolerant Hard Real-Time Systems,” IEEE Transactions On Computers, VOL. 60, NO. 9, September 2011.

[6] Jihong Kim, Tajana Simunic Rosing, “Power-Aware Resource Management Techniques for Low-Power Embedded Systems,” July 2006.

Figure 4: i.MX31 DVFS Load Tracking Module Block Diagram [1] In Figure 4 above, 16 general purpose workload signals are sampled and weighted. The next block load adder add CPU idle signal with these weighted sum signal. The output of the load adder is given to the EMA block which operates the incoming data with algorithm and predicts required performance. The estimated data from EMA is compared with threshold values.

IV. CONCLUSION In this paper we looked at hardware and software approaches people have proposed for dynamic power saving using DVFS. However employing such techniques also result in performance loss because of the overhead associated with shutdowns and wakeups. For an effective DPM policy must therefore seek to maximize power savings while keeping BUEST, Baddi

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