Int. Journal of Electrical & Electronics Engg.
Vol. 2, Spl. Issue 1 (2015)
e-ISSN: 1694-2310 | p-ISSN: 1694-2426
Design and Analysis of CMOS Instrumentation Amplifier Aayushi Sharma Chitkara University, Himachal Pradesh,India
Abstract-This paper presents the design and analysis of CMOS Instrumentation Amplifier in terms of gainas a performance metric. CMOSInstrumentation Amplifier has been designed using three Operational Amplifiers. Two basic op-amps have been used at the input stage and the output stage have been analysed for three different configurations. These configurations are: basic op-amp, body bias op-amp and folded cascode op-amp. A comparison has been drawn for all the three configurations.Most of the previous work has been done usingthe same type of op-amp at both the input and output stages of instrumentation amplifier. To obtain the desirableGain, focus has been laid upon transistor sizing for designing. The design models have been implemented using Cadence Virtuoso Analog Design Suite in 0.18µm CMOS technology.The simulations have been analysed in detail. A significant gain improvement has been observed in the circuit design with body bias and folded cascode as compared to the basic cascade design. Keywords- Instrumentation amplifier, Gain, Folded cascode amplifier, Body Bias
INTRODUCTION Instrumentation amplifier aims at the amplification of the desired signal and elimination of the noisy signals or the common mode signals that affect the original signal strength. The amplification of very weak amplitude signals in the order of few mV is a challenging task.With the help of simple operational amplifiers one is able to strengthen these weak signals along with the noise amplification. Instrumentation amplifiers are a kind of the differential amplifier which consists of the input buffer amplifier so that the need for the input impedance matching is not required.Other characteristics like low noise, low dc offset,high open-loop gain, high common mode rejection ratio and high input impedance [1].Gain improvement can be achieved by cascading of stages.Due to the very high common mode rejection ratio and less power requirement these instrumentation amplifiers are used in various applications. The rest of the paper is organized as follows:Section II describes the instrumentation amplifier design. Simulation results are discussed in SectionIII and section IV concludes the paper.
Output Stage Input Stage
Fig.1
Instrumentation Amplifier Circuit[2]
Table I shows the value of different resistances considered for the circuit design. The values of resistances are set such that to R3=R4=R5=R6 and R1 is very small as compared to other resistors to achieve high gain. The output voltage of the instrumentation amplifieris given by Vout=-(
−
)*(1+2
/
)(
/
)
TABLE I. Resistance Values Resistors
Resistance Value (Ω)
R1 R2, R3 R4, R5, R6
100 20K 20K
Operational Amplifier 1 and 2 have been designed using Differential Amplifier connected in non- inverting configuration followed by CommonSource Amplifier circuit as shown in fig 2 and 3. Current MirrorLoad
Differential Pair
INSTRUMENTATIONAMPLIFIER DESIGN The basic cascade instrumentation amplifier has been designed using three op-amps, two at the input side and one at the output as shown in fig 1. The input side of all the three implemented configurations is the same. However, at the output stage the circuit has been designed and analyzed for three different configurations. Fig. 2Input Stage of Operational Amplifier
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Int. Journal of Electrical & Electronics Engg.
Vol. 2, Spl. Issue 1 (2015)
e-ISSN: 1694-2310 | p-ISSN: 1694-2426
Fig. 3Common Source Output Stage of Operational Amplifier
Operational Amplifier 3 has been designed in three different styles and a comparison has been drawn amongst them in terms of gain as a performance metric. In the first configuration the op-amp in the output stage is same as the op-amp in the input stages as shown in fig 2 and 3. In the second configuration the differential amplifier stage remains the same as in fig 2 but body bias common source amplifier is used at the output stage of operational amplifier as shown in fig 4.
Fig.5Folded Cascode Operational Amplifier Output Stage of Instrumentation Amplifier
SIMULATION RESULTS AND DISCUSSION The schematic of the implemented Instrumentation Amplifier has been generated in Virtuoso Schematic Editor. Cadence Spectre has been used for circuit simulator in 180 nm CMOS Technology node. A 5mV amplitude signal at the input has been applied. The output AC response has been plotted within the frequency range of 10Hz to 100 MHz Fig. 6 and 7 shows the Gain vs. Frequency plot in Magnitude and dB for the first configuration in which the op-amp in the output stage is same as the op-amp in the input stage.
Fig.4 Body Bias Common Source Amplifier at the output stage of Operational Amplifier 3
In the third configuration, folded cascode technique is used to design the output stage op-amp of the instrumentation amplifier as shown in fig 5. Folded cascode is the cascade of a common source stage and a commongate stage.
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Fig.6
Gain curve in magnitude
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Int. Journal of Electrical & Electronics Engg.
Vol. 2, Spl. Issue 1 (2015)
e-ISSN: 1694-2310 | p-ISSN: 1694-2426
Fig.10 Fig.7
Gain curve in decibels
Gain curve in magnitude
Fig. 8 and 9 shows the Gain vs. Frequency plot in Magnitude and dB for the second configuration in which the differential amplifier stage remains the same but body bias common source amplifier is used at the output stage of operational amplifier.
Fig.11
Fig.8 Gain curve in magnitude
Gain curve in decibels
Tables II.shows the comparison for three different configurations: basic op-amp, body bias op-amp and a folded cascode op-amp. TABLE II: Comparison between basic op-amp, body bias op-amp and a folded cascode op-amp
.
Parameters Technology (μm) Supply voltage (v) Gain (dB)
Cascade design 0.18
body biased 0.18
cascode design 0.18
1.8
1.8
1.8
1.24
1.8
33.67
The abrupt increase in the gain of the folded cascode design as compared to the other two techniques is due to the transistors sizing. The differential pair used is to keep a check upon input voltage difference and is made to operate in saturation region not in triode region. Table III gives the aspect ratio(W/L) of the various transistors used in the folded cascode configuration. Fig.9
Gain curve in decibels
Fig. 10 and 11 shows the Gain vs. Frequency plot in Magnitude and dB for the third configuration,in which the folded cascode technique is used to design the output stage op-amp of the instrumentation amplifier.
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TABLE III: OUTPUT FOLDED CASCODE STAGE OP-AMP TRANSISTOR SIZING[2]
Transistors
Aspect Ratio(W/L)
MN1,NM2 MN3,MN4 MN5,MN6 MP1,MP2 MP3.MP4
5μ/200n 3μ/200n 20μ/200n 20μ/200n 20μ/200n
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MP5,MP6 MN8 MN7
Vol. 2, Spl. Issue 1 (2015)
e-ISSN: 1694-2310 | p-ISSN: 1694-2426
50μ/200n 5μ/200n 10μ/200n
CONCLUSION A comparative study and analysis for three different configurations: basic op-amp, body bias op-amp and a folded cascode op-amp has been done.Analysis shows that the folded cascode design achieves comparatively high gain as compared to thetwo stage Cascade Op-Amp design and body biased design. REFRENCES [1] BehzadRazavi, Design of Analog CMOS Integrated Circuits, Tata McGraw Hill Education. [2]Goel, A. and Singh, G.,” Novel High Gain Low Noise CMOS Instrumentation Amplifier for Biomedical Applications”,Machine Intelligence and Research Advancement (ICMIRA), 2013 International Conference on ,PP. 392 – 396, 2013, IEEE [3]S. Kirthy,“Performance Analysis of a High Gain CMOS Instrumentation Amplifier for Biomedical Signal Processing”,International Journal of Electronic and Electrical Engineering. ISSN 0974-2174 VOLUME 7, NUMBER 10 (2014), PP. 1133-1133 [4]Rajni, “Design of High Gain Folded-Cascode Operational Amplifier Using 1.25 um CMOS Technology” International Journal of Scientific & Engineering Research Volume 2, Issue 11, November-2011 ISSN 2229-5518 [5]Yasin FM; Yap M.T and Reaz,M.B.I, “CMOS instrumentation amplifier with offset cancellation circuitry for biomedical applications,” In Proc. Of 5th WESEAS,2006,spain,pp 168-171. [6]Shojaei-Baghini, M. Lal, R.K Sharma and D.K,” An ultra lowpower CMOS instrumentation amplifier for biomedical applications”, Biomedical circuits and systems,2004 IEEE International Workshop On, S1/1-S1,2004,IEEE. [7]Chih-Jen Yen; Wen-Yaw Chung and Mely Chen Chi, “Micropower low offset instrumentation amplifier IC design for biomedical system applications” IEEE Transactions On Circuits and Systems-I: Regular Papers, Vol.51,No.4, pp 691-699 april 2004. [8] R. C. Yen and P. R. Gray, “A MOS switched-capacitor instrumentation amplifier,” IEEE J.Solid-State Circuits, vol. SC17, pp. 1008–1013, Dec. 1982. [9]Ramakant A. Gayakward, op-amps and linear integrated circuits: Pearson Education.
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