Design of CMOS Inverter for Low Power and High Speed using Mentor Graphics

Int. Journal of Electrical & Electronics Engg.

Vol. 2, Spl. Issue 1 (2015)

e-ISSN: 1694-2310 | p-ISSN: 1694-2426

Design of CMOS Inverter for Low Power and High Speed using Mentor Graphics 1

Rachna Manchanda, 2Chanpreet Kaur 1,2

1,2

Assistant Professor Department of Electronics and Communication, CEC landran

1

Cecm.ece.rm@gmail.com, 2cecm.ece.ctoor@gmail.com

ABSTRACT:- In parallel with enhancements in the technology low power consumption have emerged as a primary design constraint in digital VLSI. This is due to the increasing demand of portable battery operated devices in the VLSI circuit design. This really implies a need to balance ultra low power with area efficient design.

So the only way to minimize energy per operation is to decrease VDD. The inverter is designed using 25nm technology in mentor graphics is presented. Further the designing is followed by the layout of the inverter is done in this paper.

KEYWORDS: Mentor Graphics, Pyxis Schematic, ELDO, Pyxis layout, Delay, temperature, Rise time, fall time.

INTRODUCTION The level of integration keeps on growing more and more refined as signal processing systems get implemented on a Very Large Scale Integration (VLSI) chip. The CMOS technology has emerged as a predominant technology in the field of nano electronics.

As the technology become compact there is rapid increase in demand of high performance and also low power digital systems [1]. These signal processing applications demands great computation capacity and consume considerable amounts of energy. While the performance and the area remain to be two major design issues, power consumption has become a critical concern in today’s VLSI system designing. The power consumption of a design determines how much energy is consumed per operation and much heat the circuit dissipates [1].

These above given factors influence a great number of demanding design decisions, such as the power-supply capacity, supply-line sizing, packaging, the battery lifetime and cooling requirements. Digital circuits in VLSI design have become more advent in recent years because of its large amount of applications. So there is need to develop low power design methodologies to design these circuits.

Propagation delay and power dissipation are two major issues for the design & synthesis of any VLSI circuits in this range [2]. Power dissipation limitations come in two ways. The first is related to cooling applications when the implementation of high performance systems is to be done. The high speed circuits dissipate very large amount of energy in a very short amount of time and generating a great amount of heat. This heat needs to be removed by the package on which integrated circuits are mounted. The second failure of high-power circuits relates to the increasing popularity of portable electronic devices. Laptop computers, compact video 71

players and cellular phones all use batteries as a power source [3].

To extend the battery life, low power operation is needed in integrated circuits. This paper briefly presents the concept of effect of temperature and delay at different voltages at 25 nm technology in mentor graphics.

CHARACTERISTICS OF CMOS CMOS circuits are made in such a way that all the PMOS transistors known as pull up networks are always connected to the voltage source or from another PMOS transistor. On the same hands all NMOS transistors known as pull downs are having either an input from ground or from another NMOS transistor [4]. The PMOS transistor is designed in such a way that it creates low resistance between its source and drain contacts, when a low gate or negative voltage at the gate of the PMOS transistor and high resistance when a high gate voltage or positive voltage is applied.

On the other hand, the NMOS transistor creates high resistance between its source and drain contacts, when a low gate or negative voltage is applied and low resistance when a high gate or positive voltage is applied.

CMOS accomplishes the current reduction by complementing every nMOSFET with a pMOSFET and connecting both gates and both drains together. A high voltage on the gates of transistor will cause the nMOSFET to be in conducting state and the pMOSFET to be in non conducting state, while a low voltage on the gates causes the reverse operation. This will reduces the power consumption and heat generation. Therefore, during the switching time both MOSFETs will conducts as the gate voltage changes from one state to another [5]. This induces a spike in power consumption and becomes a serious issue at high frequencies.

INTRODUCTION DESIGN STEPS TO MENTOR GRAPHICS TOOL The Mentor Graphics HEP2 tools for the flow of the Full Custom IC design cycle is used. It will run the DRC, LVS and Parasitic Extraction on all the designs. Initial step is to create a schematic and attach the technology library called “TSMC025”.

Other options for choosing the library are also included.

Adding a technology library will ensure that the design can be done on front to back design. A new cell called “Inverter” with schematic view is designed a01nd hence build the inverter schematic by initializing various components. Once the inverter schematic is done, symbol NITTTR, Chandigarh EDIT-2015

Int. Journal of Electrical & Electronics Engg.

Vol. 2, Spl. Issue 1 (2015)

for “Inverter” is generated. Now it will create a new cell view called “Inverter1”, here it will instantiate “Inverter” symbol. This circuit is verified by doing various simulations using ELDO. In the process EZviewer will show the waveform window options, waveform calculator, etc... The Pyxis Layout Editor is based on concentrating the design an “Inverter” through automatic layout generation, with completing the other layouts, generating steps, GDSII file. After that, by taking GDSII file as reference it will run DRC, LVS checksum the layout, Extract parasitic and back-annotate them to the simulation environment.

SCHEMATIC OF INVERTER In this paper, Schematics of inverter are drawn and the simulations are performed by ELdo simulator in pyxis Schematic. Eldo provides the most advanced simulation technology and provides extensive simulation capabilities.

e-ISSN: 1694-2310 | p-ISSN: 1694-2426

Fig 4- DC Simulation result of inverter

Another simulation result is for the transient response of the inverter both for the input and the output of the inverter as shown in fig 5. Here it is observed that output of the inverter is inverted. Here V(y) is the output of the inverter and V (a) is the input to the inverter.

Fig 2- Schematic view of inverter

Its advanced various analysis can be performed like DC analysis, transient analysis, DC mismatch, sensitivity, aging analysis, optimization of parameters, distributed computing, multi-threading, RC reduction, pole-zero, Monte-Carlo analysis, distributed computing, Sparameters, S-domain and Z-domain transfer functions can be obtained.

Here a 4 pin P-MOS and N- MOS Transistor are used in pyxis schematic as shown in fig 2. Here VDD is attached to the P-MOS inverter and ground is attached to N-MOS inverter.

Fig 5- Simulated output of the inverter

PRACTICAL OBSERVATIONS Calculation of power dissipation, delay, fall time, rise time is observed for the Simulation results under 27 degrees temperature as mentioned in table 1 given below.

Table 1- Various parameters using different VDD

VDD

3V 1.5V 1.3 V 1.1 V

Fig 3- schematic view of inverter symbol with a pulse input and a DC source

In fig 3 a symbol is generated of CMOS inverter and a pulse is applied to the input port of inverter. Pulse is of 3 V and period of pulse is 50ns is set. Similarly a DC voltage of 1.1 to 3 V is applied to the VDD of inverter.

SIMULATION RESULT Here are the simulation results of the inverter. Fig 4 is the DC simulation result of inverter. V(a) shows the graph of the input to the inverter is starting from zero to the final value of 3V, and V(y) Shows in below figure that output is inverted from 3 V to 0V.

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POWER DISSIPA TION 13.9997P ATTS 2.1273P WATTS

DELAY

FALL TIME

RISE TIME

21.165ns

133.36 ps

239.54 ps

21.310 ns

87.683 ps

181.57 ps

2.8832P WATTS 2.1273P WATTS

21.381 ns 21.447 ns

81.790 ps 63.853 ps

127.82 ps 97.420 ps

From the table 1 it is observed that power dissipation of inverter is reduced as VDD is reduced from 3V to 1.1 V. Delay is also calculated for various applied voltages. The fall time and Rise time of output waveform is also reduced for the when VDD is decreased.

PYXIS LAYOUT FOR INVERTER The same design of inverter is being implemented on pyxis layout in mentor graphics as shown if figure 5. Layout is the fabrication mask of the design for IC manufacturing.

For the low power and high speed inverter design, Layout is drawn using these following layers - Nwell layer, P

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Int. Journal of Electrical & Electronics Engg.

Vol. 2, Spl. Issue 1 (2015)

e-ISSN: 1694-2310 | p-ISSN: 1694-2426

diffusion, N diffusion, poly silicon, vias, and metal 1 contact.

Fig 5 - Inverter layout on pyxis layout tool

CONCLUSION The proposed design shows low power, high speed inverter by using TSMC025 is done. Here the power is dissipation is less for low voltages as well as fall time, rise time is also reduced. Further the inverter layout is also designed using DRC and LVS tools.

REFERENCES [1] Adil Zaidi, Kapil Garg, Ankit Verma, Ashish Raheja “Design & Simulation of CMOS Inverter at Nanoscale beyond 22nm “ in International Journal of Emerging Science and Engineering (IJESE) ISSN: 2319–6378, Volume-1, Issue5, March 2013 ,Pages: 83-87.

[2] Srinivasa Rao.Ijjada, S.V.Sunil Kumar, M. Dinesh Reddy, Sk.Abdul Rahaman, Dr.V. Malleswara Rao, “DESIGN OF LOW POWER AND HIGH SPEED INVERTER,” (IJDPS) Vol.2, No.5, September 2011, pages: 127-134.

[3] Jagannath Samanta, Bishnu Prasad De, Banibrata Bag, Raj Kumar Maity “Comparative study for delay & power dissipation of CMOS Inverter in UDSM range “ in International Journal of Soft Computing and Engineering (IJSCE) ISSN: 2231-2307, Volume-1, Issue-6, January 2012 , pages: 162-167.

[4] K. Roy, S. Mukhopadhyay, H. Mahmoodi-Meimand, “Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits,” Proceedings of the IEEE, vol. 91, no. 2, Feb. 2003, pages: 305-327.

[5] CMOS VLSI Design, NEIL H.E. WESTE, IEEE 2006.

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