Int. Journal of Electrical & Electronics Engg.
Vol. 2, Spl. Issue 1 (2015)
e-ISSN: 1694-2310 | p-ISSN: 1694-2426
Codec Scheme for Power Optimization in VLSI Interconnects 1
Dhriti Duggal,2Rajnish Sharma
1,2
Chitkara University, Himachal Pradesh, India
1
dhriti.duggal@chitkarauniversity.edu.in, 2rajnish.sharma@chitkarauniversity.edu.in
Abstract— This paper presents a codec scheme for optimizing power in VLSI Interconnects. It is based on the traditional bus encoding method which is considered to be one of the most effective ways of power and delay reduction. The work done aims at optimizing power by designing the scheme using Full-Custom design approach. The model has been designed and implemented using Cadence Virtuoso Analog Design Suite in 0.18µm CMOS technology. Power has been computed for different possible combinations of input data. Delay has been reckoned for the maximum power consuming input combination. Layout editor has been used to generate the physical description of the circuit. The 4 bit input data combination consuming maximum dynamic power of 6.44µW and propagation delay of 722.7ps is “1000” with previously transmitted 4 bit data being “0111”. A significant power reduction of 38.89% has been observed by designing the scheme using Full-Custom approach as compared to the conventional Semi-Custom approach of design.
Where, CL is the load capacitance, VDD is supply voltage, fCLK is the clock frequency and α is the average activity factor or the switching factor whose value lies between 0 and 1. This paper focuses on bus encoding method for reducing power dissipation of VLSI Interconnects by reducing the switching activity. The rest of the paper is organized as follows: Section II discusses the types of couplings in interconnects. Section III describes the implemented codec scheme. Results have been discussed in Section IV and Section V concludes the paper. II. COUPLINGS IN INTERCONNECTS The coupling between groups of three wires is classified into five types depending upon the nature of transitions of signals in the wires that are Type-0, Type-1, Type-2, Type3 and Type-4 as shown in Table 1 [3-6].
Keywords— Interconnects, Couplings, Power Dissipation, Layout Implementation. TYPE-0
I. INTRODUCTION For System on Chip (SOC) and Network on Chip (NOC) designs in Deep Submicron era, interconnects play an important role in the overall performance of the chip. They are used to distribute clock and other signals and to provide power/ground to and among the various circuits/systems functions on the chip [1, 2]. Interconnects consume around 44% of the total chip area and hence it becomes very important to estimate and minimize the power consumed by them. Coupling Capacitance located between the wire and its adjacent wires is important to analyze because it slows down the signal. It can become the major component of delay if the switching and coupling activities between the group wires are not minimized. Further it may also lead to Crosstalk and Signal Integrity related issues, which in the worst of the cases may lead to the complete circuit malfunction if not modeled properly [3-6]. There are various methods to reduce the crosstalk, power consumption and propagation delay but bus encoding method is one of the most efficient methods [3]. It reduces power consumption and crosstalk by bringing reduction in the switching activity that is by reducing the number of power consuming voltage transitions experienced by the output capacitance/clock cycle. Power consumption sources in digital CMOS circuits are broadly classified into three main categories: static, shortcircuit and dynamic power dissipation [7]. Dynamic power dissipation is one of the most dominant sources of power dissipation in CMOS circuits which cannot be ignored. Thus, to optimize power in any design successfully, dynamic power has to be estimated and minimized separately. The dissipated power is expressed as: Pdiss = α* VDD2* fCLK* CL (1) NITTTR, Chandigarh
EDIT -2015
˗˗˗ ↑↑↑ ↓↓↓
Table I. 3 bit bus couplings TYPE-1 TYPE-2 TYPE-3
˗ ˗↑ ˗↑↑ ↑˗ ˗ ↑↑˗ ˗ ˗↓ ˗↓↓ ˗ ˗↓ ↓↓ ˗
˗↑˗ ↑↑ ˗ ↑˗↓ ↑↑↓ ↑↓↓ ˗↓˗ ↓˗↓ ↓˗↑ ↓↓↑ ↓↑↑
TYPE-4
˗ ↑↓ ˗ ↓↑ ↑↓ ˗ ↓↑ ˗
↑↓↑ ↓↑↓
↑: transition from 0 to 1; ↓: transition from 1 to 0; ˗: no transition
Type-0 coupling occurs when all the 3 bit wires undergo the same transition [1-2].Type-1 coupling occurs when there is transition in one or maximum two wires (including the centre one) while the third wire remains quite [12].Type-2 coupling occurs when the centre wire is in the opposite state transition with one of its adjacent wires while the other wire undergoes the same state transition as the centre wire [1-2]. Type-3 coupling occurs when the centre wire undergoes the opposite state transition with one of the two wires while the other wires are quite[1-2].Type4 coupling occurs when all the three wire transitions in the opposite state with respect to each other[1-2]. III. IMPLEMENTED CODEC SCHEME Fig 1 shows the block diagram of the implemented codec scheme. Transition Detector compares the present 4 bit input data with the previously transmitted 4 bit data. Output of the transition detector acts as an input to the coupling detectors which help in detecting crosstalk couplings. XOR Stacks are used at both the encoder and decoder side to transmit and receive data. 96