Int. Journal of Electrical & Electronics Engg.
Vol. 2, Spl. Issue 1 (2015)
e-ISSN: 1694-2310 | p-ISSN: 1694-2426
Codec Scheme for Power Optimization in VLSI Interconnects 1
Dhriti Duggal,2Rajnish Sharma
1,2
Chitkara University, Himachal Pradesh, India
1
dhriti.duggal@chitkarauniversity.edu.in, 2rajnish.sharma@chitkarauniversity.edu.in
Abstract— This paper presents a codec scheme for optimizing power in VLSI Interconnects. It is based on the traditional bus encoding method which is considered to be one of the most effective ways of power and delay reduction. The work done aims at optimizing power by designing the scheme using Full-Custom design approach. The model has been designed and implemented using Cadence Virtuoso Analog Design Suite in 0.18µm CMOS technology. Power has been computed for different possible combinations of input data. Delay has been reckoned for the maximum power consuming input combination. Layout editor has been used to generate the physical description of the circuit. The 4 bit input data combination consuming maximum dynamic power of 6.44µW and propagation delay of 722.7ps is “1000” with previously transmitted 4 bit data being “0111”. A significant power reduction of 38.89% has been observed by designing the scheme using Full-Custom approach as compared to the conventional Semi-Custom approach of design.
Where, CL is the load capacitance, VDD is supply voltage, fCLK is the clock frequency and α is the average activity factor or the switching factor whose value lies between 0 and 1. This paper focuses on bus encoding method for reducing power dissipation of VLSI Interconnects by reducing the switching activity. The rest of the paper is organized as follows: Section II discusses the types of couplings in interconnects. Section III describes the implemented codec scheme. Results have been discussed in Section IV and Section V concludes the paper. II. COUPLINGS IN INTERCONNECTS The coupling between groups of three wires is classified into five types depending upon the nature of transitions of signals in the wires that are Type-0, Type-1, Type-2, Type3 and Type-4 as shown in Table 1 [3-6].
Keywords— Interconnects, Couplings, Power Dissipation, Layout Implementation. TYPE-0
I. INTRODUCTION For System on Chip (SOC) and Network on Chip (NOC) designs in Deep Submicron era, interconnects play an important role in the overall performance of the chip. They are used to distribute clock and other signals and to provide power/ground to and among the various circuits/systems functions on the chip [1, 2]. Interconnects consume around 44% of the total chip area and hence it becomes very important to estimate and minimize the power consumed by them. Coupling Capacitance located between the wire and its adjacent wires is important to analyze because it slows down the signal. It can become the major component of delay if the switching and coupling activities between the group wires are not minimized. Further it may also lead to Crosstalk and Signal Integrity related issues, which in the worst of the cases may lead to the complete circuit malfunction if not modeled properly [3-6]. There are various methods to reduce the crosstalk, power consumption and propagation delay but bus encoding method is one of the most efficient methods [3]. It reduces power consumption and crosstalk by bringing reduction in the switching activity that is by reducing the number of power consuming voltage transitions experienced by the output capacitance/clock cycle. Power consumption sources in digital CMOS circuits are broadly classified into three main categories: static, shortcircuit and dynamic power dissipation [7]. Dynamic power dissipation is one of the most dominant sources of power dissipation in CMOS circuits which cannot be ignored. Thus, to optimize power in any design successfully, dynamic power has to be estimated and minimized separately. The dissipated power is expressed as: Pdiss = α* VDD2* fCLK* CL (1) NITTTR, Chandigarh
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˗˗˗ ↑↑↑ ↓↓↓
Table I. 3 bit bus couplings TYPE-1 TYPE-2 TYPE-3
˗ ˗↑ ˗↑↑ ↑˗ ˗ ↑↑˗ ˗ ˗↓ ˗↓↓ ˗ ˗↓ ↓↓ ˗
˗↑˗ ↑↑ ˗ ↑˗↓ ↑↑↓ ↑↓↓ ˗↓˗ ↓˗↓ ↓˗↑ ↓↓↑ ↓↑↑
TYPE-4
˗ ↑↓ ˗ ↓↑ ↑↓ ˗ ↓↑ ˗
↑↓↑ ↓↑↓
↑: transition from 0 to 1; ↓: transition from 1 to 0; ˗: no transition
Type-0 coupling occurs when all the 3 bit wires undergo the same transition [1-2].Type-1 coupling occurs when there is transition in one or maximum two wires (including the centre one) while the third wire remains quite [12].Type-2 coupling occurs when the centre wire is in the opposite state transition with one of its adjacent wires while the other wire undergoes the same state transition as the centre wire [1-2]. Type-3 coupling occurs when the centre wire undergoes the opposite state transition with one of the two wires while the other wires are quite[1-2].Type4 coupling occurs when all the three wire transitions in the opposite state with respect to each other[1-2]. III. IMPLEMENTED CODEC SCHEME Fig 1 shows the block diagram of the implemented codec scheme. Transition Detector compares the present 4 bit input data with the previously transmitted 4 bit data. Output of the transition detector acts as an input to the coupling detectors which help in detecting crosstalk couplings. XOR Stacks are used at both the encoder and decoder side to transmit and receive data. 96
Int. Journal of Electrical & Electronics Engg.
Vol. 2, Spl. Issue 1 (2015)
e-ISSN: 1694-2310 | p-ISSN: 1694-2426
Fig. 1 Block Diagram of the implemented codec scheme
Layout of different blocks of the implemented codec scheme are shown in the figures below: Fig 2 shows the layout of the transition detector which acts as a comparator and is used to compare the 4 bit present input data with previously transmitted 4 bit data on the same data lines. The combination of first four NOT and AND gates are used to detect ‘low’ to ‘high’ transitions on the data bus whereas the combination of last four NOT and AND gates are used to detect ‘high’ to ‘low’ transitions on the data bus.
Fig. 3 Layout of Type-2 Coupling Detector
1 bit output of the individual coupling detectors acts as an input to the 5 input OR gate which is used to generate the desired 1 bit control signal as shown in fig 4. If its output is ‘high’ then the inverted data is sent to the output side using XOR stack 1 and if its output is ‘low’ then the original data is sent to the output side using XOR stack 1. Fig. 2 Layout of Transition Detector
8 bit output of the transition detector acts as an input to the coupling detectors where type-0, type-1, type-2, type-3 and type-4 coupling detector individually are used to detect the occurrence of any of the types of type-0, type-1,type2,type-3 and type-4 crosstalk couplings. Further it generates a 1 bit output signal. If any of the output signal is ‘high’ it indicates the occurrence of that particular crosstalk coupling else not. Fig 3 shows the layout of type2 coupling detector which covers the maximum number of coupling cases as explained in table I. Similar ways, layouts of all other coupling detectors have been designed.
Fig. 4 Layout of 5 Input OR gate
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Int. Journal of Electrical & Electronics Engg.
Vol. 2, Spl. Issue 1 (2015)
Fig 5 shows XOR Stack 1 which is used to transmit the data to the decoder end according to the implemented logic and the status of the control signal. A similar type of XOR stack is used at the output end to decode the received information depending upon the implemented logic and the status of the control signal
1100 1101 1110 1111
e-ISSN: 1694-2310 | p-ISSN: 1694-2426
1011 1100 1101 1110
2.540 1.521 1.848 1.521
2.917 1.582 2.074 1.586
Table III. Power and delay results for the worst combination when present and previous data is “1000” and “0111”
Total power (mW) Dynamic power (µW) Total delay (ps)
Pre layout 2.937 5.40 402.4
Post layout 3.508 6.44 722.7
Table IV shows the comparison of present work with previously done work in terms of power consumption and propagation delay. TABLE IV. Comparison of present work with previous work
Fig. 5 Layout of XOR Stack 1
IV. RESULTS AND DISCUSSION The design has been implemented using Cadence Virtuoso Analog Design Suite in 0.18µm technology. Virtuoso layout editor has been used to generate the physical description of the circuit. Table II highlights the total pre and post layout power consumption of the implemented codec scheme individually for all 16 possible combinations of present and previous data. Power and delay results for the maximum power consuming present and previous data are shown in table III. Table II. Total power results
Present data
Previous Data
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010
1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001
Pre-layout total power consumption (mW) 2.705 1.521 1.851 1.521 2.542 1.521 1.849 1.519 2.937 1.521 1.849
1011
1010
1.521
NITTTR, Chandigarh
Post-layout total power consumption (mW)
1.592
3.190 1.590 2.072 1.590 2.929 1.590 2.082 1.592 3.508 1.592 2.082
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Parameter [1] Present Work Power (µW) 10.54 6.44 Propagation Delay 296 722.7 (ps) There is a significant improvement of 38.89% in power consumption in the work done as compared to the previous work. A codec scheme has been presented which focuses mainly on reducing the switching and coupling activity so as to reduce the power consumption. Modeling the complete scheme using Full-Custom design approach has been the focus point instead of using the traditional SemiCustom approach of design. Full-Custom design methodology gives the liberty to the designer to specify the layout of each and every transistor and the interconnections between them. Whereas, in case of Semi-Custom designing pre defined and pre characterized libraries are used, not giving the privilege of complete customization to the designer. Though there has been improvement in power but increase in delay has been observed in the present work as previous work focused the research on couplings associated with either RC or RLC modeled interconnects. In the present work, stress has been laid upon both of them equally. The scheme has been designed for all types of crosstalk couplings rather than focusing on only inductive or resistive couplings in particular leading to a trade-off between power and delay. V. CONCLUSION Codec Scheme implementation for optimizing power in VLSI Interconnects has been presented. The pre and post layout results have been compared. Also the comparison of the present design has been done with the previously done work in terms of power and propagation delay and a significant improvement in dynamic power consumption has been observed. REFERENCES [1]Deepika Agarwal, G. Nagendra Babu, B.K. Kaushik, S.K. Manhas, “Reduction of Crosstalk in RC Modeled Interconnects with Low Power Encoder” Emerging Trends in Networks and Computer Communications (ETNCC),IEEE International Conference, pp. 115120, 2011. [2]G. Nagendra Babu, Deepika Agarwal, B.K. Kaushik, S.K. Manhas, Brijesh Kumar “Crosstalk avoidance in RLC modelled interconnects using low encoder,” Recent advances in Intelligent Computational Systems (RAICS),pp 921-924, 2011.
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[3]Chih-Peng Fan and Chia-Hao Fang, “Efficient RC Low-power bus encoding methods for Crosstalk reduction,” Integration VLSI Journal, Elsevier, vol. 44, no. 1, pp. 75-86, Jan. 2011. [4]M.R Stan, and W.P. Burleson, “Bus-Invert Coding for Low-power I/O,” IEEE Trans. On Very Large Scale Integration System, vol.3, no. 1, pp. 49-58, March 1995. [5]S.K. Verma and B.K. Kaushik, “A Bus Encoding Method for Crosstalk and Power Reduction in RC Coupled VLSI Interconnects” International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.2, April 2012, pp.29-39.
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[6]S.K. Verma and B.K. Kaushik ,“Crosstalk and Power Reduction Using Bus Encoding in RC Coupled VLSI Interconnects” Third International Conference on Emerging Trends in Engineering and Technology (ICETET), IEEE computer society, November 2010, pp.735-740. [7]Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic, “Digital Integrated Circuits,” 2nd Edition, PrenticeHall Publication, 2003.
NITTTR, Chandigarh
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