Int. Journal of Electrical & Electronics Engg.
Vol. 2, Spl. Issue 1 (2015)
e-ISSN: 1694-2310 | p-ISSN: 1694-2426
Layout Design Analysis of SR Flip Flop using CMOS Technology Avneet Kaur Department of ECE, National Institute of Technical Teachers’ Training & Research, Chandigarh, India avneetkaur.ak92@gmail.com
Abstract:- This paper presents an area, delay and power efficient design of SR flip flop. As the chip manufacturing technology is on the threshold of evaluation, which shrinks a chip in size and enhances its performance, here the flip flop is implemented in a layout level which develops an optimized design using recent CMOS layout tools. The proposed SR flip flop has been designed and simulated using 45nm technology. After that, parametric analysis has been done. In this paper, flip flop has been developed using full automatic design flow and semi-custom design flow. The performance of SR flip flop layouts using different design flows has been analyzed and compared in terms of area, delay and power consumption. The simulation results show that the design of SR flip flop using semi-custom design flow improved the area occupied by 46.9% and power consumption is reduced by 38.4%. Keywords: Bistable circuits, Latches, Flip flops, CMOS integrated circuits, Design methodology
1. INTRODUCTION A flip flop is an electronic circuit that has two stable states and can be used to store information. The circuit can be made to change its state by applying signals to one or more control inputs and will have one or two outputs. Flip flops are often used in computational circuits to operate in selected sequences during recurring clock intervals to receive and maintain data for a limited period of time sufficient for other circuits within a system to further process data [1]. Thus, flip flops are the basic storage elements in a sequential logic circuit. Memory elements play a vital role in digital world and the basic memory elements are latches and flip flops. These bistable circuits are the basic building blocks of a data path structure. They allow for the storage of data processed by combinational circuits and synchronization of operation at a given clock frequency [2]. For high performance chip design in VLSI, the choice of the back-end methodology has a significant impact on the design time and the design cost. Latches and flip flops directly impact the power consumption and speed of VLSI systems [3]. The main improvement in terms of feature size reduction for CMOS integrated circuits is increased number of metal interconnects to link MOS devices together within the chip [4]. Also, in synchronous systems, any violation of the timing constraints of the flip flops can cause the overall system to malfunction. Moreover, the process variations can create a large variability in flip flop delays impacting the timing yield [5]. Flip flops have a wide area of applications such as counters, shift registers and level shifters. A binary synchronous counter is one of the essential building blocks in very large scale integration design. Its operation is usually based on a synchronous timing principle in which the data signal is evaluated at each clock cycle and assigned to its associated flip flop [6]. A counter is NITTTR, Chandigarh
EDIT -2015
designed by using a number of D registers. The D latch is a simple gated SR latch with an inverter connected between its S and R inputs [7]. Steady miniaturization of transistors with each new generation of bulk CMOS technology has yielded continual improvement in the performance of digital circuits. Thus, power efficiency if of increased importance, to meet the performance requirements of VLSI design [8]. Also, the leakage power increases as technology is scaled down [9]. A tradeoff between speed and power is always possible. In high-performance and low-power applications, both features are equally important. The point of minimum power-delay product is the point of optimal energy utilization at a given clock frequency [10]. In this paper, area, delay and power consumption for an SR flip flop have been compared using DSCH and Microwind tools. Basically, two types of design methodologies have been compared, full automatic and semi-custom. Both the designs are created using 45nm CMOS technology. The SR flip flop or the gated SR latch having a second level of AND gates along with a level of direct SR latch using NOR gates has been discussed in the paper. 2. SR LATCH A latch is a circuit that has two stable states. Thus, it is a bistable multivibrator. It can be used to store state information. It is made up of several transistors and is used in the design of static memories and hardware registers. When using static gates as building blocks, the most commonly used fundamental latch is the SR latch, where S stands for set and R stands for reset. It can be constructed from a pair of cross-coupled NOR logic gates. The stored bit is represented on the output marked Q.
Figure 1. SR Latch
The truth table for a simple SR latch is shown in Table 1. Table 1. SR latch operation
R 0
S 0
Q NC
Comment No change. Latch remains in present state.
0 1 1
1 0 1
1 0 0
Set Reset Invalid condition 52