Int. Journal of Electrical & Electronics Engg.
Vol. 2, Spl. Issue 1 (2015)
e-ISSN: 1694-2310 | p-ISSN: 1694-2426
Design and Implementation of FPGA Based Low Power Pipelined 64 Bit Risc Processor for Data Logging System Udit Singh Thakur[1], D. S Ajnar[2], P. K. Jain[3] MicroElectronics & VLSI Design, Electronics & Instrumentation Department S.G.S.I.T.S. Indore (M.P.), India uditsingh17@gmail.com[1], ajnards@gmail.com[2], prjain@sgsits.ac.in[3]
Abstract: This paper presents an efficient design and implementation of a 64 bit RISC Processor for Data Logging System. RISC is a design mechanism to reduce the amount of space, time, cost, power and heat etc. reduces the complexity of instruction. The processor is designed for both fixed and floating point number arithmetic calculation. A Data Logger is an electronic instrument that records environmental parameters such as temperature, Humidity, Wind Speed light intensity, water level and water quality. Data Loggers find its key application where automation and control is required. The necessary code written in the hardware description language Verilog HDL. Keywords: 64-bit RISC Processor, Data Logger
I. INTRODUCTION In conventional approach the system consumes too much of power. The power reduction in conventional RISC processor is done at fabrication step itself, but which is too complex process. Here the utilization of chip area is more and the system consumes more power which leads to increased performance. To overcome this disadvantage, low power RISC Architecture is designed with less number of Gates. Low power design means reducing the power consumption. Low power consumption helps to reduce the heat dissipation, increased battery life and more device reliability. This technology strongly affects battery size, design, electronic packaging of ICs, heat dissipation and circuit reliability. Low power embedded processors are used in a wide variety of applications including cars, mobile phones, digital cameras, printers and other devices. Low power has emerged as a principle theme in today’s electronics industry. The need for low power has caused a major paradigm shift where power dissipation has become an important consideration as performance and area. RISC is termed as Reduced Instruction Set Computer [1].
II. ARCHITECTURE OF THE DESIGN The 64bit RISC Processor designed has the architecture in which the separate access ports are provided for Data and Instruction. This RISC processor has a central control unit that controls all the operation execution in different units such as comparator, ALU, clock generator. It has a pipelined structure that continuously waits for next instruction as soon as the previous instruction executed the next instruction in fetched from register and the processing for next instruction starts accordingly. All basic operation such as arithmetic addition, subtraction, division, multiplication and logical operations like AND, OR, NOT, are being performed by ALU. Shifter is used to shift numbers bitwise to the left and right. Comparator is used to compare two 64 bit numbers. Resistors are being used to store values as well as the next instruction. A separate execution unit for comparison shifting is used to reduce the overhead of ALU which eventually leads to the reduction of complexity and the execution time. While ALU is performing its operation meanwhile comparator and shifter is also performing their operation which reduces the execution time and increases the overall speed and performance. Block diagram of 64 bit RISC processor is been shown in figure 1. With this RISC processor while one instruction is executed next instruction is fetched and decoded and is maintained into a queue for next instruction. This type of branch prediction reduces the wastage of time [1]. In this paper, a 64 bit RISC processor with classified functionality of each block is designed with as architecture that is useful for data logging facility. This RISC processor is been designed keeping in mind about its specific operations where automation and control is required [2].
In this paper a low power 64 bit RISC processor for data logger has been proposed. This RISC Processor tracks the controlled process at regular interval of time and takes the III. DESCRIPTION OF LOGIC BLOCKS. sample data such as conveyor belt speed and direction, The proposed RISC processor contains login block such as temperature, Pressure, water level. Upon the comparison of control unit, register, ALU, comparator, shifter, the sampled data with standard data, Data Logger issues temperature comparator, conveyor belt speed comparator, corresponding signal to the mail computer to take etc as shown in figure 2. necessary steps such as, if the temperature is higher than Control unit serves as the top level module that controls the allowed value than then it issues signal to main CPU everything that is been executed. It also works as such as to take necessary steps to reduce the temperature. instruction decoder that initiates each logical block upon Data logger remains ideal if all the parameters or the opcode occurrence. Registers are useful for storing sampled data is in specified range of operation. Its main incoming input, output as well as the opcode. The program working contains 4 steps namely Fetch, Decode, Execute, counter is been implemented in the instruction resistor. Store. 159
NITTTR, Chandigarh
EDIT-2015
Int. Journal of Electrical & Electronics Engg.
Vol. 2, Spl. Issue 1 (2015)
e-ISSN: 1694-2310 | p-ISSN: 1694-2426
Figure 1 Block diagram of RISC Processor[3] ALU is used for the logical and arithmetic operations, shifter and comparator are used for shifting and comparison respectively.
Figure 2 logical blocks of RISC Processor Figure 3 Flow chart for conveyor belt speedComparator & temperature comparator
IV. SIMULATION RESULT Figure shows the simulation result obtained.
Figure 4 Simulation Result for Control Unit
NITTTR, Chandigarh
EDIT -2015
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Int. Journal of Electrical & Electronics Engg.
Vol. 2, Spl. Issue 1 (2015)
e-ISSN: 1694-2310 | p-ISSN: 1694-2426
Figure 5 Simulation Result for DataLogger V. CONCLUSION A 64 bit RISC processor with 14 instruction set is been designed. Design is verified using exhaustive simulation. This RISC processor has reserved opcode set for other application implementation in future as well. This RISC processor is also useful in ATM, Printers, gaming Kits, etc. REFERENCES
Precision Floating Point Unit”. International Conference on Communication and Signal Processing, pp 1054-1058, April 3-5, 2014, India [2] Seung Pyo Jung, Jingzhe Xu, Donghoon Lee, Ju Sung , Kang-joo Kim, Koon-shik Cho ,“Design & Verification of 16 Bit RISC Processor”, 2008 International SoC Design Conference, pp III.13III.14. [3] Rohit Sharma, Vivek Kumar Sehgal, Nitin Nitin1, Pranav Bhasker, Ishita Verma, “Design and Implementation of a 64-bit RISC Processor using VHDL”, UKSim 2009: 11th International Conference on Computer Modelling and Simulation, pp 568-573.
[1] Jinde Vijay Kumar, Boya Nagaraju, Chinthakunta Swapna and Thogata Ramanjappa, “Design and Development of FPGA Based Low Power Pipelined 64-Bit RISC Processor with Double
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NITTTR, Chandigarh
EDIT-2015