Int. Journal of Electrical & Electronics Engg.
Vol. 2, Spl. Issue 1 (2015)
e-ISSN: 1694-2310 | p-ISSN: 1694-2426
An Implementation and Comparison of IO Expander on Zed Board and Spartan 3E for Low Cost & Area Efficiency Jyoti Saini1, Priyanka verma2, Channpreet Kaur3 1
M.Tech(VLSI), CGC Landran, Punjab, India
jyotisainipbce@gmail.com, 2priverma77@gmail.com, 3cecm.ece.ctoor@gmail.com
Abstract: A port expander is a computer hardware that allows more than one device to connect to a single port to a computer.A port expander can be any device to which one existing or onboard port will become two or more. It allows more devices of a particular port type to be utilized at the same time .The expander will connect to a single spot, but have multiple connections for devices.This paper includes the comparison between Xilinx design suit 12.4(on Spartan 3E) and vivado 2014.4( on zedboard).The comparison is shown with the help of an IO expander.The comparison is clear with the utilization of less number of LUTs and flip flops in vivado’s design summary.We can use C,C++ in vivado unlike Xilinx[1].The parameters like efficiency and speed are high in vivado and cost is low because of utilization of less number of LUTs. Keywords: Xilinx, vivado, LUT, FF, RTL
I. INTRODUCTION The Vivado Design Suite was introduced in April 2012, and it is an integrated design environment (IDE) with a system-to-IC level tools built on a shared scalable data model and a common debug environment.The Vivado IDE provides design visualization and exploration capabilities for our use.The Elaborated Design enables various analysis views including an RTL Netlist, Schematic,and Graphical Hierarchy. The ZED BOARD contains all the necessary interfaces and supporting functions to enable a wide range of applications[2]. The expandability features of the board make it ideal for rapid prototyping and proof-of-concept development. 1.1 I\O Expander An I/O Expander is used to increase the input output capability of a microcontroller. A microcontroller’s I2C port can be used as a communication channel with I/O expander to expand the microcontroller’s I/O count. I/O expander has three address pins which can be used to provide unique addresses for up to eight devices as shown in figure 1. Each device attached to the I2C bus must be assigned a unique address unless all devices (with the same address) are receiving the same data and do not transmit any data. When the master initiates a data transfer, the address of the slave device is transmitted. 1.2 RTL Design The Vivado IDE includes an RTL analysis and IP customizing environment. There are many RTL Design Rule Checks (DRCs) to examine ways to improve performance or power on the RTL design [4]. NITTTR, Chandigarh
EDIT -2015
Figure. 1.1 IO Expander The views have a “cross-select” feature, which helps us to debug and optimize the RTL.In the above RTL view, the design consists of macro blocks, such as number of registers, multipliers, adders as shown in figure 1.2. .
Figure. 1.2 RTL view of io expander in vivado.
1.3 I/O Planning The next step in the implementation of an I/O expander with the help of zynq board(zed board) is I/O planning . The I/O planning features include an integrated design environment (IDE) to make, configure, assign and arrange the I/O Ports and clock logic objects in the design.it describes performing I/O planning at various stages of the design process including pre-RTL, with RTL and after synthesis. The density shows the number of transistors used in the design. we can do I/O planning at any step in the experiment. But mainly it is done after the synthesis. The below figure 1.3 shows the I/O planning of an IO expander. 8
Int. Journal of Electrical & Electronics Engg.
Vol. 2, Spl. Issue 1 (2015)
e-ISSN: 1694-2310 | p-ISSN: 1694-2426
Figure 1.3. I/O planning in vivado.
1.4 Simulation The Vivado IDE integrates the Vivado Simulator, which enables us to add and manage simulation sources in the project. We can configure the simulation options, create and manage simulation source sets[6]. we can run behavioral simulation on RTL sources, prior to synthesis. we can give different values of the input output and in out ports. These can be either force constant or force clock. And output is obtained with the help of run simulation option. The below figure 1.4 shows the simulated result of an io expander.
Figure 1.5 Net list result
1.6
Vivado Design Summary Logic Used Existing Usage utilization No of Slice 18 106400 0.02% FF No of LUTs 25 53200 0.05% No of IOBs 15 200 7.50% No of BUFG 1 32 3.12% Table1. Synthesis report in vivado
II. XILINX The Spartan 3E Starter Board provides a powerful and highly advanced features. It features a 500K gate Spartan 3E FPGA with a 32 bit RISC processor . The features and capabilities of the Spartan-3E family are optimized for high –volume and low cost applications[3].The below figure 2.1 shows the simulated result for an io expander in Xilinx software . we can get the result for either force clock or force constant.
Figure 1.4. Simulated output in vivado.
1.5 Analyzing Routing After the design has been placed and routed, we can generate a timing report to verify that all the timing constraints are met. We can select paths from the Timing Report window to examine the routed path in the Device window as shown in figure 1.5. If there are timing problems, we can revisit the RTL source files or design constraints to address any problem. Graphical representation of the post-synthesis (“optimized and mapped“) net list contain primitives as defined in the library such as LUTs, I/O buffers, and flip-flops. The below table 1 shows the design summary. It shows the number of flip flops and look up tables used.
Figure 2.1 Simulated output
The design summary in Xilinx shows the number of flip flops and number of LUTs used in it[7].The number of sources used here are more than the sources used in vivado. The design summary is shows in below table 2. 2.1 Xillinx Design summary
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NITTTR, Chandigarh
EDIT-2015
Int. Journal of Electrical & Electronics Engg.
Logic utilization No of Slices No of Slice FF No of LUTs No of IOBs
Vol. 2, Spl. Issue 1 (2015)
Used
Available
Usage
20 30 21 15 1
4896 4896 9312 158 24
1% 1% 17% 9% 4%
Table2 Synthesis report in Xilinx
e-ISSN: 1694-2310 | p-ISSN: 1694-2426
Logic utilization No of Slices No of LUTs
Vivado Used 20 21
Xillinx 18 25
Improvem ent 5% 8%
Table 3. Comparison between vivado and Xilinx 25 20
2.2 RTL design The following figure 2.2 shows the RTL view of an io expander in Xilinx.RTL View is a Register Transfer Level graphical representation of our design[5]. This is generated by the synthesis tool at earlier stages of a synthesis process when technology mapping is not yet completed.
15
Zed Board
10
Spartan 3E
5 0 Slices
Luts
III. CONCLUSION In this paper an IO expander is designed, implemented, and simulated on different softwares like Xilinx design suit 12.4 and vivado 2014.4. The result shows that zedboard implementation of an IO expander is efficient than Spartan 3E in terms of number of LUTs and slices used. Hence the number of sources used are less that makes the efficiency difference of 5% and 8% in terms of slices and LUTs respectively. Thus vivado can be used to provide effective solutions with high efficiency. REFERENCES
Figure 2.2. RTL view in Xilinx
2.3 Comparision Table Of Vivado And Xilinx This comparison includes the number of LUTs and slices used in vivado and Xilinx. From table 3 and the below graph ,the comparison is clear that vivado uses less number of sources (LUTs and slices). Zed board (vivado) area utilization is 5% less than Spartan 3E (Xilinx) in terms of Slices, and 8% less in terms of LUTs.
NITTTR, Chandigarh
EDIT -2015
[1] EDN, "The Vivado Design Suite accelerates programmable systems integration and implementation by up to 4X." Jun 15, 2012. Retrieved Jun 25, 2013. [2] Clive Maxfield, EE Times. "WebPACK edition of Xilinx Vivado Design Suite now available." Dec 20, 2012. Retrieved Jun 25, 2013. [3] Brian Bailey, EE Times. "Second generation for FPGA software." Apr 25, 2012. Retrieved Jan 3, 2013. [4] Circuit Design with VHDL, MIT Press, 2004 [5] Embedded Systems Design with Platform FPGAs, Morgan Kaufmann, 10-Sep-2010 [6] "Foundation Series ISE 3.1i User Guide". 100728 xilinx.com.
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