Layout Design Comparison of CMOS and Gate

Int. Journal of Electrical & Electronics Engg.

Vol. 2, Spl. Issue 1 (2015)

e-ISSN: 1694-2310 | p-ISSN: 1694-2426

Layout Design Comparison of CMOS and Gate Priyanka Gupta B. Tech, student Department of Electronics & communication Engineering Jasdev Singh Sandhu Institute of Engineering & Technology, Kauli, Patiala ,India 147201 Prnkgupta504@gmail.com

Abstract: In this paper a CMOS AND gate layout has been designed and simulated using 90nm technology. The layout has been designed using two approaches, namely fully automatic and semicustom. In fully automatic technique AND gate schematic is developed which is constructed into its equivalent spice file for the automatic layout generation. In semicustom technique layout has been developed mainly to optimize area and power. It can be observed from the simulated results that semicustom layout results in 11.2Âľm2 area consumption by consuming almost the same power as compared to fully automatic design.

Keywords: VLSI design, CMOS Tehnology, layout.

1. INTRODUCTION This paper explains the design of AND gate in VLSI design. Development of digital integrated circuit is challenged by higher power consumption. Logic gates are primarily implemented using transistors acting as electronic switches. Logic circuits include such devices as multiplexers, registers, ALU and computer memory. A logic gate is an elementary building block of digital circuit in VLSI design. AND gate is a basic digital logic gate that implements logical conjunction. A high output results only if both the inputs to AND gate are high. Output is always 0 except when all the inputs are 1s. The suggested design for AND gate offer ON to OFF logic level [1]. In this paper DSCH 3.1 is used as logic editor and simulator. In this design schematic of AND gate is designed and the layout is created in MICROWIND. Following figure 1 shows the ON and OFF logic level of the AND gate.

The truth table behavior and symbol of the AND gate shown as:

Figure 1 schmatic diagram of AND gate

Table 1 the truth table behavior of AND gate as A B Pull Pull up Output down 0 0 OFF OFF 0 0 1 OFF ON 0 1 0 ON OFF 0 1 1 ON ON 1 53

DSCH is easy to understand, but not easy to modify. The DSCH designer software has the advantage and opportunity of removing all possible errors in proceeding expensive manufacturing components in the design.

MICROWIND provides the easy platform for the layout design part. MICROWIND provide the single key to check error in the layout design by using a design rule check key.

So in this way errors are removed in the layout design part and correct design in obtaining. But the speed in this layout design decreases. AND gate built from two levels of inverting complementary CMOS gate. AND gate could be constructed from NAND/NOR gates and inverters [2].

The proposed design is formed by the combination of NAND gates and inverter. Performance of proposed logic gate has been analyzed and simulated using DSCH 3.1[3].

In this paper, new methods have been proposed for power reduction in 90nm technology. The proposed method will be compared with the previous existing reduction techniques. In this leakage current is the current that flows through a transistor when it is switched off. It depends on the gate length, oxide thickness and various exponentially with threshold voltage, and other parameters. Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (CMOS) technology. This technique is better area efficient than the existing techniques [4]. In this design 90nm technology used for circuit simulation of NMOS and PMOS transistor.

In this sizing of PMOS to NMOS is done by using some spice calculations [5, 6]. A basic gate is composed of the logic family gate, which can be a conventional CMOS gate and an additional transistor [7]. CMOS technology parameters variation depended on the overall leakage current [8]. Basic circuit of CMOS inverter, a logic gate also called a NOT gate. The inverter of CMOS logic, which is using one PMOS transistor and one NMOS transistor. In this when the input A is 0, NMOS transistor is OFF and PMOS transistor is ON and vice versa [9].

2. Fully automatic Layout Design of AND gate In this paper, the schematic circuit is created in DSCH and layout has been designed in the MICROWIND. AND gate can be built with CMOS technology. AND gate is created by using a combination of PMOS and NMOS transistors.

The formed AND gate having two inputs A,B and one output out1. This schematic of AND gate is designed first in DSCH using PMOS and NMOS transistors.

NITTTR, Chandigarh

EDIT-2015

Int. Journal of Electrical & Electronics Engg.

Vol. 2, Spl. Issue 1 (2015)

e-ISSN: 1694-2310 | p-ISSN: 1694-2426

In this layout design part foundry is selected in CMOS 90nm technology consumes more power as compared to the fully automatic layout in MICROWIND tool. But semicustom layout consumes less area as compared in the case of fully automatic layout in spice tool. P-MOS selected with low leakage current 0.71mA and N-MOS selected with low leakage current 0.64mA.Layout of AND gate can be designed by using different techniques. In this design input is applied using polysilicon and output obtained using metal.

Fig1. Schematic of AND gate

Timing analysis shows verification results of AND gate using DSCH simulator. In this result clk1, clk2 are inputs and out1 is output. Figure 2 shows timing verification of AND gate.

Fig 4 Semicustom layout of AND gate

Analysis of the parameters in the two different layout designs as:

Fig. 2 Timing waveform of AND gate After this Verilog file is made in DSCH and compiled in MICROWIND tool. Then fully automatic layout of AND gate has been generated. This layout consumes power of 3.1µw in MICROWIND technique.

Table 2 comparison of different parameters Param A Automat Semicust eter techniqu ic layout om used e used layout Area(μ 90nm 43.7 11.2 m2 ) Width( 90nm 8.1 4.0 μm) Height( 90nm 5.4 2.8 μm)

Fig 5 Fully automatic layout of AND GATE Fig 3 Verilog file of AND gate

3. Semicustom design Layout of AND gate NITTTR, Chandigarh

EDIT -2015

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Int. Journal of Electrical & Electronics Engg.

Vol. 2, Spl. Issue 1 (2015)

3 Fig. 6 Simulated waveform of fully automatic layout design

e-ISSN: 1694-2310 | p-ISSN: 1694-2426

6. CONCLUSION This paper presents the analysis of auto generated and semicustom layout. This paper presents auto generated and semicustom techniques have been used to optimize area and power. Results of the above two approaches have been analyzed and compared in this paper. AND gate layout has been designed and simulated using two different techniques for area and a power comparison. In both the layouts, 90nm technology has been used for simulation.

Simulation results express that semicustom technique based AND gate layout consumes 11.2µm2 area than in the case of fully automatic AND gate which consumes 43µm2 area. It can also be observed from simulated results that semicustom AND gate consumes more power than a fully automatic AND gate. But some other techniques can be used for reduction of power in the future.

4. PROPOSED DESIGN SIMULATION Simulation of semicustom layout design of AND gate has been done in MICROWIND tool. Simulated result shows the equivalent waveform to the fully automatic layout of AND gate schematic. figure 7 shows wave analog simulated waveform of AND gate in semicustom.

ACKNOWLEDGEMENT I am highly thankful to Mr. Rajesh Mehra for their guidance and support. I would like to express my gratitude towards my parents and friends for their co-operation and encouragement which help in completion of my research paper.

REFERENCES

Fig 7 analog simulated waveform of AND gate

[1] Raghda M. Younis, Nihal F.F. Areed, and Salah S.A. Obayya, Senior member, IEEE, “Fully integrated AND and OR optical logic gates”,IEEE photonics technology letters Vol.26, pp.1900, October 1, 2014.

[2] Neil Weste and Devid Harris, CMOS VLSI design, circuit and system perspective, pp. 8.

[3] Dinesh Sharma and Rajesh Mehra, “Low Power delay Optimized, Buffer Design using 70nm CMOS Technology”, International Journal of Computer Applications, Vol. 22, No. 3, May 2011.

[4] Pushpa saini, “Leakage power Reduction in CMOS VLSI circuits”, International Journal of Computer Applications, Vol. 55, pp. 8, October 2012.

[5] Srinivasa Rao. Ijjada, Raghavondra Sirigiri, B.S.N.S.P Kumar, V. Mallleswara Rao, “Design of high efficient and Low power basic gates in Subthreshold Region”, International Journal of advances in engineering & Technology, Vol.1, Issue 2. pp. 215.

[6] M. Horawitz, et, al. “Low power digital design”, IEEE symposium on low power electronics, pp. 8-11. 1994.

[7] Itamer Levi, Alexander Belenky and Alexander fish, member, IEEE “Logical effort for CMOS based Dual mode logic gates”, IEEE Transactions on very large scale integration(VLSI) systems, Vol. 22, pp. 5, May 2014.

[8] Oleg Semenav, Andrzej pradzynski seniour member, IEEE and Mnoj.

Sachdav Senior member, IEEE, “Impact of gate induced drain leakage on overall leakage of submicrometer CMOS VLSI circuits”, IEEE Transactions on semiconductor manufacturing, Vol. 45, pp. 17, Febrary 2002.

[9] Ms. Rakhi R. Agrawal, “Systematic design of high speed and low power demino logic, International Journal of advanced Research in computer science and software engineering, Vol. 2, Issue 3, pp. 219, March 2012.

Fig.8. Bar chat represent of two layout designs. In this two different layouts are compared.

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NITTTR, Chandigarh

EDIT-2015