Int. Journal of Electrical & Electronics Engg.
Vol. 2, Spl. Issue 1 (2015)
e-ISSN: 1694-2310 | p-ISSN: 1694-2426
High Performance Binary to Gray Code Converter using Transmission GATE Ravi Kumar Anand Department of ECE, National Institute of Technical Teachers’ Training & Research Chandigarh, India ravi88.anand@gmail.com Abstract: This paper gives an idea to improve power efficiency and effective area of binary to gray code converter using very popular transmission gate technology. Some sensors send information in gray code. So this must be important to convert a given binary stream into its equivalent gray code. In this paper the binary to gray code converter has been developed using gate, circuit level. The conversion has been done using conventional and transmission gate level and comparing these two in terms of power, number of transistors used and last but not the least area. The simulation result shows that binary to gray code converter using transmission gate has improved power efficiency and area by 76.22% and 72.3% respectively .This paper gives the true comparison between transmission gate and conventional gate implemented binary to gray code converter in many aspects like power, area, and number of transistors used for fully automatic and semicustom layout design.
the designers. The performance of the complex logic circuits is affected by XNOR-XOR circuits [6]. To summarize, this paper focused on some of the performance criteria are considered in the designing and evaluation of this converter cells while some are utilized for the ease of design, robustness, silicon area, delay and last but not the least power consumption. The technology used in this paper i.e. Transmission gate use less area and less transistors compare with conventional design logic. In this paper the circuit simulation has been done on DSCH3 and layout simulation on Microwind3.1.
Keywords: CMOS Transmission Gate(TG), Power dissipation, Semi custom design, CMOS logic gates, Effective area.
2. BINARY TO GRAY CODE CONVERTER
1. INTRODUCTION Low power and area efficient technologies are the prime concern for VLSI system designers. Together with that, the high speed binary to gray code converter that use low power consumption have indisputably become one of the most crucial components of a processor because they are mostly used in arithmetic logic unit.
This code converter combinational circuit is designed to convert binary to gray code. The input code of code converter is binary and output code of code converter is gray code. Table.1 shows the truth table of 4-bit binary to gray code converter. Table.1 truth table of binary to gray converter
Second term of consideration for designing of low power area efficient binary to gray code converter is delay which affects the overall performance of circuit to be concern. The extensive development in the field of portable system and cellular network has intensified the research efforts in low power micro-electronics [1]. This paper concern with 3 XOR gate as one unit which is the basic building block in various circuit especially arithmetic circuit .Here we propose a new design of XOR gate using transmission gate with CMOS inverter circuit. It cover less area compared to 12 transistor X-OR with CMOS circuit as well as less power with smaller delay[2].The strength of a signal is measured by how closely it approximates an ideal voltage source[3].
Corresponding circuit using basic CMOS gates on DSCH is shown in fig.1
Transmission gates require lower switching energy and it reduces the count of transistors used to make different logic gates [4]. In VLSI implementation, major problems are heat dissipation and power consumption. To solve this problem it is required to reduce power supply voltage, switching frequency and capacitance of transistor [5]. Area, delay and power dissipation have emerged as the major concern of NITTTR, Chandigarh
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Int. Journal of Electrical & Electronics Engg.
Vol. 2, Spl. Issue 1 (2015)
e-ISSN: 1694-2310 | p-ISSN: 1694-2426
Fig.1 CMOS equivalent on DSCH3
Fig.2 shows the output simulation of CMOS equivalent of binary to gray code converter on DSCH3 as. Fig.3 binary to gray code converter using transmission gate on DSCH3
It also gives an idea about lambda rule to design our desire logic circuit. The development of digital integrated circuits is challenged by higher power consumption [9]. Energy loss is an important consideration in digital design. Part of the problem of energy dissipation is related to non ideality of switches and materials [10]. Fig.4 shows the fully automatic layout generated on Microwind3.1 of binary to gray code converter when use conventional CMOS logic gates. So this is the gate level implementation of our desire logic circuit. It uses total 36 CMOS logic gates.
Fig.2 simulation result of equivalent CMOS logic on DSCH3
Now the equivalent CMOS logic design is constructed using transmission gate which help to reduce the number of CMOS logic gates as shown in fig.3. The DSCH3 program is a logic editor and simulation. It provides user friendly and fast simulation [7]. 3. LAYOUT SIMULATION This paper focuses on three layout designs which are given in below with simulation results. Full automatic layout has been developed on Microwind3.1. It compile Verilog file generated on DSCH3 and give an idea about all PMOS and NMOS connection with ground and supply voltage. As a basic computation function of data processing, integer addition is the most commonly used and important operation in digital circuit designs. Therefore the speed and area consumption of adders have great impact on the overall system speed and scale. [8]. 117
Fig.4 full automatic layout using conventional CMOS logic
The simulation result has been shown in fig.5
NITTTR, Chandigarh
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Int. Journal of Electrical & Electronics Engg.
Vol. 2, Spl. Issue 1 (2015)
e-ISSN: 1694-2310 | p-ISSN: 1694-2426
Comparative analysis between various types of design layout of binary to gray code converter is shown in table.2. Comparison aspects are based on power dissipation, effective area, delay and number of transistors used. Comparison shows that transmission gate based binary to gray code converter is better than other conventional CMOS logic gate design in every aspect. Table.2 Comparative analysis
Fig.5 Simulation result of full automatic layout using conventional CMOS logic
The next step is to design desire circuit using transmission gate which help to reduce number of CMOS devices.fig.6 shows full automatic layout using transmission gate as
1.
2.
3.
Fig.6 full automatic layout using transmission gate
Type of design
Power (µw)
Area (µm2)
No. of MOS devices
Full automatic layout design using basic CMOS logic gates(Design1) Full automatic layout design using transmission gates(Design2) Semi custom layout design using transmission gates(Design3)
47.1
249.32
36
11.2
69.4
18
10.7
47.5
18
S.N.
Fig.8 shows all comparisons on bar graph as
Semi custom layout design using transmission gate In the next step the circuit is customized using transmission gate as shown in fig.7.
300 200 100 0
POWER
AREA
Fig.8 graphical comparison
5. CONCLUSION Above analysis conclude whole discussion that transmission gate is very useful technique to reduce the effective area on a chip, number of transistors, delay and power dissipation. This paper focus here on semi custom design analysis of binary to gray code converter and find the better result for all parameters. Thus as shown in table.2 power consumption is reduced by 76.22%, area is reduced by 72.3% and number of transistors are reduced by 50%. REFERENCES
Fig.7 semi custom layout using transmission gate
4. Result analysis
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[1] Saradindu Panda, A.banerjee, B.maji and Dr. A.K. Mukhopadhyay, “Power and delay comparison in between different types of full adder circuits”, International Journal of advanced research in electrical, electronics and instrumentation engineering, volume 1, issue 3.pp.168-172, 2012. [2] Swati Sharma and Rajesh Mehra, “Area and power efficient design of XNOR-XOR logic using 65nm technology”, International Journal of engineering and technical, pp.57-60, 2014 [3] Neil H.E.Weste, David Harris and Ayan Banaerjee, “CMOS VLSI design”. Pearson Education,Inc., pp. 11, Third Edition, 2005
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Vol. 2, Spl. Issue 1 (2015)
e-ISSN: 1694-2310 | p-ISSN: 1694-2426
[4] S,Goel.M.A. Elgamel, M.A. Bayoumi, and Y.Hanarty. “Design methodologies for high performance noise-tolerant XOR-XNOR circuits,” circuits and systems I:Regular papers, IEEE Transactions on, vol.53,pp.817-878,2006 [5] Richa Singh and Rajesh Mehra , “Power efficient design of multiplexer using adiabatic logic”, International Journal of advances in engineering and technology, pp 247-254, march 2013. [6] Nabihah Ahmad, Rezaul Hasan, IEEE “A New Design of XOR-XNOR gates for low power Electronic Devices”, System and Applications(ICEDSA), pp.45-49, 2011. [7] I. Hassoune, D. Flandre, I. O’Connor and J.D.Legat:ULPFA: ANew Efficient Design of A Power Aware Full Adder”, IEEE Transactions on Circuits and Systems I-5438,pp.2066-2074, 2008 [8] Zhanfeng Zhang, Liyuan Sheng, Wenming Jiang, Shuai Tong, Hua Cao, “A New Adder Theory Based on Half Adder and Implementation in CMOS Gates”, I.J. Image, Graphics and Signal Processing, pp.11-17 2012. [9] PushpaSaini, Rajesh Mehra:“A Novel Technique for Glitch and Leakage PowerReduction in CMOS VLSI Circuits”, International Journal of Advanced Computer Science and Applications, Vol. 3, No. 10,pp.161-168 2013 [10] V.Kamalakannan, Shilpakala.V, Ravi.H.N, “Design of Adder/Subtractor Circuits Based on Reversible Gates”, International Journal of Advanced Research in Electrical Electronics And Instrumentation Engineering, Vol 2, issue 8,pp.3796-3804, 2013.
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