Layout Design of Low Power Half Adder using 90nm Technology

Int. Journal of Electrical & Electronics Engg.

Vol. 2, Spl. Issue 1 (2015)

e-ISSN: 1694-2310 | p-ISSN: 1694-2426

Layout Design of Low Power Half Adder using 90nm Technology Neha Yadav Department of ECE, National Institute of Technical Teachers’ Training & Research Chandigarh, India neha.yadav075@gmail.com

Abstract: The basic building block of any digital operation is addition. This paper compares fully automatic and proposed semicustom layout design; the proposed design has been optimized for power consumption, low area and high speed.

Power consumption and area are the major design issue for a designer. All the design result of fully custom and proposed semicustom design taken at 1.2V. In this the circuit simulation has been done on DSCH3 and layout simulation on Microwind3.1.

Keywords: Half Adder, CMOS circuit, VLSI, Microwind 3.1 power dissipation, logic gates, delay

1. INTRODUCTION Addition is the basic operation which is applied various field of VLSI, such as application specific DSP architecture and microcontrollers; half adder is used to adding two binary numbers, as we know that addition is the base of other operation also like subtraction, multiplication, division and address calculation.[1] sometimes we required to increasing the speed of the circuit it need parallel operation compare to series operations, then we need no. of CMOS for designing the layout of that particular circuit which increases the area and power consumption.

So the factor like power, area and speed depends upon the no. of CMOS and the circuit complexity. Arithmetic operation like multiplication done by ALU, and it is depending on addition. [1, 2]. Recently the work on low power VLSI system has high demand because of limited amount of power available in case of mobile communication. [1]

propose a new design of half adder circuit using CMOS. The strength of a signal is measured by how closely it approximates an ideal voltage source [3, 4] VLSI implementation, major problem are heat dissipation and power consumption. So it is required to reduce power supply voltage. Area, delay and power dissipation have emerged as the major problem of the designers. [4, 5] So in this paper the main point is the performance like robustness, and delay silicon area and power consumption.

[6, 7] 2. CMOS HALF ADDER DESIGN Half adder is used to addition of two binary no. A, B are with its sum and carry. The output of sum of A and B is XOR and carry of A and B is output of AND gate. Half Adder is also use for two or more bit for parallel addition, which increases the operation time of the circuit in two bit parallel adder and the operation of two bit adder is same as the half adder shown below: Sum= A XOR B Carry= A AND B Table.1 Truth table of half adder

So designer Bfacing more 0 constraint 1 with the high speed low power area efficiency and high performance [1]. Here we

A0

1

1 0

B A

Sum

0 0 1 1

0 1 0 1

0 1 1 1

Carry 0 0 0 1

Boolean Expression of Sum Boolean expression is obtained using k map, which is filled by truth table output. It is in SOP form which is based on min terms.

Boolean Expression of Carry

0

1

0

0

0

1

0

Fig.1 Sum=A’B+AB’

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B

Boolean Expression of Carry is obtained same as Boolean Expression of Sum with k map using truth table output.

0 1

A

1

Fig.2 Carry=AB

So from the Boolean expression circuit of half adder at gate level and at CMOS level are designs with DSCH shown below. Fig.3 shows gate level design and fig.4 equivalent CMOS logic design. The simulated output of CMOS circuit using DSCH is given in fig.5.the simulated NITTTR, Chandigarh

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Int. Journal of Electrical & Electronics Engg.

Vol. 2, Spl. Issue 1 (2015)

e-ISSN: 1694-2310 | p-ISSN: 1694-2426

output at gate and CMOS level are same but CMOS circuit design is more efficient because it opens the path for layout design of the required circuit. With the help of CMOS circuit firstly stick diagram of circuit has made and then with the help of stick diagram layout of given circuit has been designed. Stick diagram shows different layers with different colours and it is shown same in layout design whether it is fully automatic layout design or semicustom layout design. In semicustom layout design library components are used for layout designing example NMOS and PMOS which reduces the time for manufacture.

Fig.5 simulated output of CMOS design

3.

LAYOUT DESIGN SIMULATIONS

Full automatic layout has been generated on Microwind3.1. After compile verilog file generated on DSCH. In DSCH first we have to draw schematic design and after saving this circuit make verilog file. It gives an idea about all PMOS and NMOS connection with ground and supply voltage. It gives also gives an idea about interconnections between two different metals, between metal and polysilicon also about lambda rule to design our desire logic circuit. Layout of fully automatic design with its simulated output is shown in fig.6 and fig.7.

Fig.3 Half adder with XOR and AND gate

Fig.6 Fully Automatic Layout Design

Fig.4 Half Adder using CMOS Fig.7 Output of Fully Automatic Layout Design

Semicustom design layout using CMOS logic with8 MOS devices and its simulated output is shown in fig.8 and fig.9 NITTTR, Chandigarh

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Int. Journal of Electrical & Electronics Engg.

Vol. 2, Spl. Issue 1 (2015)

e-ISSN: 1694-2310 | p-ISSN: 1694-2426 Fig.8 Proposed Semi Custom Layout

Fig.9 Proposed semi custom layout output

4. RESULT ANALYSIS Comparative analysis between various types of design layout of half adder is shown in table.2.Comparison aspects are based on power dissipation, effective area, delay and number of transistors used. From the table it is obvious that layout design using semicustom is better than the layout design of fully automatic. Area and power semi custom layout design improves more in percentage (%).

In the table.2 we are comparing area, power, delay and the no. of gate between fully automatic layout and semicustom layout designs which shows that area, power and delay with same no. of gates are less in semicustom than fully automatic. From the table power and delay improved more than 25% compare to fully automatic layout design and area remains only which are less than one third of fully automatic layout design.

Table and graph of result of fully custom layout design and proposed semi custom layout design

parameters

Fully

Automatic

Semicustom

Design

Design

Power

847nW

678nW

Area

132.7μm²

42 μm²

Delay

29ps

11ps

CMOS

8(no. of CMOS)

8

Table .2 Analyses of different parameters

Figure shows graph of fully automatic and semicustom layout design with various parameters like power, area, delay and no. of CMOS. Graph describe comparison between fully automatic and semicustom layout design and it is observed that semicustom is more optimum lay out design.

99

900 800 700 600 500 400 300 200 100 0

fully autatic semi custom

power

area

delay

no. Of cmos

Fig.10 Graphical Analyses of different parameters

5. CONCLUSION It is observed from the result that the proposed layout design is area efficient, low power consumption with high speed and high performance compare to fully automatic layout design. So semicustom layout design is very useful technique to reduce the effective area on a chip, number of transistors, delay and power dissipation. Semicustom layout design is optimum than fully automatic layout design.

REFERENCES [1]. Pardeep Kumar, Susmita Mishra, Amrita Singh “Study of existing Full Adders and To Design a LPFA (Low Power Full Adder)”. International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 Vol. 3, Issue 3, MayJun 2013, pp.509-513 [2]. Chakshu Goel, Puneet Jain, Gurjeevan Singh “Design and Simulation of Low Power CMOS Adder Cell at 180nm using Tanner Tool”. International journal of Computer Applications (0975 – 8887) Volume 62– No.16, January 2013 [3]. M.Geetha Priya K.Baskaran “Low Power Full Adder with Reduced Transistor Count”. International Journal of Engineering Trends and Technology (IJETT) Volume 4, Issue 5, May 2013

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Int. Journal of Electrical & Electronics Engg.

Vol. 2, Spl. Issue 1 (2015)

[4]. MICHAEL J. BATEK and JOHN P. HAYES, “Optimal Testing and Design of Adders”. Gordon and Breach Science Publishers S.A. Printed in the United States of America Vol. 1, No. 4, pp. 285-298 VLSI Design 1994 [5]. Zhanfeng Zhang, Liyuan Sheng, Wenming Jiang, Shuai Tong, Hua Cao, “A New Adder Theory Based on Half Adder and Implementation in CMOS Gates”. I.J. Image, Graphics and Signal Processing, ISSN: 2074-9074 Vol. 2, No.2, Dec.2010 [6]. Habsah Abdul Shaer, Md. Mamun, Mohd. Marufuzzaman and H. Husain “Design of a High Speed Low Power 2’s Complement Adder Circuit”. Research Journal of Applied Sciences, Engineering and Technology ISSN: 2040-7459, March 15, 2013 [7]. R.UMA, Vidya Vijayan, M. Mohanapriya, Sharon Paul, “Area, Delay and Power Comparison of Adder Topologies”.

International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.1, February 2012.

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e-ISSN: 1694-2310 | p-ISSN: 1694-2426

ACKNOWLEDGMENT Author would like to thank Mr. Rajesh Mehra, assistant professor of electronics and communication engineering department, National Institute of Technical Teachers’ Training & Research, Panjab University Chandigarh, India for their constant inspirations, support and helpful suggestions throughout this research work.

ABOUT AUTHOR Neha Yadav completes the Bachelors of Technology degree in Electronics and Communication Engineering from U.I.E.T. C.S.J.M. University Kanpur. She is pursuing M.tech from National Institute of Technical Teachers’ Training & Research, Panjab University Chandigarh.

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