Int. Journal of Electrical & Electronics Engg.
Vol. 2, Spl. Issue 1 (2015)
e-ISSN: 1694-2310 | p-ISSN: 1694-2426
Efficient Design of 64:1 Hybridized MUX for Low Area and Power VLSI 1 1
Yashika Thakur1, Anjali Sharma2 M. E. Student, Department of ECE, NITTTR, Chandigarh, India 2 Assistant professor, Department of ECE, A.P.G, Shimla, India
yashika04thakur@gmail.com, 2anjali.iitt@gmail.com
Abstract— This paper presents an efficient design of 64:1 GDI PTL Multiplexer circuit using tree topology logic design. The proposed design schematic consists 63 PMOS and 127 NMOS with transistor count of 190. The proposed design schematic is realized in 180 nm technology on BSIM 4 with input power supply of 1.2 V. This design has a power consumption of 444 µw with an overall chip size of 38653.7µm2. All results are simulated using DSCH and MICROWIND 3.1. Keywords—Gate diffusion Multiplexer, tree topology.
input,
Pass
transistor
logic,
I. INTRODUCTION Multiplexer is one of the key components in many circuits. It is abbreviated as MUX. Multiplexer consists of a number of input lines with single output line. A multiplexer having two input lines is called 2:1 MUX and so on. So 64:1 MUX circuit contains 64 input lines. Gate Diffusion Input Technique is a new method of reducing power dissipation, propagation delay with less area. Pass transistor logic uses less number of transistors which also results in less area and low power consumption A tree-type multiplexer is composed of multiple 2-to-1 MUX cells which are organized in a tree type structure. A multiplexer tree is a network topology where the output of one multiplexer is used as the input to another multiplexer and so on [1]. To construct 64:1 MUX number of 2:1 MUX required are 63 which is given by N-1 and in this case N=64. II.
Fig.1. Proposed 64:1 MUX design
Timing simulation is important to simulate the design on the chip. It shows the exact functionality of the logic circuit. Timing simulation of 64:1 GDI PTL MUX is shown in figure 2 as:
PROPOSED 64:1 GDI PTL MUX DESIGN
The design of 64:1 GDI PTL MUX has been designed using 63 PMOS and 127 NMOS with a transistor count of 190 . In proposed design both the logic styles has been combined in order to provide better results in terms of area and power. With tree topology a total of 63 - 2:1 MUXs are used. The schematic design of the proposed MUX is shown in figure 1. In the proposed schematic circuit design we have 64 input lines and a single output line. Here we have 6 select inputs which are used to select any one of the above input combinations. For example if all the select inputs are zero i.e. S5S4S3S2S1S0 = 000000 then we have input D0 at the output. Fig.2. Timing simulation of 64:1 MUX
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Before the actual layout design of proposed MUX it is necessary to validate the schematic of logic circuit. To NITTTR, Chandigarh EDIT-2015