Int. Journal of Electrical & Electronics Engg.
Vol. 2, Spl. Issue 1 (2015)
e-ISSN: 1694-2310 | p-ISSN: 1694-2426
Efficient Design of 64:1 Hybridized MUX for Low Area and Power VLSI 1 1
Yashika Thakur1, Anjali Sharma2 M. E. Student, Department of ECE, NITTTR, Chandigarh, India 2 Assistant professor, Department of ECE, A.P.G, Shimla, India
yashika04thakur@gmail.com, 2anjali.iitt@gmail.com
Abstract— This paper presents an efficient design of 64:1 GDI PTL Multiplexer circuit using tree topology logic design. The proposed design schematic consists 63 PMOS and 127 NMOS with transistor count of 190. The proposed design schematic is realized in 180 nm technology on BSIM 4 with input power supply of 1.2 V. This design has a power consumption of 444 µw with an overall chip size of 38653.7µm2. All results are simulated using DSCH and MICROWIND 3.1. Keywords—Gate diffusion Multiplexer, tree topology.
input,
Pass
transistor
logic,
I. INTRODUCTION Multiplexer is one of the key components in many circuits. It is abbreviated as MUX. Multiplexer consists of a number of input lines with single output line. A multiplexer having two input lines is called 2:1 MUX and so on. So 64:1 MUX circuit contains 64 input lines. Gate Diffusion Input Technique is a new method of reducing power dissipation, propagation delay with less area. Pass transistor logic uses less number of transistors which also results in less area and low power consumption A tree-type multiplexer is composed of multiple 2-to-1 MUX cells which are organized in a tree type structure. A multiplexer tree is a network topology where the output of one multiplexer is used as the input to another multiplexer and so on [1]. To construct 64:1 MUX number of 2:1 MUX required are 63 which is given by N-1 and in this case N=64. II.
Fig.1. Proposed 64:1 MUX design
Timing simulation is important to simulate the design on the chip. It shows the exact functionality of the logic circuit. Timing simulation of 64:1 GDI PTL MUX is shown in figure 2 as:
PROPOSED 64:1 GDI PTL MUX DESIGN
The design of 64:1 GDI PTL MUX has been designed using 63 PMOS and 127 NMOS with a transistor count of 190 . In proposed design both the logic styles has been combined in order to provide better results in terms of area and power. With tree topology a total of 63 - 2:1 MUXs are used. The schematic design of the proposed MUX is shown in figure 1. In the proposed schematic circuit design we have 64 input lines and a single output line. Here we have 6 select inputs which are used to select any one of the above input combinations. For example if all the select inputs are zero i.e. S5S4S3S2S1S0 = 000000 then we have input D0 at the output. Fig.2. Timing simulation of 64:1 MUX
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Before the actual layout design of proposed MUX it is necessary to validate the schematic of logic circuit. To NITTTR, Chandigarh EDIT-2015
Int. Journal of Electrical & Electronics Engg.
Vol. 2, Spl. Issue 1 (2015)
overcome this problem DSCH and MICROWIND designing tools works parallel. Firstly the design is simulated in DSCH designing tools to know the exact functionality of the circuit and then implemented on the layout in MICROWIND [2]. Here in the figure 2 we can see that when all the input select lines are zero i.e. S5S4S3S2S1S0 = 000000, then at this point what we get at the output is input D0 which will be given by the OUT1 in the figure 2. In this way with different select input combinations we can get anyone of the inputs at the output. III. LAYOUT ANALYSIS The layout analysis is process to identify and categorize the area of interests in picture. In DSCH tool the schematic design has been firstly designed and validated at logic level on DSCH designing tool. DSCH 3.1 tool is used to generate the VERILOG file of schematic which is compiled by the MICROWIND3.1. In MICROWIND 3.1 we have different simulation parameter models like LEVEL 1, LEVEL 2 and BSIM 4. The layout of proposed MUX is shown in Figure 3 as:
e-ISSN: 1694-2310 | p-ISSN: 1694-2426
The performance evaluation of 64:1 GDI PTL MUX has been done in terms of area and power on 180 nm technology. Results are measured in terms of power variation with respect to variation in voltage on BSIM 4. For 180 nm technology the values for Vss and Vdd are fixed to 1.2 V and 0 V respectively. Simulation has been performed using the MOS empirical BSIM Model-4 at different power Vdd.
Power consumption in µw
500 450
444
400 350 300 250
227
200 150 100
87.72
50 21.64
0 0.6
0.8
1
1.2
Fig.4. Power vs. Supply Voltage on BSIM-4
From figure 4 it is clear that the power consumption increases with the increase in power supply as we can see that the power consumption at 0.6 V is 21.64 µW and that at 1.2 V is 444 µW. Fig.3. Layout of proposed MUX
The following table shows the analysis of proposed 64:1 GDI PTL MUX in terms of area and power both on 180 nm technology as : Table 1. Analysis of proposed 64:1 MUX in terms of area and power on 180nm technology Proposed 64:1 GDI PTL MUX 64:1 MUX design design 127 NMOS 63
PMOS 2
IV.
SIMULATION RESULTS
NITTTR, Chandigarh
Table.2 Power consumption at different supply voltages
Power consumption in µw BSIM 4
0.6
0.8
1
1.2
21.64
87.72
227
444
V. CONCLUSION 64: 1 GDI PTL MUX has been successfully designed and realized in 180 nm standard CMOS process technology. This circuit has been implemented by using 127 NMOS and 63 PMOS. It has a power consumption 444 µw and a
38653.7 444
Area (µm ) Power (µW)
From Table 2 it is clear that power dissipation increases with increase in supply voltage.
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Int. Journal of Electrical & Electronics Engg.
Vol. 2, Spl. Issue 1 (2015)
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chip size (area) of 38653.7 µm . The simulation proves that the proposed circuit has been implemented using less area with minimum power consumption.
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REFERENCES [1] Yashika thakur; Rajesh Mehra; Anjali Sharma, “CMOS design of area and power efficient multiplexer using tree topology”, International Journal of Computer Applications, Vol. 112, No. 11, pp. 32-36, 2015. [2] Pranshu Sharma; Anjali Sharma; Richa Singh, “Design and Analysis of Area and Power Efficient 1-Bit Full Subtractor using 120nm Technology” International Journal of Computer Applications, Vol. 88, No.12, pp. 36- 42, 2014. [3] Morgenshtein, A.; Fish, A.; Wagner, I.A., “Gate-Diffusion Input (GDI): A Power Efficient Method for Digital Combinational circuits,” IEEE Transaction on Very Large
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[5]
[6] [7]
e-ISSN: 1694-2310 | p-ISSN: 1694-2426
Scale Integration Systems, Vol. 10 , No. 5, pp. 566 - 581, 2002. Vivechana Dubey; Ravimohan Sairam, “An Arithmetic and Logic Unit Optimized for Area and power” International Conference on Advanced Computing & Communication Technologies, pp. 330-334, 2014. Arkadiy Morgenshtein; Alexander Fish; Israel A. Wagne, “Gate-Diffusion Input (GDI) - A Technique for low power design of digital circuits; Analysis and Characterization” IEEE International Symposium on Circuits and Systems , Vol. 1, pp. 477-480, 2002. N. Weste and K. Eshraghian, (2002) Principles of CMOS VLSI Design: A System Perspective Reading, Pearson Education, Addison–Wesley. Microwind and DSCH version 3.1, User’s Manual, Copyright 1997-2007, Microwind INSA France, pp. 97-103, 2006.
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