Int. Journal of Electrical & Electronics Engg.
Vol. 2, Spl. Issue 1 (2015)
e-ISSN: 1694-2310 | p-ISSN: 1694-2426
Analogy with Human Brain Design Implementation on FPGA Payal Arora1 , Disha Chauhan2 1,2
Department of Electronics and Communication, Chitkara University, Baddi, H.P, India 1
payal.ece@chitkara.edu.in , 2disha.chauhan@chitkara.edu.in
Abstract— Just like the ALU is used to perform various arithmetic and logical operations , in a similar manner our brain also performs these same operations. The brain is divided into two separate hemispheres of which the left hemisphere performs the logical operations like AND , OR, NOT and XOR whereas the right hemisphere is used to perform the arithmetic operations like ADDITION, SUBTRACTION, MULTIPLICATION and SUBTRACTION. The design is simulated with Xilinx ISE 12.1 using verilog module code. The analysis is done using the FPGA families VIRTEX-6 (40 nm) and SPARTAN-6 (45 nm).The design is tested on different frequencies ranging from 100MHz, 500MHz, 1000MHz, 2000MHz and at different ambient tempratures like 10, 30, 55, 70 degrees celsius to get optimised result for the design.
and right part of the brain [10], which is used when dealing with arithmetic operations. Similarly, the Pingala Nadi is used to control the right part of the body and left part of the brain [10], which is used when dealing with logical operations. Here, the verilog code is designed to perform some operations based on left brain and right brain . The design is simulated on Xilinx ISE 12.1 and implemented on two different FPGA.
Keywords— virtex-6 and spartan-6 FPGA; left hemisphere; right hemisphere; ambient tempratures
I. INTRODUCTION The human brain comprises of two halves. These halves are called as the left brain and right brain, but more commonly they are termed as hemispheres. The purpose of the left hemisphere is to process the small details of the visible object and that of the right hemisphere is to process the overall shape. The left hemisphere lays emphasis in grammar and decoding literal meaning whereas the right hemisphere lays emphasis in understanding verbal metaphors and decoding indirect or ambiguous meaning. For example, a person is called leftbrained if he is more congruent, inquisitive and objective, while a person is said to be right-brained if he is more instinctual, prudent and subjective. The left brain is also sometimes called as the digital brain as it controls functions like reading, writing, calculation, and logical thinking. Similarly the right brain is referred to as the analog brain and it controls three-dimensional sense, creativity, and artistic senses. The two hemispheres work together, to allow us to function as humans. A systematic analysis of brain and data is required for the simulation of the brain [1], usage of neuro modulator signals for writing the data that has been provided as input to the target brain circuits directly [2], usage of large scale imaging in order to decode the brain circuit [3], neurobiology [4], human information processing systems (HIPS) [5] and the capability to process information or we can say the spatial aspect of brain [6]. If a brain requires less time to respond to an event it is called as a High Performance Brain and to employ this we require intra operative cortical surface displacement [7], finite element models of the human brain [8] and in order to examine the brain connections it requires 2-D neural maps [9]. According to the Brain Theory Ida Nadis is used to control the left part of the body 157
Figure 1: RTL schematic of human brain
II. RELATED WORK There is an inclination towards minimum delay and lower consumption of power in energy efficient VLSI Design to operate for wider range of device operating frequencies [11]. According to simulations shown in [12], there is a drop in leakage power and total power by 22%-32% and 18%-24% respectively. X-Power 14.2 is used for creating UCF and NCD files for analyzing the power consumed [13]. In this design also power optimization is given utmost importance and a User Constraint File (UCF) is created to calculate the total power consumed. The various possibilities to reduce power and its usage at different abstraction levels is discussed in [14]. The power consumption is reduced if we scale down the voltage and frequency [15]. Xilinx Power Estimator which is an Electronic design association tool is used to outline the average power consumption under enable rate, toggle and frequency of operation [16].
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Int. Journal of Electrical & Electronics Engg.
Vol. 2, Spl. Issue 1 (2015)
III. POWER ANALYSIS ON VIRTEX-6 FPGA
0.66
Clock
Signals
IO
Leakage
100 500 1000 2000
0.001 0.007 0.014 0.027
0 0 0 0.001
0.002 0.010 0.020 0.040
0.464 0.464 0.465 0.465
Total Power 0.467 0.481 0.498 0.533
From the table we infer that while implementing the technology Virtex-6 , as we are scaling up the frequency from 100MHz to 2000MHz there is increase in clock power , signal power , IO power , leakage power and thus an increase in total power .
0.62 0.6
Total Power
0.58 0.56 0.54 100
500
1000
2000
Frequency(MHz)
Figure 3: Total Power (W) v/s Frequency(MHz)
The graph depicts an increase in the total power with the increase in frequency from 100MHz to 2000MHz when the design is implemented using Virtex-6 technology. Table 6: Power variations with different frequencies on Virtex-6 at 55 degree Celsius
0.54 0.52 T o tal Po w er (W )
0.64 T o tal Po w er (W )
Table 4: Power variations with different frequencies on Virtex-6 at 10 degree Celsius F(MHz)
e-ISSN: 1694-2310 | p-ISSN: 1694-2426
F(MHz)
Clock
Signals
IO
Leakage
100 500 1000 2000
0.001 0.007 0.014 0.027
0 0 0 0.001
0.002 0.010 0.020 0.040
0.753 0.753 0.754 0.755
Total Power 0.756 0.770 0.787 0.822
0.5
0.48
Series1
0.46 0.44 0.42 100
500
1000
2000
Frequency(MHz)
Figure 2: Total Power (W) v/s Frequency (MHz)
From the table we infer that while implementing the technology Virtex-6 , as we are scaling up the frequency from 100MHz to 2000MHz there is increase in clock power , signal power , IO power , leakage power and thus an increase in total power .
The graph depicts an increase in the total power with the increase in frequency from 100MHz to 2000MHz when the design is implemented using Virtex-6 technology.
F(MHz)
Clock
Signals
IO
Leakage
100 500 1000 2000
0.001 0.007 0.014 0.027
0 0 0 0.001
0.002 0.010 0.020 0.040
0.572 0.572 0.572 0.573
Total Power 0.575 0.589 0.606 0.640
From the table we infer that while implementing the technology Virtex-6 , as we are scaling up the frequency from 100MHz to 2000MHz there is increase in clock power , signal power , IO power , leakage power and thus an increase in total power .
0.84 0.82
T o ta l P o w e r (W )
Table 5: Power variations with different frequencies on Virtex-6 at 30 degree Celsius
0.8
0.78 Total Power
0.76 0.74 0.72 100
500
1000
2000
Frequency(MHz) Figure 4: Total power (W) v/s Frequency (MHz)
The graph depicts an increase in the total power with the increase in frequency from 100MHz to 2000MHz when the design is implemented using Virtex-6 technology. IV. POWER ANALYSIS ON SPARTAN-6 FPGA
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Int. Journal of Electrical & Electronics Engg.
Vol. 2, Spl. Issue 1 (2015)
From the table we infer that while implementing the technology Spartan-6 , as we are scaling up the frequency from 100MHz to 2000MHz there is increase in clock power , signal power , IO power , leakage power and thus an increase in total power .
0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0
T o tal Po w er (W )
Table 7: Power variations with different frequencies on Spartan-6 at 10 degree Celsius
e-ISSN: 1694-2310 | p-ISSN: 1694-2426
0.1 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0
Series1
100
500
1000
2000
T o tal P o w er (W )
Frequency(MHz)
Figure 6 : Total power (W) v/s Frequency (MHz) Series1
500
1000
2000
Table 9: Power variations with different frequencies on Spartan-6 at 55 degree celsius
Frequency(MHz)
Figure 5 : Total power (W) v/s Frequency (MHz)
The graph depicts an increase in the total power with the increase in frequency from 100MHz to 2000MHz when the design is implemented using Spartan-6 technology. F(MHz)
Clock
Signals
Ios
Leakage
100 500 1000 2000
0.001 0.004 0.008 0.016
0.001 0.004 0.008 0.017
0.002 0.01 0.02 0.04
0.011 0.011 0.011 0.011
F(MHz)
Clock
Signals
Ios
Leakage
100 500
0.001 0.004
0.001 0.004
0.002 0.01
0.022 0.022
Total Power 0.025 0.04
1000 2000
0.008 0.016
0.008 0.017
0.02 0.04
0.022 0.022
0.059 0.096
Total Power 0.014 0.029 0.048 0.085
Table 8: Power variations with different frequencies on Spartan-6 at 30 degree Celsius F(MH z) 100
Clock
Signals
IO
Leakage
0.001
0.001
0.015
500 1000 2000
0.004 0.008 0.016
0.004 0.008 0.017
0.00 2 0.01 0.02 0.04
Total Power 0.019
0.015 0.015 0.015
0.034 0.052 0.089
From the table we infer that while implementing the technology Spartan-6 , as we are scaling up the frequency from 100MHz to 2000MHz there is increase in clock power , signal power , IO power , leakage power and thus an increase in total power .
T o tal Po w e r (W )
100
The graph depicts an increase in the total power with the increase in frequency from 100MHz to 2000MHz when the design is implemented using Spartan-6 technology.
0.1 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0
Series1
100
500
1000
2000
Frequency(MHz)
Figure 7 : Total power (W) v/s Frequency (MHz)
From the table we infer that while implementing the technology Spartan-6 , as we are scaling up the frequency from 100MHz to 2000MHz there is increase in clock power , signal power , IO power , leakage power and thus an increase in total power The graph depicts an increase in the total power with the increase in frequency from 100MHz to 2000MHz when the design is implemented using Spartan-6 technology. V.
CONCLUSION
From the analysis we infer that the Spartan-6 is better to implement the design of human brain as compare to
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Int. Journal of Electrical & Electronics Engg.
Vol. 2, Spl. Issue 1 (2015)
Virtex-6. As the total power is increasing when we are moving from lower frequency to the higher frequency as well as lower ambient tempratures to the higher tempratures. When the temperature is 10 degree Celsius Spartan-6 is giving 97%, 93.97%, 90.36% and 84.05% more efficient result than the Virtex-6 at 100MHz, 500MHz, 1000MHz and 2000MHz respectively. When the temperature is 30 degree Celsius Spartan-6 is giving 96.69%, 94.22%, 91.41% and 86.09% more efficient result than the Virtex-6 at 100MHz, 500MHz, 1000MHz, 2000MHz respectively. When the temperature is 55 degree Celsius Spartan-6 is giving 96.69%, 94.80%, 92.50% and 88.32% more efficient result than the Virtex-6 at 100MHz, 500MHz, 1000MHz and 2000MHz respectively. FUTURE SCOPE
[12]
[13]
[14] [15] [16]
e-ISSN: 1694-2310 | p-ISSN: 1694-2426
international conference on power electronics (IICPE) (pp. 15),2011. K. Dhanumjaya, G. Kiran Kumar, M. N. Giriprasad, M. Raja Reddy, “Design and Modeling of Power Efficient, High Performance 32-bit ALU through Advanced HDL Synthesis”, Information and Communication Technologies Communications in Computer and Information Science Volume 101, pp 13-21,2010. B.Pandey and M.Pattanaik, “Low Power VLSI Circuit Design with Efficient HDL Coding”, IEEE International Conference on Communication Systems and Network Technologies (CSNT), Gwalior, India, April 5-8 2013 P.R Panda, B.V.N Silpa, A.Shrivastava & K.Gummidipudi, “Power-efficient system design,” Springer Press, 253 p, ISBN 978-1-4419-6388-8,2010. M.Maurice & J.PGyvez, “Technological boundaries of voltage and frequency scaling for power performance tuning”, Springer Integrated Circuits and Systems, ISBN 978-1-4419-4553-2 ,2008. K. Arshak, E. Jafer, and C. Ibala, “Power Testing of an FPGA based System Using Modelism Code Coverage capability”, IEEE Design and Diagonistics of Electronic Circuits and Systems,2007.
There is a vast scope to work on this project , we have implemented this design for logical and arithmetic calculations there we can different functions. This implementation is based on 40-nm Virtex-6 FPGA and 45nm Spartan-6 FPGA. There is a wide scope to implement this design on different FPGA like Virtex-7 and Kintex-7 FPGA device. To test this design, in term of power we can use IO Standard like SSTL, HSTL and verify the low power design efficiency on the latest FPGA. REFERENCES [1]
J. Chen, N. Zhong , "Toward the Data-Brain Driven Systematic Brain Data Analysis", IEEE Transactions on Systems, Man, and Cybernetics: Systems, Volume:43 , Issue: 1, pp.222-228, 2013 [2] K.V. Shenoy, A.V. Nurmikko, "Brain Enabled by Next-Generation Neurotechnology: Using Multiscale and Multimodal Models", IEEE Pulse, Volume:3 , Issue: 2, pp.31--36, 2012 [3] X. Hu, K. Li , J. Han, X. Hua , L. Guo , T.Liu, "Bridging the Semantic Gap via Functional Brain Imaging", IEEE Transactions on Multimedia, Volume:14 , Issue: 2, pp.314-325, 2012 [4] S. Jaume, K. Knobe, R.R. Newton, F. Schlimbach, M. Blower, R.C. Reid, "A Multiscale Parallel Computing Architecture for Automated Segmentation of the Brain Connectome", IEEE Transactions on Biomedical Engineering, Volume:59, Issue: 1, pp.35-38, 2012 [5] N. Zhong , J. Chen , "Constructing a New-Style Conceptual Model of Brain Data for Systematic Brain Informatics", IEEE Transactions on Knowledge and Data Engineering, Volume:24 , Issue: 12, pp.2127-2142, 2012 [6] J. Weng , M. Luciw, "Brain-Like Emergent Spatial Processing", IEEE Transactions on Autonomous Mental Development, Volume: 4 , Issue: 2, pp.161-185, 2012 [7] C. DeLorenzo, X. Papademetris, L.H. Staib, K.P. Vives, D.D. Spencer, J.S. Duncan, "Volumetric Intraoperative Brain Deformation Compensation: Model Development and Phantom Validation", IEEE Transactions on Medical Imaging, Volume: 31, Issue: 8, pp.1607-1619, 2012 [8] C. Schmidt, U.V. Rienen, "Modeling the Field Distribution in Deep Brain Stimulation: The Influence of Anisotropy of Brain Tissue", IEEE Transactions on Biomedical Engineering, Volume:59 , Issue: 6, pp.1583-1592, [9] R. Jianu, C. Demiralp, D.H. Laidlaw, "Exploring Brain Connectivity with Two-Dimensional Neural Maps", IEEE Transactions on Visualization and Computer Graphics, Volume:18 , Issue: 6,pp.978-987, 2012 [10] Swami Ramdev, "Yog Its Practice & Philosphy", Divya Yog Mandir, 2011 [11] M.Sharma,K.G Sharma, T.Sharma,B.P Singh & N.Arora, “SET Dflip flop design for portable applications”, iN IEEE India
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