Int. Journal of Electrical & Electronics Engg.
Vol. 2, Spl. Issue 1 (2015)
e-ISSN: 1694-2310 | p-ISSN: 1694-2426
High Performance Layout Design of SR Flip Flop using NAND Gates Bhupinder Kaur Department of ECE, National Institute of Technical Teachers’ Training & Research Chandigarh, India bhupinderk606@yahoo.com
Abstract: This paper presents optimized layout of SR flip flop using NAND gates on 90nm technology. The proposed SR flip flop has been designed using different technology namely fully-automatic design and semi-custom design. In the first approach layout has been generated using fully automatic technique with the help of SR flip flop schematic. In second approach layout has been generated manually by using one finger. In the last approach semicustom layout is further optimized by using two fingers. The area and power consumption of all the designs has been compared and analyzed. It can be observed from the simulated results that SR flip flop with two fingers and SR flip flop with one finger using semicustom technique consumes (62.92% , 91.20%) and (40.04%, 80.40%) less (area, power) as compare to the SR flip flop using fully automatic technique respectively. Keywords: Electronic circuits, Circuit simulation, Flip-flops, Power dissipation.
I. INTRODUCTION There are three types of MOS models in which we can work that are level 1, level 3 and Bsim4. Bsim4 model was introduced in 2000. A simplified version of this model is supported by Micro wind 3.1. It is a very accurate model. An accurate active device model plays an important role for the circuit designers. Technology scaling is one of the driving forces behind the tremendous improvement in performance, functionality, and power in integrated circuits over the past several years greatly reduced [1]. In the past, the major concerns of the VLSI designer were area, performance, cost and reliability; power considerations were mostly of only secondary importance. In recent years, however, this has begun to change and, increasingly, power is being given comparable weight to area and speed in VLSI design [2]. Low Power digital CMOS becomes more and more interesting, due to the general advances in process technology and new low power applications [3]. In electronics, a flip flop or latch is the special hardware device that is widely used in synchronous finite state machines. The name for flip flop stems from the days when basic cells were implemented with cross coupled relays. The set and reset operations of this electromechanical cell gave rise to distinctive audible flip and flop sounds [4]. It is a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems [5]. These are very useful, as they form the basis for shift 193
registers, which are an essential part of many electronic devices. It is a sequential circuit. all sequential circuits contain combinational logic in addition to the memory elements [6]. II. LITERATURE REVIEW In literature many designs have been proposed for the flip-flops to reduce power and area constraints. One paper enumerates a low power, high speed design of flip-flop having less number of transistors. In that flipflop design only one transistor is being clocked by short pulse train [6]. A new D flip flop design which is named as Switching Transistor Based D Flip Flop (STDFF) is used in the paper [5]. A new design of CMOS DET flipflop was proposed and simulated with SPICE and 1Îź technology for the reduction of power [2]. The efficient methodologies have been proposed for reducing leakage current in VLSI design. The proposed methods results in ultra-low static power consumption with state saving [1]. Figure-1 shows the schematic of SR flip flop using NAND gate. The characteristic and excitation table for SR flip flop is showing in the table.
Figure 1- schematic of SR flip flop using nand gate. Table 1- Characteristic and Excitation table for SR flip flop Characteristic table S R Q next Action previous 0 0 Q state 0 1 0 Reset 1
0
1
Set
1
1
X
Forbidden state
The operation of the R-S flip-flop of Figure-1 is follows: NITTTR, Chandigarh
EDIT-2015
Int. Journal of Electrical & Electronics Engg.
Vol. 2, Spl. Issue 1 (2015)
e-ISSN: 1694-2310 | p-ISSN: 1694-2426
1. S=R= 0. It has no effect on the output state of the flip-flop. Both Q and Q’ outputs remain in the logic state they were in prior to this input condition. 2. S = 0 and R = 1 resets the flip-flop. Q and Q’ respectively go to the ‘0’ and ‘1’ state. 3. S =1 and R =0 sets or clears the flip-flop. Q and Q’ respectively go to the ‘1’ and ‘0’ state. 4. S = R = 1 is forbidden as such a condition tries to set (that is, Q = 1 ) and reset (that is, Q’ = 1) the flip-flop at the same time[9]. The characteristic equation of the SR flip flop is Q+ = R'Q + R'S or Q+ = R'Q + S [8]. III.
SR FLIP FLOP SCHEMATIC DESIGN
For the schematic design of SR flip flop 16 MOS devices is used which is shown in figure-2.
Figure 3- Simulation of SR flips flop by using 16 nMOS and pMOS
After this the fully automatic layout of the above SR flip flop is generated which is represented in figure-4.
Figure 4- fully automatic layout of SR flip flop
IV.
Figure 2- schematic of SR flip flop by using 16 nMOS and pMOS
After that we do the simulation in DSCH 3.1. Figure-3 is showing the simulation of SR flip flop with fully generated technique.
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PROPOSED SR FLIP FLOP LAYOUT :
Here the SR flip flop layout is generated using semicustom technique where we further use two methods for this one with one finger in nMOS and pMOS and other with two fingers in nMOS and pMOS.
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Int. Journal of Electrical & Electronics Engg.
Vol. 2, Spl. Issue 1 (2015)
e-ISSN: 1694-2310 | p-ISSN: 1694-2426
Figures 7- simulation of SR flip flop with two finger
V. RESULT AND ANALYSIS This paper shows that our proposed method of making the layout of SR flip flop is showing better results than the conventional method of making layout of SR flip flop. Our proposed simulations work on the 90 nm technology and the results are given below. Table 2- Showing the comparative analysis of three different techniques Figure 5- SR flip flop with one finger
Figure-5 shows the semi-custom layout of the SR flip flop using nMOS and pMOS (having one finger) with some connections using polysilicon and metal. After this we generate the second layout of SR flip flop using nMOS and pMOS (having two fingers) which is shown in figure-6 and then simulation is done.
Parameters considered Automatic layout Semi-custom layout with one finger Semi-custom layout with two finger
Area
Power
124.6 μm2
363μw
Number of nodes 17/3000
74.7 μm2
70.946μw
28/3000
46.2μm2
31.625μw
24/3000
With this we also observe that the number of nodes increases in semi-custom layout than the fully custom latout.
Figure-8 Bar chart showing area and power consumption of SR flip flop using different approaches
The result by two different techniques rather than the conventional technique shows the following improvements. Table-3 represents the percentage variation of parameters. Figure 6- SR flip flop with two finger
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Table 3- variation in parameters
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Int. Journal of Electrical & Electronics Engg.
Decrease in Parameters
Semi-custom layout with one finger
Vol. 2, Spl. Issue 1 (2015)
Semi-custom layout with two fingers
Area
40.04%
62.92%
Power
80.40%
91.20%
Number of nodes
-64.70%
-41.10%
Note: Negative sign shows the increase in parameters
VI. CONCLUSION This paper concludes that area and power consumption in semicustom technique using 90nm technology is reduced with the compensation of increase in number of nodes. If we use nMOS and pMOS with one finger the power consumption and area is less than the auto generated layout but more than the layout which is generated by using two fingers in nMOS and pMOS . In future we can add some other power and area reduction techniques which also improve the number of nodes and signal to noise ratio used in the layout design.
NITTTR, Chandigarh
EDIT -2015
e-ISSN: 1694-2310 | p-ISSN: 1694-2426
REFERENCES [1]. Pushpa Saini, Rajesh Mehra “Leakage Power Reduction in CMOS VLSI Circuits’’. International Journal of Computer Applications Issue-4, Volume 55– No.8, October 2012 [2]. Massoud Pedram Xunwei Wu ‘’a new design for double edge triggered flip-flops’’ IEEE design automation conference pp. 417 – 421 Feb 1998 [3]. M.Arunlakshman “Power and Delay Analysis of Double Edge Triggered D-Flip Flop based Shift Registers in 16nm MOSFET technology” international Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering Vol. 3, Issue 4, April 2014 . [4] William I. Fletcher “An Engineering Approach to Digital Design”, the University of Michigan, Prentice-Hall, 1980 [5]. D. Prasanna Kumari, R. Surya Prakasha Rao, B. Vijaya Bhaskar “A Future Technology For Enhanced Operation In Flip-Flop Oriented Circuits” International Journal of Engineering Research and Applications (IJERA) Vol. 2, Issue4, pp. 2177-2180 JulyAugust 2012. [6]. M.Arunlakshman, T.Dineshkumar, N .Mathan “Performance Evaluation of 6 Transistor D-Flip Flop based Shift Registers using GDI Technique” International Journal of Advanced Research in Computer and Communication Engineering Vol. 3, Issue 3,pp 5858-5861, March 2014. [7]. Priyanka Sharma, Rajesh Mehra , “True single phase clocking based flip-flop design using different foundries” International Journal of Advances in Engineering & Technology; May2014, Vol. 7, Issue 2, pp. 352, May 2014. [8]. Langholz, Gideon; Kandel, Abraham; Mott, Joe L.; Abraham Kandel, Joe L. Mott (1998).’’Foundations of Digital Logic Design. Singapore’’ World Scientific Publishing Co. Ptc. Ltd. P. 344 , 2011. [9] Anil K. Maini “Digital Electronics: Principles, Devices and Applications” John Wiley & Sons, Ltd. 2007
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