Int. Journal of Electrical & Electronics Engg.
Vol. 2, Spl. Issue 1 (2015)
e-ISSN: 1694-2310 | p-ISSN: 1694-2426
High Performance Layout Design of SR Flip Flop using NAND Gates Bhupinder Kaur Department of ECE, National Institute of Technical Teachers’ Training & Research Chandigarh, India bhupinderk606@yahoo.com
Abstract: This paper presents optimized layout of SR flip flop using NAND gates on 90nm technology. The proposed SR flip flop has been designed using different technology namely fully-automatic design and semi-custom design. In the first approach layout has been generated using fully automatic technique with the help of SR flip flop schematic. In second approach layout has been generated manually by using one finger. In the last approach semicustom layout is further optimized by using two fingers. The area and power consumption of all the designs has been compared and analyzed. It can be observed from the simulated results that SR flip flop with two fingers and SR flip flop with one finger using semicustom technique consumes (62.92% , 91.20%) and (40.04%, 80.40%) less (area, power) as compare to the SR flip flop using fully automatic technique respectively. Keywords: Electronic circuits, Circuit simulation, Flip-flops, Power dissipation.
I. INTRODUCTION There are three types of MOS models in which we can work that are level 1, level 3 and Bsim4. Bsim4 model was introduced in 2000. A simplified version of this model is supported by Micro wind 3.1. It is a very accurate model. An accurate active device model plays an important role for the circuit designers. Technology scaling is one of the driving forces behind the tremendous improvement in performance, functionality, and power in integrated circuits over the past several years greatly reduced [1]. In the past, the major concerns of the VLSI designer were area, performance, cost and reliability; power considerations were mostly of only secondary importance. In recent years, however, this has begun to change and, increasingly, power is being given comparable weight to area and speed in VLSI design [2]. Low Power digital CMOS becomes more and more interesting, due to the general advances in process technology and new low power applications [3]. In electronics, a flip flop or latch is the special hardware device that is widely used in synchronous finite state machines. The name for flip flop stems from the days when basic cells were implemented with cross coupled relays. The set and reset operations of this electromechanical cell gave rise to distinctive audible flip and flop sounds [4]. It is a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems [5]. These are very useful, as they form the basis for shift 193
registers, which are an essential part of many electronic devices. It is a sequential circuit. all sequential circuits contain combinational logic in addition to the memory elements [6]. II. LITERATURE REVIEW In literature many designs have been proposed for the flip-flops to reduce power and area constraints. One paper enumerates a low power, high speed design of flip-flop having less number of transistors. In that flipflop design only one transistor is being clocked by short pulse train [6]. A new D flip flop design which is named as Switching Transistor Based D Flip Flop (STDFF) is used in the paper [5]. A new design of CMOS DET flipflop was proposed and simulated with SPICE and 1Îź technology for the reduction of power [2]. The efficient methodologies have been proposed for reducing leakage current in VLSI design. The proposed methods results in ultra-low static power consumption with state saving [1]. Figure-1 shows the schematic of SR flip flop using NAND gate. The characteristic and excitation table for SR flip flop is showing in the table.
Figure 1- schematic of SR flip flop using nand gate. Table 1- Characteristic and Excitation table for SR flip flop Characteristic table S R Q next Action previous 0 0 Q state 0 1 0 Reset 1
0
1
Set
1
1
X
Forbidden state
The operation of the R-S flip-flop of Figure-1 is follows: NITTTR, Chandigarh
EDIT-2015