Area and Power Efficient Up-Down counter Design by Using Full Adder Module

Int. Journal of Electrical & Electronics Engg.

Vol. 2, Spl. Issue 1 (2015)

e-ISSN: 1694-2310 | p-ISSN: 1694-2426

Area and Power Efficient Up-Down counter Design by Using Full Adder Module 1

Anjali Sharma, 2Richa Singh

1

PHD Scholar Chitkara University, Punjab, India, Assistant Professor Department of Electronics and communication Engineering, VSGOI Unnao,U.P. India

2

1

anjali.iitt@gmail.com, 2singhricha51@gmail.com

Abstract- In this paper an area and power efficient 98T UpDown counter design has been presented by using Pass transistor logic designing technique. The proposed Up-Down counter design consist of 53 NMOS and 45 PMOS. Four PTL full adder modules has been used to design this Up-Down counter which consumes less area and power at 120 nm as compared to CMOS, TG and GDI full adder designs. The proposed Up-Down counter design is based on this area and power efficient 10 transistors PTL full adder module. The proposed Up-Down counter has been designed and simulated using DSCH 3.1 and Microwind 3.1 on 120nm. For proposed design Power variation with respect to the supply voltage has been performed on BSIM-4 and LEVEL-3 using 120nm technology. Results show that Area of proposed PTL UpDown counter design is 1288.4 µm2 on 120nm technology. At 1.2V input supply voltage the proposed Up-Down counter design consumes 111µW power at BSIM-4.

Keywords- BSIM, CMOS, Gate Diffusion Input, NMOS, PMOS, PTL, Transmission Gate, VLSI.

I. INTRODUCTION In present technology world use of portable devices has been increased and measurement of power and area consumption is major concern in schematic design of these portable devices before their actual implementation in the layout. Large power and area consumption is a key limitation in many electronic devices and these parameters also act as show stopper for VLSI applications. So there is need of new VLSI designing techniques and methodologies to control and limit power and area consumption [1]-[2]. In digital processing, there is requirement of area and power efficient counter design.

The critical path in VLSI circuit design is increased no of transistors that produce the delay in the output signal [3]. It is also the speed limiting and more power consuming element of many VLSI applications. The design of faster, smaller and more efficient counter architecture should be there for VLSI applications. Two most important properties of the counter architectures are power consumption and propagation which basically are against each other. Decrease in the power consumption can cause delay in the circuit and vice versa, hence, most architectures referring to one of those important properties.

Traditional CMOS technology, results in full voltage swing but consume large area. Transmission gate technology consumes less area as compare to CMOS technology because it consumes less no of transistors. One another logic that consumes less power is PTL - passtransistor logic. Advantages of PTL over standard CMOS logic design are: High speed - due to the small node capacitances, Low power dissipation - as a result of the reduced number of transistors, Lower interconnection effects - due to a small area [5]. But implementations of 11

circuit by PTL logic have two basic problems [6] i.e. threshold drop across the single-channel pass transistors and static power dissipation. Logic design which can overcome this problem is Complementary pass-transistor logic (CPL) which features complementary inputs/outputs using NMOS pass-transistor logic.

II. 4- BIT UP-DOWN COUNTER In digital processing and computing applications, a counter is a device which stores and displays that with any clock input how many times a particular event or process has been occurred. A most common type of counter is a sequential digital logic circuit with a clock input line and multiple output lines. The values on the output lines represent a number in the binary or BCD number system. Each pulse applied to the clock input increments or decrements the number in the counter. A counter circuit can be constructed by number of flip-flops connected in cascade. Counters is most widely used digital component in digital circuits which are further used in the various digital processing applications, and are manufactured as separate integrated circuits and also incorporated as parts of larger integrated circuits. UpDown counter design by using full adder module has been shown in Fig.1.

Fig.1 Up-Down Counter by using Full adder modules III. SCHEMATICS DESIGNS OF 1-BIT FULL ADDER Full adder is one of the basic building blocks of arithmetic unit used in various digital electronic devices.

Full adder can be designed by using different logics. Area consumption, speed and power consumption are the main parameter estimation criteria’s and should be investigated and analyzed for the efficient performance of the digital circuits [7].

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Int. Journal of Electrical & Electronics Engg.

Vol. 2, Spl. Issue 1 (2015)

e-ISSN: 1694-2310 | p-ISSN: 1694-2426

this circuit is that it can’t give full voltage swing at the output.

Fig.2 CMOS Full Adder Design [7] Fig.4 PTL Full Adder Design In Fig. 2 a full adder design has been shown by using CMOS logic which consist 36T transistors and a TG Full adder design by using 22 transistors has been shown in Fig 3 [7]. As CMOS and TG based full adder designs consume less power but it consists large transistors and hence consume very large area.

In [7] also a new and area efficient full adder design has been achieved by using GDI technique shown in Fig.5.

Adder circuit by using GDI technique uses 10 transistors to generate adder output. In this circuit simultaneously generation of XOR and XNOR output has been implemented which further acts as a input for the SUM and CARRY Module. Sum and Carry output has been obtained by using 2x1 MUX.

Fig.5 GDI Full Adder Design Fig.3 TG Full Adder Design [15] If a logic style shows good performance in terms of one estimation criteria it can give degraded performance in other. The majority of the power dissipated in CMOS VLSI circuits is by dynamic power dissipation which is the power dissipated during charging or discharging of the load capacitance of a given circuit. A full adder design by using PTL logic has been shown in Fig 4. This design has been implemented by using 10 transistors. This design consists less transistors as compared to CMOS and TG full adder designs so this design consumes less area as compared to CMOS and TG design but disadvantage of NITTTR, Chandigarh

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IV.PROPOSED UP-DOWN COUNTER SCHEMATICS In proposed Up-Down counter design four Full adder modules has been used as a basic building block shown in Fig. 6. MICROWIND and DSCH 3.1 designing tool has been used for the designing of this circuit. MICROWIND 3.1 VLSI designing tool deals with both front end and back end designing of digital circuits. DSCH work in front end which has ability to design the circuit by using transistors as well as gates. DSCH designing can generate VERILOG file which can be compiled by the MICROWIND back end designing tool to observe parameters such as power and area consumption.

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Int. Journal of Electrical & Electronics Engg.

Vol. 2, Spl. Issue 1 (2015)

e-ISSN: 1694-2310 | p-ISSN: 1694-2426

Fig.7 Layout of Up-Down Counter

Fig.6 Design of Proposed Up-Down Counter Proposed PTL Up-Down counter is best in terms of area as compared to CMOS, TG and GDI Up-Down counter design. Comparative analysis of various Up-Down counter designs on 120nm has been shown in Table.1. Up-Down counter by conventional CMOS consist 202 transistors, TG Up-Down counter consists 146 transistors and GDI and PTL Up-Down counter consists 98 transistors.

Up-Down Counter design NMOS PMOS Width (µm) Height (µm) Area (µm2 )

CMO S

TG

GDI

Propose d PTL

105 97 213.2

53 45 109.

6 12.2

53 45 109.6

13.7

77 69 178.

7 11.3

2917.

1

2015 .5

134.

1

1288.4

Fig.8 3D view of proposed Up-Down counters design 11.8

V. LAYOUT ANALYSIS For a very complex circuit it is not possible to conduct the manual layout so an automatic layout generation approach is preferred. Required schematic diagram has been firstly designed and logically validated using DSCH tool at logic level. Although at logic level DSCH have feature to analyze timing simulation as well as power consumption but accurate layout information is still missing. A VERILOG file is generated by the DSCH 3.1 designing tool which is understandable by the MICROWIND 3.1 designing tool to construct the corresponding layout with exact desired design rules. Another way to create the design is by NMOS and PMOS devices using cell generator provided by the MICROWIND. The advantage of this approach is to avoid any design rule error. W/L can be adjusted by the MOS generator option on MICROWIND tool [8]. Layout of Up-Down Counter has been shown in Fig. 7.

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3D view of proposed Up-Down counters design has been shown in Fig.8. Various steps used for the creation of this structure are- initial substrate creation, N- diffusion, SiO2 isolation, thin oxide growth, thin oxide reduction, polysilicon deposit, N+ implant, P+ implant, 2nd polysilicon deposit, contact creation, metal layers deposition and via hole creation, passivation oxide deposition and passivation etching. This layout consist 6 metal layers and 2 polysilicon layers.

VI. SIMULATION RESULTS Area and power consumption of proposed Up-Down counters has been evaluated on 120nm technology by using MICROWIND designing tool. Simulation of proposed Up-Down counters has been performed to get power and current variation with respect to the supply voltage.

Parametric analyses of proposed Up-Down counters have been performed using the MOS Empherical model Level-3 and BSIM Model-4 at different power five different supply voltages.

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Int. Journal of Electrical & Electronics Engg.

Vol. 2, Spl. Issue 1 (2015)

Fig.9 Power vs. Supply Voltage on BSIM-4 Threshold voltage has been taken as 0.4V for both levels which is the voltage above which the power and current starts increasing with the increase in supply voltage.

Operating temperature has been taken 270C for both LEVEL-3 and BSIM-4.MOS Empherical model Level-3 and BSIM Model-4 provides the feature of different curve fitting parameters which is useful in parametric analysis.

e-ISSN: 1694-2310 | p-ISSN: 1694-2426

Morgenshtein, A.; Fish, A.; Wagner, I.A., “Gate-diffusion input (GDI): A Power Efficient Method For Digital Combinational circuits,” IEEE Transaction on Very Large Scale Integration Systems, Vol. 10 , No . 5, pp. 566 - 581, 2002.

Anjali Sharma, Rajesh Mehra, “Area and Power Efficient CMOS Adder Design by Hybridizing PTL and GDI Technique,” International Journal of Computer Applications, Vol.66, No. 4, pp. 15-22.

Etienne Sicard, Sonia Delmas Bendhia, Basic of CMOS Cell Design, tata mc graw-hill, pp. 51-90, 2007.

Fig.10 Power vs. Supply Voltage on LEVEL-3

MOS Empherical model Level-3 has features of 10 different curve fitting parameters whereas BSIM Model-4 works with 19 different parameters. Graph for variation in power with respect to Vdd has been shown in Fig.9 for BSIM-4 and in and Fig. 10 for LEVEL-3.

VII. CONCLUSION An alternative Up-Down counters design by using PTL approach has been proposed which consists 98 transistors.

Proposed Up-Down counters have been implemented by using 58 NMOS and 45 PMOS transistors. Proposed UpDown counters have been designed using an area efficient PTL Full adder module which has been implemented by using only 10 transistors. Area and power consumption of proposed Up-Down counters has been shown on120nm using LEVEL-3 and BSIM-4 analytical models. Area of proposed Up-Down counters design is 1288.4µm2 on 120nm technology. At 1.2V input supply voltage the proposed Up-Down counters consumes 62.197µW power at BSIM-4 and 32.824 µW power at LEVEL-3. The proposed Up-Down counters circuit can work efficiently with minimum voltage supply of 0.4V and can work on wide range of frequency range between 2MHz to 400MHz. REFERENCES N. Weste and K. Eshraghian, (2002) “Principles of CMOSVLSI Design” A System Perspective Reading, Pearson Education, Addison–Wesley.

Anjali Sharma, Richa Singh, Pankaj Kajla “Area Efficient 1-Bit Comparator Design by using Hybridized Full Adder Module based on PTL and GDI Logic,” International Journal of Computer Applications, Vol.82, No. 10, pp. 5-13.

Chiou-Kou Tung; Yu-Cherng Hung; Shao-Hui Shieh; Guo-Shing Huang,” A Low -Power High-speed Hybrid CMOS Full Adder For Embedded System,” IEEE transactions on Design and Diagnostics of Electronic Circuits and Systems, vol.13, No.6, pp.-1 – 4, 2007.

Anjali Sharma, Richa Singh, Pankaj Kajla “Area Efficient 1-Bit Comparator Design by using Hybridized Full Adder Module based on PTL and GDI Logic,” International Journal of Computer Applications, Vol.82, No. 10, pp. 5-13.

A Morgenshtein, Fish, Wagner, “Gate - Diffusion input (GDI) - A novel power efficient method for digital circuits: A Design Methodology ,” IEEE International Conference, pp. 39 – 43, 2001.

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